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Everybody panic: A Valve developer said "HLX" in public
Sound designer lets Half Life-related codename slip at a conference.
Designers’ notes: The River of Bones rules
The Warhammer: The Old World team tells us about the rules from the latest supplement.
Dee Snider to induct wife into Long Island Music and Entertainment Hall of Fame
Suzette Guilot-Snider created Twisted Sister’s iconic, trend-setting fashion Fashion designer Suzette Guilot-Snider will be inducted into the Long Island Music and Entertainment Hall of Fame (LIMEHOF) at their Stony Brook Village location at 97 Main Street on Saturday, November 14th at 8:30 pm. Her husband, Twisted Sister lead singer and LIMEHOF Inductee Dee Snider, will […]
AMC Movie Trivia App Launch At AMC Stock Has Changed Its Investment Story
AMC Entertainment Holdings has launched AMC Movie Trivia Game Show, a free mobile trivia app created with Hoyt Games and puzzle designer David L. Hoyt, featuring daily movie themed puzzles and AMC Stubs integration. The app shifts part of AMC Entertainment Holdings' customer interaction into mobile gaming and extends the loyalty program into everyday engagement beyond theater visits. The next point of consideration is how AMC Entertainment Holdings' investment narrative might be influenced...
'AI slop' or a boost for business?: How online AI promos are changing jobs in Sarpy County
As small businesses turn to generative AI for labels, menus and advertising, an Omaha-area graphic designer says the technology is reducing opportunities for human creatives.
Things an interior designer would never have in her kitchen
Interior designer Lane Mari shared some common design mistakes, cabinet styles, and lighting options she would never put in her own kitchen.
Veronica Leoni Exits Calvin Klein After Four Seasons
The Italian-born designer led the return of Calvin Klein Collection to New York Fashion Week. A successor has not yet been named.
Legendary FPS level designer Richard "Levelord" Gray passes away at 68
Tributes pour in for the man behind iconic Duke Nukem 3D levels and much more.
Daldrop Opens for Business in Southern Oswego County
$10 Million Facility in the L. Michael Treadwell Oswego County Industrial Park marks the largest expansion outside of Germany in the company’s 73-year history By Stefan Yablonski [caption id=attachment_11076 align=alignright width=450] Daldrop SBB CEO Jens Daldrop addresses attendees at the 2025 groundbreaking for the project. Daldrop also chairs the advisory board of Germany-based Daldrop Group.[/caption] A new era of cleanroom technology is underway in Central New York. The Daldrop Group’s advanced manufacturing facility and U.S. headquarters is physically built within the L. Michael Treadwell Oswego County Industrial Park. This industrial park is located in the town of Schroeppel. It marks the largest expansion outside of Germany in the company’s 73-year history. Daldrop SBB is based in Neckartailfingen, Germany. It is a global supplier of cleanroom technology, primarily to the pharmaceutical industry. It designs and builds advanced cleanroom environments for the pharmaceutical, biotechnology and medical technology industries. It nvested $10 million in the new project. “We broke ground in 2025; we were under construction all winter. We just opened this spring, early spring,” said Benjamin Morrow, operations manager and control. The company consolidated sites in Salina and DeWitt into the industrial park in Schroeppel, Morrow added. “The next move here is to maximize every square inch of this facility and then we are already looking at the expansion. So, it is more capital investment on equipment — definitely higher-end automation in additional equipment so we can produce more components and then to support the ever-growing base in North America,” Morrow continued. “We are the headquarters for service, maintenance and spare parts. So as Daldrop has more and more installations, they need more and more service, maintenance and spare parts. So that will come out of this facility as well — it already is.” “As a global leader in GMP (global manufacturing support) pharmaceutical cleanrooms for decades, I am very proud to bring manufacturing jobs to Upstate New York,” said Mike Sullivan, president of Daldrop US operations. Key to choosing Southern Oswego County [caption id=attachment_11077 align=alignright width=450] Daldrop SBB at the L. Michael Treadwell Oswego County Industrial Park when the company announced the start of construction.[/caption] Sullivan said that the selection of the Schroeppel industrial park was mainly due to the help of Operation Oswego County and two people in the organization. “Prior to being purchased by Daldrop International from the Stuttgart region of Germany, Vince Bongio was a founding partner in SBB Inc. as well as our head of engineering. We based out of Syracuse due to Vince’s skills in HVAC and the manufacturing capabilities found in Syracuse,” said Sullivan. Bongio moved to Syracuse from California in the 1970s to work in Carrier’s Industrial Division of Large-Scale Petrochemical Refrigeration. Next, he advanced to General Electric’s TV Tube Plant where he got into cleanrooms ,leading to his role of head of engineering for Clestra Cleanrooms where he met Sullivan, their New England distributor. “Vince Bongio is a phenomenal engineer. Formerly of Carrier, he grew up in California and went to Cal Poly,” Sullivan explained. “Carrier hired him right out of college and he moved to Syracuse. He is the reason we are in Syracuse today. He is retiring this year. We are very proud and his legacy is having brought Daldrop to Syracuse.” In 2000, Sullivan, Bazinet, Bongio Inc (SBB) was formed with engineering and manufacturing, based in Syracuse, and sales and construction based in Massachusetts as it is today. “SBB Inc. started in Syracuse. I had a design–build contracting firm out of Massachusetts that was primarily doing all the new technologies coming out of MIT,” Sullivan said. “I started a manufacturing side. A big thing for cleanrooms is the HVAC. Most cleanroom suppliers are architecturally focused people. The strength in Syracuse is HVAC. So, SBB developed with me running sales and construction out of Massachusetts and manufacturing out of Syracuse.” “Daldrop wanted to have a relationship in the States and of those who approached us, they were the only ones who really understood HVAC. So, we were the right fit for them. We did a joint venture focused out of Massachusetts from 2012 to 2018 leveraging their technologies,” Sullivan explained. “The commitment was if we brought their product to the States, we would do that if they built it here. “The pieces that had to be in place to make the investment, they wanted to acquire us, we were great with that. If you looked at business recommendations the general guidance was to build in a low labor area — something like North Carolina — but Syracuse had a strong background in HVAC and we chose Syracuse and Oswego County to be our headquarters in the States. So, it is built off of history, technology and the existing supply chain — bringing jobs back to the area.” During the initial discussions with Daldrop about coming to the U.S., SBB agreed to sell under the conditions Daldrop would manufacture in the U.S. There are many areas that offer incentives and economic packages, but the strength of HVAC expertise and skilled manufacturing was a big part of the discussions for site selection. Coming home [caption id=attachment_11078 align=alignright width=451] Construction moves forward in March at the L. Michael Treadwell Oswego County Industrial Park.[/caption] The second key person to building in Oswego County is Ben Morrow, Sullivan added. “Ben has been working with Daldrop SBB for more than 12 years and has advanced to COO of manufacturing and engineering. Ben grew up in Phoenix, so building a factory for the Germany company in Phoenix is a strong success for both his community and the appreciation of Ben’s skills as a team leader,” Sullivan said. “I went to high school in Phoenix. So, this is like full circle for me. It’s a small world,” Morrow said. “I hadn’t been back to Phoenix since graduation. This is one of the properties that John Trimble of C&S, he is the former president of C&S, he just retired, suggested. He and I were very good personal friends. John was from Mexico and I was from Phoenix. We knew each other from high school. And the architect of this building, Ed Smart of smartDESIGN Architecture in Batavia — I went to high school with him. So, this was a project that’s full circle a coming home kind of thing. The three of us knew each other — kind of like it was meant to be. Very serendipitous.” Schroeppel was one option for Daldrop to consider; the original intent was just to get a warehouse to store some product, he added. The facility is Daldrop’s largest outside of their native country. Total payroll at the facility will be approximately $2.4 million once fully staffed. “Here is 32,000 square feet and we plan to expand and put in an additional 10,000 square feet,” Morrow said. “We have 17.5 acres. We can put at least three more facilities here, just on this property. The master plan submitted for the current building is the first of possible three buildings on the campus.” “If we can find the right people and advance the production according to the plan, we should be able to grow for the next decade. One of the first jobs we filled was our new HR manager, with a primary focus posting and filling new positions,” Sullivan said. Stop the exodus, start hiring [caption id=attachment_11080 align=alignright width=452] Principals at the local Daldrop SBB headquarters, from left: Ben Morrow, Mike Sullivan and Jens Daldrop.[/caption] “I have been coming to Syracuse for 30 years. One of the things I had a hard time watching was the exodus of factories. One of the toughest things is to watch it with my partners’ kids who had to move away for jobs. It is important for us to give opportunity where people’s kids don’t have to leave the area to get work,” Sullivan said. “My responsibility is to find people who have skill sets that want to work and then I have to build opportunity for that work to happen. “After years of watching companies and Vince’s three sons all move out of the areas to get jobs, it is important to us to provide opportunities for the Syracuse region and help grow our company. We have been hiring for our new factory and will continue for the next few years.” “We are hiring and will continue to hire. Currently we have about 19 on staff right now,” Morrow said. “We expect to grow that by about 10 to 15 in the next 12 to 18 months or so. We are at 19 currently — one in the wings. It’s been great being able to hire locally. All these folks that we’ve been hiring, they all live within a few miles from here.” “We hired someone this past week (end of August). She grew up in the area, raised a family and is working down in Florida. She just took a job with us so she can move back and be with her family. We will be moving her back and she should be starting in October. We are very happy to see this happen,” Sullivan said. “I feel strongly about having a spot for the kids to not have to move out of the area. It is better to have people moving into the area.” Currently, Daldrop SBB has openings for finance manager, COO of construction and delivery, as well as mechanical, electrical designers and Revit modelers, construction managers, commissioning agents and many other skills that are needed. Along with Daldrop’s reputation in life science cleanrooms, there is a strong history in semiconductor, electronics, glass, photonics, aerospace and other markets. This may be helpful with any new technologies building in the market such as the Micron expansion and the support network, Sullivan said. “We acquired this property and closed on it two months before any announcement from Micron. It is serendipitous that they’re right down the street from us,” Morrow added. “Everybody started thinking ‘you guys are supporting Micron.’ We were here first. That is not a goal of ours. We may or may not … they are talking to us; it is an opportunity.” The long run [caption id=attachment_11079 align=alignright width=450] Benjamin Morrow, operations manager and control at Daldlrop, speaks during a recent ribbon-cutting event in Schroeppel.[/caption] “Long term, we will expand the Phoenix facility,” Sullivan said. “We built our facility with a campus approach. Sustainability is big. We designed our rooms to be more sustainable. Our building has no gas lines for heat. We put geothermal wells in the ground. We put heat pumps in for heating and cooling out of those wells and we put a large layer of solar panels up on the roof. We worked with National Grid for metering. Our building is a high efficiency model. We upgraded all the instillation and the glass filtering. So, it is a very green building. We will have a very minimal carbon footprint. It also adheres to LEED (Leadership in Energy and Environmental Design) construction standards.” “We are a bunch of HVAC engineers. We did a large scale geothermal and spent the money up front because we knew it made sense in the business sense in the environmental sense and sustainability,” Morrow said. “We have insulated metal panels on walls and roof; we are an envelope from the exterior.” Daldrop, as a global player, has a strong culture of sustainability that is found in all its products including the new facility. The building has been designed with (sixteen) 400-foot deep geothermal wells, high efficiency construction methods, approximately 70 kilowatt solar photovoltaic panels, electric vehicle chargers and 26% recycled content. “Daldrop thinks of long-term investing,” Sullivan said. “On the roof, photovoltaic panels supplement our power. Over half the energy that I use is coming from the sun. We have chargers up front for employee electric vehicles. This place is built to last. This slab that we are walking on, normal buildings are four inches, some go to six inches, we are nine inches all the way through — except where the heavy equipment is — that is 10 to 12 inches thick, solid concrete. It allows us to reconfigure for whatever type of equipment we want to bring in,” Morrow said. “We are authorized by Underwriters Laboratory to self-certify so we don’t need to have an inspector come out and recertify. We get audited often, but we certify our own electronics. The control system in this building is rather high-end. Our thermostat in every room is zoned, independent. We analyze the data; incorporate it with our solar panels.” “There is a lot of competition for people to work. It’s not just about how much salary they are going to make — it’s about the work environment, the ability for stability. We want to make sure our employees have the best environment to work in,” Morrow added. Similarities “One of the reasons I believe why Daldrop chose this area, Phoenix in particular, is because it is a village, a river-based village. Neckartailfingen in Germany where Daldrop is based is also a river-based village, manufacturing community. So, there is a lot of similarities — that smalltown feel,” Morrow said. “We have a lot of connections through multiple employees that lead back to Carrier, also. Everything came together, the timing everything.” “We are thankful for all the economic development support. Everyone has been helping make this happen. So, keep it up, it is working, that is all I got to say, Sullivan said. “If you look at historical industrial manufacturing, this region has skills that have been un-utilized. The northern industrial region has a lot of skills that if we can tap before they go away, we can leverage them. That is what we are trying to do. You’d be surprised at the supply chain left behind from Carrier — that supply chain is still there.” “Operation Oswego County has been fantastic,” Morrow added. “I can’t say enough good things about that group.” What Is Cleanroom Technology Cleanroom technology is a system of specialized engineering, filtration and operational controls used to maintain an extremely low concentration of airborne particles, microbes and chemical vapors. How It Works • Air Filtration: Uses HEPA or ULPA filters to remove 99.97% of tiny particles down to 0.3 microns. • Airflow Control: Directs air in a steady, unidirectional (laminar) or filtered turbulent pattern to push dust away from work areas. • Environmental Regulation: Maintains precise control over temperature, humidity and positive air pressure to block outside air leaks. • Specialized Attire: Requires personnel to wear full-body garments (“bunny suits”), gloves and masks to stop human shedding
Bob Mackie's surprising cause of death is revealed
A death certificate reveals fashion icon Bob Mackie’s true cause of death, clarifying initial reports that the designer died of pneumonia.
Famous And Innovative Duke Nukem, Quake Level Designer 'Levelord' Has Died
News of Richard Gray's death was shared online by his wife
Chinatown businesses say teen fights, robberies are hurting business as crime rises
D.C. police seek two suspects after a man was robbed of designer shoes and a phone in Chinatown. Nearby workers describe recurring disturbances.
How ‘Sense and Sensibility’ costume designer used color to show a family in mourning
‘Sense and Sensibility’ costume designer Grace Snell tells EW about how she used color and fabric to depict a family in mourning — and the difference between the sisters’ personalities.
Lightsprint secures funding to enhance AI coding for non-techies
Lightsprint, a San Francisco startup, raises $6.1M to help non-engineers like designers and product managers edit code using AI tools.
Q&A: Brian Eno on relaunching Opal Records, 'Music for Airports,' AI and Palestine
Brian Eno, the multi-hyphenate artist, producer, sound designer and political activist best known for his pioneering work in ambient and electronic music, relaunches his transformative label Opal Records on Friday | KNSS Radio
Q&A: Brian Eno on relaunching Opal Records, 'Music for Airports,' AI and Palestine
Brian Eno, the multi-hyphenate artist, producer, sound designer and political activist best known for his pioneering work in ambient and electronic music, relaunches his transformative label Opal Records on Friday | KCBS All News 106.9FM and 740AM
‘Play On!’ hits all the right notes
The English Renaissance meets the Harlem Renaissance in “Play On!,” a sparkling show that marries a loose adaptation of Shakespeare's “Twelfth Night” with the music of Duke Ellington. Conceived by Sheldon Epps, who also directed the original 1996-97 production (first in San Diego, then on Broadway), the show is getting a marvelous revival under his direction to open Chicago Shakespeare Theater's 40th anniversary season.While the title “Play On!” refers to the famous quote about music being the food of love and thus to the dozens of Ellington songs—among them “It Don’t Mean a Thing,” “Don’t Get Around Much Anymore,” “I Got It Bad (And That Ain't Good),” “Solitude” and “I’m Beginning to See the Light”—incorporated into the plot, one of the highlights for me is the clever way Cheryl L. West's book reworks the story. Apparently, it's also been updated for this outing, among other things to give the women more agency. In the big opening number (there's a six-piece, horn-heavy onstage band), aspiring songwriter Vy (Hailee Kaleem Wright) is the one to “Take the 'A' Train” to “Drop Me Off in Harlem.” She wants to meet the famous Duke (Edred Utomi) — Ellington, not Orsino, that is — and she seeks the help of Jester (an engaging James Harkness) to find out how. When Jester tells her in no uncertain terms that the music industry is a man's world, she disguises herself as Vy-Man and persuades the Duke to listen to one of her songs. He's suffering from a creative block because he's pining for Lady Liv (Krystal Joy Brown), queen of the Cotton Club, and convinces Vy-Man to bring the Lady the song as if the Duke had written it, promising to reward her with employment. Vy reluctantly complies, and the predictable complications ensue. Lady Liv is attracted to Vy-Man, while Vy is attracted to the Duke and he to Vy, though it disturbs him because he thinks she's a man. The fallout when the deception comes to light bodes ill—at least for a while.Here's where West's book cannily diverges from Shakespeare. Vy's twin brother Sebastian really is dead, so West devises another love interest for Lady Liv basically by rehabilitating the Malvolio character, here named Rev (Alan H. Green), the Lady's uptight, self-important manager. His unrequited love for her is magically transformed after he gets his comeuppance (minus the torture) from Miss Mary (Alanna Lovely), her honey Sweets (James Earl Jones II) and Jester, the stand-in for Sir Toby, who has romantic problems of his own with a woman named CC (Kaylah Janssen). In other words, Rev gets the girl — and also a show-stopping yellow zoot suit from costume designer An-Lin Dauber. All the costumes are dandy, though those for the men have more pizzazz than the women's day dresses. The bilevel, slanted scenic design by Beowulf Boritt brings 1930s Harlem to life in a slightly expressionistic way with the help of Adam Honoré's lighting and Ray Nardelli's sound design. Edgar Godineaux's choreography adds to the period feel, though there could be even more of it.Most of all, the leads have splendid voices, and the performances are terrific. Green's Rev and Harkness's Jester get my vote for comedy chops, and Brown's Lady Liv probably will stay with me the longest for her complexity and big blues number, “I Ain't Got Nothin' But the Blues.”
Designers Predict These 5 Flooring Trends Will Take Over in 2027—and Bring a Fresh Look to Every Room
Before making a change to your flooring, find out what materials, colors, and styles will be trending in 2027 to give your home an updated appeal.
Mobile Trivia Launch Could Matter For AMC Stock And AMC Entertainment Holdings (AMC)
AMC Entertainment Holdings recently introduced AMC Movie Trivia Game Show, a free mobile app created with Hoyt Games and puzzle designer David L. Hoyt, offering daily movie-themed puzzles and thousands of trivia challenges across major app stores. The game links directly to AMC Stubs, turning loyalty membership into in-app bonuses that could deepen engagement with frequent moviegoers and digital audiences. We will now look at how AMC Entertainment Holdings' investment narrative interacts...
Bob Mackie’s death certificate reveals shocking new details after rep confirmed designer died of pneumonia
The fashion designer suffered a fall in the days before his death.
A New Live Business Show Wants to Be CNBC for Gen-Z. A TBPN Designer Called It a 'Shameless Ripoff'
A social-media debate erupted after a tech entrepreneur posted side-by-side comparisons of the two live business shows.
Saint Laurent ends decade-long tenure of designer Vaccarello as part of wider group revamp
Belgian designer Anthony Vaccarello is leaving Saint Laurent after a decade as the brand's creative director, the brand's owner Kering said on Friday.
Anthony Vaccarello Exits Saint Laurent After a Decade
The designer leaned into the glamour and sex appeal of the storied Parisian fashion house. Sales nearly tripled during his tenure before sliding in recent years.
Trump bucks and the politics of mailing checks
The checks started going out last week, nearly one million of them, and mostly to battleground states. With a return address for the U.S. Treasury and a letter enclosed signed by President Donald Trump, these one-time checks for $500 were ostensibly government rebates for Obamacare enrollees who overpaid. In the accompanying letter, however, Trump attacks his predecessor and talks about his record in office on an important issue he’s not polling well on, which makes it seem more like the most expensive political mailer in U.S. history. The average piece of direct mail costs between 30 cents and $3, according to Mail Processing Associates, a print, mail, and fulfillment company. At $500 a pop plus roughly 50 cents each to issue the paper check, the cost of Trump’s healthcare mailer sent to more than 950,000 enrollees comes in at more than $475 million. Trump’s midterm healthcare message “For years, the Biden Administration overcharged you to fund the operation of HealthCare dot gov,” Trump wrote in the letter. “That money belongs to hard-working Americans, not the Government, and now, I am returning it to you!” In the letter, Trump makes false and misleading claims about his administration’s record on healthcare costs, an issue Democrats have a 20 point advantage on over Republicans, according to a recent poll from KFF, a nonpartisan health policy think tank. Trump touts his administration’s TrumpRX program, which he claims is “delivering massive discounts.” However, new research from KFF found that of a selection of drugs available on the TrumpRX platform, just five were the lowest price, while 13 were the highest price. Trump also falsely claims in the letter that he’s fighting to lower healthcare costs. In reality, average monthly premium payment costs for enrollees rose 58% under Trump while marketplace sign-ups declined 5%, per KFF. Under Trump’s One Big Beautiful Bill Act, it’s estimated 10 million more Americans will be uninsured by 2034. You get a check and you get a check and you get a check Trump’s long promised cash outs to his fans, from his days as a casino operator and gameshow host to his presidency. During the early days of the COVID-19 pandemic in 2020, the first Trump administration made the unprecedented move to put Trump’s name on checks that went out under the CARES Act (notably the $500 refund checks this time around don’t feature Trump’s name). Ever since, Trump’s been chasing that high. In his second term, Trump’s promised more stimulus that never arrived, like refund checks from DOGE cuts and tariffs, while he said at his party’s convention last month that he’d give out $5,000 checks to everyone if Republicans win in November. In reality, DOGE overstated its cost cutting and Trump’s government actually now spends more than former President Joe Biden’s, while Trump’s tariffs actually grew the trade deficit. His proposal for $5,000 checks would add about $1.2 trillion to the national debt. The problem is there’s no money to give. These $500 checks — plus $90 Medicare rebate checks also going out as well as $250 deposited this week in some Trump Accounts for kids courtesy Dell Technologies CEO Michael Dell and his wife Susan — represent the closest Trump’s going to get to making good on his promise to deliver cash fast. And the checks seem especially targeted. Though the $500 checks went out to enrollees in one of 30 states that use the federal HealthCare dot gov marketplace, a Reuters review found 71% of the payments, or $339 million, went to enrollees in 13 states that have the most competitive elections for governor and U.S. Senate. Most Americans don’t buy it Could Trump bucks sway the election? An Economist-YouGov poll found 57% of U.S. adults doubt Trump will deliver on his promise for $5,000 checks, compared to 21% who do. “I’m waiting on my DOGE check and I’m still waiting on my tariff check,” one 2024 Trump voter who’s since turned on him told a recent focus group. “It felt like kind of trying to buy people’s votes, which honestly felt like in elementary when the class president was like, hey we’re going to take you to the water park if you vote for me. It’s like, I don’t think it works like that.” But for voters in swing states who got a check, it could still matter. One survey published in 2022 found receiving a physically personalized check in the mail during the pandemic was associated with a much greater self-reported likelihood of voting for Trump in 2020, and those gains mainly came from out partisans. The issue for Trump comes if these checks are mostly going to Obamacare enrollees whose premiums have gone up by more than just $500 since he took office and who view the money as something like a bribe before the election rather than an actual long-term solution to lowering household costs. Spending $500.50 per mailer would be absurd as a normal campaign expenditure, but since Trump’s checks and letter are a government rebate, his campaign and super PAC didn’t have to spend a dime and he got out his message regardless. If enough voters in key states are swayed by the one-time payment, it could prove to be the best $0 the Trump campaign spent. Subscribe [ ](https://www.yellopolitics.com/p/why-independent-candidates-are-making) [ Why independent candidates are making independence central to their brand ](https://www.yellopolitics.com/p/why-independent-candidates-are-making) Hunter Schwarz · Oct 6 [ Read full story ](https://www.yellopolitics.com/p/why-independent-candidates-are-making) [ ](https://www.yellopolitics.com/p/these-designers-and-grocery-nerds) [ These designers and grocery nerds will brand Mamdani’s NYC grocery stores ](https://www.yellopolitics.com/p/these-designers-and-grocery-nerds) Hunter Schwarz · Oct 2 [ Read full story ](https://www.yellopolitics.com/p/these-designers-and-grocery-nerds) Trump wants to turn his first-ever golf course into a government course for presidents
'Home of the Future' at LACMA explores dark side of American dream
Across six decades, designers and corporations sold the home as a route to health, freedom and security. The exhibition raises the harder question of who paid for that dream.
HPMA sets Saturday entertainment lineup, plus return of Market-at-Market
The High Point Market Authority (HPMA) has planned its evening entertainment lineup for Saturday, Oct. 17, along with the return of its signature “Market-at-Market.”
Behind the Seams | Wildwood
Go behind the scenes at LAIKA Studios for an up-close look at the extraordinary costumes of ‘Wildwood,’ the studio’s most intricately designed stop-motion film yet. Nearly 20 years after ‘Coraline,’ LAIKA’s artists and designers reveal how every tiny stitch, button and layer of fabric is handcrafted and engineered to help bring its puppets to life, combining costume design, fabrication and animation at an astonishing scale.
The Science Behind Female-Specific Firefighting PPE
Camilla Callesen, chief designer at VIKING Fire & Rescue, and retired firefighter Kendall Taylor discuss the research, engineering, and field testing behind the VIKING VALKYRIE.
Solo law firm owner shares advice on running your own business
It offers general legal services but also has niches in representing other attorneys as well as designers, artists and publishers in the board gaming industry.
TCL’s new ‘Designer’ Google TVs are just like Samsung’s The Frame, starting at $899
TCL has launched a new “Designer Series” of TV sets running Google TV with a flush mount design and matte...
Stanley Parable Co-Designer Perfectly Explains Why People Play 1,600 Hours Of Dota 2 And Still Hate It
This is exactly how I've felt
L. Ruth Interior Design celebrating 18 years in business with community event
Laura Ruth Edge said she had dreamed of becoming an interior designer since she was young.
Armani’s business and creative evolution on show in Milan a year after founder’s death
MILAN (AP) — The future of Giorgio Armani ’s empire is coming into sharper focus a year after the designer’s death. On the runway in Milan, his signature elegan
Armani’s business and creative evolution on show in Milan a year after founder’s death
Giorgio Armani’s empire is taking shape a year after the designer’s death.
Armani's business and creative evolution on show in Milan a year after founder's death
Giorgio Armani’s empire is taking shape a year after the designer’s death. His latest collection, previewed Sunday, showcases his signature elegance. Behind the scenes, discussions are starting...
Armani's business and creative evolution on show in Milan a year after founder's death
Giorgio Armani’s empire is taking shape a year after the designer’s death. His latest collection, previewed Sunday, showcases his signature elegance. Behind the scenes, discussions are starting...
Armani's business and creative evolution on show in Milan a year after founder's death
Giorgio Armani’s empire is taking shape a year after the designer’s death
Armani's business and creative evolution on show in Milan a year after founder's death
The future of Giorgio Armani ’s empire is coming into sharper focus a year after the designer’s death. On the runway in Milan, his signature elegance defined the latest collection previewed on Sunday...
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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The Nova Games Foundation is a new philanthropic initiative aimed at supporting the next generation of game makers
Exclusive: Two of gaming’s biggest names are making a big investment in gaming’s future
The first thing to know about the Nova Games Foundation is that it isn’t about The Game Awards. And it’s not about PlayStation. The ambitious new grant program is the brainchild of Geoff Keighley and Mark Cerny. Keighley is the host of The Game Awards, Summer Game Fest and Opening Night Live. Cerny is a game designer of some 45 years and the lead architect for the PlayStation 4 and 5. But this new thing, which they’re revealing through Game File, isn’t about their day jobs. It’s an unaffiliated, standalone philanthropic project. It’s a bet on the artistic future of video games and a way, they tell me, to give back. “I’m nearing the end of my career,” Cerny recently told me over email. “I’m not done yet, but paying it forward—in the best way possible—is very much on my mind these days,” The Nova Games Foundation is a university-affiliated fellowship program, intended to offer six-figure grants to 20 young game designers each year, potentially for decades to come. It will offer no-strings-attached funding along with mentorship from games industry leaders, a combination intended to aid the development of groundbreaking new games, Cerny and Keighley told me. Nova will begin accepting applications in December, from class of 2026 and 2027 students from 13 affiliated gaming programs at universities in eight countries. The schools working with Nova include the New York University and the University of Southern California in the U.S., along with Abertay University in Scotland, Cnam-Enjmin in France, TH Köln in Germany, and the Royal Melbourne Institute of Technology in Australia, Cerny and Keighley said. The plan: $100,000 per recipient, with about a quarter of Nova fellows eligible for up to $500,000 more for projects that are shaping up particularly well. Payments will be delivered based on development milestones, and recipients will own their games. Nova will help promote the work, and developers will be free to pursue the publishers and platforms of their choice. Nova can help introduce fellows to publishers, but won’t take a cut. “I’ve always wanted to give back, but given my role in the industry, I’ve never felt it appropriate to commercially invest in games,” Keighley told Game File. “I’ve never owned stock in a game company or taken a financial stake in a game. Nova is philanthropy: we aren’t taking equity or looking to recoup the grants. The return we’re hoping for is creative—helping new voices make games and find their footing. “Mark and I have each made multi-million-dollar donations to establish the foundation, and we intend to keep contributing. We hope others will join us.” Cerny and Keighley have already hired an executive director, John Maconga, and a head of grants, recent Game Developers Conference director Ashley Corrigan, to help launch the effort. They’re working to recruit game industry leaders to join the effort. Keighley says “dozens of leading game directors have already expressed interest in contributing their time.” To name one, they’ve already gotten Josef Fares, lead designer from It Takes Two and Spit Fiction studio Hazelight on board with a donation and pledge to help out. “I’m proud to support Nova because it gives the next generation of creators the freedom to explore their creativity and hopefully bring their unique visions to life,” Fares told Game File. A plan forged from a friendship Keighley and Cerny have known each other a long time. It’s been so long, Cerny isn’t even sure exactly when they met. “We travel in much the same circles and I’m sure first intersected in the 90s or early 2000s,“ Cerny said. Keighley thinks it might have been during his stint writing a column about the mid-’90s console 3DO for a gaming magazine while Cerny was working on games with Crystal Dynamics or on Way of the Warrior with Naughty Dog. They became genuine friends about a 10 years ago, Keighley said, as they bonded over a shared love of games and a hope to improve the industry. “About a decade ago, we started having dinner a few times a year in LA,” Keighley said. “Just to catch up on life and the industry. Those conversations continued over Zoom during COVID. Nova grew out of that friendship and a question we kept coming back to: ‘What could we do to help the next generation of game directors get started?’” Keighley credits Cerny with the idea to figure out a way to put their money and time back into the industry. At one of those dinners, Keighley proposed the idea of a fellowship program. He’d recalled applying for a Rhodes Scholarship when he was younger. “Spoiler: I didn’t get it,” he said. He’d admired the MacArthur Foundation’s so-called “genius grants.” He liked these kinds of programs that recognized people’s talents and gave them the financial boost and the freedom to realize their potential. With Cerny, he had pondered what a game industry version of that could be. Keighley liked the idea of centering the fellowship on students, drawing inspiration from the accomplishments of Jenova Chen, the USC game design graduate who went on to lead the creation of gently moving, ambitious games such as Flower and Journey. Keighley also thought it could be useful to help promising graduates bridge the transition from student to professional. “Joining an established studio isn’t always possible—especially in today’s market—and even then, it isn’t the right path for everyone,” Keighley said. A fellowship, he realized, could give “graduates the time, resources and guidance to pursue a game of their own and not worry about the commercial viability.” As the idea took shape, Cerny also saw an opportunity to enable more games of a certain type: “The target with the grants is games as an artistic medium,” Cerny told me. “We like to say games with ‘artistic, literary and societal value.’” He added: “I’m a pretty big gamer myself, though I tend to gravitate towards the smaller and more unique or artistic titles, games like Neva, Abzu, Gorogoa, Stray or Outer Wilds. I was just playing and Roger on a flight to Japan, and was getting misty eyed to a degree that I was concerned that a flight attendant would ask me if I was OK. “So one fun benefit here is the games that will come out of the Nova Games Foundation – I can’t wait to play them myself.” Cerny believes it will also be useful for Nova fellows to hone their craft and team leadership skills. “We are looking for the next generation of visionaries,” he said. “The trick is that they will also need to have the executive function necessary to drive a small project to completion.” Game File is a reader-supported publication. To receive new posts and support my reporting, please consider becoming a free or paid subscriber. Subscribe Going big with this Keighley and Cerny may have started Nova and may be the ones primarily backing it right now, but they’re dreaming of something that goes beyond them. “Mark and I may have helped get it started, but one of our measures of success is that Nova grows into something the entire games industry feels a sense of ownership in,” Keighley said. “Our ambition is to build a lasting endowment supported by people and companies across the industry, and an equally broad community of creators willing to give their time and experience to the next generation.” The industry has a lot of knowledge that it can pass to the next generation, Keighley said: “Nova can hopefully become a way to connect that generosity with talented young creators at the moment when it can make the biggest difference.” Cerny, who told me he believes Nova can mature “over the next 10 or 20 years,” sees an opportunity to give generations of game makers momentum. “The industry has changed immeasurably since I started in games in 1982,” he said. “These graduates have talent, training and tools that outclass what we had back in the day by an astonishing amount. But they face a tough road ahead getting traction in the industry, and many could benefit from our support. We want to be there to give it to them.” “There’s a personal side to this, too,” Keighley said. “I don’t have children, and I’ve spent a lot of time thinking about what I can do for future generations. Games have been my entire career. I’ve been incredibly fortunate, and helping someone else build a life in this industry feels like a meaningful way to give back.” Cerny’s oeuvre dates back to Marble Madness and Sonic the Hedgehog 2. He has stood on stage multiple times to reveal the future of PlayStation hardware. He’s been an executive producer for a string of modern PlayStation classics such as The Last Guardian and Marvel’s Spider-Man. Nevertheless, of Nova, he said, “It’s certainly not like anything I’ve done before.” Nova Foundation applications will be due in December and the first wave of fellows will be announced in March 2027. A full list of participating universities and steps students and recent graduates can take to apply to become a Nova Fellow is forthcoming.
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