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Auburn football's latest bowl projections following upset win over UGA
How much did Auburn football's postseason trajectory change following its win over Georgia?
Oral Health Disparities and Parental/Caregiver Role in Dental Care Among Children With Special Healthcare Needs and Children Without Special Healthcare Needs in Sriganganagar, Rajasthan: A Cross-Sectional Study
Background: Children with special needs often face greater challenges in maintaining oral health due to physical, intellectual, or behavioral limitations. Their oral hygiene depends largely on c...
Changing shape of healthcare careers: Medical AI, Bioinformatics and Health Data Science
Changing shape of healthcare careers: Medical AI, Bioinformatics and Health Data Science
Tracking tsunamis triggered by extreme weather
As much of Western Europe faced record-breaking temperatures and extended drought this summer, Croatia experienced another weather event that could also set a worrisome precedent.Over the course of two weeks, a series of meteorological tsunamis (meteotsunamis) struck Croatia’s Adriatic coast, alarming both residents and tourists. Social media posts showed flooded seaside promenades and people walking through knee-deep water. Fortunately, no deaths or major damage were reported.In a world where natural disasters seem to be increasing, meteotsunamis — tsunamis caused by rapid weather changes – rarely make headline news. But warming sea temperatures and changing atmospheric conditions may help explain why these phenomena could become more common, especially in shallower seas and inland lakes with wide coastal shelves.“We have definitely become more aware of them, and there have been a lot more reports of these events in the last 10 years,” says Jadranka Šepić, an associate professor of environmental physics at the University of Split whose research focuses on efforts to track meteotsunamis in real time. She is also one of Croatia’s ambassadors for Science Comes to Town (SCTT), a European Commission-funded programme aimed at making research more accessible to the public.Šepić sees two possible reasons for the apparent increase in meteotsunamis. One is that photos and videos shared on social media are providing more empirical evidence, while rising air and sea temperatures could also play a role. The geophysicist “cannot say with certainty” that warming is a contributing factor because research is still ongoing. “But I can say that previously in Croatia we might have had one exceptionally strong event every 10 or 15 years, and one strong event every five years, and within 15 days this summer we had five strong events,” Šepić notes. “This is not typical.”‘A fist against the sea surface’Unlike tsunamis that are triggered by underwater earthquakes or volcanoes, meteotsunamis are caused by sudden changes in atmospheric pressure combined with other rapidly developing weather events, such as thunderstorms. The effect “is like pushing a fist against the sea surface,” Šepić explains. The resulting oscillation intensifies as it reaches shallower water, and “can be far more destructive than a wind-driven wave because meteotsunamis are accompanied by very strong currents than can penetrate much deeper inland.” The meteotsunami, she continues, “then behaves the same as a tsunami — they slow down and grow as the sea shallows, and then grow further in places like harbours due to further shallowing and narrowing. When they come ashore, they can be very destructive — taking everything with them out to sea and then taking it back.”Croatian research institutions have tracked such sea oscillations since the 1930s because the relatively shallow Adriatic Sea is prone to meteotsunamis. The strongest recorded so far was in June 1978, according to the Adriatic Meteotsunami Catalogue, which is supported by the European Research Council (ERC), Croatian Science Foundation and the country’s leading research institutions. During that event, six-metre-high waves flooded the coastal town of Vela Luka on Korčula Island, causing major damage.Other meteotsunami “hotspots” in Europe include the Mediterranean Sea as well the Atlantic coastal shelves off France, Portugal and Spain. In June 2006, a meteotsunami with five-metre-high waves swept through the harbour of Ciutadella in Spain’s Balearic Islands, causing widespread damage to boats. Several less powerful events were reported in the Balearics and off the coast of Spain this summer, leading to some beach closures.Forecasting is challenging because of how quickly meteotsunamis can develop and their uncertain trajectory. Šepić is involved in two ERC-funded research projects — SHExtreme and MeD-Track — aimed in part at strengthening monitoring and real-time data collection. Access to accurate and immediate information is essential for early-warning systems.Early exposure to meteotsunamisŠepić first learned about meteotsunamis from her parents while growing up in Croatia. She later had the opportunity to investigate these events during her master and doctoral studies in geophysics at the University of Zagreb. The geophysicist has also conducted research at the Institute of Oceanography and Fisheries in Split, the University of the Balearic Islands in Palma de Mallorca and the Institute of Ocean Science in the Canadian province of British Columbia.Projects like SCTT are important to raise awareness about research and inspiring young people to pursue studies and careers in science, notes Šepić. She credits her colleagues at the University of Split and the Institute of Oceanography and Fisheries for their community outreach and engagement in the European project, which includes partner universities and institutions in Brest (France) and Kiel (Germany). As an example of town-gown collaboration, Šepić highlights her own university’s ‘Oceanographers on the Island’ programme. This initiative offers workshops and hands-on learning for children living on numerous Croatian islands.“It is a great privilege for Split to be involved in a project like Science Comes to Town, which is the first of its kind in the European Union," Šepić says. As for encouraging new generations of scientists, “This is a great effort, and I hope that we will see an effect in a few years.”Science|Business, which connects policymakers, academics and industry through its news reporting, analysis and events, is an SCTT partner.
How knocking on doors can help beat measles
“As measles outbreaks spread in the U.S., it may be time to learn how other countries get their outbreaks under control,” writes Raj Panjabi.
Sundar Pichai: Google’s Frontier Imperative, Compute Scarcity Dilemmas, Future AI Products and Businesses
Alphabet CEO Sundar Pichai has little patience for doubts about Google’s willingness or capacity to compete at the frontier of AI. His company’s latest Gemini 4 Argon model — long-promised and recently delivered — beats OpenAI and Anthropic’s latest public models on coding, math, science, and knowledge-work benchmarks and has placed Google’s AI back among the world’s best. Amid chatter that Google was fine with good-enough lightweight ‘Flash’ models, Pichai pushed back hard against any suggestion that company is limiting its research ambitions. “We won’t do it any other way,” he told me in a Big Technology Podcast interview recorded this week at Google’s Mountain View headquarters. Pursuing cutting-edge research is costly for Google, requiring compute and chips that otherwise could be sold at a high markup by its cloud business. But Pichai said allocating resources to frontier AI development is “ground zero” for Google. “Our cloud business is at any given moment in time forgoing short-term revenues because we are making compute trade-offs to support frontier AI development,” Pichai told me. In our conversation, we discussed Argon (which Pichai says processed three times as many tokens as Gemini 3 in the 72 hours after launch), AI’s role in developing better models, the AI interface of the future, competition with OpenAI, Google’s partnerships with Anthropic and Apple, data centers in space, and the nature of his optimism. You can read the full conversation, lightly edited for length and clarity, below, or listen to it on Apple Podcasts, Spotify, YouTube, or your podcast app of choice. Alex Kantrowitz: Google is back at the frontier with Gemini 4 Argon, which beats OpenAI’s and Anthropic’s public models on benchmarks spanning coding, math, science, and knowledge work. The conventional wisdom was that Google had given up on the frontier to focus on fast, good-enough models for its products. That was wrong? Sundar Pichai: Very wrong. Look, we are so committed to being at the frontier. It’s in our DNA. We won’t do it any other way. We’ve been thinking about the AI frontier for well over a decade now. The frontier is very dynamic. It’s very competitive. It’s very exciting. I couldn’t be more pleased with how Argon has come together. We took our time with it. We made sure we tested it safely and deployed it carefully. We took a bit longer than our other models, given its capabilities. Across the board, be it for agentic work, knowledge work, coding, creative tasks, Argon is one of the really good frontier models. The first 72 hours since we launched, it’s almost up to 25 trillion tokens used, which is about three times what Gemini 3.0 had in the first 72 hours. And we are capacity constrained as we are serving it. Excited, but there are always areas….. You know, the frontier is very dynamic, and you have to keep evolving the models. There are areas which we can see we need to improve as well. We’ll be at work on all of that as well. Which areas? On any given model, Argon would be across the board better at everything if you just look even two months back. But the space is so evolving. Even on coding, for example, there are pockets where we know we need to do better, and there’s clear feedback. We’ll make it better. The argument for standard models is that they’re already good enough to build great products, with the frontier valuable only for certain tasks. Meta built Muse with good models rather than the best, and Google could put standard models into Maps, Gmail, and Search. Why isn’t that sufficient? It’s definitely not how I have thought about it at all. We are deeply committed to driving the state of the art and actually pushing where this technology can go, all the way from transformers. That’s a journey we’ve been on. You will see us continue to do that. When you’re at the frontier, you get an earlier look into the emerging capabilities, earlier than others, which helps you better prepare for the future. We are fortunate to have a wide set of opportunities across consumer and enterprise. Some of our cloud customers, for sure, want the model at the frontier. The frontier models will be better at developing the next set of models in an era of recursive self-improvement. I would argue it matters there. Internally, we have definitely seen a steep point of inflection by deploying Argon to our developers. It definitely tackles problems which our previous models could not do. Being at the frontier puts you at the innovation frontier and helps you drive that as well. There is room for models of all sizes and capabilities. That’s why we did Flash, Flash-Lite, etc. I agree with you that you can develop very good product experiences with not necessarily the most frontier model, because they tend to be slower and more expensive too. But we care about the Pareto frontier, and we’re committed to doing all of that. You said developing frontier models gives you a look at what’s coming. What do you see on the horizon? What makes this moment so exciting is you build something which you think is a culmination of months of work, and you put it out. You already see clear headroom ahead. We’ve all been working on these agentic, long-horizon capabilities, but clearly the frontier is going to have multiple of these agents working together to do things. That’s an example of an exciting paradigm underway. It’s also clear to me that users, both in consumer and enterprise, will have access to some multi-agent framework for them, working all the time doing things. It feels like a moment of infinite possibilities. Sergey Brin said one of Argon’s core innovations was relying more on the model to help develop the model. Yet incidents involving OpenAI’s bots breaking containment and Google’s bots accessing a site they shouldn’t have suggest these systems still aren’t perfectly aligned. Isn’t there reasonable cause for concern about accelerating toward recursive self-improvement? There are three parts to your question. Let’s first talk about RSI itself. You’re right, Sergey mentioned RSI being a critical contributor as we are developing Argon. But to be very clear, today, in a continuum, we are pretty far from the end state of RSI or something like that. The right way to describe it is you have RSI loops along with AI researchers in various aspects of model development. You almost have agents helping AI researchers in some automated way work together to build these models. It’s good to at least understand where we are today, and it’s super exciting. I expect that continuum to keep making progress as we go into next year. The second question is around safety. Security comes from defense in depth. You’re talking about alignment, obviously. We all are doing a lot of work to make sure the models are as aligned as possible. But it’s an active area of research, and there are clear gaps. That’s not the only thing we rely on. You have the work you do on alignment, but beyond that, we put a lot of effort into real-time monitoring as these models are working. Making sure you have good telemetry into what’s happening so that you can intervene in real time if you see unexpected behaviors. How you do that, the architecture with which you do that, how you make sure it’s all sandboxed and isolated in a way that it can continue doing its job during real-time monitoring — these are all areas of investment. Obviously, when we deploy these models, giving customers, enterprises, control, both with real-time monitoring, but their ability to decide where they deploy, what type of data which models ever have access to, etc. All that work is very, very important, and we are doing a lot of that. As an industry, we need to constantly up our game and take the time to do all this stuff, including dedicating the compute required to make sure you can safely deploy these models. The third part is: Is it all enough? This is why there are a lot of conversations in the industry, and I think it’s reasonable to be worried. The right way to approach something you worry about is early on thinking about what more we can do. As an industry, you’re definitely seeing increased levels of work on alignment, testing for safety, etc., as we deploy these models. The next step would be developing better standards so there are cross-industry standards of how we do these things, including the ability to evaluate using independent evaluators. If you look at areas like financial controls, we have accounting standards, we have independent auditors. Those are all the next natural steps for us as an industry to work toward, and regulation will end up playing a role as we go through all of that as well. Google pursues both language models and world models, while some other AI companies like OpenAI have focused more heavily on LLMs as the path to AGI. Why is world-model research important to you? As humans, you obviously perceive the world around you, and you’re taking all those inputs. Making sure these models are able to understand the laws of physics, simulate the world in high fidelity. All that, I think, are key enabling blocks for intelligence. We are working across all possible applications of this. Take an area like robotics. It’s not an accident: If you look at embodied reasoning benchmarks, Argon is state of the art. That all comes from our experience building world models. Inherently, I would expect there will be architectures which will converge all of this in the future. But for us, we view this as, today, this jagged frontier that is intelligence. We want to be at the frontier of all the possible approaches, and that will help us both drive better research, better insights, and develop a much better AGI model, is how we think about it. Some people argue Google should focus on selling its computing resources rather than using them for AI research. Cloud wants to sell compute at a high markup, while researchers need a very big computer to build the best models. How do you balance those demands? Ground zero for us is making sure we are investing in the compute that’s needed to be at the AI frontier. In 2015, I set the company to be AI-first. AI is that key horizontal ingredient across everything we do, all the way from Search to Cloud to Waymo. That is ground zero for us, making sure both for research and developing the models that we have enough compute needed. Beyond that, we have these independent businesses which each have their own long-range plans. They’re using those long-range plans to project forward, and we plan for compute for all of them. The cloud team, they have a business and they have a projection and they have demand signals. They have committed contracts. With that help, we can plan on a long-term compute trajectory for them. We’re fortunate to have this wide set of opportunities. There’s no company in the world which isn’t making trade-offs at any given moment in time. But the first principles we operate on is making sure we have enough compute to invest in the frontier, and that’s non-negotiable, and everything else works on top. Remember, we are building our own compute, our own data centers. There are long lead times. The compute we have today is a function of decisions I made in 2024. Even if you think back to a year from today, last year the agentic coding takeoff hadn’t happened. Today, obviously, when you sit and look at anything, everyone is short—not just us, other companies—and everyone wishes you had two times what you had planned for. That comes with the territory. At any given moment in time, we are planning for what we would need two to three years out in the future. You’re going to find some decisions you make may look suboptimal two years out, depending on where the state of the art is. I don’t spend too much time thinking about it. The way I think about compute allocation is making sure Google DeepMind, both for research and frontier model development, is cutting edge in terms of compute access. After that, we plan for all our businesses. It’s great we can provide our compute to other people too, like we have done. It allows us to scale that up, get real tests for it in the widest application set possible, test it in the real world, and make sure we are at the cutting edge of technology at every layer of our AI stack as well. Ben Horowitz relayed on a podcast that Andy Jassy had said compute was sold out until 2028. Are you seeing the same thing? If today a customer is coming out and asking us for compute in ’27, that is incredibly difficult to do. Even last year we went out and leased some short-term compute to accommodate some customers and help them out. But yes, we are all dealing with similar timelines. Every major technology shift seems to involve overbuilding, from railroads to fiber. Do you think that’s happening here? It depends on the time frames you’re looking at. This level of build, if I take a long enough time frame, it makes complete sense to me. We are at early stages of the most consequential technology ever, and this is not like fiber. It’s not dark. We are using it. We are capacity constrained on a daily basis. The applications, the underlying technology is improving rapidly. But running a company, the way I work through the moment is you look at your demand signals. You look at your committed revenue opportunities that you’re getting in the form of contracts. You balance that with the underlying technical capability, or internally you balance how we are using it internally, the model trajectories. Based on all that, you take a disciplined approach—a confident, aggressive, but disciplined approach—to plan out compute. But when you talk about the broader economy as a whole, you’re having people operate with various levels of risk. I focus on what I can control as a company and plan through it. If your question is, can there be an overbuild? Yes, because you can have some constrained components. Remember, what matters is a set of everything you need to build out that compute. Memory, electricity, electricians…. Land. Like 2,000 components or more. You could get constrained at some point. There could be things which cause bottlenecks, and then you could have overbuilds. There could be external shocks to the economy. There are macro risks. All that is possible at any given time. But am I confident that the compute we are planning for, we will have uses for it given enough time? Absolutely, yes. I was in the room when you said AI would be as profound as fire and electricity. If you believe that, shouldn’t you give researchers the biggest possible computer, even at the expense of today’s cloud profits? We’re all doing some form of that. Our cloud business is at any given moment in time forgoing short-term revenues because we are making compute trade-offs to support frontier AI development. What you’re seeing is true already. But you want to be thoughtful. Even our AI researchers have some constraints, which are also good. That’s what inspires creativity. That’s what helps you come up with a more efficient algorithmic breakthrough, maybe to use less memory. What we are committed to is to invest what’s needed to stay at the frontier. OpenAI President Greg Brockman told me a few months ago that the ideal AI product might have no interface at all—just as natural as conversation. What do you think the interface looks like in the age of AI? Computing historically has been humans adapting to computing. With AI, it’ll be the other way around. The technology will adapt seamlessly to how humans live and go about their day-to-day life. You want to be able to speak to that AI when you want to. It has context. It can be persistently running somewhere, give you continuity. You’re not dealing with a lot of complexity. It’s natural. All that makes sense to me. That doesn’t mean it won’t have any interface, however. Nowadays, even on my phone, Gemini voice models are so good. I can just press the microphone button. I can just ramble. That’s why we call it Rambler. I can ramble. It intelligently corrects with my personal context. Even my friends’ names, weird names, it gets it right, even if it first guesses it wrong. It’s amazing. I’m not going in, backspacing, editing once I finish saying it. It’s remarkable how good it’s gotten. But there are going to be moments you will need an interface. You may want to entertain yourself. You may want to watch a video. You may ask your AI to create something, and you want to watch it, consume it. The way I think about it is, you want it to be as seamless and as natural as possible, and that you are not doing the hard work adapting to whatever the interface is. The technology is adapting to how you’re working at any given moment in time. When I asked Sam Altman about competition from Google, he argued that OpenAI was building AI-native products and implied Google was bolting AI onto existing ones. Do you accept that framing, and can a “bolt-on” compete with an AI-native product? First of all, it’s a very dynamic moment. We are all pushing each other. OpenAI has pushed us as a company too. This is not just we are doing something to them. Far from it. Yes, Google went into its own version of a code red too. In the AI moment, all of us have to respond with varying levels of urgency at any given moment in time. We are constantly building new products as well. Gemini was built from the ground up as a product—the Gemini app I’m talking about. Or tomorrow, as all of us are adapting to agents, are you bolting agents onto ChatGPT, or are they building it natively? How would you think about that? You can always put these questions back. I don’t think of it that way. I think of it as you want to build world-class product experiences that are AI-native and they are winning. Some of it is adapting products, some of it is rethinking new experiences. They will all be part of how you approach this moment. How do you expect to make money from these AI interfaces? If an agent recommends a product and I buy it, should it take a cut of the sale, even if that’s disclosed? I’m going to put enterprise aside. Consumers are going to increasingly value this technology. Take software developers today. Developers are willing to pay for these coding models because it really helps make them more productive. Nobody would want to code the way they were coding three years ago, or even the same time last year. When you’re delivering value, there’s value to be had. I’ve never seen examples where consumer products really scale to billions of users, where people are using it intensely, and haven’t had monetization to go along with it. If you’re providing value to people, there is inherent value to be had. The nature of it may change. You’re asking a scenario in which agents are doing stuff for you. At the end of the day, you will have commercial needs. The agents need to fulfill those commercial needs. The providers on the other side are going to see value in that. There’s going to be some mechanism by which it gets fleshed out. That’s what an efficient system does. But what matters is that you’re building those world-class consumer experiences. I promised myself one product feature request: Can you make Gemini-powered search in Gmail as good as searching Gmail through ChatGPT? What’s going on here? One of the exciting things we announced recently is the unified Gemini agent for enterprise, and we’re bringing that to consumers. These are persistent agents which run 24/7 in the cloud. We’re spinning up a micro VM effectively for every query, and from the runtime, the harness, the model—it’s all a headless service. It’ll work everywhere, and it has your context with you. You can address this agent whether you’re in Workspace, in Search, in Gemini. Agents are going to drive this unification from a customer experience, which people are looking for. When you have a broad product portfolio and you’re moving forward fast, there are always areas where you’re moving forward faster than some other areas. That’s valid feedback. But we are putting a lot of time and effort into making sure, as we build out our agentic experience, that unification and that capability works well across all these services. People have asked where Google’s equivalent of Muse or Dots is. Do you anticipate creating a new product to compete with them? Our goal with Gemini is to be a personal, proactive, and powerful assistant. That’s what we are working toward. You saw us describe the early versions of it at Google I/O this year with Spark. Effectively, already, if you open the Gemini app as a Pro or an Ultra user, you see Chat and Task, and they start giving you that agentic experience. With Argon now, that capability is dramatically accelerated. What we announced recently in our enterprise event, we are bringing that to consumers as well. Soon in Gemini, you will be able to ask something, and it’s a continuum. You don’t need to think about whether you’re asking a chat or an agentic task. It’ll just automatically do the right thing, and it can work persistently in the background securely and get things done for you. Already, empirically, when I look at what’s coming into Gemini in our app, last year you would have tagged them and most of them would have been chats. But a steadily growing percentage is already agentic tasks in Gemini. Yes, we are going to bring personal agents to our consumers. It’ll work in the Gemini app. It’ll work in Google Search. It’ll work in Gmail. You can address it, call it, etc. We want to make sure we’re getting it right. It’ll be powered by Argon, and we are very excited to bring it to our users. Google has invested and committed tens of billions of dollars to Anthropic. What do you see in Dario Amodei that makes you want such a deep investment and partnership? Very early on, when we looked at the founding team of Anthropic, it was very clear to us this was a world-class team which was involved in some of the earliest GPT models. We were quickly able to assess that they would be at the frontier. We’ve always tried to identify and partner with companies which would be at the cutting edge of technology. We’ve done that with SpaceX. We’ve done that with Anthropic. That’s what we saw, and we had a chance to partner. Is your partnership with Apple to license Gemini for Siri expanding, contracting, or standing still? For both us and Apple, that partnership was about translating the capabilities of AI into better experiences for users. I thought Apple has done a phenomenal job of incorporating—they customize these models and build it into Siri—and it’s been great to see the reception. We are committed to doing more. You’re going to do more with them? There’s nothing specific to comment, but it’s a partnership. It’s working well. What have you learned so far about the feasibility of data centers in space? It’s a very exciting project. Projects like this remind me—I still recall that moment in the desert for the DARPA Grand Challenge, watching the Stanley car compete in it, which ended up being the basis for Waymo. With all these technologies, you’re at a moment in time where it looks a bit like sci-fi, but 10 to 20 years down the line, it’s actually working in a meaningful way. I feel the same in space. We’ve always believed in betting big on these technologies. Quantum has been a great example of it. We’re probably 10 years into the journey. Waymo, we are almost 20 years into the journey. Space, we are two to three years into the journey. It’s clear to me that it’s an approach which will make a lot of sense in the future. Being in sub-synchronous orbits with 24/7 access to the most abundant form of energy we have access to will make a lot of sense for this exponential increase in compute that we are going to need. Having said that, this is a challenging project. The team has disciplined milestones. It was a super exciting milestone to send the TPUs up to space. Sometime, as we are speaking, we are expecting a “hello world” moment from them. I look forward to seeing that happen, and we’ll continue investing here too. You previously said 25% of the code written within Google was written by AI. What’s the number today? That number in our world today is meaningless in the sense that every part of what we now touch is influenced by AI deeply. What we are tracking with Argon, for example, it’s been a point of inflection. People are using Argon to really go tackle complex projects, including projects which affect millions of lines of code. In the four weeks since we have launched Argon, we have seen a 30% increase in CLs, and more importantly, almost a similar increase—a one-third decrease in rollbacks. People are writing code more productively and better code with it. We are tracking it with newer metrics now. How are you dealing with opposition to data centers? If you can’t build in the U.S. the way you want to, where else do you go? We’re very committed to building our data centers very responsibly. When I look at our largest data centers in some of the communities where we have been the longest, I visit them, I talk to people. There are people who come and tell us their kids have gone to college because of our investments in these communities, and we’ve grown in those communities. To me, this is about doing it right. Engaging with the communities early, doing it transparently. We are committed to making sure we are bringing incremental power, and we cover 100% of the cost of our power needs for these projects. It’s understanding the impact on neighborhoods and making sure you’re working thoroughly to address them. Done rightly, you can continue making progress. But we are constantly taking feedback into account. I do worry not everyone operates the same way. People have been surprised by data centers showing up in their backyard. Those are all important. As an industry, we should continue to do better. But part of the reason, in a 20-year time frame, we are thinking about things like data centers in space is making sure we are able to put these data centers where maybe the trade-offs will be different. What unproven area of AI is Google working hardest to crack? Is it continual learning—getting models to keep updating after release—or something else? There are multiple parallel paths. You saw with Argon we have a million output tokens. With our Gemini models early on, we had a one-million context window on the input side. These are all examples of breakthroughs we are constantly working on. How do you think about synthetic data? How do you think about continual learning? How do you think about more efficient architectures? We do dedicate a meaningful percentage of our compute to these research bets too. It always goes hand in hand, including our world models. Those are all bets we are placing. Sometimes, as part of these bets, there are ideas that emerge which just make their way into the mainline models. Maybe we don’t fully talk about it, but we have multiple steps in these areas. Working in technology requires optimism that building something will improve the world, but those bets can leave real consequences when they fail. I recently returned to a town in El Salvador where enthusiasm for Bitcoin had given way to unfinished construction and something resembling a ghost town. How do you maintain the optimism you spoke about in your Stanford commencement address while accounting for those risks? I genuinely have a deep conviction that improving technology and improving access to technology makes people’s lives better. It’s been my personal experience in my life, out of which comes that deep conviction, optimism. But with that, I’ve always felt humanity’s journey is always about working hard to harness that technology to make it work well for society. The optimism is not an optimism that you just build whatever you want, whenever. You work hard to make sure you’re building technology in the service of humanity, to make the human condition better. That’s got to be the defining goal as we are approaching it. With that framework, I’m very, very optimistic. We are in very early stages of the kind of progress that we are going to see on many areas. We’re all talking about areas like healthcare. A lot of the progress is ahead. The ability to make things in a fundamentally cheaper way on many things where things have been getting expensive for a long, long time, discovering new materials, etc., which really bend the curve—it’s tough to step today and understand the impact of all that, but they’re going to be very profound. I’m very optimistic, but we have to be rightfully concerned about all the ways this technology can go wrong. Sundar, I know you don’t do many of these. Thank you. Thanks, Alex. Appreciate it.
NBAA-BACE Flight Deck Launches Bizav Expert Sessions
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Science Applications International (SAIC) Could Be 12% Overvalued On CFO And Leadership Changes
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Mike Rogers discusses contentious Senate race at Detroit business luncheon
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Debt service and the Pentagon. Private equity and the politics of the US housing market. The return of black lung disease & the Franco-Prussian War in color.
Thank you for opening your Chartbook email. RALPH BALSON. 1890—1964. Oil and enamel, signed. Source: Gavekal This going to hurt - the two 7s in the US: diesel and mortgage rates Source: Gavekal In the US housing market, costs are soaring and the role of corporate, private equity-backed buyers is high on the mid-term election agenda. HEY READERS, THANK YOU for opening the Chartbook email. I hope it brightens your day. I enjoy putting out the newsletter, but tbh, what keeps this flow going is the generosity of those readers who clicked the subscription button. If you are persuaded to click, please consider the annual subscription of $60. It is both better value for you and a much better deal for me, as it involves only one credit card charge. Why feed the payments companies if we don’t have to. Subscribe It is striking how, since 2020, big banks have dropped out of the political spotlight in the US. For contributing subscribers only. Subscribe Rates of the lung disease pneumoconiosis among working US coal miners have risen to levels not seen in nearly 40 years Source: Bloomberg Chinese Clean Technology Exports For contributing subscribers only. Subscribe Ralph Balson (1939) Portrait of Grace Crowley Cole, G. O. & Haseman, S. M., (2023) “‘The Substance of Paint’: Class and Materiality in the Work of Ralph Balson”, Open Library of Humanities 9(2). Ralph Balson (1890–1964) was an English plumber and house painter who emigrated to Australia in 1913 and subsequently became a key member of Sydney’s artistic avant-garde. He is credited with having the first solo exhibition of purely abstract painting in Australia in 1941. Despite his role in developing Australian non-objective painting, Balson remained principally a house painter, working on his art practice at weekends. In 1955 he retired on a state pension and became a full-time artist. Balson’s artistic education and methods were critically shaped by his working-class background. He did not travel abroad until 1960 and was an avid auto-didact. His materials, palette, techniques and compositional strategies were likewise informed by his trade. Balson’s profession as a painter-decorator made him conspicuous within the predominantly middle-class Sydney art scene, though his painting partner Grace Crowley considered it an advantage in their pursuit of constructive painting. This paper explores the impact of Balson’s trade on his trajectory towards pure abstraction. While his art was at odds with the predominantly figurative mode of class-conscious art in Australian Modernism, we argue that it is embedded in the experience of class through its creative adaptation of labour into aesthetics. Source: OLH Svetlana Alexievich, The Art of Oral History No. 1 Paris Review Issue 257, Fall 2026 Interviewed by Elena Kostyuchenko INTERVIEWER How were you able to go to Chernobyl? Did you need special papers? ALEXIEVICH It was a time of chaos. They let me right into the zone. … More than anything, there was confusion. Adamovich [Ales Adamovich, the Soviet Belarusian writer], I remember, persuaded Gorbachev to send in the scientists, who showed up without even bringing their shaving kits. They were told that there had been an explosion at a nuclear power plant, but for some reason they thought that they’d be there for only a day or two. The first time I went was several months later, and people kept telling me about things they didn’t understand—how the fishermen couldn’t find worms, because they’d burrowed deep into the earth, how the milk wouldn’t curdle at the cheese factories. The honeybees wouldn’t come out of their hives. The evacuations started, I think, in the first month. The old women hid, they wouldn’t leave. I mentioned radiation to one of them and she said, “I’ve seen that radiation, all right! It’s yellow with green in it. I saw puddles of it in my garden, and I told the other women, and we ran and looked, and she had it in her garden, and the other one, too!” God, it was wild, the way the mind made sense of it. There was a story going around about Gorbachev telling the scientists to show him the radiation. “We can’t, it’s invisible.” “But I want to see it!” I also ran into the soldiers who’d been flown in on helicopters from Afghanistan. I asked them, “What are you doing here with your machine guns?” They said, “We’re collecting the radiation, that’s what.” So you had some of them running around with their guns, others out in the village washing off firewood or burying soil in the soil. These were the kinds of things that exploded our worldview. They made you realize that culture was just a chest filled with old manuscripts. There were no books in there that could help me. Our philosophers turned out to be useless when faced with the unprecedented. Derrida, Baudrillard—philosophy fell silent. What was happening? How would we live with it? That’s when I decided it simply needed to be witnessed. Which is what I did. INTERVIEWER I wanted to ask about how you talk to people. … ALEXIEVICH Yes, we sit and we talk—about what interests me and about life in general. About love, about everything in the world. That way, what comes out is three-dimensional. If you cut straight to the part you need, which is what journalists do, it won’t be interesting, and it won’t be the truth, either. Not the whole truth. INTERVIEWER Do people always open up when you ask questions, or can questions get in the way? ALEXIEVICH You have to ask questions, of course. Your job is to scour away the banality and return people to their true selves, to make them face what they rarely tap into. With every new person, you have to find a new way to do it. When you ask an interesting question or you share what happened to you, you help people really think about what they’re saying and not just repeat whatever they’ve picked up from the newspaper. But not everybody is capable of it, not everyone wants to put themselves through that. Either the chemistry starts to kick in or it doesn’t. A person might be wonderful, but you can tell that the conversation just isn’t going to happen. You can try to push it, but it will be a product of your own intellect, rather than of that mysterious connection. Life doesn’t come from the mind. Some people I can call two years after our last conversation, and they’ll say, “Oh, Svetochka! I think of you all the time,” and we’ll start talking again. With others, that won’t happen. That doesn’t mean they’re not extraordinary people, just that you can’t connect with them. They might have some insight, but you don’t have the right antenna to pick up their signal. Source: The Paris Review Colorized Franco-Prussian war … the ruins of Strasbourg with a French photographer and his mobile dark room. Ralph Balson (1961) Matter Painting If you’ve scrolled this far, you know you want to click: Subscribe
Pistons Exec Hasn’t Spoken to Jalen Duren All Summer
Trajan Langdon said he has not spoken to Jalen Duren once all summer. #Pistons
Trajan Langdon confirms that the #Pistons have not …
Trajan Langdon confirms that the #Pistons have not …
Routt County to host free mental health support training Tuesday, Sept. 29
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Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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What Does the Science of Climate Change Really Look Like?
Editor’s Note: This is the second in a three-part series on how the Right should think about environmental and climate policy. Read Chris Barnard on Reclaiming Environmental Policy from the Left. More than a decade ago, the world’s governments negotiated and signed the Paris Climate Agreement, committing to hold global warming well below 2 degrees Celsius. In the following years, climate had immense cultural power. Greta Thunberg emerged. Fortune 500 companies established net-zero plans. The U.S. got the Inflation Reduction Act. Then the pendulum swung back. President Donald Trump returned to the Oval Office, speaking of green energy as a “scam” and carbon footprints as a “hoax” and on all matters of international policy emphasizing bilateral engagement and power over globalism and cooperation. The technology companies that had been at the forefront of net-zero pledges and green leadership discovered the importance of all-of-the-above power to their visions for artificial intelligence and began quietly postponing or removing their targets. On the left side of the political spectrum, rising concerns about inflation and cost pushed climate lower down in the stated priorities of voters and stump speeches of politicians. The moment is ripe for a reset on the politics of climate change and for conservatives especially to chart a course that acknowledges and addresses the real challenges in plausible ways. So what should we think about climate change as we enter a post-peak climate era? If it is neither an apocalypse nor a hoax, what will hold up as a durable view of climate change? And how does it project onto the concerns and priorities of the right-of-center’s emerging coalition? New to Commonplace_? Subscribe below to get the magazine in your inbox._ Subscribe A Solid Foundation As the politics and economics of climate careened over the past ten years, the physics carried on regardless. In 2015, the year the Paris Climate Agreement was adopted, the world emitted 41.2 gigatonnes of carbon dioxide. By 2025, emissions had risen only 2.4%, to 42.2 gigatonnes, because falling emissions from land use offset increasing emissions from fossil fuels. But slow growth in annual emissions is not rapid decline, let alone net-zero, so carbon dioxide kept accumulating in the atmosphere, going from 399 to 426 parts per million. Global temperature kept rising too, from about 1.1 degrees Celsius above the 1850–1900 average in 2015, to 1.4 degrees above it in 2025. None of this should surprise anyone. Even most prominent skeptics, like the authors of the 2025 report commissioned by the Trump administration’s Department of Energy, accept the basic physics. Carbon dioxide added to the atmosphere at industrial volumes accumulates and traps heat that would otherwise escape to space. That heat warms the upper ocean and increases temperatures at the surface. Increased ocean heat and melting of land ice cause sea levels to rise. Changes in the climate become noticeable to us as subtle shifts in temperature and precipitation, seasons arriving early or late, changes in the surrounding ecosystem, and weather extremes. The much more meaningful debate is not about whether these things are happening, but about what it all means for human societies. (While it is a proxy measure of overall risk, no one experiences global surface temperature.) This debate invokes at least three interesting questions: how much today’s warming is showing up in regional climate trends, how much more warming we should anticipate, and how extreme weather events can be understood in the context of climate change. Recent scientific advances give us new insights into each of these, but there is still much to learn. This is the context in which the next generation of conservative leaders will be the first to deal with significant climate change as a fact, not a forecast. It will be with them for their entire careers. Our evolving scientific picture of climate change will come from weather and climate records stretching further into the past, new kinds of observations in the present, better modeling tools for the future, and simply more time to observe the emergence of climate signals and their tangible effects on ecosystems and communities in the United States and around the world. The policy landscape will be shaped by not only the impacts of changes in the climate, but also by the ways in which societies respond and by the emergence of new technologies for both altering the trajectory of emissions and adapting to new climate realities. Global climate records now show the fingerprints of warming in different phenomena around much of the world. The IPCC, in its most recent assessment report, documents warming trends over all land regions, even as natural variability adds substantial variance to local trends. And the highest temperature extremes have become more intense and frequent, almost everywhere, since the 1950s. Scientists are highly confident that these changes are attributable to human influence. But confidence in detecting trends and attributing them to human influence degrades across heavy precipitation events; drought trends are heterogeneous and not attributable to human activity with great confidence. For hurricanes, tornadoes, and other severe storms there is even less confidence in trends or their relationship to climate change. In general, a fair summary of the evidence is that for well-observed phenomena, like surface temperature or heavy rainfall, with a clear relationship to warming, our multidecadal observations are consistent with human influence overcoming natural variability over long time periods and extremes increasing. For regions that are sampled more sparsely, or phenomena with a higher noise-to-signal ratio, we will need to observe them longer to understand the magnitude of the climate signal or improve dynamical understanding using models and observations together. But for Climate For those who can’t wait, we also have new techniques that attempt to understand the role climate change has in influencing particular extreme events. When the climate is changing and disaster strikes, it is natural to ask whether that disaster was somehow “caused” by climate change. For scientists and policymakers acting in good faith, answering that question helps develop a more accurate picture of the problem, how it may be getting worse, and what preparations we should be making to respond to it. It may, at some point, give some weight to how liability is assigned by courts or adaptation funding is distributed by society. But how we ask this question is extremely important. It is easy to get the analysis wrong by discounting the role that meteorology plays. As meteorologist Theodore Shepherd explained in a clear 2016 review of climate attribution methods, “if a weather or climate event is truly extreme in the present climate, then perforce it requires unusual meteorological conditions, which means that climate change is at most a contributing factor.” Share Scientists have two ways to probe climate as a contributing factor, both of which have entered media coverage of extreme weather events. One asks a probabilistic question: How much more likely is a particular event (e.g., a temperature record over a particular area) amid global warming? The answer involves using historical records and computer simulations to estimate the likelihood of such an event in both a changed and a preindustrial climate. The findings are less about the specific event, and more about events of that nature. The other question is: How has the changed climate affected the specific event in question? Here, scientists try to understand what a similar event would have looked like in the preindustrial climate. This is sometimes called the storyline approach, where the story is the specific meteorological details of the event. These methods offer ways to test the intuition of scientists about real weather extremes. In late June and early July of 2021, a persistent high-pressure ridge, or heat dome, set up over the Pacific Northwest and an extraordinary heat wave affected the area from Oregon to British Columbia. For six days, it shattered temperature records across the region and hundreds died from heat-related causes, in an area where such high, and persistently high, temperatures were well outside of experience and many live without air conditioning. Scientists have studied its connection to climate change using multiple approaches. This specific event was created by a rare combination of meteorological factors, a strong high-pressure ridge created the conditions for extreme heat, which occurred on top of higher average temperatures in the region from global warming. Probabilistic analyses showed that climate change increased the likelihood of such an event by at least 8-fold to more than 100-fold. One standout example found that such an event had effectively zero probability of occurring in the preindustrial climate. The enormous range in these assessments reflects how hard it is to estimate probabilities of events at the tail of the historical record. Estimates of the effect on the temperature of the event are more clustered. A recent review paper documents how multiple methodologies have found a positive influence, roughly 1-2 degrees Celsius of an anomaly that exceeded 15 degrees, of climate change on the temperature magnitude of the event. Multiple studies have investigated and found some positive influence of climate change in other extreme events. Attribution studies found climate likely increased the heavy rainfall that accompanied Hurricane Helene in North Carolina and surrounding regions in 2024. The extensive fires that struck Los Angeles in 2025 illustrate how the causal chain can become messy, though. Studies do detect a positive influence of climate on the event’s likelihood, but while climate change likely contributed to underlying aridity, it would not have played a role in the heavy winds or land practices that preceded disaster. These event attribution studies will become more common for extreme, or damaging, weather events. They can be produced quickly, and often are reported before peer review. As the Pacific Northwest heatwave example shows, when multiple methods converge on a positive attribution, the finding should probably carry some weight even if you have to be careful about accepting the results from a single study. I expect that as climate change proceeds and the climate thus departs further from a preindustrial counterfactual, the influence will become more detectable across a variety of extreme events and more easily identified. This will be used to cast blame, but can also be used to inform how communities and society adapt to ongoing change. We May Still Be Surprised One positive development, insofar as less climate change is better, has been that our central estimates for future climate change should probably be revised downward. Mostly, that is because the high-end warmings that scientists regularly analyzed about ten to 20 years ago, driven by high emissions throughout the twenty-first century, now appear to be somewhere between unlikely and impossible. At one time, the upper end of mainstream climate projections extended well into 4 to 6 degrees Celsius of warming by the end of this century, which, models suggest, would have wrought enormous real-world damage. Current energy and policy trends now point toward 2.5 or 3 degrees. Damages and risks are commonly modeled as increasing steeply with more warming, so this is already a better-than-previously-expected outcome for the climate (which is independent of the physical response to emissions). But we should maintain a wide range for plausible outcomes and prepare for the possibility of being surprised. Emissions trajectories are subject to deep uncertainty, the physical climate response is still developing, and whatever change occurs in the climate will then be mediated through unpredictable economic, social, and political institutions. Over the past decade, the pace of warming surprised some keen observers and appeared to accelerate, though not yet outside the range of expectation provided by climate models. The reasons for that apparent acceleration are being actively studied (as was the apparent pause in warming from 1998 to 2012), but no single driver has emerged. Some blame it on the El Niño, variability which would have no bearing on climate. Some think it is a result of factories in East Asia and global shipping fleets cutting aerosol emissions, which in the strongest version of the argument would indicate higher climate sensitivity to carbon-dioxide emissions. Others are more measured, not yet ready to draw solid conclusions as to whether climate projections require revision. We will have to see. Long-Term Thinking Climate change asks us to think over long time scales. But the pace of human-driven warming is compressing a large global change into a century. Changing weather patterns and extreme events are already causing adjustment costs and damages and will do more. Adaptation will help, but it is not free. For some communities, these costs will erode livelihoods and well-being, and may force migration. Are we prepared for large-scale managed retreats in the United States? Thankfully, American wealth, geographical diversity, and moderate climates may leave us better prepared than many around the world. But wealthy countries can still suffer serious disruption from narrowly concentrated costs, even if they appear entirely manageable in aggregate. Readers of Commonplace are familiar with the challenges of rapidly adapting to economic forces. The displacement that came from the China Shock is barely perceptible in aggregate GDP and employment data, but it affected millions of people and those people were far less mobile than economic models tended to assume. Deindustrialization rippled through the nation with enormous effects for not only our economic vitality, but also our national security. The forces surrounding climate change may not be so different; the world gets richer and must accept some diffuse costs. Those may be modest overall, but cause all manner of unpredictable effects with which policymakers must cope. In the case of the China Shock, our faith in a growing pie served us poorly. We’ll need to do better on climate. Leave a comment
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Authorities in Rome have unveiled what is believed to be the largest fresco and mosaic complex of ancient Rome | 1010 WINS
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His wedding guests gave $6k to fund a health startup. Now it's won a $3 million prize
Dr. Raj Panjabi founded Last Mile Health to bring healthcare to people living in remote areas. The group is the 2026 recipient of the Conrad H. Hilton Humanitarian Prize.
Why is climate action “easier said than done”? The key lies in the strong coupling between climate and society
A new Perspective in Science Bulletin argues that the persistent gap between climate science and climate action stems from a conceptual blind spot: treating climate and social systems as separate domains rather than as one integrated, co-evolving entity. The authors introduce the Climate-Social Coupling System (CSS) paradigm and, by re-contextualizing the classic Environmental Kuznets Curve, sort national trajectories into “strong,” “weak,” and “de-coupling” states, showing that governance is the decisive, reversible steering mechanism that determines a country’s climate future.