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11 PS Plus Extra Game Removals for November 2026 Confirmed
Rockstar drops PS Plus support again
U.S. Supreme Court lets Hastings name change remain
The U.S. Supreme Court rejected a challenge by Serranus C. Hastings’ descendants to the removal of his name from San Francisco’s 148-year-old law school.
Americans With Disabilities Worry About Proposed Changes to Major National Health Survey
Questions that have been proposed for removal deal with memory, fatigue, arthritis, difficulty walking and climbing stairs, as well as others about the use of hearing aids, canes, wheelchairs and scooters.
Berkeley's Nabolom Bakery blames political backlash for decline ahead of closure
Nabolom's owners say an Instagram removal and backlash over its political positions hurt sales, but they also point to rising costs, staffing problems and fierce competition.
Berkeley’s Nabolom Bakery blames political backlash for closure
Nabolom’s owners say an Instagram removal and backlash over its political positions hurt sales, but they also point to rising costs, staffing problems and fierce competition.
Trump says he will close historic D.C. golf course for 15 months of renovations
A judge last week, however, ordered a halt to his redevelopment plans until at least Oct. 26 after scolding the government for starting a large-scale tree removal at the course over a holiday weekend while providing little notice to the court or the plaintiffs trying to stop the makeover.
Kelly Clarkson’s Home Decor Collection Contained Bird Products Before Apparent Removal Amid Store Feud
Trump administration seeks to remove judge in golf course case, accusing her of ‘egregious’ behavior
The Trump administration has requested the removal of the federal judge overseeing a legal challenge to President Donald Trump’s plans to overhaul a Washington, DC public golf course, accusing her of having “bias.”
Business owners call for boycott of lottery sales in response to the removal of skill games
G-Pro Snow Removal celebrates 10-plus years in business with new home base
SOUTH LAKE TAHOE, Calif. – What started out as a hobby for Gino Bedwell has expanded into a thriving business over the last decade, and due to its growing success, G-Pro Snow Removal has found...
How the Zelda Ocarina of Time remake changes the classic game’s script
At the start of the iconic 1998 Nintendo 64 game The Legend of Zelda: The Ocarina of Time, our playable hero Link wakes up in his tree cabin, heads outside and is greeted by his friend Saria. “Yahoo! Hi, Stotil!" she says. In other people’s copies of the games, she might say “Hi, Link!” or “Hi, Brick!” or use whatever other name the player was allowed to input when first launching the game. The more important point is that she starts with a “Yahoo!” In Nintendo’s 2011 remake of Ocarina of Time for the 3DS handheld, Saria greets Link with that same word. But for the 2026 Switch 2 re-remake of Ocarina of Time, out November 5, Saria’s salutation has changed: “Hello, Link!” she exclaims. There’s no “Yahoo” to be heard. Last month, in an official Nintendo video preview, Zelda series producer Eiji Aonuma described the remake as a “faithful interpretation using modern technologies.” Faithful means the gameplay hasn’t changed much. Dungeons, quests, and just generally what you do in the game doesn’t seem to have changed, not based on what Nintendo has shown nor the hour of the game I played in New York City a couple of weeks ago. The graphics have been overhauled. The controls have been tweaked. Players can now manually control the camera and make Link jump with the press of a button, both notable differences from the original 1998 design. But Link’s journey appears to take the same path, with the same obstacles in its way. The remake’s biggest alteration to Ocarina of Time that I’ve spotted so far just might be the script. About the game’s story, Aonuma said in September, “We’ve added quite a lot of new dialogue for the characters, so that their personalities shine even more.” Earlier this month, I played a chunk of the Ocarina of Time remake at a Nintendo showcase. In the game’s earliest moments, I made a point of talking to characters and recording what they said. I found the script to be more colorful, more natural in its phrasing, more careful to establish its characters, and certainly more wordy even with the removal of that one “Yahoo!”. I’ve got some very early-game examples, so you can judge the new writing for yourself.
Iran: Political infighting deepens as economic woes mount during war
Hardliners are stepping up pressure on Iran's government and calling for Foreign Minister Abbas Araghchi's removal. The oil minister resigned, but that's doing little to ease the pressure on President Masoud Pezeshkian.
Skill game machines shut off statewide, leaving Lancaster County businesses struggling
Businesses in Lancaster County are facing financial losses after Pace-O-Matic shut off skill game machines statewide, requiring their removal by a midnight deadline.
Why a wave of ‘cockroach’ protesters are defying India’s bid to stamp out their movement
Demonstrators are demanding the resignation of India’s election chief over the removal of 130 million names from voter lists, which they say favors Prime Minister Narendra Modi’s party.
Monroe County health board sets Oct. 22 hearing on possible removal of health officer
Monroe County’s health board voted 5–0 to schedule an Oct. 22 hearing on whether to remove health officer Sarah Ryterband, less than two years into a four-year term. The board disclosed no specific allegations and raised the possibility of terminating her contract without cause.
Judge Orders Trump Administration to Answer for Tree Removals at D.C. Golf Course
During a four-hour hearing, a federal judge demanded answers from the Trump administration about who authorized the removal of hundreds of trees at the East Potomac Golf Links.
Scientists Discover Groundbreaking Clues to Tissue Regrowth and “Immortality” in the Ocean
Sea cucumber tissue kept growing for more than three years after removal, surviving in seawater teeming with microbes. Like Thing, the disembodied hand in The Addams Family, a severed piece of sea cucumber tissue kept living without the body it came from, prompting scientists to describe the animal as a “real-life zombie.” Weeks after being
Business owners brace for removal of skill machines
It’s a challenging reality for many in the state right now that, after Oct. 13, skilled games will be considered illegal.
The Math Singularity Is Here, and Science May Be Next
OpenAI has released an extraordinary body of mathematical work produced by an unreleased frontier model: 722 manuscripts spanning 372 research families across fields including number theory, complexity theory, and mathematical physics. Each result required, on average, the equivalent of roughly three hours of ChatGPT Pro reasoning. A New Era of Discovery We may be witnessing the beginnings of a “math singularity”: a point at which machine-generated discovery accelerates beyond humanity’s ability to independently reproduce, verify, or fully absorb it. If frontier models can generate hundreds of meaningful results in the time it takes a human researcher to investigate one, the constraint will no longer be producing new mathematics. It will be our capacity to validate, interpret, and integrate it. This does not make mathematicians obsolete. It changes their role. They may increasingly serve as guides, critics, and meaning-makers. Increasingly, they will decide which questions matter, determining which results can be trusted, and explaining why they are important. Mathematical insight may become abundant, while human judgment becomes more valuable than ever. Mathematics May Be Only the Beginning Every scientific discipline could eventually experience a similar acceleration. AI systems could generate and test hypotheses, connect findings across specialized fields, and explore possibilities at a scale no human research community could match. In medicine, imagine models identifying overlooked disease mechanisms, designing drugs and clinical trials, personalizing treatments, or discovering cures in months rather than decades. In materials science, AI could help create better batteries and cleaner industrial processes. In climate science, it could accelerate advances in energy, forecasting, and carbon removal. In biology, it could uncover relationships hidden across enormous genomic and molecular datasets. The result would not simply be faster research. It could expand the frontier of what is scientifically possible. The New Bottleneck Scientific discovery, however, is not the same as scientific progress. A medical breakthrough must still survive laboratory testing, clinical trials, regulatory scrutiny, manufacturing constraints, and real-world deployment. As machine-generated ideas multiply, the bottleneck may shift from producing breakthroughs to validating them safely and translating them into practice. We may soon have more hypotheses than laboratories can test, more drugs than clinical trials can evaluate, and more mathematical results than experts can review. That imbalance will require better systems for automated verification, reproducible research, prioritization, peer review, and collaboration between AI and domain experts. The importance of OpenAI’s work is not merely the number of manuscripts produced. It offers a glimpse of a world in which intelligence can explore thousands of intellectual paths in parallel. If ideas cease to be scarce, humanity’s defining challenge will be deciding which are true, which matter, and how to turn them into progress. The math singularity is not the end of human inquiry. It is the beginning of a new kind—one in which machines expand the frontier of knowledge and humans decide where it should lead. Subscribe Share Leave a comment
Who Won August and September: Original Films or Franchises?
(Welcome to the Entertainment Strategy Guy, a newsletter on the entertainment industry and business strategy. I write a weekly Streaming Ratings Report and a bi-weekly strategy column, along with occasional deep dives into other topics, like today’s article. Please subscribe.) I just heard someone say that if you’re reading a pundit or data analyst, and they don’t tell you that they got anything wrong, they’re not a pundit but an “influencer”. I agree with that. You have to tell your audience when you get things wrong, or they won’t (or shouldn’t) trust you as much. Today, we’ve got another edition of “What I Got Right, What I Got Wrong”. In general, I’m patting myself on the back (and patting very hard) about a few things like IP at the box office, LIV golf, horror films, crowdfunding movies, superheroes, and old people going to the theaters. That said, I also made a couple of data mistakes on the streaming bubble popping and HBO’s datecdotes, so I’m not perfect. But first, I need your feedback... Subscribe Follow-Ups: What Should We Call Mid-Budget Movies Which Aren’t Cinematic Enough for Theaters But Are Too Expensive to Make Money on Streaming? After I asked for feedback on what we should call straight-to-streaming films that are too big to pencil out on streaming but not really big enough to resonate in theaters, I got some great suggestions from you all, including... “Moldilocks” from John Aboud “Little Big Indie” from Travis Frick1 “Midflicks” from Jonathan Funke. “Extra-Medium” from Jona Nwuke. (Read the explanation in the footnote.) Between these and Brandon Katz—who suggested “Bermuda Budget Triangle”, “The Platform Gap” and “The Distribution Deadzone”—we’ve got some excellent suggestions. And they’re better than my suggestion, the “Streaming Budget Dead Zone”, so let’s take a poll! The winning entry becomes the new term. Loading... RIGHT: LIV Golf is Fully Bankrupt…Is Anyone Else Next? A few years ago, I was always a bit perplexed at all the articles I’d read praising LIV Golf and their strategy to disrupt the PGA. LIV Golf, a brand new professional golf league, offered PGA stars ten times what they made on the PGA Tour to join their new league. And folks praised this strategy for its initial “success” in that a lot of big names did indeed leave the PGA. Yeah, of course the players came over. LIV Golf paid them so, so, so much more! But LIV Golf hadn’t discovered a way to increase potential revenue. So think about this in basic business terms… They paid much more in costs… …but had no real way to increase revenue. That’s not a strategy! That’s deficit financing. It won’t work unless you bankrupt the competition (and then turn around and pay those same golfers much, much less). It’s not a sustainable strategy and only lasts as long as the company/person/nation backing it decides they’re cool with losing money. For LIV Golf, that meant Middle East oil wealth, in particular Saudi Arabian money. Clearly, the current Iran War has hurt Middle East finances, so they need to trim their more exorbitant spending. And LIV Golf was part of that trimming. This should be a major warning for others. TGL’s parent company, TMRW Sports, just got a $1 billion valuation, despite TGL’s (the indoor golf league) horrible TV viewership of less than half a million viewers per match. Unrivaled, the women’s basketball league, just secured a $650 valuation, despite its horrible TV viewership and a new rival (Project B) entering the scene next year. To relate this to streaming, Hollywood should ask which streamers may have wealthy patrons funding their losses. (Let’s be clear: Google, Amazon and Apple.) Could those patrons lose their appetite? For Amazon, probably not. But Apple has a new boss, so maybe! WRONG: My Analysis of the Streaming Bubble Was Missing a Week I’m going to be congratulating myself a lot today, but I make mistakes too, like this data goof. When I last compiled the data on the decline in TV shows, I was missing one week at the end of June. If you look at the first image, you can see that one week was mislabelled as “July”. Mainly, this image got updated to show a 27% decline, not 29%: This change doesn’t really impact the overall analysis, but it is two percent better. By the way, through the third quarter, the decline increased and it’s now a 30% decrease since 2022. (I’ll write/visualize this in an upcoming article.) But I want you to trust me and my data. Especially these days, when many people are using LLMs that I know are inserting faulty data into their charts, I want to keep earning my audience’s faith. So that’s the accurate data. RIGHT: IP Remains Very, Very Popular In July, I wrote a giant (and I mean giant) article on Backrooms, Obsession, and the box office, going over what we know, what we don’t know about what works in theaters, looking at YouTubers, IP, the horror genre, comic book movies, and a whole lot more. The month of August really tested a lot of my theses and, being honest, mostly supported my arguments. Let’s start with IP. Looking at 8-Aug (the weekend after Spider-Man: Brand New Day came out) to 18-Sep (the weekend that Resident Evil came out, which I think provides a nice bookend to this time period), there were seven films based on pre-existing IP: Resident Evil (2026) ($126 million) Practical Magic 2 ($65 million) _Insidious: Out of the Furthe_r ($65 million) Coyote Vs. Acme ($59 million) Paw Patrol: The Dino Movie ($53 million) Tony ($15 million) Super Troopers 3 ($7 million) Compare those to the notable original films from the past month—I actually could have included more movies, but here are just thirteen, bringing us to an even twenty films—including.... The End of Oak Street ($54 million) Buddy ($26 million) Mutiny ($15 million) By Any Means ($15 million) The Dog Stars ($14 million) Runner ($14 million) One Night Only ($11 million) Hope ($8 million) Spa Weekend ($7 million) The Uprising ($6 million) Teenage Sex and Death at Camp Miasma ($6 million) Onslaught ($3 million) Eli Roth’s Ice Cream Man ($2.8 million) Here’s that in chart form: Five of the top six films in this time period were all based on IP. I made a big chart of films that grossed over $200 million at the box office before Spider-Man: Brand New Day and The Odyssey hit theaters. Let’s update that chart! By the way, if you want to see how I categorized each film—so another bar chart—here it is: I know that many of my fellow critics/pundits/analysts dislike films based on IP and how Hollywood is making so many of them. And I’m sympathetic to this point of view. As I’ve written many, many times before, you need a balance between existing franchises, new IP, and original films. And Hollywood clearly needs to make more films like Resident Evil (a well-made film from a visionary director) and fewer Practical Magic 2’s (which didn’t get critical or customer buzz). But at some point, critics and pundits need to contend with what audiences are telling them: Movie-goers aren’t showing up to original films. Audiences are speaking with their dollars, telling you they want more IP and franchises. You can try to convince studio heads to make fewer IP-based films and franchises, but the data and numbers aren’t there. Instead, critics need to work harder to convince audiences to show up for original films. Aim your ire/concern at the average person, not studio heads.2 Because they’re just making the films that audiences are telling them to make. WRONG: Original Horror Films Didn’t Break Out I’ll be honest, even though I wrote an article casting some skepticism on the horror genre in July, if you asked me to make a prediction, I would have predicted that, in August, a new, original horror film would have blown up. No, seriously, I just assumed that Obsession and Backrooms presaged a change in audience behavior. But none of the buzzy new original horror films from August—Teenage Sex and Death at Camp Miasma, Onslaught (not an action film in spite of the ads), The End of Oak Street, Eli Roth’s Ice Cream Man, or _Buddy—_broke out. To be clear, exactly one of those films (Buddy) had good “ROI”, but again—I try to be specific in my language—none were “popular” in any broad sense of the word. None of them will be “saving” movies theaters like Backrooms or _Obsession_helped save the summer. The new Insidious film and Resident Evil, both based on IP, were far and away the biggest horror films since July. (We’ll see if this changes in October/Halloween season.) RIGHT: Stay Skeptical about Crowdfunding... I’ve long been skeptical about crowd-investing platforms as one of Hollywood’s saviors, mainly because there’s so much hype/buzz. People need to stay more skeptical about more things, explaining both the potential upside but also the downsides. In particular, the media often hypes crowdfunding at the start and never checks in on the actual results after they’ve come in later. And August gave us our first update! _Ice Cream Man—_directed by Eli Roth—grossed $6 million off of a $5.5 million budget. This is a production of The Horror Section, which was one of the first “crowd investing” studios with 2,400 investors, which means that 2,400 investors probably lost money. They certainly aren’t getting as great of returns as if they had just invested their dollars in the stock market. Hopefully Stiletto (Tagline: “Someone’s Going to Make it Rain Blood!”) does better next month. WRONG: Another Data Goof Here’s another data error. When the first episode of House of the Dragon came out, HBO put out that it had 21.5 million viewers in the first three days, and I read that to mean in the US…but no, it was global. So my US-only datecdotes charts shouldn’t have included it. We never got US-only numbers for the first episode, but for the final episode, HBO put out that it had 11 million US viewers. (And that global dropped to 21 million viewers.) Here’s the updated chart (which I’ve since used in the Streaming Ratings Report): Still, this show is absolutely huge. RIGHT: Superhero Films Remain Very, Very Popular After Supergirl flopped, I read a few takes that “comic book movies are going the way of the Western”. Post-Spider-Man: Brand New Day, that take didn’t age well. To be fair, I have a very nuanced take on the superhero genre right now; it’s down right now, for a lot of reasons. But it’s not “dead”. Maybe _Spider-_Man is just a really popular character? I saw that take, and it’s a fair counter-argument. (But pundits arguing that superhero movies were dead should have mentioned this $1.5 billion counter-argument…) But is it just Spider-Man? The next Avengers film already has $50 million in pre-sales (and I was skeptical that that film would do well) and the Avengers: End Game re-release topped the box office two weekends ago (over three original films). And I wouldn’t bet against Batman or Superman. So maybe it’s just Spider-Man, Batman, Superman and the Avengers. Oh, and Deadpool, of course. And Black Panther. And Wolverine. And probably the X-Men. Plus a well-made Wonder Woman or the Hulk film could break out. But that’s it! It’s just those ten characters/teams. Oh, what’s that? Lanterns is also doing well on HBO? (See previous section…) To be fair, I’m actually pretty sympathetic to the argument that more popular characters—like Spider-Man and Batman—anchor more popular films. In fact, I made that exact argument three years ago when I first wrote about the “Marvel-cession”. In many ways, you can blame The Guardians of the Galaxy for fooling Marvel Studios (and the rest of us) into believing that any character could pop. It turns out, the list of iconic characters is probably smaller than most people think. But it’s probably too early to say that superhero films and comic book movies are dead unless “death” means a slight decline over a longtime. RIGHT: Who Killed Theaters? Old People I get frustrated whenever I see headlines or analysis about how young people are “returning” to theaters. As I’ve detailed(for years), young people have always powered the US box office, despite narratives about “kids these days” and their “phones”. Really, what’s changed post-2020/pandemic is that old people aren’t going to the movies nearly as much. This summer, I saw a movie (from an older director) in a theater near a retirement community, and multiple older people at the theater were talking about how this was their first time seeing a movie in years. I dislike personal anecdotes, so YouGov can fill in the data, best summarized by this headline: “Who killed movie theaters? Not the youths”. According to them, 64% of people aged 18-29 have seen a movie in the last year, but only 30% of 65-and-older. 20% of 18-29 have seen a movie in theaters in the last week and 42% in the last month. Here’s the polling data: Most concerning? Many Americans (17%) think theaters are a worse or much worse experience than watching films at home. Slight WRONG: Hadestown Opens Big A live theater capture of the Broadway musical, Hadestown, made $20 million at the US box office, which begs the question: was I wrong to be skeptical about musicals a few years ago? Yes and no. On the one hand, $20 million is a far cry from being “popular”, so yeah, the genre isn’t that popular overall and Hadestown is one of the more popular musicals from recent years (i.e. the “Taylor Swift Data Fallacy” in action). On the other, I doubt filming this cost all that much, and I don’t think that they spent much on marketing, so this is a good source of ancillary revenue. Smaller Updates WRONG: As I mentioned in a Streaming Ratings Report, I underestimated the budget for Enola Holmes 3. It probably cost more like $50 million, if not more. But... I’m not sure that it really matters? At sub-10 million hours, prices have to come down to make this work. WRONG: Netflix is giving Ink a 27-day in theaters! To quote the kids/YouTubers these days, let’s go! Now I might actually have a chance to see Danny Boyle’s latest in theaters. I’d complained about this in a “Coming Soon” section, but I was heartened to read that Netflix is giving multiple films longer theatrical windows this year. RIGHT: Netflix is sending 4-5 films per year to theaters. Netflix is slowly but surely sending more and more films to theaters, as I cautiously predicted earlier this year. For now, it’s just three big films and a number of awards contenders, but still, this is great news. And they’ll be releasing box office grosses! Just this week, Ted Sarandos confirmed that KPop Demon Hunters 2 will come to theaters (and my guess is it performs in the box office top ten at a minimum). WRONG: Angel has 3 million subscribers! How do I know this? Well, they told Deadline, who reported it. I marked this as “wrong”, since they’ve doubled their subscribers in one year but, you know, they don’t really have a hit film to speak of and they’re still losing money. WRONG: Furious was only renewed for one more season. I accidentally wrote “two more seasons” in my latest “Renewals, Cancellations, Un-Orders and Removals Update”. RIGHT: House of David is ending with its third season. In July, Prime Video renewed House of David for a third season, as I just wrote in my latest “Renewals and Cancellations” report. Well, now it’s ending after that third season. Why? As I’ve been writing, its viewership wasn’t great. I got feedback that this show didn’t cost very much, but it cost enough that its limited viewership didn’t save it. WRONG: Adults was a Hulu original! So I missed Adults when it first came out last year; I saw that it aired on FX and just assumed that it was a linear-first program. Turns out, it aired three episodes on FX, but binge-released the rest of its episodes the next day on Hulu. Huh. So I should have covered it last year! But I just wrote about it. 1 “When I was a kid in the 90s, if you wore a t-shirt to school that wasn’t too big and also wasn’t too small, but somehow didn’t quite fit, we’d say you were wearing an “extra-medium” shirt.” 2 As always, a huge exception is Disney, which barely makes anything original anymore.
State police launch skill game compliance info webpage
PSP has opened a new webpage to help business owners better understand compliance requirements for the removal of skill game machines. Starting Oct. 14, business owners may be subject to criminal charges for maintaining the machines.
Dave Portnoy on Fox ‘Big Noon’ Exit: Ryan Day Thinks I ‘Doxxed’ Him
Portnoy tells FOS that Ohio State pushed for his removal.
Collaborating with Canadian Scientists on Marine Carbon Dioxide Removal Research
I first met Dr. Helen Gurney-Smith in fall 2024, when Dr. Shannon Meseck and I drove just beyond the U.S.-Canada border to the St. Andrews Biological Station in New Brunswick. We went there to study larval sea scallop respiration when exposed to near-future temperature and pH. This past winter, Dr.
Mac Users Reclaim Storage With New Apple Intelligence Removal Tool
A new open-source tool is making waves in the Mac community by helping users reclaim valuable storage space taken up by Apple's AI models. Called "RemoveMacAI," the tool disables Apple Intelligence on macOS 27, removes its downloaded models, and prevents them from being downloaded again. In macOS 27, Apple removed the toggle to disable Apple Intelligence wholesale, and simply disabling individual features doesn't remove the models from your Mac's drive.
Ed Sheeran's newest opening act praises Macklemore amid tour drama
After other musical acts quit his tour following Macklemore's removal for pro-Palestinian messaging during a performance, Ed Sheeran found a replacement opening act for a night.
Ed Sheeran's new tour opener speaks out on Macklemore, calls for 'common ground'
After other musical acts quit his tour following Macklemore's removal for pro-Palestinian messaging during a performance, Ed Sheeran has found a replacement opening act.
ACA fraud crackdown removing 760,000 enrollees is squeezing health insurer profits
Shares of Centene, Molina, Elevance, and UnitedHealth have all fallen since Vice President JD Vance announced the removals last week
Analytics vs. players: Red Sox tensions boil over
The Red Sox's wild card sweep exposed a deeper rift between players and management over analytics-driven in-game decisions, most notably the early removal of Sonny Gray in Game 2.
Judge blocks Trump from firing Seattle US attorney who had job for an hour
President Donald Trump cannot fire US attorneys who have been appointed by courts, a federal judge in Washington state said Thursday in a first-of-its-kind ruling that tests the scope of a president’s removal power under the Constitution.
Scientists Found a “Third State” Of Being Between Life and Death
Frog and human cells can reorganize after removal from their host, raising open questions about biological death and potential uses in regenerative medicine.
Video Essayist And YouTuber Jacob Geller Removed From MinnMax Following Sexual Assault Allegations
Jacob Geller has not commented on the allegations or his removal from the games podcasts.
90 Ideas in 90 Minutes: Billy Weathers
Impactful leadership takes removal of ego Leaders can unintentionally halt their own mission. Leadership is servitude. Sometimes the idea outgrows you, or was never about you to begin with. The best leaders are able to remove themselves from the equation to focus on the outcome and betterment of the collective. You can build an organization around…
Business Community Signals Openness to Removing Public Vote on Nuclear
PLYMOUTH — Gov. Maura Healey’s mission to restore nuclear power to Massachusetts has put the local business community at odds with nuclear watchdog groups. Advocates worry that the removal of […]
Ranking Member Markey: SBA Administrator Loeffler, Trump Administration are Refusing to Answer to America’s 36+ Million Small Businesses and Workers, Leaving Main Street Behind
Loeffler canceled her scheduled Sept. 30 appearance before the Senate Small Business Committee, has not appeared before SBC in more than a year (Washington, September 28) – Ranking Member Edward J. Markey (D-Mass.) today released the following statement after Small Business Administration (SBA) Administrator Kelly Loeffler canceled her scheduled Wednesday appearance before the Small Business and Entrepreneurship Committee. Administrator Loeffler has not appeared before the committee in more than a year and has consistently refused to provide substantial answers to committee members in person, in writing, or via requested briefings. In June, Ranking Member Markey led every Democratic member of the committee in calling on Administrator Loeffler to appear before the committee to answer for the Trump administration’s cruel attacks on American small businesses, entrepreneurs, and workers. The Democratic lawmakers still have not received a response from Administrator Loeffler. “It is unacceptable that Administrator Loeffler chose to cancel her appearance before the Senate Small Business and Entrepreneurship Committee. The Trump administration is once again ignoring the more than 36 million American small businesses, entrepreneurs, and workers who drive our economy and enrich our communities by refusing to answer questions about this administration’s reckless economic policies. It has been more than a year since Administrator Loeffler has appeared before our committee and answered questions from both Democrats and Republicans. Since then, the Trump administration’s attacks on Main Street have only worsened. “Small businesses are facing record high gas and diesel prices, skyrocketing healthcare costs, and never-ending uncertainty from Trump’s trade war with the world. Trump has terrorized Main Streets across the country with violent ICE raids, destroying families, communities, and local economies. Meanwhile, Administrator Loeffler and the Trump SBA have been in a Witness Protection Program, ignoring the Pain on Main Street that they have created. They have chosen to make drastic cuts to SBA funding and essential, bipartisan programs, including the closure of the SBA office in Springfield and removal of the SBA office from Boston; directly attacked immigrant small business owners and destroyed the promise of the American Dream; and proposed shortsighted small business size rules that would benefit billion-dollar businesses over actual small businesses. “It’s clear that Administrator Loeffler, President Trump, and their CEO billionaire buddies want to turn the Small Business Administration into the Big Business Administration, tear down our economy, and abandon Main Street. If that is indeed this administration’s goal, Administrator Loeffler must answer to the millions of small businesses, workers, and families in Massachusetts and across the country that this administration is leaving behind.” ###
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Junk-collecting small business adapts Temu rack to double its hauling capacity
A three-person junk-removal company in Maryland doubled how much it can haul in a single trip, thanks to a $150 bed rack from Temu.
Growing threat to free speech: Bogus copyright claims are making political stories disappear
Google’s removal of stories underscores mounting concern that federal copyright law is being used by people relying on automated, AI-driven and anonymous complaints to file fraudulent takedown notices, all in the name of suppressing headline news.
Everything you wanted to know about political signs but were afraid to ask
With the Sept. 8 primary approaching, learn NH laws for campaign signs, including placement rules, removal deadlines, and their effectiveness.
Week Ends Aboard Station With Robotics, Spacewalk Reviews, and Science
Expedition 75 ended the week studying Canadarm2 robotic arm maneuvers and reviewing procedures for a spacewalk to support the removal and replacement of a space-to-ground antenna on Tuesday, Aug. 18. Science remained on Friday’s schedule as the International Space Station residents studied space exercise techniques, explored aerodynamic drag forces, and more.
Tel Aviv U. removes Sackler name from science faculty — the final department still named for the opioid-tied family
School says the removal allows for a new major naming donation, as occurred with its medical faculty that was also previously named for the Sacklers
Health Officer Issues Emergency Order to Accelerate Removal of…
Spokane Regional Health District Health Officer Dr. Francisco Velázquez today issued a public health order authorizing the U.S. Environmental Protection…
Steam reportedly refunds Battlefield 6 player with 470 hours logged after EA quietly pulled Rush mode from Quickplay
A Battlefield 6 player "upset" at the removal of the popular Rush mode claims to have secured a full refund from Steam despite having clocked up 470 hours.
TikTok says moderator error delayed removal of Perez Hilton's livestream showing acts of self-harm
TikTok says a moderator error delayed the removal of Perez Hilton's livestream showing self-harm, prompting a law enforcement response and the celebrity blogger's hospitalization.
Telegram CEO Says Extortionist Manipulated Apple Into App Store Removal
Telegram was subject to a "takedown extortionist" who planted AI-modified child sexual abuse material (CSAM) to get Apple to remove the app from the App Store, Telegram CEO Pavel Durov said today. Apple removed Telegram from the App Store for about 40 minutes on Monday night after discovering CSAM, but reinstated the app after Telegram removed the content.
Telegram appears to have been pulled from the App Store worldwide
Telegram appears to have been removed from the App Store in multiple countries, although the reason for its apparent removal remains unclear.
Politics & Power: Voting rights, election fears & the battle for Congress in 2026 midterms
A former White House attorney is warning that a series of executive actions — from changes to voting rules to the removal of election oversight officials — may be laying the groundwork for unprecedented federal intervention in the upcoming midterm elections.
Business People: Edric Funk to take over as Toro Co. CEO
MANUFACTURING The Toro Co., a Bloomington-based maker of lawn mowers and snow removal machines for consumers and businesses, announced President and Chief Operating Officer Edric C. Funk will be promoted to chief executive officer,…
'Street justice’: Maryland’s Squatter King removal business fills area divide
When property owners call Sanchez Deandre Lewis, they are often already locked out.The Maryland contractor, known as “Mikey,” says unauthorized occupants have h
Turkey's Ozel launches new party to challenge Erdogan
Former CHP leader Ozgur Ozel is set to launch a political party after his removal from office through a court ruling.
Nearly 400 noncitizens voted in New Jersey elections, governor says
Mikie Sherrill (D) said she learned of the problem, which she attributed to a software error, last week and ordered the removal of ineligible voters from the rolls.
Samsung makes One UI 9.0’s new power menu security feature easier to understand
Samsung’s latest Android skin for Galaxy smartphones, One UI 9.0 (Android 17), introduces several changes and improvements. One of them is the removal of the Lo
Trump calls for review after climate manual for judges withdrawn
President Trump called for a “review” on Sunday of an updated judges’ manual that he claims the left improperly influenced. It follows the removal of a controversial climate science chapter from th…
Justice Department activates untested court for 'alien terrorist' deportations
The Alien Terrorist Removal Court was established in 1996 but had never received a petition until this past Wednesday.
How 2 brothers started a junk removal business with less than $10,000
The McKinney brothers said "almost anyone can do it." They describe how they started their junk removal business with about $8,000.
Winter Sports Club responds to Nordic combined’s removal from Olympics
In a gut-punch to the Steamboat Springs Nordic combined community, the sport has been removed from the Alpes 2030 Winter Olympic games in France. Nordic combined has long been a bread-and-butter sport for the Steamboat...
Team Welch demanded ‘misleading’ ad’s removal. Crist’s camp replaced it
A political committee backing Charlie Crist uploaded a new ad calling out City Hall spending with tweaked language.