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Tracking tsunamis triggered by extreme weather
As much of Western Europe faced record-breaking temperatures and extended drought this summer, Croatia experienced another weather event that could also set a worrisome precedent.Over the course of two weeks, a series of meteorological tsunamis (meteotsunamis) struck Croatia’s Adriatic coast, alarming both residents and tourists. Social media posts showed flooded seaside promenades and people walking through knee-deep water. Fortunately, no deaths or major damage were reported.In a world where natural disasters seem to be increasing, meteotsunamis — tsunamis caused by rapid weather changes – rarely make headline news. But warming sea temperatures and changing atmospheric conditions may help explain why these phenomena could become more common, especially in shallower seas and inland lakes with wide coastal shelves.“We have definitely become more aware of them, and there have been a lot more reports of these events in the last 10 years,” says Jadranka Šepić, an associate professor of environmental physics at the University of Split whose research focuses on efforts to track meteotsunamis in real time. She is also one of Croatia’s ambassadors for Science Comes to Town (SCTT), a European Commission-funded programme aimed at making research more accessible to the public.Šepić sees two possible reasons for the apparent increase in meteotsunamis. One is that photos and videos shared on social media are providing more empirical evidence, while rising air and sea temperatures could also play a role. The geophysicist “cannot say with certainty” that warming is a contributing factor because research is still ongoing. “But I can say that previously in Croatia we might have had one exceptionally strong event every 10 or 15 years, and one strong event every five years, and within 15 days this summer we had five strong events,” Šepić notes. “This is not typical.”‘A fist against the sea surface’Unlike tsunamis that are triggered by underwater earthquakes or volcanoes, meteotsunamis are caused by sudden changes in atmospheric pressure combined with other rapidly developing weather events, such as thunderstorms. The effect “is like pushing a fist against the sea surface,” Šepić explains. The resulting oscillation intensifies as it reaches shallower water, and “can be far more destructive than a wind-driven wave because meteotsunamis are accompanied by very strong currents than can penetrate much deeper inland.” The meteotsunami, she continues, “then behaves the same as a tsunami — they slow down and grow as the sea shallows, and then grow further in places like harbours due to further shallowing and narrowing. When they come ashore, they can be very destructive — taking everything with them out to sea and then taking it back.”Croatian research institutions have tracked such sea oscillations since the 1930s because the relatively shallow Adriatic Sea is prone to meteotsunamis. The strongest recorded so far was in June 1978, according to the Adriatic Meteotsunami Catalogue, which is supported by the European Research Council (ERC), Croatian Science Foundation and the country’s leading research institutions. During that event, six-metre-high waves flooded the coastal town of Vela Luka on Korčula Island, causing major damage.Other meteotsunami “hotspots” in Europe include the Mediterranean Sea as well the Atlantic coastal shelves off France, Portugal and Spain. In June 2006, a meteotsunami with five-metre-high waves swept through the harbour of Ciutadella in Spain’s Balearic Islands, causing widespread damage to boats. Several less powerful events were reported in the Balearics and off the coast of Spain this summer, leading to some beach closures.Forecasting is challenging because of how quickly meteotsunamis can develop and their uncertain trajectory. Šepić is involved in two ERC-funded research projects — SHExtreme and MeD-Track — aimed in part at strengthening monitoring and real-time data collection. Access to accurate and immediate information is essential for early-warning systems.Early exposure to meteotsunamisŠepić first learned about meteotsunamis from her parents while growing up in Croatia. She later had the opportunity to investigate these events during her master and doctoral studies in geophysics at the University of Zagreb. The geophysicist has also conducted research at the Institute of Oceanography and Fisheries in Split, the University of the Balearic Islands in Palma de Mallorca and the Institute of Ocean Science in the Canadian province of British Columbia.Projects like SCTT are important to raise awareness about research and inspiring young people to pursue studies and careers in science, notes Šepić. She credits her colleagues at the University of Split and the Institute of Oceanography and Fisheries for their community outreach and engagement in the European project, which includes partner universities and institutions in Brest (France) and Kiel (Germany). As an example of town-gown collaboration, Šepić highlights her own university’s ‘Oceanographers on the Island’ programme. This initiative offers workshops and hands-on learning for children living on numerous Croatian islands.“It is a great privilege for Split to be involved in a project like Science Comes to Town, which is the first of its kind in the European Union," Šepić says. As for encouraging new generations of scientists, “This is a great effort, and I hope that we will see an effect in a few years.”Science|Business, which connects policymakers, academics and industry through its news reporting, analysis and events, is an SCTT partner.
A timeline of Mike Causey’s sometimes-turbulent tenure as NC insurance chief
A look at Insurance Commissioner Mike Causey’s career as a second complaint about his behavior with women surfaces.
First iPhone Duo unboxing videos surface ahead of official reviews
A series of iPhone Duo unboxing videos are now on YouTube, showing how the device ships in its open configuration, and how the display crease is practically invisible.
Scientists Use Ancient Rains to Map the Possible Origin Life on Mars
Billions of years ago, rain may have helped shape where the chemistry of life could begin on Mars. A new study maps how formaldehyde, an important prebiotic molecule, may have reached the surface. This map could help guide future missions searching for signs of past life on Mars.
Some Olathe retirees frustrated after health insurance premiums rise again for 2027
These concerns first surfaced last fall when retirees learned their city health insurance premium costs were going up by 500% to 900% for 2026.
There's A Suspicious-Looking Hole On The Moon, And NASA's Going To Investigate It With A Surface Mission
The Moon is covered in pits and craters to choose from, but the Marius Lunar Pit has NASA's attention.
How Science Is Helping Coastal Communities Build Resilience to El Niño
The current El Niño may become the strongest in modern recorded history. The naturally occurring climate phenomenon, primarily associated with persistent, high ocean surface temperatures in the central and eastern tropical Pacific Ocean, could have global-scale effects on weather and ocean conditions through 2027.
Yankees' Intriguing Trade Rumor Resurfaces — But Does It Make Sense?
Does it make sense for the New York Yankees to pursue this trade?
Old Fidel Castro interview resurfaces in attack ad against Miami congresswoman
“She cozied up to a dictator and, now, she is cozying up to another wanna be dictator, Donald Trump,” Eliott Rodriguez said in the ad.
Clarksville Area Chamber of Commerce’s Veteran Business of the Month, Above Standard Building Maintenance - Clarksville Online - Clarksville News, Sports, Events and Information
Clarksville, TN - Above Standard Building Maintenance has been providing services like janitorial services and hard-surface stripping and waxing to folks in
‘The Field Is Atrocious,’ ‘Risking Players’ Health’ — Super Bowl Champion, NFL Fans Rip Playing Surface in London for Jaguars-Texans Game
The NFL’s 2026 international series has gotten off to a solid start, with games in Australia and Brazil followed by two matchups in London. Now, the fifth international game of the season, and third in London, features the Jacksonville Jaguars and Houston Texans at Wembley Stadium in Week 6.
Chinese scientists develop nanoparticles to improve pesticide
In a study published in the Journal of Controlled Release, researchers mimicked gut bacteria pili-hair-like structures that function as hooks-to design hollow, rough-surfaced silica nanoparticles
Salt crystals could hold clues to life beneath Enceladus's ice
The ocean beneath Saturn's moon Enceladus lies under kilometers of ice, but some of its contents do reach the surface. Jets near the south pole spray out water vapor and icy particles, offering a way ...
Microplastics and water create free radicals, new study finds
When water comes into contact with plastic surfaces, a key chemical reaction does take place, new research indicates.
Has there ever been a mountain taller than Everest?
Mount Everest may be the king of the planet today, but has Earth ever thrust a larger mountain from its surface?
Tech stocks erase $1 trillion of wealth as oil surges to $110 for the first time since May
The sharp drop in tech shares came as concerns resurfaced about ballooning AI debt, rising interest rates and high gas prices.
Windows 11 Is Finally Becoming the OS It Should Have Been From the Start
Microsoft is completely redesigning parts of its OS so it doesn't hog all the resources of lower-end PCs with 8GB of RAM.
Plague is stoppable. The next health threat may not be.
The word plague is scary. Centuries ago, the Black Death killed tens of millions of people and changed the course of history. Plague still kills people around the world, and the word still evokes catastrophe. New fears of plague surfaced on October 2, when a lab worker in Irkutsk, Russia, died of pneumonia. Reports suggested that she may have contracted plague through a laboratory exposure. Understandably, people were alarmed. On October 7, the World Health Organization called for the Russian Federation to be transparent about what it knew. WHO issued an update on October 10. Russian authorities told WHO that testing did not identify plague and that investigations found no laboratory release. WHO said confidence in its risk assessment remained limited and that further clinical, epidemiological, and laboratory information was needed. The cause of the woman’s illness remains unknown, and WHO says a laboratory-associated exposure cannot be excluded. As I explained in a recent interview, this incident is very unlikely to lead to a pandemic. Plague is still active, including in the U.S., which sees a handful of cases each year. But it is a disease we can prevent and treat. Plague doesn’t spread readily, and it responds to antibiotics. The standard response—isolate the patient, trace contacts, and administer antibiotics and monitor for symptoms among contacts for seven days—works. We have even planned for antibiotic-resistant plague. At CDC, we developed a playbook for antibiotic-resistant plague and ran exercises on how to find and stop it. CDC guidance anticipates engineered resistance and recommends two different classes of antibiotics if there’s reason to suspect it. There is no evidence that resistance—or even confirmed plague—is involved in this incident. We have thought through how to address plague, but we’re not ready for the next major health threat that emerges from a lab or from animal spillover to humans. What should concern people is how little stands between the world and the next pathogen to get loose. Since peak COVID, epidemic preparedness has fallen off the political agenda, but the risk is greater than ever. More labs handle dangerous pathogens with more ways to make those pathogens deadlier, and more people live and work in close contact with animals. There are actions we can take now: We need better lab safety in every country. The number of labs that work with dangerous pathogens has increased worldwide over two decades, but there’s no enforceable international standard and no inspection regime; the Biological Weapons Convention, fifty years on, still has no verification mechanism. Labs that study dangerous germs need strong safety systems, training, and oversight. We need to reduce spillover events. Three in four emerging human infections start in animals, and there’s a lot we can do to reduce spillover risk, but the world is doing very little of it. Live-animal markets are one place to act. For instance, closing live-bird markets helped control H7N9 influenza in China. Reducing opportunities for people to encounter infected animals can prevent infections before they become outbreaks. In The Formula for Better Health, which is now out in paperback along with the hardcover, Kindle, and audiobook versions, I argue that labs do too many risky experiments with too many dangerous pathogens in too many institutions, and that every experiment should first answer one basic question: Is the likely benefit greater than the risk? Spillover risk can also be reduced: In the book, I discuss how Brazil cut its deforestation rate by 70% from 2004 to 2012 while increasing agricultural production and reducing risky contact between people and forest animals. We need faster detection and response. Delay costs lives. Strong surveillance, good labs, and trained responders can turn a single case into a small cluster of infections instead of an epidemic. Resolve to Save Lives has worked for nearly a decade to help countries find and stop outbreaks faster. The 7-1-7 target, which Resolve to Save Lives developed with partners in Uganda and elsewhere, provides a clear standard: detect within 7 days, notify within 1 day and complete all essential early response actions within 7 days. In Uganda’s Kasese district, for example, a review of a measles outbreak using 7-1-7 identified shortages of accessible funds, fuel, and vehicles that delayed the response. District leaders established funds they could access quickly. When, a few months later, the Crimean-Congo hemorrhagic fever appeared, the district detected it in three days, notified authorities in one, and mounted an effective response in two. Only one case was confirmed, and the patient survived. Because funds were available before the emergency, authorities were prepared and able to act. This kind of preparation can’t wait until the next crisis begins. Plague is an old disease we that know how to stop. The next threat may be harder to recognize, harder to treat, and easier to spread. Safer labs, less risk of spillover, and faster outbreak detection and response need sustained investment now, while we still have time to prevent the next emergency. Share
Microsoft Surface Laptop Ultra Review: Complicated, yet So Damn Worth Getting Stuck In
The Microsoft Surface Laptop Ultra isn't just a MacBook Pro for PCs. It's a strong sign that local compute power is what we actually need in the so-called "AI era."
The Surface Laptop Ultra delivers on most of Microsoft's promises
Microsoft promises one machine for dev, AI, and gaming, and mostly gets there.
I've lived with Microsoft's $6,000 Surface Laptop Ultra, and it's so close to being the best MacBook Pro alternative you can buy
Microsoft's top of the line Windows 11 PC is finally here, and it's giving the MacBook Pro a real good run for its money.
Cattle futures higher waiting on direct business
At the Chicago Mercantile Exchange, live and feeder cattle were up, optimistic about the week’s direct business. Direct cash cattle trade activity was relatively quiet on Thursday. There was a lone bid that surfaced in Kansas at $226 live, but the rest of cattle country has been quiet. It appears sellers are holding out for […]
How This Zombie Foot is Helping Scientists Fight Stingray Strikes
Warm El Niño waters are driving an increase in stingray injuries. These labs are devoted to understanding what’s going on under the surface.
Precision weather radar visualization requires better science, not just new tech
Learn how multi-source atmospheric science, GRAF modeling, and precision weather radar visualization create a more accurate representation of surface weather.
2026 State of the Climate Report Shows a Planet Reaching Its Limits
The seventh edition of an annual report analyzing Earth’s "planetary vital signs” indicates that Earth systems are rapidly destabilizing, some at an accelerating rate. The report, published today in BioScience, analyzed 16 of these signs, including greenhouse gas emissions levels, ocean heat content and acidity, the mass of major ice sheets, the number of hot days, Earth's surface temperature, and more.
BUSINESS UPDATE: Attracting World-Renowned Piercing Educators to Oswego
Growing number of renowed piercers are coming to Oswego to share knowledge at newly opened Aqua Spa Float Center piercing suite Submited by Aqua Spa Float Center & Wellness Boutique [caption id=attachment_11066 align=alignright width=450] Recent opening of Aqua Spa Float Center piercing suite.[/caption] Professional piercers and educators from countries including France, Scotland and India have come to Oswego’s Aqua Spa Float Center & Wellness Boutique to share their knowledge In the past year and a half, the Port City has become a destination for some of the industry’s most respected educators through the efforts of the Aqua Spa Float Center & Wellness Boutique. Beginning in January of 2025, Aqua Spa Float Center envisioned a new version of body piercing, one where elegance, safety and personal expression could converge. According to the Aqua Spa, piercing is no longer just a trend — it’s a refined form of personal identity, luxury styling and self-investment. It’s not only about the jewelry — it’s about the entire experience. The team welcomed first guest piercer Ruben Triguero, a senior French piercer, piercing stylist and international educator, who has over two decades of experience and has worked in some of the world’s best studios, including Paris, Rome, New York, Miami, Los Angeles and Dubai. In those studios, he offered his expertise and refined styling skills. Triguero is a prominent figure and leader in the piercing community and shares his knowledge with piercers teaching classes for the industry’s most prestigious organizations, including Latinoamérica Body Piercing Association (LBP) and Association of Professional Piercers (APP). He is currently the senior international instructor of the APP. Triguero has a passion for creating stunning, personalized piercings for clients around the world. Education and Mentorship Following a year of success and popularity, Aqua Spa Float Center hosted the grand opening of its private dedicated piercing suite in March. Aqua Spa Float Center & Wellness celebrated this next chapter with a grand opening and ribbon-cutting ceremony attended by the Oswego Mayor Robert Corradino, members of the Greater Oswego-Fulton Chamber of Commerce, local business owners and community members. The educational focus, aligned with Aqua Spa Float Center’s vision and mission, had already begun expanding beyond clients. Aqua Spa has hosted multiple workshops and continuing education opportunities for professional piercers, inviting studios from across the region to gain hands-on experience from internationally recognized instructors without the expense of traveling to national or international conferences. These educational events have welcomed nationally and internationally recognized professional piercers and educators from countries including France, Scotland, India, and throughout the United States. Aqua Spa also continues to collaborate with talented regional and local professionals, creating opportunities for education and mentorship that benefit both industry peers and clients throughout Central New York. Aqua Spa Float Center & Wellness Boutique owners — Tammy Wilkinson and Terry LeRoi — have been deeply rooted in the piercing industry with over 30 years in business as LeRoi Fine Body Jewellery. Combining that experience with holistic wellness, self-care and self-expression is the new concept with the client Luxe Piercing Experience at the Aqua Spa Float Center. “At LeRoi Fine Body Jewellery and Aqua Spa Float Center, we’ve been fortunate to work with many of the world’s most respected piercers through our involvement with the Association of Professional Piercers and by attending conferences across North America and Europe,” said LeRoi, founder of LeRoi Fine Body Jewellery and co-owner of Aqua Spa Float Center & Wellness Boutique. “Those experiences have shown us that education is what drives our industry forward. “Not every piercer or studio can travel to major conferences like the APP Conference in Las Vegas or APP Benelux in the Netherlands, so we’re committed to bringing that level of education here. Hosting internationally respected educators like Jef Saunders allows our clients to experience the highest standards of professional piercing while giving piercers throughout the Northeast the opportunity to learn from some of the very best in the profession. That’s something we’re incredibly proud to offer our community.” When asked about the client experience, Wilkinson explained that education is at the heart of every appointment as well. “Our vision is to nurture and enhance wellness, balance and harmony through a multi-modality-centered facility, and we aspire to empower sustained, positive change, well-being and self-awareness; and educate to the benefits of natural health, holistic wellness and life balance,” Wilkison explains. “Piercing is no different. The piercing experience feels just as peaceful and rejuvenating as any other spa services. From the moment our clients arrive, they are in the very best hands with our kind and professional Wellness Ambassadors and experienced APP guest piercers.” Wilkinson also explained that piercing clients receive stellar care: every Luxe Piercing appointment includes a one-on-one private piercing in Aqua Spa’s dedicated piercing suite, their choice of custom jewellery by LeRoi Fine Body Jewellery, thorough after-care instructions and complementary check-up appointment, complementary whole-body red light therapy session in the Class II NovoTHOR medical device to promote healing, and access to many rejuvenating spa services. Piercing clients get 15% off during any event. According to Wilkinson, “Health and safety are always our highest priority when you come in for a piercing or jewelry installation. Before each appointment, all tools and jewelry are sterilized in a Statim autoclave, and every surface in the piercing room is carefully disinfected. During the procedure, your piercer will wear a mask and change gloves as needed to maintain a sterile environment. Once your piercing is complete, your piercer will go over detailed aftercare instructions with you. Following these steps is crucial to ensure proper healing before you leave our sanctuary.” As a part of the experience, guest piercers include a thorough anatomy review of the client’s desired piercing to ensure the new addition will work in harmony with the existing. “Our clients are enjoying building and creating ear curations with these international professionals. It’s a unique styling event and a chance to highlight self-expression,” Wilkinson said. Clients and piercers throughout the region are flocking to this piercing destination in Upstate New York. The Luxe Piercing Experience has welcomed clients and piercers alike from around the globe. Owners Wilkinson and LeRoi hope to continue the momentum with more educational seminars with industry experts to be a hub of knowledge and expertise. They hope to establish LeRoi Fine Body Jewellery and Aqua Spa Float Center as legacy businesses known for their lasting, positive impact on the piercing and holistic wellness industries.
Sony takes down PS5 piracy store offering 1,600 games, multiple clones appear just hours later
Sony reportedly took down Overdrive, a PS5 piracy store offering more than 1,600 games. However, the project quickly resurfaced on GitHub with a new release.
Student Artists Produce Themed Mural for Department of Political Science
On the surface, the Lane Room Mural is simply a new painting on an old wall. But beneath the vibrancy and impressive scale of the work is a story of art
Deep-Sea Rocks Spontaneously Combusted After Scientists Brought Them to the Surface
A recent discovery highlights an unforeseen potential hazard of deep-sea mining.
Comparing Off-World Rover Driving Distances
This infographic illustrates the distances driven by various rovers on the surface of Earth’s Moon and Mars. Of the vehicles shown, the NASA Mars rovers
Eye Microbiome: How Bacteria May Influence Eye Health and Disease
The ocular surface hosts a low-abundance microbial community that may help regulate immune defenses, while changes in its composition have been associated with inflammatory and infectious eye diseases. Research into the gut-eye axis and microbiome-targeted therapies suggests possible diagnostic and treatment applications, but the underlying mechanisms, causal relationships, and clinical effectiveness remain uncertain.
NASA’s Perseverance Sets Off-World Record for Total Distance Driven
NASA’s Perseverance Mars rover has driven farther than any vehicle ever has on the surface of another world. On Oct. 11, the rover’s odometer reached
M5 Pro MacBook Pro vs Microsoft Surface Laptop Ultra: Compared
The Microsoft Surface Laptop Ultra uses Nvidia graphics in a bid to take over from the 14-inch MacBook Pro with M5 Pro as a productivity favorite. Here's how the two powerful notebooks compare.
Packers’ Christian Watson Leaves Teammate in Awe With ‘Nasty’ TD
Christian Watson gave the Green Bay Packers a touchdown worth watching again.Javon Bullard surfaced the locker room review.Following Watson’s second score in Sunday’s 31-7 victory over the Chicago Bears, the Packers defensive back needed some time to describe what he had seen.“I ain’t going to lie. That [expletive] was nasty. That was nasty,” Bullard said, […] The post Packers’ Christian Watson Leaves Teammate in Awe With ‘Nasty’ TD appeared first on HEAVY.
Apple MacBook Pro 16 vs Microsoft Surface Laptop Ultra: Poll shows clear winner
With the launch of the newest Microsoft Surface Laptop Ultra, many people are comparing the laptop to the Apple MacBook Pro 16 with the M5 Pro. This comparison is quite apt, as both machines target the same audience. A poll run by Hardware Canucks has now revealed which laptop users prefer more.
Microsoft Is Taking AI Beyond the Data Center, But Its Surface Business Is Just a Small Piece of the Pie
The tech giant's latest Nvidia-powered Surface devices add another dimension to its growth strategy as shares trade near all-time highs.
Microsoft Is Taking AI Beyond the Data Center, But Its Surface Business Is Just a Small Piece of the Pie
The tech giant's latest Nvidia-powered Surface devices add another dimension to its growth strategy as shares trade near all-time highs.
Microsoft Is Taking AI Beyond the Data Center, But Its Surface Business Is Just a Small Piece of the Pie
The tech giant's latest Nvidia-powered Surface devices add another dimension to its growth strategy as shares trade near all-time highs.
Artemis II crew describes yellow and green hues on the Moon’s surface
Artemis II astronauts reported yellow, green, brown, blue and beige hues on the Moon during an April flyby, according to a preliminary NASA report.
NVIDIA’s CUDA Moat Is Accelerating RTX Spark Laptop Sales, Higher 128GB Unified Memory Options Belonging To Surface Laptop Ultra Already Out Of Stock
NVIDIA’s CUDA platform is speeding up RTX Spark laptop sales, with the higher 128GB unified memory options of the Surface Laptop Ultra already out of stock
Microsoft offers MacBook Pro owners up to $1,000 to switch to Surface Laptop Ultra
Microsoft is offering MacBook Pro owners up to $1,000 in extra cash back when they trade in their Apple laptop and preorder the new Surface Laptop Ultra. The bonus is paid in addition to the device’s normal trade-in value, as Microsoft tries to lure Apple users to its $2,599.99 RTX Spark-powered flagship.
Scientists Discover a Hidden Hydrogen Pathway That Could Transform CO2 Into Valuable Fuel
Scientists have uncovered an unexpected pathway for hydrogen transfer during catalytic CO2 conversion. A computer model designed to predict how carbon dioxide becomes useful chemicals produced a surprising error: It identified formic acid as the main product instead of methanol. When scientists expanded the model to account for thousands of previously overlooked reactions, its predictions
James Talarico Resurfaces At ACL; Mental-Health Claim Unverified
James Talarico returned at ACL after a nine-day absence. The mental-health-facility claim remains unverified as scrutiny of his record grows.
Assistant Professor of Climate Data Science | The Journal of Blacks in Higher Education
Boston University invites applications for a faculty position at the rank of Assistant Professor in the Department of Earth Environment. This tenure-track position in Climate Data Science , beginning on July 1, 2027, is part of the ongoing cluster hire in Environmental Data Science and complements faculty searches within the Faculty of Computing and Data Science.rnrnWe particularly welcome candidates whose research focuses on the physical basis of climate, climate variability, and climate change, and who employ data science methodologies to deepen our understanding of how the climate system is changing and how these changes affect the global environment. Areas of interest include—but are not limited to—the changing frequency and intensity of extreme weather events; interactions between the atmosphere and terrestrial, oceanic, biospheric, and cryospheric systems; and improved understanding of Earth system predictability at seasonal, decadal, and longer time scales. We envision this position playing a central role in connecting and enhancing existing departmental strengths in climate-related research and teaching, including terrestrial and marine biogeosciences, land surface and coastal processes, paleoclimatology, energy and economic policy, and environmental sustainability. This faculty member will also contribute to university-wide interdisciplinary initiatives — including the Urban Biogeoscience and Environmental Health (URBAN) program, the Institute for Global Sustainability, and the Center for Climate and Health at the School of Public Health — and is expected to develop collaborative ties with the Faculty of Computing and Data Sciences, where shared interests in machine learning, large-scale data analytics, and Earth system modeling provide natural ground for joint advising, co-teaching, and grant development. This hire reflects our commitment to advancing interdisciplinary scholarship at the intersection of climate and data science. This position contributes to the University convergence themes of Global Sustainability as well as Artificial Intelligence, Data Science, Computing that are core pillars of BU's cross-disciplinary research priorities.rnrn Position Qualifications:rn Candidates should have a PhD or equivalent degree, demonstrated ability to obtain external funding to support their program of research and scholarship, and a commitment to excellence and innovation in teaching, education, and mentorship of students. The successful applicant will be expected to supervise graduate research in Ph.D. programs, teach at all levels in the Earth Environment curriculum, and maintain an externally funded research program. We seek applicants whose research complement strengths in the Department and around the University. For more information about the Department, see
Microsoft wants you to "break up with your MacBook" for a Surface Laptop Ultra, and it's paying big bucks to make it happen
You can get up to $1,000 cash back on top of trade-in value if you send Microsoft a MacBook Pro and buy a Surface Laptop Ultra.
Scientists create new statewide surface geologic map of Nebraska
A new academic paper by Paul Hanson and Matthew Joeckel of the Conservation and Survey Division in the University of Nebraska–Lincoln's School of Natural Resources contains a brief phrase—"new linework"—that ...
NASA is searching for hidden caves to build its first Moon base
NASA is preparing for humanity’s first Moon base with three investigations that will hunt for underground shelters, uncover hidden ice, and track dangerous conditions on the lunar surface. The findings could reveal how astronauts can survive and thrive on the Moon while laying the groundwork for future journeys to Mars.
Commercial muralist builds brand identity, value
Riveting Paint & Pearl owner Desire McGinn approaches murals less like commissioned fine art and more like a skilled trade, working directly with business owners, contractors, and design firms to turn walls and other surfaces into extensions of a client's brand.
MSFT Stock On 4-Day Winning Streak: Microsoft Takes On Apple's Macs With Nvidia-Powered Surface Ultra, More On-Device AI
Microsoft is pushing Windows deeper into the local-AI era with Nvidia-powered Surface, on-device models and hybrid Copilot features.
Pokémon Ruby & Sapphire Switch Port Rumours Resurface Following Pokémon HOME's Latest Update
Two GBA games were made compatible this week
With the internet’s rise, politics carry more meme than meaning
Our columnist argues Americans must take political communication more seriously, rather than reducing nuanced issues to surface-level content.
Microsoft Launches $2,599 Surface Laptop Ultra to Take on MacBook Pro
Microsoft today announced launch timing and pricing for the Surface Laptop Ultra that it unveiled earlier this year. The 15-inch Surface Laptop Ultra is priced starting at $2,599, undercutting Apple's $2,999 16-inch MacBook Pro, and it targets the same creator and developer market. Microsoft says it is built for "demanding creative, software development, AI, engineering, and 3D workloads".
Cristiano Ronaldo Portugal Retirement: Georgina Rodriguez's Admission on Future Resurfaces
Microsoft releases new Nvidia-chip AI PCs with revamped Windows 11
Microsoft revealed the specs and price for its Surface Laptop Ultra, AI PCs that run on Nvidia chips that are designed to run AI models and agents.
The first Nvidia RTX Spark laptops cost up to $7,000
Prices start much lower, but 128GB of unified memory is going to really cost you.
Microsoft debuts Nvidia-powered Surface Laptop Ultra, as it aims for AI market
Microsoft debuted its Surface Laptop Ultra, powered by Nvidia's RTX chip on Wednesday.
Everything announced at Microsoft’s Surface Laptop Ultra event
Check out our coverage of the show.
The Surface Laptop Ultra finally has a release date — and a starting price of $2,599
The Surface Ultra is designed to handle creative workloads, gaming, and AI.
Surface RTX Spark Dev Box is available for preorder for $5,999
Microsoft’s high-end AI mini PC for developers starts shipping in November.
Microsoft’s Surface Laptop Ultra has built-in magnetic USB-C charging
The charger snaps into place when you bring it close to the port.
Nvidia Takes Aim at Intel’s $32 Billion PC Business With Microsoft’s Surface Laptop Ultra
Microsoft (MSFT:NASDAQ) and Nvidia (NVDA:NASDAQ) are set to unveil the Surface Laptop Ultra in San Francisco on Wednesday, October 7, with Satya Nadella and Jensen Huang taking the stage together. The laptop runs on Nvidia’s RTX Spark chips, announced in June, and it’s built to run AI agents on the PC itself instead of in the cloud.
Microsoft Surface and Windows Event 2026: All the Announcements and Analysis Live From San Francisco
Today's the day! We hope to learn fresh details about the Surface Laptop Ultra, the next chapter for Windows, and the future of Copilot at Microsoft's fall event. Follow along with all of our expert commentary and on-the-ground updates, and tune in to the livestream later this afternoon.
Argonne-Led Campaign Aims to Improve Midwest Storm Predictions
A new U.S. Department of Energy research campaign will deploy advanced instruments from Ames, Iowa, to Chicago, Illinois, to study how differences in land surfaces, from farmland to cities, impact the formation and intensity of energy-disrupting storms. LEMONT, Ill., Oct. 7, 2026 — Every year, destructive storms cause billions of dollars of damage to homes, […]
Teladoc Health unveils new AI capabilities within Solo platform for hospitals
Teladoc Health announced Wednesday the launch of two new artificial intelligence capabilities within its enterprise smart care platform Solo. | The two new tools aim to help health systems surface timely patient insights into their care environments while reducing technology fragmentation, executives say.
Footage From Canceled Perfect Dark Reboot Surfaces, Showing Off Fruit Physics and Parkour
New footage of Xbox’s canceled Perfect Dark reboot has appeared online, via a report from gaming website MP1ST.
Earth's magnetic field: An enigma that could affect how long we live
Generated by a vast dynamo-like churn of molten iron in the Earth’s core, the magnetic field that surrounds the planet protects its surface and everything on it from space radiation as well as helping...
Leak Tips NVIDIA RTX Spark-Powered Microsoft Surface Laptop Specs
Following what appears to have been a series of unfortunate events that led to a roadside laptop find resulting in confirmation that Microsoft will be launching a 20-core NVIDIA RTX Spark Surface Laptop, we now appear to have confirmation that Microsoft will also be launching a Surface Laptop...
Report: Cancelled Perfect Dark Project Over 2 Minutes of Gameplay Surfaces Showcasing New Zones and Combat
Last year, we reported on gameplay details and screens for The Initiative's Perfect Dark reboot, which was unfortunately canned by Microsoft. Today. we unearthed more about the project and its…
Microsoft’s MacBook Pro Rival Is Looking Even More Ridiculous
We thought Microsoft was preparing a wild laptop. Turns out it's preparing two.
Apple TV 4K Rumored to Support Four HomePods for Surround Sound
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Surface Edge taps new business development director
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Nebraska vs Maryland – Game Thread of Winning Fun!
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What Does Your Office Say About Your Business? by Jennifer Kraner
What does your space say about you and your business? More importantly, does it give you the best possible first impression? The minute a client, customer or patient walks through your door, they’re forming an opinion about your business – sometimes consciously, sometimes without even realizing it. Your space is communicating something about you, whether you intend it to or not. At Big Sky Design, we work with all kinds of commercial businesses, including many medical practices, law firms and other corporate offices, and I’ve seen first hand how much thoughtful design can influence that first impression. For businesses in medical, legal, and financial fields, three things are particularly important: trust, privacy and professionalism. Your space should communicate all three while also reflecting who you are as a business. That can be challenging, especially in a new construction project. Often, so much of the budget goes toward the actual construction that things like lighting, comfortable seating, artwork and finishing touches get pushed to the side. But those are often the elements that make a space feel complete – and memorable. Think about your waiting room. Is it comfortable? Is the lighting welcoming? Does the layout make sense? When someone walks through the door, do they immediately know where to go and whom to speak with? In a medical office, there’s another important consideration: privacy. Reception areas can become surprisingly noisy places, with phone calls, conversations between staff and patients, and people discussing personal information. Hard surfaces throughout a space allow sound to bounce around, making it difficult to maintain privacy. We recently worked with an eye doctor's office that had exactly this problem. The reception desk had a large opening, and staff were making and taking phone calls right next to patients who were waiting. We designed an acoustic treatment that acted as a divider between the staff and waiting areas. It absorbed sound, but it also became a branded design element. It was a visual reminder to everyone in the space to be mindful of their voices and what others might be able to hear. Those kinds of thoughtful details can make a tremendous difference. And good commercial design doesn't have to mean making your space flashy. Sometimes it’s as simple as a calming color palette, beautiful artwork, plants, carefully selected lighting or comfortable upholstered furniture. In a medical setting, those touches can help soften what might otherwise feel clinical and reduce anxiety for patients who are already nervous about an appointment. I’ve been in waiting rooms where everyone feels packed together, and you can hear every conversation – even what’s happening in the restroom next door. That’s not the experience you want to create. Your office should also feel like your business. Are you telling people that you’re clean and modern? Sophisticated and unique? Warm and welcoming? Or, unintentionally, are you telling them that your business is outdated? You don’t necessarily need a complete renovation to change that message. Fresh paint, updated lighting, new artwork, better seating or a few branded design elements can make a space feel current and intentional. At Big Sky Design, we’ve worked with radiology, dermatology, and dental practices, among many others. Every practice is different, but the goal is always the same: creating a space that reflects the business behind it and gives every person who walks through the door a positive first impression. Because your office is part of your brand. Make sure it’s telling the story you want people to hear. Read more at bigskydesignonline.com.
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Nebraska vs Michigan State
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Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Two astronauts who flew farther than anyone before are taking new NASA roles
Artemis II astronauts Victor Glover and Reid Wiseman are transitioning to emeritus status at NASA after their historic journey around the Moon earlier this year. The pair will continue advising and mentoring NASA teams as preparations accelerate for Artemis III and future lunar missions. Their experience with Orion and deep-space operations could prove especially valuable as NASA works toward returning astronauts to the lunar surface.
Rosholt fourth-graders kick off yearlong NASA science program
Over the coming months, students will work in small groups called Crews to take surface temperature readings.