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How to submit high school sports highlights to The Palm Beach Post
The USA TODAY Network has launched a new portal that lets fans upload and share their athlete's best high school sports highlights.
Compeer Rochester launches new campaign to end loneliness, improve mental health
Compeer Rochester just launched its "Scroll Less, Connect More" volunteer campaign. The group's research found American adults spend an average of 64 hours on screens per month. The campaign asks Rochesterians to put their phones on pause for just four of those hours to make a new friend and support a person struggling with a mental health diagnosis.
From Mexico to Houston: Nurse turns side hustle into growing business
Houston registered nurse Joao Casiano, born in Monterrey, Mexico, launched a mobile IV hydration business as a side venture while continuing his nursing work, quickly gaining repeat customers.
Trump uses taxpayer funds for another TV ad, warns of 'final battle'
President Trump launched a second taxpayer-funded television ad ahead of the midterm elections, this one warning of a \
Providence Alaska Launching Residential Youth Behavioral Program
To expand psychiatric treatment for teenagers, Providence Alaska is opening a Youth Behavioral Health Center in Anchorage this fall.
SpaceX’s Starship launches on 14th flight, first headed to orbit
SpaceX's Starship rocket launched from Texas on its 14th flight, marking the first operational satellite release and debut flight to orbit.
There's Something Strange About Googlebook Prices
Not even Google seems certain about how much customers are willing to spend on a laptop in 2026.
Beach Institute, Savannah African Art Museum hosting community chat on women’s health
The Beach Institute and the Savannah African Art Museum are partnering to launch a community conversation focused on women’s health and wellness in October.
Meta is launching an enterprise AI business, sending MongoDB stock plunging
Chirantan "CJ" Desai stepped down from MongoDB on Monday to become Meta's chief enterprise platform officer, reporting to Mark Zuckerberg
‘Starship is in orbit’: cheers go up as huge SpaceX rocket circles Earth for first time
Mission goes ahead despite some fears an initial engine failure after the Texas launch would scupper the attempt
Kerecis Reimagines Fish-Skin for Deep Wounds with Launch of Compact
ARLINGTON, Virginia & REYKJAVIK, Iceland--(BUSINESS WIRE)--Sep 28, 2026--
12 New Things to Expect From Apple This October
October will be an especially busy month for Apple this year, with the company set to release the iPhone Duo, both iOS 27.1 and iOS 27.2, and a new Mac Studio configuration with 512GB of RAM. In addition, up to six more Apple products may be unveiled next month, such as new iPad mini, HomePod mini, and Apple TV 4K models. Below, we have outlined 12 new things to expect from Apple this October. Confirmed iPhone Duo: The foldable iPhone Duo launches on Friday, October 23.
Sports gambling critics launch movement to put limits on industry
Advocates traveled to Washington, DC to urge lawmakers to take action and keep both gambling companies and sports leagues accountable for the risks of sports betting.
SURI: The Seventh Note launches October 30
PlayStation India Hero Project-supported rhythm action platformer SURI: The Seventh Note will launch for PlayStation 5 and PC via Steam on October 30 for $19.99 / £15.99 / €19.99 / ¥3,190, develope…
SpaceX launches Starship on 10-hour test flight, aiming to orbit Earth 6 times
SpaceX's massive Starship rocket lifted off from Texas Sunday morning on its most ambitious mission yet, marking its first attempt at orbit.
Peanuts Entertainment Launches With Mirabel Sisters Feature
Amílcar Franco has launched the London-based Peanuts Entertainment, a production company focused on developing Latin American stories
Peanuts Entertainment, London-Based Production Company Focusing on Latin American Stories, Launches With Mirabal Sisters Feature ‘Alive in Their Garden’ (EXCLUSIVE)
Peanuts Entertainment, a production company focused on developing what it describes as “culturally rooted Latin American stories for international audiences,” has launched in London. The new outfit ha...
SpaceX’s supersized Starship launches toward orbit for the first time
SpaceX has launched its enormous Starship toward orbit for the first time, aiming for six full laps around Earth to prove its readiness for NASA's Artemis moon program.
Al Akhawayn University, ICESCO Establish Ibn Battuta Center for Science Diplomacy
Al Akhawayn University in Morocco (AUI) and ICESCO announced the launch of the ICESCO Ibn Battuta Center for Science Diplomacy
KU School of Education & Human Sciences launches online master’s in higher education administration
The University of Kansas School of Education & Human Sciences is launching a fully online M.S.E in Higher Education Administration housed within the Department of Educational Leadership & Policy Studies. The program builds on KU's established in-person higher education administration graduate degree.
Anatomy IT Launches Health IT™ 360 Solution for Healthcare Leadership
/PRNewswire/ -- Anatomy IT, a leading managed service provider for healthcare, announces today the launch of Health IT™ 360, an innovative healthcare...
Starship Attempts Its First Launch To Orbit Today Carrying Big Dreams You Can Watch Take Flight
If the launch is successful, plans for humanity’s return to the Moon may look a touch less improbable.
Salesforce and Innovation City Launch AI-Powered Business Registration Platform
The new implementation combines AI platform capabilities powered by Salesforce with Innovation City's digital ecosystem, enabling businesses to access services and complete registration processes faster through more responsive interactions, while operating within Innovation City’s established governance and regulatory framework.
Mass. launched a program to stop school sports bullying. Why are so few schools using it?
A state government initiative started four years ago specifically to prevent hate and bias in athletics, called Addressing Hate in School Sports. Yet reports of such incidents remain common across the booming school sports landscape.
AMC Entertainment (AMC) Plans $3.97 Billion Refinancing. Can It Buy More Time?
AMC Entertainment Holdings, Inc. (NYSE:AMC) launched a $2 billion offering of first-lien notes due 2031 and an $850 million first-lien term-loan syndication on September 21. It also secured a conditional commitment for a $1.12 billion second-lien term loan, dependent on completion of the first-lien financing and other conditions. The proposed $3.97 billion package would replace […]
Adexo Advertising Surpasses 500 Active Businesses and $20 Million in Managed Ad Spend
MINNEAPOLIS, MN / ACCESS Newswire / September 28, 2026 / , a Minneapolis-based AI advertising platform that builds and optimizes Facebook and Google Ads for local and service-based businesses, today announced that it now serves more than 500 active businesses and has managed more than $20 million in advertising spend since launching in 2022.The milestone reflects growing demand among small and mid-sized businesses for advertising measured by qualified leads and booked jobs rather than clicks.
Haredi anti-draft march in Bnei Brak doubled as launch event for a protest political party
"In Netanyahu's Government of Evasion, the deserters are the heroes," Gadi Eisenkot claimed, dubbing the march "Netanyahu's walk of shame."
‘Your Mother Your Mother Your Mother’ Starts Strong, Eyes ‘American Fiction’-Style Rollout
Bassam Tariq’s Mahershala Ali-starring TIFF favorite Your Mother Your Mother Your Mother had a strong limited opening as distributor Amazon MGM launched the awards contender into a platform release he...
Spacecraft burns up in atmosphere after failing to rescue NASA telescope
The robotic spacecraft that failed to rescue an aging NASA telescope has plunged back to Earth, disintegrating in the atmosphere, less than three months after launching on the bold mission.
[Science Bulletin] KERI develops direct carbon coating technology for substrates
Korea Electric Research Institute grows graphene and graphite thin films at room temperature while MSIT launches safety inspections for semiconductor labs
White House airs another government-funded ad, this time with Trump warning of ‘final battle’
The Trump administration is set to launch another overtly political campaign ad funded by taxpayer dollars, attacking the “fake news media” and “the sick political class that hates our country.”
Amazon Just Knocked $900 Off Apple's Latest 16-Inch MacBook Pro
Amazon has introduced a major discount on the 16-inch MacBook Pro with the M5 Max chip, 32-Core GPU, 36GB RAM, and 2TB SSD, now available for $3,499.00, down from $4,399.00. This is a massive $900 markdown on the high-end MacBook Pro, and it's joining a few other MacBook Pro discounts on Amazon this week. Note: MacRumors is an affiliate partner with Amazon. When you click a link and make a purchase, we may receive a small payment, which helps us keep the site running.
South Brooklyn Health Launches New Bedside Recreation Program
Patients at South Brooklyn Health can now take part in creative activities, games and health education without leaving their hospital rooms.
Rogers Tries to Make El-Sayed’s Health Care Plan Scary
_Taylor, Michigan_HERE’S HOW YOU CAN TELL Mike Rogers is anxious to make up ground in the Michigan Senate race: He held a press conference on health care last weekend. Health care is usually a rough issue for Republicans, because voters associate the GOP with attacking cherished programs like Medicare and Medicaid that Democrats have historically supported. It’s a particularly difficult issue in this campaign, because a few months ago Donald Trump and the Republicans refused to extend temporary financial assistance in the Affordable Care Act. As a result of that decision, more than 20 million Americans faced higher insurance prices this year. That’s not a policy choice you want to be defending at a time when voters frequently cite the cost of health care as a top concern. Throw in the fact that Democratic nominee Abdul El-Sayed can draw on his credibility as a doctor and former public health director in Detroit, and it might seem like Rogers’s best bet would be to avoid health care altogether. But Rogers had his reasons to spotlight health care last Saturday. And they became apparent a few minutes before he spoke, when members of his campaign staff There’s a lot happening. Too much, some days. We can’t promise to have all the answers. But we can promise to keep asking the questions, following the facts, and figuring things out alongside people who care about where this country is headed. Read with us. Learn with us. And when it matters, stand with us. Join the side you’re already on. Join Bulwark+
Democrat José Javier Rodríguez launches 'Give 'Em Hell' statewide ad campaign in Florida AG race
The ad, released in both English and Spanish, centers on Rodríguez's background and career while sharply criticizing incumbent Republican Attorney General James Uthmeier.
AMC Entertainment Holdings (AMC), What Is Driving The Fresh Attention?
AMC Entertainment Holdings (AMC) has launched a major balance sheet reset, pricing US$2.0b in first lien notes, arranging new term loans, and running a cash tender offer to retire older secured debt. AMC Entertainment Holdings has seen momentum build through 2026, with a 90 day share price return of 44.83% and an 82.61% share price gain year to date, while the 5 year total shareholder return is still down 98.59%. Surf 16 high quality undiscovered gems that, like AMC Entertainment Holdings...
4D Wizard Of Oz Success Could Be A Game Changer For Sphere Entertainment Stock
Sphere Entertainment Co. reported that The Wizard of Oz at Sphere in Las Vegas has generated over US$500 million in ticket sales and 4 million tickets since its August 2025 launch, and recently introduced expanded 4D effects including animatronic Winged Monkeys, themed scents, scented apples, pyrotechnic fireworks, and “Glinda Glitter.” The scale of ticket revenue and attendance for The Wizard of Oz at Sphere, combined with continued investment in new 4D effects, suggests that Sphere...
Covington to launch pedestrian-friendly ‘Entertainment Destination Center ‘during Oct. 8-11 BLINK festival
Covington will launch an Entertainment Destination Center during BLINK 2026, creating a pedestrian-friendly environment where visitors can experience the festival while enjoying Covington’s…
2026 Beijing International Week for Science Literacy Launched in Beijing
PR Newswire | BEIJING, Sept. 27, 2026 /PRNewswire/ -- The 2026 Beiji
2026 Beijing International Week for Science Literacy Launched in Beijing
/PRNewswire/ -- The 2026 Beijing International Week for Science Literacy opened at the Beijing Science Center, running from September 22 to 26. Representatives...
MEDIMPACT DATA BREACH: Edelson Lechtzin LLP Launches Investigation Into Exposure of Social Security Numbers and Health Information
/PRNewswire/ -- Edelson Lechtzin LLP, a national class action law firm, is investigating data privacy claims arising from the MedImpact Healthcare Systems, Inc....
Meta Launches $1 Million Competition For "Hands-First" Apps Ahead Of VR Glasses
Meta launched a $1 million developer competition for new and updated "hands-first" Quest and VR Glasses apps.
New Open-Access Journal Puts Sustainable Polymers at the Center of Materials Science
Polymers are quietly the most successful materials story of the modern era, and the scientific community is now giving them a dedicated stage. Springer Nature has launched the Journal of Materials Science: Polymers, a new open-access title created to advance the science,
Hims & Hers Health (HIMS) Unveils AI Native Weight Loss Care Platform
Hims & Hers Health (NYSE:HIMS) introduced an AI native weight loss care platform built around a closed loop clinical system. The new offering uses continuous learning, real time monitoring, and automation to support clinician decisions within the weight loss program. Management positions the platform as a way to scale weight management services while aiming to keep safety controls embedded in workflows. The AI native weight loss care launch matters, but investors also need to weigh other...
Oscar Health (OSCR) Stock May Be Undervalued Following Its AI Marketplace Launch
Oscar Health has delivered very strong long term gains for shareholders, yet the recent pullback raises a simple question for anyone looking at the stock today: is the current price still in line with what its earnings can support? Over the past 3 years, Oscar Health has produced a very large share price return, which puts extra focus on whether its earnings can justify that kind of move. Management is talking about higher future earnings per share and better medical loss ratios, which can...
‘Charming and disarming’ … how Meta’s technology-packed Muse harnesses the power of cuteness
The tech giant has launched a cute ‘little guy’ that can answer emails, book travel or do your weekly food shop
Washington County Continues Commitment to Veteran Mental Health
Washington County Health and Human Services continues to strengthen its commitment to those who have served our nation by launching a free monthly Mental Health Skills Group designed specifically for …
Alaska to launch second funding round for Rural Health Transformation Program
The federal program is meant to produce long-term transformation, but strict rules are leading to short timelines.
Control Resonant becomes Remedy's top Steam launch, and even pirates are telling people to buy it
The game hit first place on the Steam bestseller chart with an 88 percent positive review score right out of the gate at its launch.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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US scientists launch workaround after Trump administration dismantles National Climate Assessment
Major scientific groups moved quickly to keep the work alive after the Trump administration dismantled key parts of the federal process behind the next National Climate Assessment.
US scientists launch workaround after Trump administration dismantles National Climate Assessment
When that system is interrupted, the consequences reach far beyond Washington.
Inside Meta's AI success and how Nat Friedman drove Muse's launch
Meta's Muse became an App Store hit after a rocky start for its AI team. Here's how Nat Friedman, new hires, and AI training turned things around.
T-Mobile is giving away the new Apple iPhone 18 Pro for free
Launch offers don't come any better than this.
San Joaquin County shelter opens new health and wellness center
Haven of Peace has launched the Roos Family Health and Wellness Center, providing isolation rooms to support women and children in need.
Facility where Presley Gerber died target of inquiry by California regulators
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Florida Department of Education launches B.E.S.T. science standards listening tour
This review of the B.E.S.T. Science Standards gives Floridians an opportunity to help shape the future of science and health education in Florida and establish a strong foundation built on knowledge, observation, inquiry, experimentation, evidence, and reason.
ProTributeBands.com Clarifies Direct Booking Model for Corporate Event Entertainment Planners
SAN RAMON, CA - September 25, 2026 - PRESSADVANTAGE -ProTributeBands.com, the curated booking and lead generation platform for high-end tribute bands, has outlined how its direct-booking structure works for event planners seeking corporate event entertainment. Under the model, bands featured on the platform negotiate terms and close each booking directly with the client, while ProTributeBands follows up to keep the transaction moving smoothly.The structure separates ProTributeBands.com from traditional booking agencies that insert themselves into every contract. Rather than acting as an intermediary that controls the final agreement, the platform connects event planners, performing arts centers, festivals, wedding clients, and private party hosts with pre-screened, national-act-caliber tribute acts, then steps back so the parties can settle details themselves. The platform maintains contact with both sides to ensure momentum is not lost during the process.Founded by David Victor, former guitarist and co-lead vocalist of the multiplatinum band BOSTON, ProTributeBands.com features tribute acts covering artists such as Queen, The Beatles, ABBA, Journey, The Eagles, and Pink Floyd. Selected bands receive optimized profile pages and booking leads generated through the platform."Event planners often assume a booking platform means another layer of negotiation and markup," said David Victor, Founder of ProTributeBands.com. "The approach here is different. The bands negotiate terms and close each booking directly, which keeps the conversation honest and the details accurate. The platform stays involved by following up so nothing stalls between the first inquiry and the signed agreement."The direct-booking method reflects how corporate and private event planning typically operates. Planners frequently need to confirm technical requirements, stage dimensions, scheduling, and performance specifics with the people who will actually be on stage. By allowing those conversations to happen between the client and the band, the model aims to reduce miscommunication that can occur when information passes through a third party.ProTributeBands.com applies a screening process before an act appears on the platform, focusing on production quality, musicianship, and readiness for larger venues. The company ranks tribute bands across categories including Queen, The Beatles, The Eagles, Journey, Pink Floyd, and BOSTON tributes, drawing on performance quality and audience response.The ProTributeBands guide to hiring a tribute band offers additional context for planners weighing these decisions, covering topics such as understanding the audience and event, assessing entertainment value, viewing an act in person before hiring, and reviewing rider and insurance requirements. The guide addresses the practical considerations planners face when selecting an act for a corporate function, festival, or private celebration."A tribute production for a corporate audience has to hold the room the same way a headline act would," Victor said. "The vetting exists so planners can trust that the act they see listed can deliver at that level, and the direct-booking structure lets them confirm every detail with the band before committing."ProTributeBands.com serves clients across the United States and abroad, working with tribute acts that perform at performing arts centers, summer concert series, product launches, corporate parties, private parties, and wedding receptions. The platform also accepts artist submissions from tribute bands seeking consideration for inclusion. The company operates online at protributebands.com.###For more information about ProTributeBands.com, contact the company here:ProTributeBands.comDavid Victor(925) 236-0217hello@protributebands.com11040 Bollinger Canyon Road Suite E-938, San Ramon, CA 94582
NASA teases new PRIMA telescope that could peer even deeper into the infrared universe than the James Webb Space Telescope
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The business case for pacing AI
Spacing out model launches and more efforts on safety could spur wider business adoption - if the political support is there.
Friday, September 25th: Wake Forest Mental Wellness Fair, Launch Family Entertainment, One Hit Wonder Day
Join Trent and Brea for a fantastic Friday show filled with area businesses and fun events.
Joe Neguse launches initiative to boost Democrats running statewide
Democratic Rep. Joe Neguse is sending volunteers into competitive Colorado districts, backing candidates challenging Republicans Lauren Boebert and Gabe Evans.
Wici Wireless eGPU Promises RTX 5060 Ti and 5090 Performance Over Wi-Fi 7
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University of Richmond receives record $150M gift
The University of Richmond received a record $150 million gift as it launches a $600 million fundraising campaign.
Sophie Cunningham wants a new nickname inspired by Patrick Mahomes
Sophie Cunningham jokingly claims a Patrick Mahomes-inspired nickname after launching a signed ball into the second deck.
José Javier Rodríguez launches multimillion-dollar ‘Give ’Em Hell’ statewide ad campaign
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AMD Takes the Lid off of Next-Gen EPYC 9006 Venice As Zen 6 Comes to Servers
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Control Resonant's post-launch plan includes a Photo Mode and New Game Plus Plus coming next month: "Do 665 runs if you want!"
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SCORE Iowa to launch statewide organization Oct. 1
Iowa’s existing SCORE chapters will consolidate into one statewide organization, effective Oct. 1, expanding access to business mentoring and educational resources for entrepreneurs and small businesses across all 99 counties. SCORE Iowa provides free, confidential, one-on-one mentoring by connecting entrepreneurs with volunteers whose experience matches their business needs, regardless of location. “Bringing our Iowa chapters…
How to submit your high school sports highlights to FLORIDA TODAY
The USA TODAY Network has launched a new portal that lets fans upload and share their athlete's best high school sports highlights.
Nelson University Launches Doctor of Business Administration Program
Nelson University has launched an online Doctor of Business Administration program with Christian business professionals in mind.
Apple has big October coming for new hardware and software, here’s the lineup
Apple has a big October ahead, with several major hardware and software launches coming. Here’s everything to expect from Apple in October.
Control Resonant Devs Officially Confirm Fans’ Most-Requested Feature Is Coming in Post-Launch Update
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5 Side Hustle Businesses That Cost Almost Nothing to Start
These side hustle service business ideas can largely be launched with your skills, contacts, internet access, and time.
RioMarket to feature a Tik Tok program and online business meetings
RioMarket to launch an app connecting film markets as it boasts strong presence of Asian countries
RioMarket to feature a Tik Tok program and online business meetings
RioMarket to launch an app connecting film markets as it boasts strong presence of Asian countries
Empath Health Unveils Dementia Education Program for Clinicians, Caregivers, First Responders
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Fox Sports Radio launches ‘College Football with Stugotz & The Bear’ podcast
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Gurucul Launches AI Risk and Response to Detect and Stop Risky AI Behavior Before It Escalates
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Microsoft unveils Copilot super app, targeting business users with AI agents
Microsoft is launching its super app as a central interface through which customers can chat with AI bots, write code, and access a new "Autopilot" feature that brings agentic capabilities to its flagship AI app.
Gears of War: E-Day Preload Times, Install Size, And Global Launch Dates
Start practicing your perfect reloads, because Gears of War: E-Day is almost here.
The Next Halo Game From Halo Studios Was Reportedly Still Years Away, Before Microsoft Handed the Franchise to Activision
The next Halo game from Halo Studios was reportedly still years away from launch before Microsoft canceled it this week.
Smith takes helm of Des Moines schools
A national search could have been launched by the Des Moines school board in its search for a new superintendent. Instead, the board turned to Matt Smith, an education leader with 16 years of experience in the district who brings a deep understanding of its challenges and a plan for its future. The Sept. 15…
'Soar' wars: Inside two AI startups' messy fight over a name
A founder known for viral antics sent a LinkedIn request to the CEO of Soar, a travel startup. Days later, he launched a rival — also called Soar.
North Carolina restores perinatal program after Medicaid funding dispute delayed research
Perinatal Quality Collaborative revives projects on newborn screenings and maternal mental health to launch in 2027, officials said.
Nebraska Department of Health and Human Services prepares to launch TANF pilot program in October
The Nebraska Department of Health and Human Services will launch a redesigned Employment First Program on Oct. 1 as part of a federal Temporary Assistance for Needy Families pilot.
Intelligence from Chinese groups aiding in Iran’s increasingly effective targeting of US sites, sources say
Satellite imagery and intelligence support provided by Chinese groups has helped Iran threaten ships in the Strait of Hormuz and launch precision strikes on US military bases in the Middle East, part of a dramatic improvement in Iranian targeting capabilities over the past several months, according to a series of recent American intelligence assessments described to CNN by four sources.
Can Genius Sports (GENI) Justify A Higher Valuation Following Prediction.com Launch?
Genius Sports (GENI) has moved further into the consumer arena with the launch of Prediction.com, a site that aggregates prediction markets and tracks how contract probabilities shift as events unfold. The launch of Prediction.com comes at a challenging time for Genius Sports’ shareholders, with the 30-day share price return down 27.04% and the year-to-date share price return down 46.20%, while the 1-year total shareholder return has declined 54.51%. However, the 3-year total shareholder...
Microsoft Copilot+ Branding Disappears from Latest Surface PCs
Microsoft's recent Snapdragon-powered Surface Laptop and Surface Pro launch was surprisingly absent the usual Copilot+ branding, aside from as a callout to the inclusion of the actual AI assistant on the devices. Apparently, this was an intentional branding change, according to Surface Corporate...
Des Moines University Medicine and Health Sciences Launches Doctor of
WEST DES MOINES, IOWA (September 24, 2026) — Des Moines University Medicine and Health Sciences has opened applications for its new Doctor of Medical Science program — the first of its kind in
What's up this week: Paly students' science book, political satire sketch show, '90s rockers, a PBS travel host and more
This week, Paly students launch a science-focused children's picture book; Molly Tuttle plays Stanford Live; former lovers reunite at The Pear; Los Altos Stage Company skewers current events and more.
What’s up this week: Paly students’ science book, political satire sketch show, ’90s rockers, a PBS travel host and more
This week, Paly students launch a science-focused children's picture book; Molly Tuttle plays Stanford Live; former lovers reunite at The Pear; Los Altos Stage Company skewers current events and more.
Not just physics: Quantum to make business case at Chattanooga conference
EPB knows most businesses don't have a clear idea of how quantum technology could be useful to them. That's why the Chattanooga utility is hosting its inaugural "Quantum in Business" conference.
ARTSwork announces new Invitational Art Fair
ARTSwork, the sister organization of the Des Moines Arts Festival, will launch a new fall event, the Invitational Art Fair, Nov. 6-7 at the Val Air Ballroom in West Des Moines. The two-day event will feature 50 professional Iowa visual artists showcasing and selling original works, including ceramics, glass, jewelry, photography, printmaking and sculpture. The…
Google rolling out Android 17 QPR2 Beta 6 for Pixel
Android 17 QPR2 Beta 6 is now available for Pixel devices, barely a week after Beta 5 launched. Beta 6...
Mamdani opens Met Opera to new audiences with 70,000 free tickets
Mayor Zohran Mamdani launched "Opera For All" with The Met Opera, providing free tickets to bring new audiences to performances.
Aurora police launch initiative to prevent crime at local businesses
Aurora Police Department launched an initiative at the beginning of the month intended to strengthen relationships with local businesses to prevent crime.
Entire Prince of Persia: The Lost Crown Game Available to Play for Free in Nintendo Switch Demo, But There’s a Catch
Players who haven’t yet experienced Prince of Persia: The Lost Crown can play the entire game for free right now on Nintendo Switch and the Nintendo Switch 2 until September 30.
The Division's New Release is Going Up Against Zelda
The Division 2: Echoes of Central Park launches in November with a new story set in Central Park and the Upper West Side.
Emory launches Center for Civic Reasoning to foster constructive dialogue
Emory University’s new Center for Civic Reasoning will prepare students for democratic citizenship through courses that study how to engage in constructive disagreements around issues related to politics and daily life.