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State health officials investigate Novi death, illnesses after dialysis
Police say no evidence of foul play in death, sicknesses following dialysis at DaVita.
Brad Stevens discusses ‘excitement’ surrounding Chris Cenac Jr.
“I hope we’re good enough that it’s hard for any 18-year-old or 19-year-old to come in here and be really good out of the gate.”
Another look at carrots and eyesight; how to get more fiber; why mosquitoes bite some people and not others; plus other stories with Vanderbilt Health sources
AARP reporter Stacey Colino interviewed Milam Brantley, MD, Associate Professor of Ophthalmology and Visual Sciences, in 2020 for a story about whether eating carrots can improve vision. Sacramento Bee reporter Samantha Agate has now used Brantley’s comments in an AI-curated story created by content specialists on the same topic that has been picked up by MSN and others. Prevention magazine interviewed Heidi Silver, RD, PhD, Founding Director of the Vanderbilt Diet, Body Composition, and Human Metabolism Core, for a story about the importance of fiber and how people can get more of it in their diet. William Schaffner, MD, Professor of Preventive Medicine, was quoted by several news outlets about public health issues, including: Women’s Health (tick bites and alpha-gal syndrome); The Washington Post (tetanus); and Healthline (why mosquitoes prefer to bite some people and leave others alone). A visit to Monroe Carell Jr. Children’s Hospital at Vanderbilt by some Banana Ball baseball players was covered by The Tennessean and WZTV Fox 17 News, and The Tennessean’s story was also picked up by Yahoo! Sports. Clarksville Now published a story written by the Montgomery County Economic Development Team, whointerviewed Bradley Stancombe, MD, professor of Clinical Pediatrics, Vanderbilt Neonatology, about the new energy of Vanderbilt Clarksville Hospital and how the facility is recruiting physicians. Healio Allergy/Asthma group editorial director Richard Gawel interviewed Mark Rolfsen, MD, Clinical Fellow in the Division of Allergy, Pulmonary and Critical Care Medicine, for a story about his presentation at the American Thoracic Society meeting on metal health outcomes following ICU discharge. Nashville Scene reporter Hannah Herner interviewed James Crowe, MD, Director of the Vanderbilt Center for Antibody Therapeutics, for a story about his efforts to prepare for the next pandemic by isolating antibodies that can neutralize dangerous viruses. Medscape reporter Kathleen Doheny interviewed Neesha Choma, Associate Chief of Staff of Vanderbilt University Hospital, for a story about how hospitals can reduce readmissions.
AMC Entertainment Holdings, Inc. Announces Closing of $200 Million Registered Direct Offering of Common Stock
LEAWOOD, Kan., June 25, 2026--AMC Entertainment Holdings, Inc. (NYSE: AMC) ("AMC" or "the Company"), announced today that it closed its previously announced registered direct offering of an aggregate of 95,250,000 shares of AMC common stock for gross proceeds of approximately $200 million (the "Offering"), before deducting agent fees and offering expenses.
Who gets to decide Colorado’s economic future?
By Sarah Blackhurst Colorado’s prosperity depends on industries that grow our food, build our future and power our homes. But today, these sectors face an invisible threat from 5,000 miles away: the European Union’s Corporate Sustainability Due Diligence Directive (CS3D). This foreign regulation requires companies to mitigate environmental and human-rights effects throughout their entire global […]
Department of Education investigates Maryland schools over boys access to girls sports and facilities
The U.S. Department of Education has launched an investigation into Maryland's Department of Education and three public School districts, claiming that boys are joining girls athletic teams and accessing girls facilities.
Mercy Helps Position St. Louis as Global Gateway for Healthcare Innovation
Mercy continues to bring innovative thought leadership to the communities it serves and beyond. Dr. Damon Broyles, Mercy vice president of clinical innovation, informatics and precision medicine, recently shared insights and helped attract new companies to St. Louis’ nationally recognized healthcare industry as part of BioSTL.
New Patient Guidebook Helps Puget Sound Beneficiaries Navigate Their Health Care
MADIGAN ARMY MEDICAL CENTER, Joint Base Lewis-McChord, Wash. -- Great news for military communities and TRICARE beneficiaries across the Pacific Northwe...
Police investigate after protests at skincare business
Accused of aggression, skincare sellers at center of demonstration, town ordinance, allege antisemitism.
Fire at Whiteaker business now being investigated as arson
KVAL CBS 13 is the news, sports and weather source for Eugene, Oregon and nearby communities, including Springfield, Santa Clara, Coburg, Pleasant Hill, Creswell, Churchill, Alvadore, Marcola, Dexter, Thurston, Junction City, Brownsville, Harrisburg, Alvadore, Veneta and Alpine.
AHA’s refreshed Rural Health Services website features resources to strengthen results and long-term viability
The refreshed AHA Rural Health Services website gives rural hospital leaders quick access to the advocacy insights, strategic resources and field-informed guidance they need to navigate change, strengthen performance and sustain care in their communities.
Trump alleges gas price gouging, calls for DOJ investigation
President Donald Trump alleged that customers are facing fuel price gouging and said that he had ordered the Justice Department to investigate.
New Guidebook Helps Puget Sound Beneficiaries Navigate Their Health Care
Great news for military communities and TRICARE beneficiaries across the Pacific Northwest: navigating military healthcare just got easier. The recently released Puget Sound Patient Guidebook is a comprehensive resource designed for local TRICARE beneficiaries throughout the region. Inside, beneficiaries can find information on enrolling in the Defense Enrollment Eligibility Reporting System, understanding TRICARE plans, locating a Military Treatment Facility (MTF), scheduling appointments, accessing online services, ordering medications and much more.
Bill Gates: Jeffrey Epstein used billionaire connections to get to me
Bill Gates told Congress that Jeffrey Epstein wormed his way into his life with "veiled threats" to disclose extramarital affairs.
Family says they tried to get man mental health help before alleged beating
Kenneth Flagg's family says they tried to get him mental health help hours before prosecutors say he beat a PA inside a hospital. 12 News Investigates obtained new video of the encounter.
Oracle Backend for Microservices and AI: The Business Value of a Microservices Backend Platform
Discover how Oracle Backend for Microservices and AI (OBaaS) 2.1.0 provides a shared backend foundation for microservices and AI-enabled applications, helping teams standardize gateways, observability, messaging, configuration, workflow coordination, and Oracle AI Database integration.
The Best Prime Day SSD and HDD Deals From Samsung, Seagate, WD, and More
After months of RAM-related price hikes, now is the best time to score deep discounts on SSDs and hard drives on Amazon Prime Day.
Polymarket allegedly faked trades. Chances are slim Trump admin investigates, says sports-betting attorney
A recent Wall Street Journal investigation found that the prediction market hired influencers to stage fake trades as part of its marketing campaign to attract U.S. users.
Man arrested 9 years after business manager killed outside Charlotte shop
The deadly shooting happened on Fugate Avenue in August 2017.
AI's new power brokers: CFOs
As companies pour billions into AI, CFOs are the gatekeepers of one of corporate America's biggest spending booms.
Is Lowe's (LOW) Entertainment-Focused Loyalty Push a New Edge in Customer Engagement?
Lowe's Companies, Inc. recently announced a multi-year partnership with Live Nation Entertainment to offer MyLowe's Rewards and MyLowe's Pro Rewards members exclusive live music benefits, including concert perks and amphitheater tailgate experiences at select venues starting this summer. This expansion of the loyalty program into entertainment experiences highlights Lowe's effort to deepen customer engagement beyond the store and into members' leisure time. Next, we’ll explore how this...
Listening for quantum oscillations in the Kondo insulator YbB12
Magnetic quantum oscillations have been unexpectedly observed in insulators, where freely moving charge carriers are not expected to exist. A joint study by researchers from Tokyo University of Science, The University of Tokyo, and Kobe University investigated this puzzling behavior in the Kondo insulator YbB12 using ultrasound. While no oscillations were detected in the insulating state, clear signals emerged after the material became metallic, offering new insight into unusual quantum behavior in next-generation materials.
Atlanta businesses seeing benefits from international visitors, police presence during World Cup
World Cup fever is filling the stands at Mercedes-Benz Stadium, but just outside the gates, local businesses are seeing the impact up close.
Judge blocks use of database to check citizenship in voting
The judge ruled that the system aggregated Americans' sensitive personal data in a way that could result in voters being wrongly purged from voter rolls
Judge blocks use of database to check citizenship in voting
The judge ruled that the system aggregated Americans' sensitive personal data in a way that could result in voters being wrongly purged from voter rolls
Jelly Roll addresses divorce from Bunnie XO: 'Nobody cheated on nobody'
The former couple revealed in February that they had secured a surrogate after years of fertility struggles.
Sam Altman's Orb startup investigated financial misconduct allegations
Tools for Humanity hired two law firms to investigate alleged financial irregularities and bribery of foreign officials, sources say.
Air Force award supports research on electronics that can survive extremes
Betul Akkopru-Akgun, assistant research professor in Penn State's Department of Materials Science and Engineering and the Materials Research Institute, has received an Air Force Office of Scientific Research Young Investigator Program award to investigate how electricity and heat move through materials used in extreme environments.
Amazon, AI and local media at 617 Day small business summit
Speakers were optimists about how small businesses can navigate business and technology trends.
Opinion | Menopause and the Failure of Women’s Health Care
Readers respond to “Menopause Should Not Be Such a Mystery,” an Opinion guest essay by Melinda French Gates.
The Would-Be Intelligence Chief Caught Between Trump and Congress
Jay Clayton is a versatile team player who has deftly navigated the Justice Department but is now in limbo regarding two jobs.
The power of delegates: How Indiana Republicans pick statewide nominees
Every two years, Indiana Republicans gather for their state convention to nominate candidates for statewide office. In midterm election years, delegates choose the party’s nominees for secretary of state, treasurer
New Clinic for Low-Income Women and Children to Open Near Gresham
The county says the new clinic is double the size of Gateway location it is replacing.
Video: How a New York Politics Reporter Sets Priorities
Nicholas Fandos explains how he navigates coverage of the primary races this month and what he’s watching in New York politics.
Fresno City Attorney investigates unpaid wage claims after local BBQ business shuts down
Health Ministry investigates suspected Ebola case after traveler develops symptoms
Israel’s Health Ministry is investigating a suspected Ebola case after a traveler returning from the Democratic Republic of Congo developed fever and headache.
Get Real With SOMD Politics: Delegate Matt Morgan Focuses On Taxes, Housing And Protecting Southern Maryland’s Rural Character
ST. MARY’S COUNTY, Md. — Republican Delegate Matt Morgan says rising taxes, government overreach and housing affordability remain among the most pressing issues facing Maryland residents as he seeks another term representing District 29A in the Maryland House of Delegates, according to a recent appearance on The BayNet’s podcast, “Get Real With Southern Maryland Politics” […]
The MacRumors Show: Hands-On With iOS 27, Brutal watchOS 27 Cuts, and More
On this week's episode of The MacRumors Show, we continue unpacking WWDC 2026 and take a closer look at iOS 27, macOS Golden Gate, and Apple's other new software updates coming this fall. Subscribe to The MacRumors Show YouTube channel for more videos iOS 27 supports the same iPhones as iOS 26, including the iPhone 11 and second-generation iPhone SE, giving the update the widest device compatibility of any iOS release to date.
Earthshine: imaging the Moon for science
This image is part of a series captured by ESA astronaut Sophie Adenot for the European Earthshine experiment, which investigates whether we can measure how much sunlight Earth reflects by using the Moon as a natural projection screen.
The next step in your career might be becoming your own boss
It's still a tough job market to navigate. Entrepreneurship may be your best bet.
Mercedes release statement on withdrawing Monaco podium appeal
Mercedes confirmed that it has withdrawn its Right of Review request concerning the penalties George Russell received and served during the Monaco Grand Prix, explaining the reasons behind its decision to drop the appeal. The team disclosed that it had initially explored every available avenue to mitigate the impact of Russell's pit lane speeding penalty on his final result, particularly after Pierre Gasly's time penalty was overturned.
A brain-computer interface has, for the first time, restored fluent everyday speech to a person who had lost it — a man with ALS who had not spoken aloud in years until a small implant from the BrainGate clinical trial began translating his attempts to speak directly into computer-synthesised words, in a result researchers reported in June 2026
Casey Harrell can now talk for twelve hours at a stretch. Two years ago, he could not talk at all. The ALS he was diagnosed with several years earlier had progressively destroyed the motor neurons controlling the muscles of his face and throat, leaving him with the symptoms doctors call dysarthria and, eventually, anarthria — […]
The Politics Hour: A historic D.C. primary election and Montgomery County voting on new leadership
We break down D.C. primary elections with Democratic nominee for D.C. Delegate Robert White, At-Large Councilmember-elect Elissa Silverman, and WAMU's D.C. politics reporter Alex Koma. Plus, we preview Maryland's primaries with WAMU's Maryland reporter Jenny Abamu.
UNC Health proposing 92-bed hospital on 22 acres at Westgate Shopping Center
UNC Health is proposing a 92-bed, acute-care hospital and according to a map of the location provided by UNC Health, the hospital would be at Westgate.
The unwanted return of tetanus; why soccer makes people so happy; breast cancer in men; plus other stories with Vanderbilt Health sources
Women’s Health interviewed Kathryn Edwards, MD, Sarah H. Sell and Cornelius Vanderbilt Professor of Pediatrics, for a story about her JAMA Viewpoint article on tetanus making a comeback. Women’s Health interviewed Colin Armstrong, PhD, Assistant Professor of Clinical Psychiatry and Behavioral Sciences and Assistant Professor of Physical Medicine and Rehabilitation, for a story tied to the World Cup about why soccer makes people so happy. An NBC News story about the announcement by “X-Men” actor and former wrestler Tyler Mane that he has breast cancer quotes Ben Ho Park, MD, director of the Vanderbilt-Ingram Cancer Center. The story focuses on how a prominent man with breast cancer may help remove some stigma from a cancer that is rare in males. Prevention magazine interviewed Caitlyn Mooney, MD, Assistant Professor, Department of Orthopaedic Surgery, for a story about a BMJ study that suggests 90 to 120 minutes per week of strength training may lower the risk of death. William Schaffner, MD, Professor of Preventive Medicine, was quoted by several news outlets about public health issues, including: Women’s Health (norovirus is more common this summer); SFGate (measles in San Francisco just before the World Cup crowds); Travel + Leisure (how to avoid getting sick on a cruise); and Fox News (mosquito-borne diseases). Reporter Liz DeSantis from WKRN News 2 aired a story on the rehab unit at Monroe Carell Jr. Children’s Hospital at Vanderbilt. Kat Hedden, PT, DPT, PCS, CBIS, Acute Pediatric Physical Therapy Clinical Team Lead and Mary McLanahan, MD, Assistant Professor of Physical Medicine and Rehabilitation were interviewed, as well as the family of patient Will Terry. Reporter Nikki Hauser from WTVF News Channel 5 interviewed Graden Knapp, Gaming and Technology Specialist at Monroe Carell Jr. Children’s Hospital at Vanderbilt about his 3-D wheelchair project. Tennesseanreporter Sandy Mazza covered the announcement of the latest Leadership Nashville class, which includes Jane Freedman, MD, Deputy CEO, and Chief Health Systems Office for Vanderbilt Health; and also the announcement of the latest Leadership Tennessee cohort, which includes Jeff Upperman, MD, Surgeon in Chief at Monroe Carroll Jr Children’s Hospital at Vanderbilt.
Best place I've ever visited is in Vietnam: Hoi An, things to do
The best place my family visited is Hoi An, Vietnam. The affordable city has great craft villages, activities for all ages, and is easy to navigate.
A Wild Rumor Linked To Sundar Pichai Suggests Google Is “Evaluating” The Procurement Of Memory Chips From China’s CXMT
Google's move might upend the monopolistic dynamics in the memory sphere by opening a floodgate of similar DRAM deals with CXMT.
Businesses, commuters adjust for two-year Fort Bragg gate closure
The repairs to the All-American Freeway and the replacement of the Gruber Road Bridge are necessary investments, a Fort Bragg spokesperson said.
Jonathan Weber’s 'City on the Edge' Chronicles Decades-Long Battles Over Tech, Politics and the Soul of San Francisco
Weber tells the story of a war waged for the heart of San Francisco that has had an impact far beyond the city’s famed Golden Gates.
DC voters face a new political era without Eleanor Holmes Norton, after her 18 terms in Congress
For the first time in a generation, Washingtonians are waking up to a general election lineup that doesn’t include Eleanor Holmes Norton as delegate
Dems pick potential successor to DC's congressional delegate after decades-long incumbency
An at-large D.C. council member won the Democratic primary Tuesday for the district's non-voting House seat after Eleanor Holmes Norton's retirement.
'The system is critically stressed': San Andreas and San Jacinto faults scarily close to major earthquake, study finds
The San Andreas fault and a neighboring fault in Southern California have reached their highest levels of tectonic stress in 1,000 years, and a rupture at one fault could propagate to the other, researchers found.
Building trust and flexibility in small-business financing
Discover the importance of speed, trust, and flexibility in small-business deals. Learn how to navigate the challenges of financing and find the right fit.
Rice STEM-Letics camp turns sports into gateway for engineering
STEM-Letics, a summer camp hosted by Rice’s Center for STEM Engagement and Rice Athletics, introduces students in grades three through five to science, technology, engineering and math through sports and hands-on activities.
Washington, DC, voters cast ballots in crucial primaries as Trump reshapes the capital
Voters in Washington, D.C. are heading to the polls to select party candidates for mayor and congressional delegate
Pirate Problems: What Quarterback Will Buccaneers see Against Vikings?
As Minnesota navigates a brutal opening stretch, Tampa Bay prepares for a dual threat: veteran Kyler Murray’s resurgence or the raw potential of former first-rounder J.J. McCarthy.
Modernizing Front Desk Operations In Health And Wellness Practices
An administrative pain-point for patients and practices alike, agentic AI platforms are creating a seamless process to navigate health and wellness.
Modernizing Front Desk Operations In Health And Wellness Practices
An administrative pain-point for patients and practices alike, agentic AI platforms are creating a seamless process to navigate health and wellness.
Woman says popular oil change business destroyed her engine
Channel 2 Action News Investigates has reported similar cases for years.
Epstein survivors push Comer to investigate potential leads from DOJ’s files in private meeting
In a private meeting last week, a group of survivors of Jeffrey Epstein’s abuse and family members of the late Virginia Giuffre pointed House Oversight Chair James Comer to allegations from the Justice Department’s Epstein files to further investigate, arguing that acting Attorney General Todd Blanche’s suggestion there were no more leads to pursue in the case is not true.
California Gov. Gavin Newsom says Trump's Justice Department is investigating him and his wife
California Gov. Gavin Newsom, a Democrat and longtime political rival of Republican President Donald Trump, said Monday the president ordered the Justice Department to investigate him and his wife.
BioSTL Builds Gateway for U.K.'s National Health Service Innovators with St. Louis as Launch Point into U.S. Market
BioSTL Global, the international arm of BioSTL, the backbone of the region's bio-innovation ecosystem, has reached an agreement with the innovation network commissioned by the U.K.'s National Health Service (NHS) that promises to attract new companies to St. Louis' nationally recognized healthcare industry.
Weird Science: Historian uses carbon dating to show N.C.'s most enduring mystery isn't so mysterious
For nearly a century, American school children have been taught the same haunting mystery. In 1587, a group of English colonists landed on Roanoke Island. Then, they vanished, leaving behind only one cryptic clue carved into a wooden gatepost: the word "Croatoan."In this edition of Weird Science, Public Radio East's Annette Weston spoke with a Buxton native who is using science to dispel what he said is the myth behind the truth.
Weird Science: Historian uses carbon dating to show N.C.'s most enduring mystery isn't so mysterious
For nearly a century, American school children have been taught the same haunting mystery. In 1587, a group of English colonists landed on Roanoke Island. Then, they vanished, leaving behind only one cryptic clue carved into a wooden gatepost: the word "Croatoan."In this edition of Weird Science, Public Radio East's Annette Weston spoke with a Buxton native who is using science to dispel what he said is the myth behind the truth.
4Wall Entertainment Welcomes Trey Kerr As VP Of Music Production
Trey Kerr, longtime broadcast and video director for Phish and recent CEO of Gateway Production Services and Studios, has joined 4Wall as VP of | Trey Kerr, longtime broadcast and video director for Phish and recent CEO of Gateway Production Services and Studios, has joined 4Wall as VP of Music Production.
Health under the Global Gateway: achievements and future prospects
The EU has increasingly positioned global health as a strategic component of its external action through the EU Global Health Strategy and the Global Gateway in
The next mayor of DC will have to navigate its most famous resident: President Donald Trump
Janeese Lewis George, a Washington, DC, councilmember and leading candidate for mayor, was knocking on doors when her team got word that President Donald Trump said he wouldn’t “put up with it” if the democratic socialist wins her Tuesday primary.
The quiet, galactic ambitions of Cursor CEO Michael Truell
How the hottest AI coding company navigated its situationship with Anthropic and hitched its fate to Elon Musk's chaotic rocket.
Why Marketing Feels Harder as Your Business Grows by Nathan Tayloe
At some point, most growing businesses hit the same moment. What used to feel straightforward starts to feel more complicated. Marketing takes more effort. Results feel less predictable. What once worked consistently begins delivering mixed outcomes. It is easy to assume something is broken. In many cases, nothing is. The business has simply reached a different stage. What Worked Before Starts to Lose Its Edge Early on, growth is often driven by a few things working well at the same time: Referrals are strong The value of the offering is clear The team is aligned Decisions are made quickly Marketing, in that stage, tends to feel easier because the business itself is easier to understand. As the company grows, that simplicity fades. The audience expands. Services evolve. New people join the team. More channels are added. More decisions are made across more touchpoints. Marketing is no longer communicating one clear story. It is trying to represent a more complex business. Complexity Creates Friction That added complexity does not always show up immediately. It builds over time. Messaging starts to drift. Different parts of the business describe what they do in slightly different ways. The website no longer reflects how the company actually operates. Sales conversations evolve faster than the brand. At the same time, more activity is introduced to try to keep growth moving: New campaigns More content Additional platforms More tools and reporting The volume increases. The clarity does not always keep pace. That is when marketing starts to feel harder. It’s Not a Lack of Effort Most teams respond to this stage by doing more. More output More meetings More adjustments More experimentation That effort is not misplaced. It is often pointed in the wrong direction. When the underlying issue is a lack of alignment, more activity tends to create more noise. Results become harder to interpret. Decisions take longer. Progress feels inconsistent. From the outside, everything looks active. From the inside, it feels less certain. The Real Shift As businesses grow, marketing becomes less about execution and more about alignment. The companies that navigate this transition well tend to refocus on a few fundamentals: A clearly defined audience A strong, consistent position in the market Messaging that reflects how the business actually operates Alignment between leadership, marketing, and sales When those elements are in place, execution becomes more effective again. Marketing does not necessarily become easier, but it becomes more consistent. A Different Kind of Discipline Growth introduces more opportunity, but it also demands more discipline. What worked when the business was smaller often cannot be scaled without adjustment. The systems, messaging, and decision-making that once felt intuitive need to become more intentional. That is not a sign of failure. It is a normal part of growth. Marketing feels harder because the business has become more complex. The solution is not to outwork that complexity. It is to bring clarity to it. The companies that do that well tend to regain momentum quickly. Those who do not often stay busy without seeing the same level of progress. — Learn more about how we help organizations align strategy, brand, and execution. Visit tayloegray.com, or reach out directly at nathan@tayloegray.com.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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WHO urges targeted action to strengthen emergency workforce capacities for shared health risks across the Asia-Pacific region
At a time when the world is more interconnected than ever, the World Health Organization (WHO) is disseminating a comprehensive regional analysis of shared health risks across Asia and the Pacific, urging Member States to invest in enhancing workforce capacities regionwide to mitigate these risks and ensure health systems are better prepared to anticipate, tackle and withstand a range of crises and shocks. Over 100 delegates from 49 countries and areas in the Asia-Pacific region reviewed results from the regional risk analysis during the WHO-led Asia Pacific Health Security Action Framework (APHSAF) Stakeholders Meeting in Malaysia. Synthesizing insights from 21 strategic risk assessments and more than 800 multisectoral experts, the regional analysis highlighted an urgent imperative: countries must proactively invest in emergency workforce preparedness to navigate a landscape where climate hazards, disease outbreaks and geophysical events increasingly overlap. These complex converging crises create devastating, compounding impacts on health systems and communities – reiterating the need for investing in a fit-for-purpose regional health workforce and multisectoral action.Key findings: an evolving risk landscape More than half of the participating countries ranked flooding, cyclones, dengue and pandemic-potential respiratory pathogens as being of high or very high risk, while antimicrobial resistance, landslides and gastroenteritis remain widespread concerns as well. “Given that 51% – over half – of these assessed hazards are deeply interconnected, isolated health interventions are no longer sufficient,” said Dr Saia Ma’u Piukala, WHO Regional Director for the Western Pacific. “Extreme weather events like cyclones and floods directly trigger subsequent disease outbreaks, while environmental degradation – driven by sea-level rise, coastal erosion and saltwater intrusion – fuels health risks across the Pacific. Mitigating these cascading risks requires unified, cross-sectoral action linking environmental, agricultural and public health policies to build true regional resilience.” Priority recommendations for action To address critical vulnerabilities, WHO calls on Member States in the Asia-Pacific region to urgently prioritize the following strategic actions: Bridge workforce capacity gaps. Embed and standardize emergency preparedness within academia to promote regional workforce interoperability. Foster multisectoral coordination. Address ad-hoc taskforce responses and fragmented surge support through formalized contingency plans and standard operating procedures that are frequently updated and tested. Secure sustainable financing for emergencies. Overcome systemic barriers to access dedicated funding for both immediate anticipatory actions and long-term emergency preparedness initiatives. Enable emergency-ready primary health care. Embed emergency management into public health workforce readiness planning. Ensure that emergency planning is inclusive. Establish clear pathways for inclusive emergency planning that actively involves communities most at risk and other vulnerable groups. Optimize communication. Update risk communication and community engagement strategies, aligning them with seasonal risk calendars. Elevating workforce readiness to meet regional health risks While the gaps identified are significant, the Asia-Pacific region possesses solid foundational pillars, including dedicated clinicians, laboratory staff, rapid response teams, emergency medical teams and extensive community networks. However, to adequately address the compounding nature of modern crises, the various components of the emergency workforce must collaborate cohesively. True resilience depends entirely on transforming this currently fragmented workforce into a highly trained, interconnected and rapidly deployable asset. To achieve this, WHO is actively advancing regional workforce capacities through the Global Health Emergency Corps initiative. This initiative – supported by the Gates Foundation and the Institute of Philanthropy – seeks to build a seamless network of emergency workforce across borders and sectors, ensuring that when a crisis strikes, a standardized, well-coordinated and trained workforce is immediately ready to respond. “Scaling up emergency workforce readiness is no longer optional,” said Dr Gina Samaan, Regional Emergency Director for WHO in the Western Pacific. “It is the definitive factor that will determine how effectively the Asia-Pacific region safeguards health and protects lives in an increasingly unpredictable future.” ____________________For more information, or to arrange media interviews, contact: Ara Johannes, WHO Western Pacific Health Emergencies Division: johannesa@who.int WHO Western Pacific Communications: wprocom@who.int