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The Would-Be Intelligence Chief Caught Between Trump and Congress
Jay Clayton is a versatile team player who has deftly navigated the Justice Department but is now in limbo regarding two jobs.
Minisforum’s Upcoming MS-03 SFF PC Brings More of a Good Thing
At Computex 2026 Minisforum was showing off their upcoming MS-03 mini-PC, the successor to their popular MS-01 and aiming to bring more of a good thing with Intel's new Panther Lake platform
Every new iOS 27 feature that's worth knowing about
While it's not flashy like Apple’s new Siri AI and Apple Intelligence upgrades, there are still a number of additions to iOS 27 worth looking at.
Israel Is Likely to Continue Attacks in Lebanon, U.S. Intelligence Concludes
The new cease-fire between the United States and Iran calls for an end to fighting in Lebanon, but U.S. intelligence officials do not expect Israel to halt its strikes on Hezbollah.
Real Estate Is Still a People Business
Unless you’ve been avoiding the internet for the past few years, you’ve probably noticed that artificial intelligence is everywhere. From customer service chatbots to content creation and personal assistants, AI is reshaping how people work, communicate, and access information. Real estate is no exception. Buyers, sellers, and real estate professionals are incorporating AI into their […]
Tensions rise with Trump and Republican senators ahead of midterms
The relationship between President Trump and Senate Republicans seems to be nearing a breaking point after Trump upended Republicans efforts for a swift confirmation of his intelligence nominee and as he thwarted quick passage of a bill to renew a surveillance law.
‘Stranger Things,’ ‘Emily in Paris’ Outperform IP Rivals in Dentsu Fandom Intelligence Study
Streaming titles including “Stranger Things,” “Emily in Paris” and “Wednesday” outperform the average across all entertainment IP tested by 30% when it comes to converting fans into buyers, according ...
Trump’s new acting intel chief Bill Pulte arrives early, eyes firing hundreds
President Donald Trump’s pick for acting director of national intelligence, Bill Pulte, showed up at his new job a day early on Thursday after asking for a list of every employee in the office so he could assess whether to fire them, two sources familiar with the matter told CNN.
Warner says Iran war is driving up Virginia costs, warns Trump is playing politics with intelligence post
Senator points to higher fertilizer and energy prices, touts housing bill and warns of risks to elections and kids online
The Healthcare Leaders Shaping Tomorrow – and the Challenges Facing Them
Healthcare innovation is advancing at a pace few could have imagined decades ago, from gene-editing therapies and lifesaving vaccines to artificial intelligence systems that could transform how doctors diagnose and treat disease. But at a time of unprecedented scientific progress, industry leaders ...
Intel's stock levels mean investors believe its foundry business will succeed: Bernstein's Rasgon
Stacy Rasgon, Bernstein, and Dan Ives, Wedbush Securities, join 'Power Lunch' to discuss Intel's prospects of building chips in the U.S., Apple price increases and much more.
The businesses that are doubling down on Seattle
As critics warn of an antibusiness climate in Seattle, the startup artificial intelligence industry is bullish on the city's talent.
New GTA 6 Gameplay Footage Reveals Stunning Vice City Details
Rockstar Games have just released a new look at GTA 6. Alongside the GTA 6 cover art reveal and pre-order date confirmation, Rockstar Games have provided fans with just snippet of in-game footage.…
Hospital and health system leaders participate in Healthcare of Tomorrow Conference
Hospital and health system leaders gathered June 17 and 18 in Washington, D.C., for U.S. News & World Report’s Healthcare of Tomorrow Conference, focusing on the future of healthcare delivery.
Trump pulls intel nominee, demands voting law
Trump canceled the nominee’s hearing hours before it was set to start
SEC-Big Ten war is real, and Kentucky's new AD may just shift the power
J Batt was a 'game-changer' for Michigan State. Now, Kentucky's new AD may have the inside intel to change the power structure between SEC, Big Ten.
Intel Stock Jumps On Reported Apple Chip Business
Intel stock jumped after U.S. President Donald Trump said Apple has reached a chip manufacturing deal with Intel.
Architect Labs raises $24 million to take on Broadcom, Marvell custom chip business
Architect Labs said on Thursday it had raised $24 million in seed funding to build a company that will use artificial intelligence to speed and ease the design of custom chips.
Can AI help us age better? These scientists are trying to find out
A growing number of researchers are turning to artificial intelligence to understand why some people remain healthy into their 90s while others develop chronic diseases decades earlier. At labs throug...
Dentsu Expands Fandom Intelligence Globally to Guide Brand Partnerships in Entertainment
Little Black Book, Platform, first created in 2020, combines Japanese fandom data with new proprietary research across the US, UK, India and the Greater China market, covering 200 entertainment titles and more than 21,000 fans
Microsoft Makes Big AI Inroads in China by Selling OpenAI Models
Microsoft Corp. has built a big business selling AI models to Chinese companies despite the growing rivalry between the US and China over artificial intelligence.
DC Wrap: Iran deal details emerge; Trump stalls his own intel pick
A look at the day's biggest stories in national politics
DC Wrap: Iran deal details emerge; Trump stalls his own intel pick
A look at the day's biggest stories in national politics
iPadOS 27 Hands-On: Everything New for iPad
Like iOS 27, iPadOS 27 gains a smarter, more capable version of Siri, the Siri app, and new Apple Intelligence features in apps, but there are a few iPad-only standouts. Subscribe to the MacRumors YouTube channel for more videos. Siri AI on iPad has all of the same features as Siri AI on the iPhone, so it can access your personal data, search the web for answers, complete tasks in apps, and answer questions about what's on your screen.
When Health Results Raise Questions but Provide Few Answers
Older people are often treated as if their judgment is less valuable, creating the risk of a future where human intelligence is seen as something that depreciates with age.
Google Releases Free Android Upgrade To Millions: Samsung Galaxy Next
Samsung's Android 17 upgrade is coming to Galaxy phones via One UI 9. But the biggest feature, Gemini Intelligence, raises serious security questions. Here's what to know
Using AI Tools in Graduate School: Virtual Workshop: APSA Status Committee on Graduate Students in the Profession | Friday, June 26, 2026 -
“Using AI Tools in Graduate School” Friday, June 26, 2026 12:00 PM (ET) / 9:00 AM (PT) | Run Time 75 minutes Register Here Artificial intelligence’s rapid adoption and growing technological power affect nearly all aspects of the political science graduate student research process. Join the [...]
iOS 27 makes your iPhone faster in 40+ ways, here’s the full list
While Apple Intelligence and Siri AI are the biggest additions to iOS 27, the update will also make your iPhone...
Intel Advances Responsible Business Practices and AI-Driven Growth in 2025–2026 Corporate Responsibility Report
New report outlines progress and priorities as AI reshapes technology and global demand
Trade association formed for data center, AI policies
The Arkansas Connected Communities Association (ARCC) announced Tuesday (June 16) its formal establishment as a 501(c)(6) trade association dedicated to advancing data center and artificial intelligence infrastructure policy in Arkansas....
Trump Pulls Back Intelligence Pick to Pressure Congress on Elections Bill
President Trump named Jay Clayton, the U.S. attorney in Manhattan, after a bipartisan backlash to his earlier choice of Bill Pulte. The move all but assures that Mr. Pulte will hold the job, at least for a while.
Trump delays intelligence director nomination to push Congress on voter ID bill
The president said in a social media post just hours before Clayton's scheduled confirmation hearing that he will keep Bill Pulte, a top U.S. housing official, as acting director
Trump delays intelligence director nomination to push Congress on voter ID bill
The president said in a social media post just hours before Clayton's scheduled confirmation hearing that he will keep Bill Pulte, a top U.S. housing official, as acting director
Trump delays intelligence director nomination to push Congress on voter ID bill
The president said in a social media post just hours before Clayton's scheduled confirmation hearing that he will keep Bill Pulte, a top U.S. housing official, as acting director
EigenQ and Silicon Valley Acquisition Corp. Announce Definitive Business Combination Agreement to Create a Publicly Traded Quantum Technology Company
Transaction expected to accelerate EigenQ's mission to develop and commercialize quantum technologies across security, artificial intelligence, communications,...
Trump cancels hearing for intelligence chief pick, says Pulte will remain
The president linked the move to his efforts to pass voting restrictions and said Jay Clayton’s hearing would be delayed until his replacement as U.S. attorney is confirmed.
Trump says he is canceling DNI hearings as he vents frustration at legislative maneuvering over surveillance law
President Trump says he is canceling a planned hearing Wednesday for his nominee to serve as Director of National Intelligence, venting frustration at legislative maneuvering over a US surveillance authority.
Latvia pilots citizen engagement in research grant evaluations
Latvia has introduced an element of citizen engagement to the evaluation of nationally funded research grants. The aim is to both create more connections between science and society, and to improve the quality of its evaluations. The move comes as research funders across Europe are experimenting with ways to improve evaluation processes in the face of a sharpened focus on science’s impact on society. Evaluators of grant applications submitted to Latvia’s Fundamental and Applied Research Programme (FLPP), the country’s main research funder, will this year have the option of consulting citizen feedback on challenges the public thinks science should focus on to inform their decisions. “In recent years, both public discussions and policy-level debates in Latvia have highlighted the importance of demonstrating how publicly funded research contributes to society, the economy and the resolution of real-world challenges,” said a source at the Latvian Council of Science (LCS), which manages the FLPP. “At the same time, research institutions themselves expressed interest in improving the project evaluation framework while continuing to ensure that funding is awarded to the highest-quality projects,” the source added. The citizen input comes from a survey that was conducted between 25 February and 16 March 2025, to which 1,737 people responded. It gathered information on what the public views as problem areas for Latvia, and the role of science and technology in providing solutions to these problems. A summary of these responses has been included as an annex to the FLPP 2026 call for proposals that evaluators can refer to, purely in an advisory manner, when judging proposals. Results from the survey show that the main problem areas identified by the public were in healthcare and public health, followed by the development of new treatment methods and medicines, and then digital technology, data security and cyber security. At the bottom of the list was research aimed at acquiring new knowledge about the universe, matter and the laws of nature. Further analysis looked at the public view of the possible role of science in solving these problems. The survey charted 4,167 individual responses based on open-ended questions that were derived from the participants’ answers. The analysis again found that medical and health sciences topped the scoring, with 788 responses referring to the field. Humanities and the arts were bottom of the list, with 625. Digging further into the details, the survey suggests citizens are aware of and concerned about a number of research areas. This includes technologies and innovation to improve the environment or reduce pollution, the development of modern military technologies and cybersecurity tools, and the development and application of artificial intelligence, among others. “We hope this initiative will help strengthen public trust in science and create a more meaningful dialogue between researchers and society,” the LCS source said, adding that it offers benefits to researchers, evaluators and to the general public. More space for citizen engagement in evaluationsThere is a gradual but increasing use of citizen engagement in research evaluation processes around Europe, especially in healthcare, but it remains relatively rare, said Henry Sauermann, a professor at the European School of Management and Technology in Berlin and an expert in citizen science.“Given that we are at a point where citizen involvement is extremely limited, there is presumably space for more, but it's not that we should do it just because we want to do it,” he told Science|Business. He said some research lends itself better to having citizen input, and this usually tends to be on the applied end of the science spectrum where the public can offer useful feedback based on their experiences. He added that advising scientists on certain topics to study is also a useful approach, in the way that Latvia is doing. “The public does fund a lot of science, there's a lot of tax money going into this. We of course do want to preserve academic freedom, but it's also not unreasonable to incorporate more feedback or input from citizens where possible,” he said. Related articlesCitizen science: where, when, and how to let the public contribute to researchHow can Europe cope with a flood of AI-assisted research grant proposals?Data Corner: Horizon Europe’s AI, digital and data call success rate is 5.2%There are several ways of involving citizens in science funding. The most minimal way is having a few representatives on a panel, such as members of a patient group or union. The most direct way is crowdsourcing funding for specific projects. There is an increasing number of online platforms that allow the public to chip in to support scientific proposals.Sauermann studied this in a recent paper and found that it can have its uses, but it still is not clear if there are benefits to it. There are various assumptions linked to citizen engagement, for example that it increases public trust in science, or that it provides a representative view of what the public thinks about science. These are not necessarily true, Sauermann found. People who participate in engagement activities tend to already be very trusting of science, and, on the whole, it is generally the well-off and well educated who contribute, giving a narrow view of public opinion. On whether citizen input can help manage the increasing number of proposals that are being submitted due to assistance from AI, Sauermann is more sceptical. “The obvious answer to the flood of AI-written proposals is AI-driven evaluation,” he said, adding that it doesn’t mean citizen engagement shouldn’t be a part of evaluations in a well thought-out manner. Southern Denmark’s successful approachOne successful example of citizen engagement in science evaluations was implemented in southern Denmark. Between 2019 and 2025, citizens in the region were invited to vote to fund one of five pre-selected projects in the field of healthcare. The project, called A Healthier Southern Denmark, was a collaboration between regional authorities, the University of Southern Denmark, and two media partners. Over the seven years, there were 75,000 votes and significant public engagement online and on social media. “It was a bit of a wild project, we’d never done something like that before and we were a bit nervous about what would be said in the media about it. But actually, people were very positive,” said Anne Kathrine Overgaard, one of the main organisers of the project from the University of Southern Denmark. The university and its researchers have learned a lot from the experience, particularly about engaging with society and shaping their research to match real-world needs. This is important with Europe’s increasing focus on competitiveness and bringing innovations to market faster, Overgaard said. She hopes to see more citizen engagement in evaluation processes and in science more broadly. “For many years, citizen engagement has been a bit of an add-on to proposals, just to check a box. But I think things are changing,” she said. It’s less about citizens just gathering data and more “about the dialogue between the public and the scientists,” she said. The initiative ended last year as the team wanted to regroup to find fresh momentum. The development of AI and AI-written proposals has made Overgaard reflect on how the project could be reworked to help evaluators. She hopes to bring it back in the future. “It could be a good idea to try this initiative again in a slightly re-worked format,” she said.
Intel takes a major step toward turning around a business that’s bleeding cash
Intel’s new manufacturing process has entered a stage that signals the company is confident in its ability to bring on external customers, analysts say.
Apple's 2028 iPhones to Use 1.4nm A22 Pro Chips
Apple will transition from 2-nanometer chips to 1.4-nanometer chips with the high-end 2028 iPhone models, reports Bloomberg. Chip supplier Taiwan Semiconductor Manufacturing Co. (TSMC) will make the majority of Apple's A22 Pro chips, but Apple is also considering having Intel make some of them. The current iPhone 17 models use a third-generation N3P 3-nanometer process.
iPhone 17 won’t get iOS 27’s top-tier features, here’s why
iOS 27 has some exciting new Apple Intelligence upgrades, but you’ll need the most powerful iPhones to run them—iPhone 17 misses out.
Exclusive | Databricks Releases General AI Agents for Businesses
The data-analytics company is pushing further into AI applications for general work as it aims to carve out a place in the artificial-intelligence world.
Your medical provider might be recording your mental health care visits
Mental health professionals at Kaiser are raising concerns about an artificial intelligence tool that records appointments, saying it should have more safeguards.
Taiwan’s website for intelligence tips from the mainland spurs debate
‘Contact window’ launched for political, military, economic and social intelligence but critics say disinformation will be a challenge.
What's the latest on Giannis and Jaylen? O'Connor offers insight
Kevin O'Connor of Yahoo Sports joins Early Edition to share his latest intel on a potential Giannis Antetokounmpo-to-Boston blockbuster.
Mercy's Kerry Bommarito Earns "Top Women in Health IT" Recognition Again
Behind every breakthrough in healthcare technology is a leader helping move care forward — like Mercy’s own Kerry Bommarito. Mercy’s vice president of enterprise AI and decision intelligence has again been recognized by Becker’s Hospital Review, this time as part of its 2026 list of “Women in Health IT to Know.”
Blizzard sues private World of Warcraft server for "large-scale, egregious, and ongoing infringement of Blizzard's intellectual property"
Blizzard has filed a copyright lawsuit against the private World of Warcraft server project, Project Ascension.
NBA Draft Intel: Why Darryn Peterson isn't visiting Jazz
A significant shake-up appears to be brewing at the top of the lottery involving the Darryn Peterson and AJ Dybantsa
New ASU certificate lets students add AI expertise to any major
Artificial intelligence, or AI, is rapidly transforming nearly every industry, creating a growing need for students to add key technical skills to their major.
20 years of Intel Macs: Why Apple switched, and why it switched again
Remembering the ups and downs of the Intel Mac era as it finally winds down.
Intel’s Serpent Lake SoCs With NVIDIA RTX GPU Tiles Reportedly Arrive In Q1 2028
Intel's Serpent Lake SoCs featuring NVIDIA's RTX GPU tiles as integrated graphics are expected to roll out by Q1 2028.
Gen Z thinks AI is killing their career prospects. This business school has other ideas.
The University of Miami’s business school is rebuilding its curriculum from the ground up—and betting that human intelligence is still the most valuable skill in the room
WVU health care AI researcher wins prestigious NSF CAREER award
West Virginia University researcher Avishek Choudhury, who studies health care providers’ trust in artificial intelligence, has been named a Faculty Early Career Development award winner by the National Science Foundation.
Thermal Grizzly DeltaMate MPII supports AM5, AM4, LGA1851 and LGA1700, AM5 priced at $409
Thermal Grizzly has introduced its DeltaMate CPU Block MPII, a custom-loop CPU water block for AMD AM5 and Intel LGA1851 systems.
Why Squeezing Big Business Harder Won’t Close the UK Tax Gap
The UK’s tax authority should use artificial intelligence to monitor small and medium-sized businesses the way it does large corporations to help close the nation’s tax gap, Ryan’s Jenny Batchelor says.
Q+A: Faraday Future Moves Beyond EVs
Faraday Future Intelligent Electric Inc. is sizing up for a key pivot. Initially a luxury electric vehicle company, the El Segundo-based manufacturer is
‘Ponies’ merges comedy with a gritty spy story in TV dramedy
The Peacock series “Ponies” starring Emilia Clarke and Haley Lu Richardson blends comedy and drama as widows of CIA operatives become intelligence assets in the 1970s Soviet Union.
'Ponies' merges comedy with a gritty spy story in TV dramedy
The Peacock series “Ponies” starring Emilia Clarke and Haley Lu Richardson blends comedy and drama as widows of CIA operatives become intelligence assets in the 1970s Soviet Union | KMBZ
'Ponies' merges comedy with a gritty spy story in TV dramedy
The Peacock series “Ponies” starring Emilia Clarke and Haley Lu Richardson blends comedy and drama as widows of CIA operatives become intelligence assets in the 1970s Soviet Union. Despite its
No country should have to build its digital health future alone – now none of them will
WHO/Europe and Healthcare Denmark have signed a memorandum of understanding (MoU) to accelerate cooperation on digital health, health data, artificial intelligence (AI) and health system innovation in the 53 countries of the WHO European Region.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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A method to interpret artificial intelligence (AI) models used in materials discovery by analyzing their learned features has been developed by researchers from Japan. The method extracts key features from an AI model trained on atomic structural data and optical absorption spectra, and then groups materials with similar structural and spectral characteristics. This approach can be extended to reveal how atomic arrangements influence other material properties, paving the way for more efficient materials design.
Intel Raptor Lake “Next” Desktop CPUs To Come In Core 7, Core 5, Core 3 Flavors With Up To 20 Cores But Retain 8 P-Cores On LGA 1700 Socket
Intel Raptor Lake Next Desktop CPUs will bring value-oriented options to mainstream and budget gamers on the existing LGA 1700 sockets.
Intel to launch Core 200 "Raptor Lake Next" in 2027 for LGA-1700 socket
Series 2 Intel® Core Processors, it has been known since April really.
iOS 27 adds an all-new app to your iPhone’s Home Screen
Apple announced iOS 27 at WWDC this week, coming with a ton of new Siri and Apple Intelligence features. One...
Intel Reportedly Prepares Itself For Raptor Lake ‘NEXT’, As The Demand For DDR4 Platform Increases Significantly
Intel plans to launch Raptor Lake Next CPUs in early 2027 to meet DDR4 demands alongside Nova Lake processors amid high DDR5 prices.
Science facility in Newport News breaks ground on new center
The Thomas Jefferson National Accelerator Facility broke ground Friday for a new center that will expand its mission into high-performance computing, artificial intelligence and the data-driven research to meet the demands of modern science.
Science facility in Newport News breaks ground on new center
The Thomas Jefferson National Accelerator Facility broke ground Friday for a new center that will expand its mission into high-performance computing, artificial intelligence and the data-driven research to meet the demands of modern science.
UC Berkeley computer science students fail in large numbers, professors cite AI dependence
A dramatic spike in failing grades among computer science students at the University of California, Berkeley has alarmed faculty, who are pointing to an overreliance on artificial intelligence tools and a stark decline in foundational math skills as the primary culprits.
Exclusive: Iran sealed uranium cache and placed mines amid fears of US operation to seize material
In recent weeks, Iran has dramatically escalated efforts to seal off its cache of near bomb-grade uranium, deliberately collapsing tunnels and booby-trapping entrances with explosive mines, according to five sources familiar with US intelligence.
How to See Which Mac Apps Will Stop Working After macOS Golden Gate
Apple is phasing out support for Rosetta 2, which is a feature that allows Intel-based apps to run on Apple silicon Macs. Rosetta is going to stop working for most apps in macOS 28, and when that happens, apps that use it will stop working. Apple began warning customers and companies about the upcoming sunsetting of Rosetta with macOS Tahoe, and the warnings go even further in macOS Golden Gate.
Latest Utah Jazz draft intel on Boozer, Dybantsa, Peterson
The NBA Draft is less than two weeks away, and the Utah Jazz continue their preparation to make the No. 2 overall pick.
Gabbard rescinds Biden-era intel assessments that were skeptical about ‘Havana Syndrome’
In what is expected to be among her final acts as the nation’s top spymaster, Director of National Intelligence Tulsi Gabbard has rescinded a pair of Biden-era intelligence assessments that took a skeptical position on the existence of a mysterious ailment known as “Havana Syndrome” that has sickened spies, diplomats and other officials overseas.
Apple to Release These 15 New Products Later This Year
Apple's annual WWDC developers conference is drawing to a close, but there is still a lot to look forward to in the second half of the year. Apple is expected to release at least 15 more products later this year. Now that the more intelligent and personal version of Siri has finally arrived in beta, a full two years after Apple first previewed it at WWDC 2024, we should begin to see some new devices that were reportedly postponed until the new Siri was ready.
Trump taps Clayton for intel chief as spy tool expires
Clayton is currently the Manhattan U.S. attorney
Latest News In AI Chips - AI-Powered Shift: Transforming Data Into Business Intelligence
Treasure Global Inc. has secured a US$15 million contract to develop an AI-powered Social Listening Platform for Creative World Industries, emphasizing the growing demand for AI systems that convert digital data into actionable insights. This platform leverages machine learning and NVIDIA-powered infrastructure to provide real-time sentiment and trend analytics across various sectors. The deployment underscores a trend in the AI chips industry towards enhancing real-time decision intelligence...
Fisa spy powers almost certain to expire after Congress fails to act
Law due to expire at midnight tonight following unhappiness over Trump’s pick for intelligence chief
Military Science and the Intellectual Foundations of War
Military science is not guesswork; it is the study of war built by soldiers, historians, statesmen, and theorists over centuries of conflict.
Salesforce's AI Business Is Growing More Than 200%, but the Stock Is Near a 52-Week Low. Something Has to Give.
Investors seem convinced artificial intelligence will disrupt the software giant. Its most recent results tell a different story.
FISA spy powers seem likely expire after Congress fails to act
The vote Thursday reflected a protest of President Donald Trump's refusal to name a permanent head of the nation's intelligence agencies
DC Wrap: Trump cancels Iran strikes and reveals his intel chief pick
A look at the day's biggest stories in national politics
What's New in the iOS 27 Photos App
The Photos app is one of a handful of apps that Apple paid extra attention to in iOS 27. It has multiple improvements to performance, and several quality-of-life upgrades. There are also new AI photo editing tools that use Apple Intelligence. AI Tools There is a set of AI photo editing tools in the Photos app, accessible by tapping on the icon featuring three sliders, and then selecting the Apple Intelligence icon labeled "Tools".
Businesses feeling the pain from AI spending, so OpenAI reportedly weighs price cuts
An artificial intelligence price war between OpenAI and Anthropic might be brewing, with The Wall Street Journal reporting that OpenAI, the maker of ChatGPT, is considering "drastic" price cuts for business clients.
Trump plans to nominate U.S. Attorney Jay Clayton as intelligence director
He is the U.S. attorney for the Southern District of New York and a former Securities and Exchange Commission chairman
Trump plans to nominate U.S. Attorney Jay Clayton to be national intelligence director
President Donald Trump announced the nomination on social media amid pressure from Congress to name a permanent replacement for Tulsi Gabbard, who resigned last month.
Trump plans to nominate U.S. Attorney Jay Clayton as intelligence director
He is the U.S. attorney for the Southern District of New York and a former Securities and Exchange Commission chairman
Trump Picks Jay Clayton for Director of National Intelligence After Backlash Over Bill Pulte
Lawmakers had pressed the president to find someone besides Bill Pulte, the Trump ally who was the president’s interim choice but lacked experience.
Trump says he will nominate Jay Clayton to top intelligence post
President Donald Trump announced Thursday that he’s nominating Jay Clayton, the US attorney for the Southern District of New York, to be his next director of national intelligence.
House vote to extend FISA spy tool fails
The vote Thursday reflected a protest of President Donald Trump's refusal to name a permanent head of the nation's intelligence agencies
Using AI for medical advice; pelvic floor exercises; the hidden dangers of burning incense; plus other stories with Vanderbilt Health sources
Colin Walsh, MD,Associate Professor of Biomedical Informatics, was on WTVF News Channel 5‘s “Morningline” show in an interview about whether or not it is safe to use AI for medical advice. Time magazine reporter Stacey Colino interviewed Elisabeth Sebesta, MD, Assistant Professor of Urology, for a story about pelvic floor exercises for issues including menopause, erectile dysfunction and urinary incontinence in men. “Each Breath,” published by the American Lung Association, quoted Brian Christman, MD, Adjunct Professor of Medicine, for a story about the hidden dangers of burning incense. William Schaffner, MD, Professor of Preventive Medicine, was quoted by several news outlets about public health issues, including: Healthline (low vaccination rates lead to more cases of measles, whooping cough and other preventable diseases); ABC News (U.S. measles cases surpass 2,000 for second year in a row); and CIDRAP News (high-dose flu shots cut rates of hospitalization in older adults). Sarah Rohde, MD, Associate Professor of Otolaryngology-Head and Neck Surgery, was quoted in a People magazine story on patient Makalii Andrade, a surfer from Kauai Island who suffered a serious neck injury in 2022 and recently underwent surgery at Vanderbilt Health to begin the final phase of his recovery. James Crowe, MD, Director of the Vanderbilt Center for Antibody Therapeutics, for a piece in Nature about antibodies against a strain of Ebola. SFGATE reporter Gillian Mohney interviewed Xue Zhong, PhD, Research Assistant Professor, Division of Genetic Medicine and Clinical Pharmacology, for a story about a study of a blood test looking at Alzheimer’s disease biomarkers. Matthew Franklin Mart, MD, Assistant Professor of Medicine, was quoted in a Healio story about how inflammation and illness severity is linked to less cognitive resilience after a person has been an ICU patient. The “How We Really Feel” podcast host Sula Windgassen, PhD, interviewed Lindsey C. McKernan, PhD, MPH, Associate Professor of Psychiatry & Behavioral Sciences, Physical Medicine & Rehabilitation and Urology, for an episode focusing on pelvic and bladder health. The podcast is also available on YouTube and the podcast website. In addition, podcaster Monica Sanford interviewed cardiologist Mark Glazer, MD, for her podcast “The Monica Sanford Show”; the two-part interview is here and here.
INTERVENT International and Brand Engagement Network Launch INTERVENT Health AI, Inc., Combining 25+ Years of Clinically Validated Health Coaching with Enterprise-Grade Conversational AI
/PRNewswire/ -- Brand Engagement Network Inc. (NASDAQ: BNAI) ("BEN" or the "Company"), a provider of secure, enterprise-grade artificial intelligence for the...
AI is sparking a jobs boom
As Corporate America scrambles to fill artificial intelligence jobs, junior workers are getting left behind.
How Trump’s reliance on ‘acting’ officials holding multiple jobs tests the Constitution
It feels odd that President Donald Trump tapped a housing expert to oversee the American intelligence community.
‘A leader in health AI’: School of Medicine Dean talks integration of artificial intelligence and healthcare
At the annual State of the School Address on Wednesday, Dr. Mary Klotman overall took an optimistic tone, expressing excitement about the School of Medicine’s efforts to integrate AI throughout much of what they do. However, she also recognized the challenges AI presents for the medical field specifically.
New Data Center, Student Collaboration Space Put People at the Heart of Computer Science
The Computer Science and Engineering Department unveiled a new on-site data center that will accelerate computing and artificial intelligence research advances, while giving graduate students and other computer science researchers hands-on access to cutting-edge computing infrastructure.
Panel discussion on politics of AI set
CHARLESTON – Berkeley Springs will play host Sunday to a panel discussion to look at the growing use of artificial intelligence – AI – along with the data centers powering the revolution, and the politics that is growing contentious not just in West Virginia, but nationwide. Tangle News – a national news outlet that looks […]
Panel Discussion On Politics Of AI Set In Berkeley Springs
CHARLESTON – Berkeley Springs will play host Sunday to a panel discussion to look at the growing use of artificial intelligence – AI – along with the data centers powering the revolution, and the politics that is growing contentious not just in West Virginia, but nationwide. Tangle News – a national news outlet that looks […]