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Could Jack Draper Follow the Path of Robin Soderling?
The summer of 2011 should have been Robin Soderling's. He was ranked No. 4 in the world, had reached consecutive French Open finals, and had beaten Rafael Nadal at Roland Garros in 2009, the only player to do so on clay before 2015. He was 26 years old and playing some of the best tennis …
Tottenham v Everton: Key stats and talking points
Everton look to continue their unbeaten start visiting a Tottenham side yet to win in the Premier League this season. BBC Sport examines some of the key themes going into their meeting in north London. When Spurs faced Everton in their final match of last season, they needed to win to stay in the division.
Jakirovic named manager of the month for August
Hull City boss Sergej Jakirovic has been named Premier League manager of the month for August. The Tigers remain unbeaten in the league after the opening three games of the season and sit third in the table with seven points. "I'm very happy and very proud," said Jakirovic to BBC Radio Humberside.
Brennan expects tough test against Fleetwood
Newport County midfielder Ciaran Brennan expects a "tough" test against Fleetwood Town as the Exiles aim to preserve their unbeaten start at home.
Stuver has 4 saves for Austin in 1-1 tie with Rapids
Austin (6-10-8) is unbeaten in five straight following a three-game losing streak.
Bournemouth vs Brentford: Team News, How to Watch & Prediction
Brentford head to the Vitality Stadium unbeaten in the Premier League, while Bournemouth are still searching for their first league victory under Marco Rose.
Daniel Farke: A bit of a crazy game
Leeds United travelled to the capital to face Chelsea in the EFL Cup Third Round, where they were beaten after a flurry of second half goals.After the Whites' exit from the competition at Stamford Bri...
Stark contrast with McLeish shows Robinson's Dons identity crisis
On Saturday, before his team's top-of-the-table clash with Celtic, I asked St Mirren manager Craig McLeish how easy it has been to implement the style of football that is enthralling the Paisley club's supporters amid their then unbeaten start to the league season. The man who led the Saints youth team under Aberdeen boss Stephen Robinson has produced a side that plays an exciting, fast-paced brand of football with a clear identity already. Eight new signings started the narrow defeat to the champions as well as Fraser Taylor, who was on loan at Partick Thistle last season.
2004-05 deja-vu - Can Moyes inspire another fine finish?
Deadline day may have left Everton fans feeling disillusioned, but the side is four games into the season and remains unbeaten, nine goals scored, including two in added time to secure a point. After what was a chaotic close to the transfer window, even by the Toffees' own standards, the performance against Manchester United ironically saw the summer signings playing a key role in the fight. Jack Grealish and Hayden Hackney came on from the bench to turn the game on its head, Tyrique George scored to equalise before the visitors went back in front, and it was Ainsley Maitland-Niles with a stunning strike to secure the draw in the final few seconds.
Millwall vs Newcastle United – Match preview and team news
Millwall host Newcastle United in the Carabao Cup third round on Tuesday, with the Magpies looking to build on an unbeaten start under new head coach Matthias Jaissle against a Championship side findi...
The Weekend Review: Men and Women continue to impress
There were two more important results for our unbeaten senior teams across Saturday and Sunday’s action, continuing a productive start to the new campaign.On the south coast, Daniel Farke’s men ea...
🎥 Shock in Itaquera! Corinthians beaten by bottom side Chapecoense
Chapecoense had only two wins in the Brasileirão - against Santos and São Paulo.And a total of zero away victories.Then they went and stunned Corinthians right at the Neo Química Arena this Sunday ...
TENNESSEE LADY VOLS SOCCER: Derrien's goal is the difference
The No. 10 Tennessee soccer team closed its six-match nonconference schedule unbeaten with a 1-0 victory over Northwestern on Sunday afternoon at Regal Soccer Stadium.
Arsenal 2-1 Chelsea: What Arteta and Havertz said
Arsenal have come from behind to beat Chelsea in a Premier League game for the first time since October 2011 (5-3), ending a run of 14 without a victory when trailing the Blues (four draws, 10 losses). Arsenal have won their opening three games of a top-flight campaign while also conceding fewer than two goals (one) for the third time since 1924-25, when they finished 20th and in 2003-04, when they went the whole season unbeaten.
Arsenal deliver statement fightback to end Chelsea's flying start
Arsenal delivered an emphatic response to Chelsea's emergence as potential Premier League title contenders with a 2-1 win that ended their rivals' unbeaten start on Sunday.But the champions showed why they are firm favourites to retain the title with a blistering response to that early setback.
Mainz roll 5-0 over hapless SV Hamburg
Phililip Tietz scored a brace and Sheraldo Becker added a goal and two assists as Mainz claimed an impressive 5-0 Bundesliga victory at out-of-sorts SV Hamburg on Sunday. Beaten 4-0 in Hamburg last season, Mainz were determined to make amends from the kick-off and took a 19th-minute lead from Becker's solo after Kaishu Sano intercepted a terrible pass from Hamburg's Nicolai Remberg.
Arsenal u18s get first win of season
The Young Guns remain unbeaten after two matches and have yet to concede, following their opening goalless draw away to West Brom.Photo via Arsenal.comArsenal U18s secured their first win of the 2026-...
St. Louis CITY extend unbeaten run with Vancouver upset
By Ben SteinerVANCOUVER, B.C. - Let it be known, St. Louis CITY SC mean business.After a week that saw them shell out $12 million to the Colorado Rapids in a cash-for-player trade for Rafael Navarro...
Everton vs Manchester United – Predicted lineup and team news
Everton will look to extend their unbeaten start to the season when Manchester United visit Hill Dickinson Stadium on Sunday. David Moyes’s side sit seventh in the table after a win and a draw from ...
Ursuline falls to unbeaten Bishop Watterson
Bishop Watterson took down Urusline, 41-10, during high school football action on Saturday night.
TENNESSEE LADY VOLS SOCCER: Unbeaten Northwestern is next
The No. 10 Tennessee soccer team closes its six-match nonconference slate on Sunday afternoon against Northwestern at Regal Soccer Stadium. Kickoff between the Lady Vols and the Wildcats is set for 2 p.m. ET.
Hull City v Aston Villa: What Emery said
Aston Villa have recorded just one shot on target in their opening three games of a Premier League season - the lowest total on record by any side since 2003-04. Only Manchester City (31) are on a longer ongoing unbeaten run in the Premier League against newly promoted sides than Aston Villa, with the Villans unbeaten in all 22 matches under Unai Emery (won 15, drawn seven).
Bayern held to draw by stubborn Schalke
Defending champions Bayern Munich were held to a scoreless draw by promoted Schalke in the Bundesliga on Saturday.Seven-time German champions Schalke have not beaten Bayern since 2011 and had not even taken a point off the Bavarian giants in nine years -- a run of 12 straight defeats.
Arbeloa vows Fulham’s poor start ‘will not define this season’
Fulham boss Alvaro Arbeloa insists his side’s difficult start to the season will not define their campaign after suffering a third consecutive defeat.Fulham were beaten 3-2 by Crystal Palace having ...
Jayden Bogle: We were brave on the ball
Leeds United came away from the American Express Stadium with a deserved point, as goals either side of the break saw the Whites continue their unbeaten start to the new term.Jayden Bogle’s close ra...
Dortmund’s U23 remain unbeaten
Starting PointWith three wins and two draws from their first five matches, the U23 travelled to the away game at Grenzlandstadion in excellent form. After the derby win against Schalke 04 on Tuesday, ...
Brentford 1-1 Sunderland: What Andrews said
Brentford have given away more penalties than any other side in the Premier League since the start of last season (nine), conceding from six of them. Brentford are unbeaten in each of their last 14 Premier League games in which they've opened the scoring (won, drawn five), though they have drawn four of their last six such games.
Bayern learn opponent for second round
Having beaten Osnabrück 4-1 on Wednesday in the first round the 2026/27 DFB Cup, Bayern will now face Magdeburg at the Allianz Arena as they continue their defence of the trophy. The draw for the sec...
Penybont stay unbeaten in narrow win over Colwyn Bay
Penybont maintain their unbeaten start to the Cymru Premier season with a narrow 1-0 home win against Colwyn Bay to move up to sixth.
Daniil Medvedev is Having Fun Again
Daniil Medvedev is once again through to the second week of the US Open, without dropping a set and getting broken just once. The Russian had a rather manageable draw to start the tournament. However, everything was on the line in his third-round match against Arthur Rinderknech. The Frenchman had beaten Medvedev the last time …
Gary Neville predicts the outcome of Arsenal v Chelsea
Gary Neville has predicted how he expects the Chelsea-Arsenal game to end as two unbeaten clubs prepare to meet in the Premier League this weekend.Arsenal secured a hard-fought 1-0 victory against Ast...
Newcastle vs. Bournemouth
Newcastle United returns to St James’ Park on Saturday to face Bournemouth in its third Premier League game of the season. Matthias Jaissle’s new-look side remains unbeaten across its first three competitive matches and enters the weekend with four league points after Anthony Elanga and Yoane Wissa scored in a 2-0 victory away to Tottenham […]
Brighton & Hove Albion vs Leeds United: Match preview
Leeds United head to the South Coast on Saturday afternoon looking to maintain their unbeaten start to the 2026/27 Premier League season, but Daniel Farke’s side face one of their toughest tests yet against a Brighton & Hove Albion side who have already shown just how dangerous they can be in front of goal.
Titan Peterman helping lead Indian Valley football's unbeaten start
Titan Peterman helped Indian Valley control the trenches in a 37-14 win over New Philadelphia, keeping the Braves unbeaten at 3-0.
Watch: McNeil vs. Lake Belton football live
McNeil looks for its first win Friday night against unbeaten Lake Belton.
Watch: Rouse vs. Georgetown football live
Georgetown looks to stay unbeaten Friday night when the Eagles host Rouse.
Brentford v Sunderland: Key stats and talking points
Brentford are aiming to maintain their unbeaten start against a Sunderland side with one win and one defeat so far. BBC Sport takes a look at the key themes ahead of their clash at the Gtech Community Stadium on Saturday (15:00 BST). It's been a promising start to the season for the Bees, who have a win and a draw from their first two matches and were a bit unlucky to be pegged back by Leeds last weekend.
Swansea City vs Wrexham: Preview
Wrexham are back in Championship action on Saturday night as they head to the Swansea.com Stadium to face unbeaten Swansea City in an all-Welsh clash, with the match part of Sky Sports Live coverage of the EFL.
Wellington football blanks Westwood for first shutout since 2024
Wellington stayed unbeaten with a 26-0 road win over Westwood as Jay'lan Tyler rushed for 117 yards and the Wolverines posted a rare shutout.
OpenClaw that Sam Altman spent billions on and claims to have beaten GTA 6 gets 'largest update in its history'
OpenClaw has rolled out OpenClaw 2.0, marking the most extensive software upgrade in the open-source artificial intelligence (AI) agent platform’s history since its debut last year. Announcing the release, the development team playfully referenced Rockstar Games’ upcoming November title launch with the social post, “HA!
Did We Just Witness the End for Novak Djokovic?
There are losses, and then there are moments that feel like a chapter closing. Novak Djokovic’s stunning first-round exit at the U.S. Open felt like the latter. The 24-time Grand Slam champion was beaten by Mariano Navone 7-6, 5-7, 4-6, 6-2, 6-1 Sunday night in a four-hour, 36-minute marathon. It was Djokovic’s first opening-round loss…
Wisconsin High School Football Rankings: Top 25 Teams
The top five high school football teams in the state of Wisconsin remain unchanged — according to the Massey Ratings — following the second week of the 2026 season. Sixteen of the top 25 teams in the state remain unbeaten. Both No. 3 Bay Port and No. 5 West De Pere held serve with important […]
Buccaneers’ quarterback battle ends with a major surprise
Undrafted rookie Jalon Daniels entered Buccaneers camp as a long shot, but his impressive preseason changed everything. Now, he’s beaten out veteran Jake Browning for the job behind Baker Mayfield.
De Zerbi insists he remains confident in Spurs ‘project’ but admits ‘mentality’ challenge
Roberto De Zerbi admits Tottenham’s biggest challenge is finding the “right mentality” after they suffered a 2-0 defeat to Newcastle.Spurs were beaten at St James’ Park as goals from Anthony E...
“Breath of Fresh Air”: Browns Fans Commend Todd Monken for Blunt Response to Deshaun Watson Getting Booed
It wasn’t a fun outing by any means for the Cleveland Browns and their fans as they took on the Buffalo Bills at home in the NFL preseason, with the home side beaten 31-7, but perhaps most notably, the reaction against quarterback Deshaun Watson came as a major setback to the QB as well as to head coach Todd Monken. Monken, who has consistently maintained that the QB1 spot is open to both Watson and Shedeur Sanders as the first game of the season approaches, was forced to admit during the postga
Arizona Cardinals struggle in preseason loss to Dallas Cowboys
The Arizona Cardinals were beaten badly in the preseason by the Dallas Cowboys.
🤯 Incredible record broken! Pro club unbeaten in 109 (!) games
Malaysian club Johor Darul Ta'zim won the first match of the new season 3-0 against Kuching City FC last night. So far, so unspectacular. Even so, the match will go down in the history books. The reas...
Guggenheim’s beaten-down loan whipsaws as lenders digest call
Executives steered clear of details about the wide-ranging probe into Mark Walter’s business empire.
Guardians News: Hail Jo Adell!
The Guardians hosted the Giants last night. The Giants have had a terrible season, and they played like it last night. Their defense screwed up countless times, including an outfielder who Raburned a throw. But the Guardians would have beaten most opponents last night—because Jo Adell had a career night. The bad news is that […]
Early goal was a big part of the game
Enzo Maresca said that conceding an early goal had a major impact as Manchester City were beaten in the Community Shield. Match Report City defeated in 2026 Community Shield The new City boss’s firs...
David Crowley defeats Francesca Hong in Wisconsin governor primary
Centrist David Crowley is projected to have beaten democratic socialist Francesca Hong, breaking a recent nationwide trend.
Don't Worry, PS5 Has Fire Emblem: Fortune's Weave at Home
Beaten Path paves a route to release in 2027
Tactical RPG Beaten Path launches in 2027 for PS5, Xbox Series, Switch, and PC
Kickstarter-funded turn-based strategy RPG Beaten Path will launch for PlayStation 5, Xbox Series, Switch, and PC via Steam and Epic Games Store in 2027, publisher Wales Interactive and developer P…
Yankee Stadium game highlights Wrexham's rise
Goalkeeper Danny Ward believes playing against Liverpool at Yankee Stadium is the latest illustration of how far Wrexham have come in recent seasons. The Wales international had previously visited the iconic New York venue with Liverpool for a pre-season friendly against Manchester City in 2014. Ward, 33, was between the sticks for hometown club Wrexham this time around as they were beaten 1-0 by Andoni Iraola's Liverpool.
Crawley and Brook help Sunrisers beat Super Giants
Leeds Sunrisers end Manchester Super Giants' unbeaten start to the season after chasing down 182 thanks to half-centuries from Mitch Marsh and Zak Crawley while Harry Brook chips in with 42.
Kilmarnock sell left-back Thompson to Beveren
Kilmarnock have sold left-back Dominic Thompson to Belgian top-flight club Beveren. The 25-year-old Englishman, who has signed a two-year contract with the side who won the Challenger Pro League to earn promotion last season, joined Kilmarnock from Scottish Premiership rivals Motherwell last summer. Thompson told Beveren's website he was pleased to join a team that "comes into this with a lot of confidence after an incredible unbeaten season".
Switzerland boss furious over 'unacceptable rule' after World Cup elimination
The Swiss were left fuming at the officials after they were beaten 3-1 by Argentina in the World Cup, with a disputed VAR red card decision drawing fierce criticism from the Swiss camp
🎖️Spain want to keep making history
To date, the national team has gone 37 official matches unbeaten, and they want to keep this great run going. Since June 2023, Spain has not known what it is to lose an official match. So far, they ha...
BELGIUM KNOCKED OUT AFTER SPAIN'S LATE WINNER
Alexis Saelemaekers and Koni De Winter's 2026 World Cup journey comes to an end in the quarter-finals. Belgium, featuring the two Rossoneri, were beaten 2-1 by Spain, who secured their place in the se...
Man beaten to death outside Las Vegas business, two suspects at large
Authorities say they are looking for two people who beat a man to death outside a Las Vegas business on Thursday.
Man beaten to death during fight outside Las Vegas business
A man was beaten to death during a fight outside of a business early Thursday morning, Las Vegas police said.
Wimbledon Day 2 Upsets, Featuring Ben Shelton, Elina Svitolina
There were several big upsets on Day 2 of the 2026 Wimbledon Championships, as Ben Shelton, Elina Svitolina, and Donna Vekić were all eliminated as the thrilling first-round action continued. Seven-time Wimbledon champion Serena Williams was also beaten on her return to the Wimbledon stage, bowing out in the first round against Maya Joint.
The crazy numbers behind Turkey’s exit 🤯
Square feet epidemic in Turkey.At daybreak, the entire Turkish people woke up with a hangover.Beaten by Paraguay by the smallest of margins (0-1), Turkey is already heading out of this 2026 World Cup ...
Hillary Clinton says Joe Biden made a ‘terrible mistake’ by seeking reelection
Virtually "anybody else" who won the Democratic nomination could have beaten Donald Trump, she said during an interview in New York.
Hillary Clinton Says Biden’s Re-Election Bid Was a ‘Terrible Mistake’
If the former president had “passed the torch” and allowed a competitive Democratic primary in 2024, she said in a new interview, the winner “would have beaten Donald Trump.”
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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YouTuber box office boom: ‘Backrooms’ and ‘Obsession’ draw Gen Z to theaters
An indie horror with internet origins has beaten the legacy franchise Star Wars at the box office this weekend.
YouTuber box office boom: ‘Backrooms’ and ‘Obsession’ draw Gen Z to theaters
An indie horror with internet origins has beaten the legacy franchise Star Wars at the box office this weekend.
YouTuber box office boom: ‘Backrooms’ and ‘Obsession’ draw Gen Z to theaters
An indie horror with internet origins has beaten the legacy franchise Star Wars at the box office this weekend.
Rafa Jodar’s ball girl shove incident leaves tennis fans divided
Rafael Jodar’s biggest French Open win turned into a messy social-media trial after a clip appeared to show a ball girl stumbling near him. The Spanish teenager had just beaten Alex Michelsen in five sets at Roland Garros, a serious breakthrough on a major stage.
'A very underwhelming campaign'
Now the curtain has come down on the 2025-26 Premier League campaign, here is my end-of-season review - with a look back to what I predicted in August. Chelsea's poor season contained one final insult when they were beaten at Sunderland on the final day, meaning they have no European football under new manager Xabi Alonso next season. Liam Rosenior lasted only three months amid acrimony - a head coach out of his depth - before Calum McFarlane stepped in to take Chelsea to the FA Cup final, which they lost to Manchester City.
Raducanu beaten in French Open first round
Emma Raducanu's French Open campaign comes to an early end as she suffers a frustrating first-round defeat by Argentina's Solana Sierra.
Analysis: Gibbs-White omission could still haunt Tuchel
Only time will tell if Thomas Tuchel's decision to leave Morgan Gibbs-White at home for the World Cup is the right one. The Nottingham Forest playmaker and the City Ground clearly think it was the wrong one after the best and most consistent season of the 26-year-old's career. Gibbs-White's 15 Premier League goals this season leaves him as the second top English scorer in the top flight, only beaten by Ollie Watkins following the Aston Villa striker's double at Manchester City on the final day.
Nottingham Forest v Bournemouth: Key stats and talking points
Bournemouth visit Nottingham Forest on Sunday knowing they are already assured of a first European adventure next season – but they need a number of results to go their way to land a place in the Champions League. It was Forest who enjoyed their own continental quest this year, with an impressive run to the Europa League semi-finals providing a welcome distraction to their domestic woes. Vitor Pereira took over from Sean Dyche in February and has steered the Tricky Trees to safety thanks in no small part to an eight-game unbeaten run that ended with a 3-2 defeat by Manchester United last week.
Leeds 1-0 Brighton: What Farke and Calvert-Lewin said
Leeds United extended their Premier League unbeaten streak to eight games (W4 D4), which is their longest run in the competition since November 2001 (13). Daniel Farke's side have won three consecutive Premier League home games for the first time since August 2001 (5 in a row).
Guardiola's personal to-do list for Pulis
My first encounter with Manchester City boss Pep Guardiola was when I was with West Brom. It was early in Pep's first Premier League campaign, 2016-17, and Manchester City had just beaten us at home. As people will tell you, I forced him to eat with us too, while we discussed his early impressions of the Premier League and English football in general.
13 stocks to play a contrarian bet on the US consumer: Piper Sandler
Piper Sandler's Michael Kantrowitz says high yield eventually give way to lower rates, setting the stage for beaten-down consumer stock to rally.
907 Sports: Spring Sports Teams That Stand Unbeaten
More than halfway through the spring sports seasons, there are just a few unbeaten teams remaining in soccer and baseball. Plus, we check an a growing activity called ‘air pitch soccer’ that took over Anchorage’s Dome over the weekend.
Kohli hits unbeaten century as RCB move top
Virat Kohli hit a brilliant unbeaten 105 as Royal Challengers Bengaluru beat Kolkata Knight Riders by six wickets to move top of the Indian Premier League table. Opening the batting, the 37-year-old struck 11 fours and three sixes in his 60-ball innings as RCB chased down their target of 193 with five balls to spare. Kohli, who was dismissed for ducks in his two previous innings but is still averaging over 50 for the fourth consecutive year, lost opening partner Jacob Bethell for 15 when he was caught and bowled by Kartik Tyagi.
Can Brentford be effective against Palace?
Crystal Palace will hit the road to take on Brentford on Sunday, a fixture that usually see's the Bees victorious. Brentford are unbeaten in their last six home league games against the Eagles, the last home loss coming in December 1957, in the Third Division South. The Bees have only won just five of their last 30 Premier League London derby matches however.
Halley’s comet may be named after the wrong person
A medieval monk may have beaten Edmond Halley to one of astronomy’s greatest discoveries by nearly 700 years. Researchers say Eilmer of Malmesbury recognized that the blazing comet seen in 1066 was the same one he had witnessed in 989. At the time, comets were viewed as terrifying omens tied to war and royal deaths, adding even more drama to the famous celestial event shown in the Bayeux Tapestry. The discovery is sparking debate over whether Halley’s Comet deserves a different name.
European play-off final 'step too far' for Swifts
Dungannon Swifts boss Rodney McAree says the European play-off final proved to be "a step too far" for his side as they were beaten 3-1 by Linfield at Windsor Park.
Sabalenka suffers second defeat in three matches
World number one Aryna Sabalenka suffers a second defeat in three matches as she is beaten by Sorana Cirstea in the Italian Open third round.
Bournemouth 3-0 Crystal Palace: What Iraola and Tavernier said
Bournemouth have extended their Premier League unbeaten run to 15 games (W7 D8), the longest active streak of any side in the division, and the Cherries' longest ever in the top flight of English football. In Junior Kroupi and Rayan, Bournemouth are the first side ever to have two teenagers score a goal in back-to-back Premier League games.
Bournemouth vs Crystal Palace – Match preview and team news
Bournemouth welcome Crystal Palace to the south coast on Sunday as they chase a historic European qualification spot.Andoni Iraola’s side are currently enjoying a club-record 14-match unbeaten run i...
Bournemouth v Crystal Palace: Key stats and talking points
Bournemouth and Crystal Palace, two teams with Europe on their minds, meet at Vitality Stadium on Sunday. The Andoni Iraola farewell party continues with the Cherries seeking to go unbeaten for a 15th consecutive Premier League match, the longest current such run in the top flight. Only two teams have had a 14-plus game unbeaten run within a season and finished outside the top six: that was Wimbledon in 1996-97 and Chelsea – who have been linked with a move for Iraola - in 2015-16.
Naoya Inoue is the greatest show in sports today. Now comes the fight of his life
The Japanese wrecking ball known as the Monster takes center stage at the Tokyo Dome on Saturday, facing unbeaten rival Junto Nakatani in a matchup for the ages
Popular science
Isaiah Keys has beaten the odds, and is asking for help with keeping him on a winning streak. Keys, Warren High School freshman, could be the next student to tour The Planetary Society in California with Bill Nye The Science Guy, as well as appear in Reader’s Digest and receive $20,000 to invest in his […]
Cave Spring remains unbeaten in girls soccer
SALEM, Va. (WFXR) — The Cave Spring Knights stays perfect on the season in girls soccer with a 6-1 over the Salem Spartans Tuesday night at Spartan Field.
'He realised he had beaten me in ‘Sarfarosh’': Nawazuddin recalls moment with Aamir Khan; REVEALS he is fan of Dada Kondke
Nawazuddin Siddiqui has consistently entertained audiences with his distinct and unconventional roles in the film industry. His recent outings, includ.
3 takeaways from Lakers’ Game 4 loss vs. Rockets
It took four games, but the Rockets have finally beaten the Lakers.
Hibernian v Hearts: Pick of the stats
Hibernian have won both of their past two home league games against Hearts; they had won just one of their previous nine home Edinburgh derbies in the Scottish Premiership before this (D4 L4). After their 1-0 win in February, Hearts are looking to win back-to-back Scottish Premiership meetings with rivals Hibs for the first time since April 2014; this is the 28th top-flight game between the two sides since then. Hibs remain unbeaten in nine home league games (W6 D3), keeping a clean sheet in their last three; they haven't recorded four successive home shutouts in the top flight since December 2009 under John Hughes.
Smith hits fifty as Rawalpindiz misery continues
Steve Smith's half-century helped Multan Sultans inflict an eighth straight defeat on Rawalpindiz. Australia's Smith struck 56 from 31 balls at the top of the order to set up Multan's chase of 167, while his compatriot Ashton Turner hit an unbeaten 37 to see them over the line with eight balls to spare. Rawalpindiz, who are already eliminated from the PSL, immediately struggled after choosing to bat first as Shahzaib Khan fell in the first over before skipper Muhammad Rizwan trudged to 26 from 29 balls.
🚨 BREAKING: Everton and Liverpool name lineups for Merseyside derby
Liverpool and Everton will meet in the first-ever Merseyside derby at the Hill Dickinson Stadium on Sunday. David Moyes' Everton head into this game with European aspirations after going unbeaten in f...