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Lackawanna business to pay $1.5 million for improper COVID-19 loans
BUFFALO, N.Y. (WIVB) — A steel pipe and tube manufacturer based in Lackawanna will pay $1.5 million in order to resolve allegations that is improperly obtained relief funds during the COVID-19 pand…
Buffalo County Health and Human Services offering free tick prevention kits
Tick prevention kits are available at various locations throughout the county.
Big 12 football bowl projections after Week 5 results
BYU and Utah are the Big 12's CFP contenders after Week 5, while Colorado, TCU and Kansas are left out of bowl projections.
Maxwell Hairston: From Chosen One to Just Another Bust
After surrendering two touchdowns to the Patriots and skipping postgame media, the Bills' self-proclaimed superstar faces a harsh reality check following a disastrous, discipline-lacking performance in Buffalo.
The world has nearly burned through its oil stockpile buffer, executives say
The amount of oil in storage that is accessible to the global market is running low, industry executives said at a forum in London this week, making the market more fragile and putting upward pressure on prices.
Buffalo Bills HC Responds to CJ Gardner-Johnson’s Controversial Comments
The Buffalo Bills suffered their first loss of the season, losing to the New England Patriots in Week 4 NFL action. The post Buffalo Bills HC Responds to CJ Gardner-Johnson’s Controversial Comments appeared first on HEAVY.
Bills No Longer No. 1 in ESPN's NFL Power Rankings After Week 4 Loss
The Buffalo Bills are no longer No. 1 in ESPN's NFL power rankings after losing to the New England Patriots in Week 4.
3 names emerging as possible replacements for Deion Sanders
Deion Sanders’ future at Colorado is facing renewed scrutiny after the Buffaloes fell to 2-3. If the school eventually makes a coaching change, Dan Mullen, Willie Fritz and Jason Eck could emerge as possible candidates, offering different combinations of Power Four experience, program-building success and recent momentum.
Bills cornerback Max Hairston apologizes for snubbing reporters
Buffalo’s first-round pick out of Kentucky a year ago, Hairston had a forgettable outing in his fourth start of the season.
Buffalo Bills’ Josh Allen-led offense takes a sloppy step back
Buffalo’s offense hasn’t so much dried up in splitting the past two games, it’s shown signs of sputtering and being impeded by ball-security issues.
Bills player dismisses Patriots hero as ‘practice squad player’
After a 0-3 start to the season, the New England Patriots were able to bounce back in a big way on Sunday afternoon, pulling off an upset win over the Buffalo Bills on the road after Patriots wide receiver Efton Chism III made a ridiculous catch to give the Patriots the lead with under two…
Colorado football's quarterback carousel keeps going round and round
Deion Sanders struggles to find a consistent signal-caller as schematic failures and shifting offensive identities force another benching, leaving the Buffaloes searching for a desperate spark against Utah.
Allen laments not throwing ball away after interception seals Bills loss
In hindsight, Josh Allen knows he and the Buffalo Bills would have been better off if he threw the ball away.
Patriots’ HC Raves About Drake Maye Compared to Josh Allen
The New England Patriots needed a response after a lopsided loss. Head coach Mike Vrabel received one from his quarterback against a division heavyweight. New England stunned the previously unbeaten Buffalo Bills 29-26 on Sunday, Oct. 4, and Vrabel placed Drake Maye in the same conversation as reigning NFL MVP Josh Allen afterward. “Gets us […] The post Patriots’ HC Raves About Drake Maye Compared to Josh Allen appeared first on HEAVY.
Patriots’ Christian Gonzalez-Less Secondary Takes Another Hit vs. Bills
The New England Patriots entered Sunday’s matchup with the Buffalo Bills short-handed at cornerback. Their depth was tested even further early in the fourth quarter.Charles Woods left the game after making a tackle on Bills wide receiver Joshua Palmer, according to Ethan Hurwitz of Patriots on SI. Charles Woods is hurt after making a tackle […] The post Patriots’ Christian Gonzalez-Less Secondary Takes Another Hit vs. Bills appeared first on HEAVY.
Josh Allen has blunt response to Bills' loss to Patriots
Buffalo Bills quarterback Josh Allen is explaining what went so wrong.
Bills Announce Historic Josh Allen News During Patriots Game
Buffalo Bills quarterback Josh Allen earned the all-time franchise record for rushing and receiving touchdowns in Sunday's game. The post Bills Announce Historic Josh Allen News During Patriots Game appeared first on HEAVY.
Buffalo Bills Lose 29-26 To New England: Instant Reactions
Josh Allen’s late-game interception and a defensive collapse derailed Buffalo’s perfect season, overshadowing record-breaking milestones and a breakout performance from wide receiver Keon Coleman in New England.
Patriots Pull Off Tight Upset Win Over Division Rival Bills
The New England Patriots escaped with a tight win over the Buffalo Bills.
Josh Allen Sets Bills Record Against the Patriots
The dual-threat quarterback surpassed Hall of Fame legends Andre Reed and Thurman Thomas, etching his name atop the franchise leaderboard with a historic first-half touchdown plunge.
New England Nation: Inside the Locker Room
The New England Nation team takes you inside the Patriots locker room with various players ahead of their first AFC East matchup of the season against the Buffalo Bills.
New England Nation: Keys to the Game Patriots at Bills
New England Nation host Sam Knox and analyst Andy Gresh discusses the three keys to the game for the Patriots to get their first road win of the season in Buffalo.
Christian Benford, Six Others Inactive For Bills Against Patriots
The Buffalo Bills have announced their inactives for Week 4 against the New England Patriots, including number one cornerback Christian Benford and six others.
Here’s how to watch Bills vs. Patriots in Week 4
All the ways to catch the action live when the Buffalo Bills take on the New England Patriots in Week 4
Sadie Strong hosts annual health and wellness expo
BUFFALO, N.Y. (WIVB) — Buffalo-based nonprofit breast cancer support organization Sadie Strong hosted its eighth annual Community Health and Wellness Expo on Saturday at the Northland Workfor…
UB Bulls stopped at goal line in MAC upset bid
AMHERST, N.Y. (WIVB) — The University at Buffalo football team lost at the last second of its conference opener against a favored foe that suffered the most infamous last-second loss of the season. Buffalo quarterback Jason Wright was stopped at the 1-yard line on a fourth down scramble as time expired in Western Michigan’s 20-17 […]
Luukkonen gets the net for the home opener
| WGR Sports Radio Buffalo
Josh Allen Can Set Another Bills Franchise Record Sunday
One rushing score away from eclipsing Hall of Fame legends Andre Reed and Thurman Thomas, Buffalo’s dual-threat quarterback poised to claim the franchise’s all-time touchdown crown.
Bills vs. Patriots: Final injury reports for both teams
Here are the final injury reports for both the Bills and Patriots ahead of their Week 4 clash.
What to Watch For: New England Patriots Defense vs. Buffalo Bills Offense
The New England Patriots begin AFC East play this weekend with a trip to Buffalo to take on the Bills. We review what New England’s defense will need to do to slow Josh Allen and Buffalo’s high-powered offense.
Texas Tech vs Colorado Prediction: Is This When The Buffaloes Turn This Around?
It's been a rough run for Deion Sanders and Colorado, but nothing would change the momentum faster than a win over Texas Tech. Here's the CFN preview and prediction.
Chargers Star Khalil Mack Emerges as Top Trade Candidate
Khalil Mack and the Los Angeles Chargers entered the 2026 season with Super Bowl aspirations. While the defense has been solid, the offense has not held up its end of the bargain.The Chargers sit at 0-3 and are gearing up for a road game against the Seattle Seahawks. This follows a loss in Buffalo in […] The post Chargers Star Khalil Mack Emerges as Top Trade Candidate appeared first on HEAVY.
Bills Face Difficult Roster Decision Amid New Running Back Injury
The Buffalo Bills are in danger of missing running back Ray Davis for Sunday's game against the New England Patriots. The post Bills Face Difficult Roster Decision Amid New Running Back Injury appeared first on HEAVY.
3 bold takes for Bills-Patriots in Week 4
Quarterback Josh Allen and the Buffalo Bills are likely extra motivated to face the New England Patriots in Week 4
Studying Science in an Anti-Scientific Time
This Chronicle Review Deep Cut was first published in 2025. By Julianne Werlin Thanks for reading The Chronicle Review! Subscribe for free to receive new posts and support my work. Subscribe The last two decades have not been kind to science studies. Already bruised and battered by the “science wars” of the 1990s, by the 2000s sociologists of science — who had long argued that science had to be understood in its human context — were encountering the funhouse-mirror version of their own views in right-wing critiques of climate scientists. It was enough to give some prominent scholars pause. “Was I wrong to participate in the invention of this field known as science studies?” asked Bruno Latour, the most famous sociologist of science in the world, in 2003. “Should we apologize for having been wrong all along? Or should we rather bring the sword of criticism to criticism itself and do a bit of soul-searching here: What were we really after when we were so intent on showing the social construction of scientific facts?” In response, Latour proposed a change of method and attitude. Science studies, now chastened and contrite, would no longer seek to strip facts of their authority, but to enrich and enhance them. What this meant in practice was never fully clear. But his diagnosis of problems resonated, even if his solutions did not. Latour’s exercise in public hand-wringing signaled a shift in mood. By 2016, with the first election of Donald Trump, the idea that skepticism of science was a right-wing position, not a left-wing one, had become a commonplace, discussed eagerly in The New York Times. For liberals, vaccine denial during the Covid era and Trump’s second-term attacks on the funding of scientific research, covered extensively in these pages, added a new urgency to the defense of science on both practical and principled grounds. There was little appetite for a sociology or philosophy of science that emphasized the messiness and missteps of the scientific process rather than its integrity and triumphs. The distinguished historian of science Peter Dear’s new book, The World as We Know It: From Natural Philosophy to Modern Science (Princeton University Press, 2025), which seeks to tell the story of 18th- and 19th-century science for a general public, may seem comfortably remote from these bitter contests. In its 16 short chapters, Dear draws swift, sure sketches of major discoveries from Newton to Einstein, ably guiding the reader through debates on stellar nebulae, animal taxonomy, atomic chemistry, evolution, and other flashpoints in the history of science. But though a work of history, Dear’s book must still negotiate our polarized present. In a blurb on its back cover, the historian of biology Lynn K. Nyhart alludes to the “present moment, when scientific knowledge is being swamped by misinformation and its institutions are under siege.” Dear himself, in his conclusion, refers to the “yard signs” and “bumper stickers” that proclaim “Science Is Real.” One antidote to both anti-science propaganda and to reductive slogans in science’s defense is a robust history and philosophy of science: exactly what Dear’s scholarship has long offered. But his new book illustrates how difficult such work has become. Dear, an emeritus professor of history at Cornell University, is best known as a creative and philosophically minded historian of the Scientific Revolution. His edited volume The Literary Structure of Scientific Argument (1991) analyzed the rhetoric of Galileo’s thought experiments to brilliant effect. Discipline and Experience: The Mathematical Way in the Scientific Revolution (1995) was a major contribution to the analysis of scientific experiments in early modern Europe and beyond, while Revolutionizing the Sciences: European Knowledge in Transition, 1500-1700 (2001), now in its third edition, remains one of the best overviews of the profound epistemological upheavals of 16th- and 17th-century science. But Dear has also ventured into later periods. Nearly two decades ago, in The Intelligibility of Nature: How Science Makes Sense of the World (2006), he turned to the 18th and 19th centuries to sketch a history and theory of scientific knowledge. Aimed at a generalist audience, Dear’s simple prose belied serious philosophical ambitions. Science, Dear argued, has two aspects: “natural philosophy,” the quest to understand the true nature of the universe, and “instrumentality,” the applied skills and technologies that allow us to manipulate the world for human advantage. Both strands are ancient, but the innovation of the phenomenon we call “science” was to yoke them together. As Francis Bacon wrote, “Human knowledge and human power meet in one; for where the cause is not known, the effect cannot be produced,” an insight typically abridged to “knowledge is power.” Or, in Bertrand Russell’s characteristically blunt phrase, science has two functions, “1. to enable us to know things, and 2., to enable us to do things.” So far, so conventional. But Dear took issue with this familiar story in one respect. Bacon’s formula implied that theory and practice could be fused in a single method. In fact, Dear argued, the quest to understand nature and the desire to manipulate it were coupled only loosely. They could come together, but they could also pull apart. Focusing on natural philosophy, the “knowing” half of the scientific circle, he used a series of case studies from cosmology, taxonomy, chemistry, electromagnetism, and quantum theory to show how theories changed over time, in dialogue with practice, but never reducible to it. Take the case of matter, the basic substrate of the physical world. In the 18th and 19th centuries, scientists not only disagreed about what it was, but also about how well it could be known. In 1789, the chemist Antoine Lavoisier dismissed speculation about the atomic composition of chemicals as “discussions entirely of a metaphysical nature,” as he sought to orient chemistry away from philosophical abstraction and toward laboratory results. But in the 19th century, atoms returned with a vengeance in the atomic chemistry of John Dalton, who wanted to explain the underlying structure of nature. It was not just that Dalton and Lavoisier had a different set of experimental results, or even a different theory, Dear showed. What counted as an explanation had changed. In arguing that scientific theories depended on their intelligibility to human beings with complex arrays of beliefs and commitments, Dear was in sympathy with science studies. Key figures such as the sociologist Steven Shapin emphasized the importance of psychological mechanisms like trust in the formation and acceptance of scientific ideas. But in focusing on the scientific pursuit of knowledge, not its politics or economics, Dear resisted the more cynical perspective of some of his colleagues. The Intelligibility of Nature strikes a very different note than Shapin’s collection of a few years later, Never Pure: Historical Studies of Science as If It Was Produced by People With Bodies, Situated in Time, Space, Culture, and Society, and Struggling for Credibility and Authority (2010), to name just one example. Walking a very fine line, Dear depicted science as driven at once by complex social dynamics and by the intellectual power of real discoveries. It was a testament not only to his own acumen but also to the vitality of the field that he was able to do so. Nearly two decades later, The World as We Know It returns to the questions broached in The Intelligibility of Nature. Like Dear’s earlier study, it begins with the Newtonian cosmos and ends with debates between Einstein and Bohr on quantum physics. Beyond its terminal figures, many of the same characters appear in both studies, including the naturalists John Ray and the Comte de Buffon; the chemists Étienne François Geoffroy, Antoine Lavoisier, and John Dalton; as well as Charles Darwin and Michael Faraday, among others. Its subject is nearly identical: As in The Intelligibility of Nature, The World as We Know It considers natural philosophy as opposed to instrumentality, here defined as the “desire to create a picture of what the world is really like — the world as God knows it — rather than simply having instrumental or operational control over it.” The two books also overlap in insights — and sometimes even in language. The reader who has learned in The Intelligibility of Nature that Buffon’s method of classifying animals “reflected his belief in the importance of the senses and empiricism in learning about nature (a doctrine associated with Newton and the philosopher John Locke)” will experience a sense of déjà vu on reading, in The World as We Know It, that the classification “reflects Buffon’s commitment to the epistemological stance of Newton and his philosophical underlaborer John Locke, who stressed the role of the senses in creating natural knowledge.” Later in the passage, we read that, “because of its stress on understanding the ways of life of animals in their environments, Buffon’s approach could almost be labeled (anachronistically) as ‘ecological.’” And again, “an anachronistic way of putting it would be to say that Buffon recommends an ecological mode of understanding.” Likewise, in The Intelligibility of Nature we read of Dalton that he was initially drawn to meteorology, and that: He did a bit of experimental work on these things, especially having to do with the water-holding capacity of gases, but his real interest lay in understanding what, at an underlying natural-philosophical level, was really going on physically.” Whereas, in The World as We Know It: He did experimental work on these things, especially concerning the water-holding capacity of gases — although not at a very refined level quantitatively — but he was continually trying to develop a theoretical conception of what was happening physically. The final full chapter of each book closes on the same resigned note. Intelligibility: These days, most serious work on the natural philosophical underpinnings and implications of quantum mechanics is performed not by physicists but by philosophers of science. Among scientific practitioners themselves, Bohr’s attempt to use instrumentality as sufficient grounds for a respectable science has met with a high degree of success. And again, in The World as We Know It: Bohr’s and Einstein’s concerns are now questions that are mostly discussed by philosophers of science rather than by physicists themselves. The marginalization of these sorts of questions amounts to the demise of natural philosophy, at least in physics, in the 20th century. Quantum mechanics “works,” and that’s good enough for most scientists who encounter it. Examples could be multiplied. When handling the same subject matter, some echoes are inevitable. Scholars should not feel that because they have written “Isaac Newton died in 1727” in one book, in the next they must describe him as perishing, expiring, or meeting his maker. But the repetitions of language and arguments (not to mention six reproduced images) threaded throughout The World as We Know It are more extensive than that. They should have been caught by Princeton University Press or its reviewers, and revised. Because the two books have so much in common, it is easy to see where they diverge. The World as We Know It is a less theoretical work than its predecessor. The sociology of knowledge that organized The Intelligibility of Nature has been reduced in scale and folded into readings and examples. The taut interplay between history and theory, which gave the earlier study so much interest, is there, but it is subtle. In the earlier book, the case studies demonstrated theoretical claims about the character and development of science. In the later work, each narrative of discovery is an end in itself. Insights emerge from the history, but they do not control the organization of the study. With the theory muted, it can be hard to understand the logic uniting Dear’s sprawling history of more than two centuries of scientific knowledge. The 16 brisk chapters cover an enormous amount of material. But the closer the volume edges to comprehensiveness, the more obvious the missing elements become. A chapter on “Institutions and Pedagogy,” describing the birth of the research university, illustrates the problem. Inserted roughly halfway through the book, the unnumbered chapter is designed as an “entr’acte,” in acknowledgement that it does not fit the study’s organization around scientific discoveries. Yet as Dear is well aware, no general history of the development of modern science can bracket its 19th-century institutionalization and professionalization. It was the 19th-century university, after all, that gave us the “scientist,” a term coined by the Cambridge philosopher William Whewell. Dear’s history of scientific discoveries implies a wider social and institutional history, but it remains largely subterranean, only occasionally extruded under the pressure of the narrative. It must be said that the balance is not all on the side of the earlier study. There are some advantages to the more historical, less theoretical organization of The World as We Know It. Dear’s accounts of paradigm shifts are remarkably lucid, no small accomplishment given that they span fields and centuries. He makes excellent use of the wealth of new scholarship on Darwin and his influences, to which he has himself contributed. It is satisfying to see puzzle pieces from Buffon’s natural history, Georges Cuvier’s animal taxonomy, Thomas Robert Malthus’s demography, and Charles Lyell’s geology recombined seamlessly in the Darwinian jigsaw. Likewise, Dear’s discussion of stellar nebulae, divided between chapters two and 15, shows vividly how Newton, Kant, Herschel, and Hubble reimagined insights and observations as they sought to discover whether the diffuse light that filtered through early telescopes was a glowing, gaseous substance or discrete but distant stars. Yet despite such pleasures, the book remains a more modest work than The Intelligibility of Nature. Dear has clearly not changed his views about the history of science. But in the two decades that have elapsed, the discipline and the world around it have changed, making it harder to write a sociologically and philosophically ambitious history of science for the general reader. That is a shame, because in the age of Silicon Valley and biotechnology, both the reciprocity and the tensions Dear identified between the epistemological and instrumental ambitions of science are more evident than ever. In recent years, some of the most exciting new books on the history of science in early modernity have focused precisely on this pressure point. Important studies such as Pamela H. Smith’s From Lived Experience to the Written Word (2022), James Poskett’s Horizons: The Global Origins of Modern Science (2022), and Vera Keller’s The Interlopers: Early Stuart Projects and the Undisciplining of Knowledge (2023) all shed new light on how early modern science negotiated the relationship between its instrumental and epistemological ambitions, or in Russell’s phrase, knowing and doing. There is every opportunity for a philosophically informed approach to draw new insights from this wealth of material. Dear, unfortunately, has not done so in The World as We Know It. But for future scholars of the history of science, his body of work over nearly four decades may provide just the model. Julianne Werlin is an associate professor of English at Duke University. Thanks for reading The Chronicle Review! Subscribe for free to receive new posts and support my work. Subscribe
5 Patriots to watch in Week 4’s game at Bills
For the second straight week, Buffalo faces off against an opponent desperate for a win
Basil Family Dealerships expands business to Springville
BUFFALO, N.Y. (WIVB) — Basil Family Dealerships is expanding their business across Western New York with the acquisition of two dealerships in Springville. The automotive group acquired Emerl…
Allen seeks to put sloppy play behind him as Bills host Maye and the Patriots
Buffalo Bills quarterback Josh Allen understands he's got plenty to clean up after committing three turnovers in beating the Los Angeles Chargers.
Bills vs. Patriots: Thursday injury reports for both teams
Here are the injury reports for both the Bills and Patriots ahead of their Week 4 clash.
Bills Facing Heavy Backlash Over Josh Allen Decision
Three games, three wins for the Buffalo Bills to open up the 2026 season.And while they look like arguably the best team in the AFC, the Bills have been employing an offensive strategy that has their fans concerned.Buffalo is averaging the fourth-most yards per game (401.7) with the fourth-best rushing offense (155 yards per game) […] The post Bills Facing Heavy Backlash Over Josh Allen Decision appeared first on HEAVY.
Multiple Experts Have Patriots Pulling Off 'Desperate' Upset of Bills
Multiple experts believe that the New England Patriots can pull off the upset of the Buffalo Bills this week.
Stopping the Bills Rush Attack: Patriots Defense vs. James Cook
The Buffalo Bills seem to be a very run-heavy team now under Joe Brady, but can the Patriots slow their role on Sunday?
Bills Star Josh Allen Slips in NFL QB Rankings
Buffalo Bills star Josh Allen slipped in NFL.com's QB rankings.
Hershey Entertainment & Resorts to Open Mellow Mushroom in Hershey in Fall 2027
Hershey Entertainment & Resorts (HE&R) today announced it will bring Mellow Mushroom to Hershey, Pennsylvania, marking the stone-baked pizza brand’s first location in the state. Mellow Mushroom is slated to open in fall 2027 at 337 West Chocolate Avenue, in the heart of downtown Hershey. The 8,000-square-foot restaurant will be owned and operated by HE&R. […]
Bills Have a Major Problem Emerging in Their Secondary
Rising sack totals mask a vulnerable unit struggling with Christian Benford’s regression and mounting injuries. Now, Buffalo’s depth faces a brutal litmus test against the league’s elite quarterbacks.
Milestone integration for Goshen Health in century long history
WSBT CBS 22 provides news, sports, entertainment and public interest programs to the South Bend, Indiana area including Mishawaka, Notre Dame, Granger, Osceola, Elkhart, Jimtown, Dunlap, New Carlisle, Goshen, Middlebury, Bristol, New Paris, Nappanee, Howe, Lagrange, Topeka, Bourbon, Milford, Syracuse, North Webster, Warsaw, Bremen, Plymouth, Walkerton, Argos, Tippecanoe, Culver, Grovertown, Delong, Rochester, Akron, Winamac, North Judson, LaPorte, North Liberty, Wakarusa, Lapaz, Millersburg, Knox, and Michigan City, Indiana – and these areas of Michigan: St. Joseph, Benton Harbor, Buchanan, Niles, Three Oaks, New Buffalo, Harbert, Bridgeman, Stevensville, Watervliet, Berrien Springs, Dowagiac, Marcellus, Cassopolis, Decatur, Vandalia, Constantine, White Pigeon, Galien and Edwardsburg.
Bills react to tough start for Patriots QB Drake Maye
Buffalo Bills DC Jim Leonhard, New England Patriots QB Drake Maye on division matchup
Bills vs. Patriots: Wednesday injury reports for both teams
Here are the injury reports for both the Bills and Patriots ahead of their Week 4 clash.
Bills Get Injury Update on DJ Moore Before Patriots Game
Buffalo Bills wide receiver DJ Moore landed on the team's injury report before the game against the New England Patriots. The post Bills Get Injury Update on DJ Moore Before Patriots Game appeared first on HEAVY.
WATCH: Senate health committee advances Dr. Nicole Saphier's nomination for surgeon general
WATCH: Senate health committee advances Dr. Nicole Saphier's nomination for surgeon general
“Ted Lasso” says goodbye to [SPOILER] while paying tribute to late star Anthony Head
The “Buffy the Vampire Slayer” alum died earlier this year of complications from pneumonia. He was 72.
Announcers revealed for Patriots' Week 4 matchup against Bills
The announcers have been revealed for the New England Patriots' game against the Buffalo Bills on Sunday.
Dahlin eager to build on last season after Sabres snapped playoff drought
Having enjoyed his first taste of the postseason last year, the 26-year-old Swede is hungry for more as a new season is set to begin.
The summer Steph Curry’s business empire leveled up
The Golden State star signed a sneaker brand deal, dined with Warren Buffett, played in charity golf tournaments, traveled to China, and agreed to a contract extension.
Tennis star Jessica Pegula on Buffalo Bills ownership and her mother's health crisis
CNBC's Alex Sherman speaks with World No. 3 tennis player Jessica Pegula about her family's future in sports ownership and her mother's 2022 health emergency.
Bills news: Assessing Buffalo’s 3-0 start
What has gone right and where can Buffalo improve following the franchise’s fifth 3-0 start in the last eight years?
Bills Announce Historic Josh Allen News Before Key Rivalry Game
Buffalo Bills quarterback Josh Allen is one of just four players in NFL history to record six or more rushing touchdowns in nine straight seasons. The post Bills Announce Historic Josh Allen News Before Key Rivalry Game appeared first on HEAVY.
Buffalo Bills, Josh Allen Keeping Quiet About Knee Injury, Sports Doc Says
A sports doctor says the Bills and Josh Allen are keeping quiet about a possible knee injury after concerns emerged about the quarterback. The post Buffalo Bills, Josh Allen Keeping Quiet About Knee Injury, Sports Doc Says appeared first on HEAVY.
New: Part Sports, Part Science, and All Hometown Pride —Experience The Buffalo Museum of Science’s Latest Exhibit
Things to Do It’s the museum’s first brand-new permanent exhibit since 2018, and they’ve pulled out all the stops.
Alyson Hannigan’s 14-year-old daughter looks exactly like her in new selfie
Alyson Hannigan’s 14-year-old daughter Keeva looks exactly like her in a new selfie shared by the “Buffy” actress.
New “Science Stadium” exhibit opens at the Buffalo Museum of Science
Empire State Development celebrated the grand opening of the $3 million Science Stadium interactive exhibit at the Buffalo Museum of Science (BMS). Developed in partnership with the Buffalo Bills, Buffalo
New exhibit chronicles Tom Golisano’s business and philanthropic legacy
The Golisano Institute in Buffalo unveiled a permanent exhibit honoring founder Tom Golisano’s business, philanthropy and civic leadership legacy.
Big 12 football receiving leaders after Week 4
Here is a look at the top receivers in the Big 12 after Week 4, with Joseph Williams in the top 10 for the third week in a row.
Bills vs. Patriots Week 4 opening odds follow interesting narratives
The Buffalo Bills enter their Week 4 matchup against the New England Patriots with interesting odds
Highmark Foundation and Buffalo Bills Foundation Unveil “Victory Table” to Expand Access to Healthy Food and Wellness Resources Across Western New York
New mobile initiative will bring free healthy meals, nutrition education and community health support directly to neighborhoods in nee
Buffalo Museum of Science unveils permanent Bills, Sabres and Bandits exhibit
The Buffalo Museum of Science opened the $3M Science Stadium interactive, a permanent exhibit that focuses on the Bills, Sabres and Bandits and brings the science and engineering behind professional sports to life.
Josh Allen runs for two scores in Week 3 comeback win
Josh Allen ran for two scores for the third time in as many games in 2026, helping Buffalo edge the Chargers in Week 3.
Justin Herbert Gives Vague Answer to Crucial Chargers Question
The Los Angeles Chargers somehow lost Sunday in Buffalo even after the defense forced five Bills turnovers. Justin Herbert and the offense managed a total of 16 points on a day when Josh Allen had zero touchdown passes and two interceptions.This drops the Chargers to 0-3 on the season with very little hope of a […] The post Justin Herbert Gives Vague Answer to Crucial Chargers Question appeared first on HEAVY.
Bills HC Joe Brady Assigns Blame After Josh Allen’s Struggles
Buffalo Bills head coach Joe Brady took the blame after quarterback Josh Allen committed three turnovers in a win over the Chargers. The post Bills HC Joe Brady Assigns Blame After Josh Allen’s Struggles appeared first on HEAVY.
Tom Brady Takes Jab at Buffalo Bills, Old Highmark Stadium
Tom Brady takes shot at Buffalo Bills, Old Highmark Stadium during TV broadcast. The post Tom Brady Takes Jab at Buffalo Bills, Old Highmark Stadium appeared first on HEAVY.
Allen, Bills outlast Chargers 24-16 despite committing 5 turnovers
Buffalo improved to 3-0 despite Josh Allen's two interceptions and lost fumble.
Los Angeles Chargers Make Roster Moves Ahead of Week 3
The Los Angeles Chargers made a few roster moves ahead of their Week 3 matchup against the Buffalo Bills.
8 more Bills vs. Chargers predictions, scores, odds for Week 3 game
Just one NFL expert thinks the Los Angeles Chargers can escape Sunday with a win against the Buffalo Bills.
Bills Elevate One Player from Practice Squad for Week 3
With Jordan Hancock sidelined by a hamstring injury, undrafted rookie Te’Cory Couch joins the active roster to bolster a depleted secondary ahead of Sunday’s clash with the Chargers.
Bryan Rust Injured in Penguins’ Preseason Finale
Pittsburgh Penguins stalwart Bryan Rust left Saturday’s preseason finale at Buffalo because of an undisclosed injury. Rust, who has pretty […]
5 Chargers to watch vs. Bills in Week 3
Can the underachieving Chargers break through against Buffalo?
Lions Have No Excuses Against a Banged-Up Jets Team
After getting embarrassed by Buffalo, the Lions have had four extra days to stew. Now, Detroit gets a banged-up Jets team at Ford Field—and a chance to make a statement.
Preseason Gamethread: Penguins @ Sabres
Talk about the last preseason game with Pens fans here! The game will be broadcast locally on Sportsnet Pittsburgh+ and MSG-B in the respective local areas for Pittsburgh and Buffalo. Nationally, it will be carried on NHL Network. It will be available via audio on the internet/radio from 105.9 The X.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Bills vs. Chargers: Final injury reports for both teams
Here are the final injury reports for both the Bills and Chargers in Week 3.
Former Sabres First-Round Pick Lands Another Opportunity
Alex Nylander flamed out after just 19 games with the Buffalo Sabres. He has since bounced around the NHL, failing to establish himself as a full-time player at hockey’s highest level. Still, that hasn’t stopped the Calgary Flames from adding Nylander to a one-year, two-way contract off of his PTO, which they made official on […] The post Former Sabres First-Round Pick Lands Another Opportunity appeared first on HEAVY.
Bill introduced to support newborn health screenings
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Game on for Science Stadium at Buffalo Museum of Science
The Buffalo Museum of Science has opened its $3 million Science Stadium interactive exhibit. Developed in partnership with the Buffalo Bills, Buffalo Sabres, and Buffalo Bandits, the permanent exhibit brings
Quick hitters: O-line health, safety depth and Dan Campbell’s first days in Detroit with Glenn
Allen Park — Detroit Lions coach Dan Campbell and quarterbacks coach Mark Brunell met with the media on Friday. Here are the noteworthy items from those conversations. Healthier up front, banged up in the back It’s good news, bad news on the injury front. First, the offensive line is going to be far closer to full strength with starters Blake Miller (knee) and Christian Mahogany (hip) on track to return to the lineup. That provides stability the offense lacked against Buffalo, particularly at right tackle, where backup Larry Borom allowed 11 quarterback pressures and committed a trio of penalties. Subscribe However, with that same unit, veteran Ben Bartch (foot) is likely to miss Sunday’s matchup with the Jets. The left guard competition that’s been ongoing since May has effectively been whichever option is healthy that week. In the back end, safety Thomas Harper (ankle) is also unlikely to be available on Sunday. That leaves the team precariously thin at the position following Avonte Maddox going on injured reserve this week. Christian Izien is expected to get the start alongside Chuck Clark. “Izzy's been working a lot back there and had a full week,” Campbell said. “And he's gotten a ton of work this week, a ton of reps, full-speed reps. ‘This is what you're going to do, this is the calls’ and just dousing him with full-speed reps and he's done a good job this week.” Safety depth is the bigger concern. The team is expected to count on some combination of Jalen Mills, who signed to the practice squad on Monday, Bishop Fitzgerald, the undrafted rookie poached off the Steelers’ practice squad on Tuesday, and rookie cornerback Keith Abney, who doesn’t have experience at safety. “I'll say this about Abney, man, for a rookie, he's a pretty dang smart, conscientious, aware football player that's got a ton of room to really take off,” Campbell said. “…He's young. He's another one, he just needs reps and reps. But, if we need it, that'll be a guy who may have to go in for us.” You can check here for the full injury report, with game designations, later this afternoon. Reflecting on the past Responding to comments made by Jets coach Aaron Glenn this week, Campbell reflected on his earliest days with the Lions, before the coaching staff had been fleshed out and it was just he and Glenn at the facility working through what they wanted things to look like. “It was just he and I in the lab,” Campbell said. The coach said the two would fill the whiteboard that remains in current coordinator Kelvin Sheppard’s office top to bottom with notes about philosophy, coaching style, team identity and the type of players they wanted to target. “He looks different than me,” Campbell said. “I'm taller, I'm whatever. He's quicker. All these different things, man, but we're really the same. I mean we're so much the same. And he's the defensive version, I'm the offensive version. He was my right hand man. …It was fun, man. Those were good days.” Campbell said it was one of the best and worst days of his life when the Jets hired Glenn to be their coach. “AG means the world to me,” Campbell said. “He's one of my dearest friends because I know what he's made of. “…It's because you know you're losing a little piece of you. That's what he meant to me and to us. So, that's hard.” Traits under center A couple of weeks back, Sheppard noted that Brunell had identified Saints quarterback Tyler Shough as the best prospect at the position ahead of the 2025 draft. On Friday, Brunell confirmed his evaluation and explained what he looks for when studying a young quarterback. Here’s the full answer: “Young quarterbacks, you have to look at everything, you know? I look at guys coming out of college just like I look at any free agents that we might be looking at, or guys that we might add to our roster. Do they take care of the ball? Are they on time? How is their decision-making? How are their feet? “It's tough because you look at a college player, you don't understand what they're trying to do offensively, what their reads are, but you can identify when a guy is accurate, obviously, and when the ball's getting there on time. If there are a lot of interceptions, it raises a red flag. And I think with a lot of the spread offenses of what you're seeing, when you see a young player and they're running some pro concepts and he's having to make protection calls, and he's getting the right play out of the run game, and when there's a lot on his plate and he's executing it very well, and he's managing all of that, that really jumps out at you. It’s really hard to find. “That's one thing we saw with Luke Altmeyer. He had a lot of experience. We call it, ‘Hey, he's playing quarterback.’ And what does that mean? It's not just completing passes. It's getting guys lined up, getting the right play, getting the protection call right, just fixing some problems, being able to progress (through reads). And there's still some young guys out there that can do that at a high level, which is good to see.” Regarding Altmyer, who competed for the team’s backup job through the offseason and currently resides on the practice squad, Brunell acknowledged physical development slows once the season starts, because there aren’t reps to go around. However, there’s still extensive mental development that’s ongoing. “The key for him is approach the game as if you're the starter, mentally,” Brunell said. “And that's really all you can do. Approach the game as if you're the starter and be good in the (class)room. You come in alongside Jared (Goff), and you come in alongside Josh (Dobbs) and (do) whatever they need. And if you get an opportunity to talk to Luke, he'll tell you he does have a lot of responsibilities besides just getting donuts for us on Saturday. “For him, it's mentally staying focused, and even though there's really no chance this Sunday of him playing, he has to approach it as if he's taking the first snap and playing the whole game. So what's our game plan? What are our checks? What are we anticipating? And then during the game, we keep him involved as far as looking at coverages and pressures. And so, really, for him, it's just a mental game. And for now, that's all we can do.” Reason for more zone The Lions have significantly increased their usage of zone coverage on defense this season. I asked Campbell if that was a reaction to their personnel or driven by the focus to generate more turnovers, given it can be easier to produce interceptions when you can keep eyes on the quarterback while playing zone. “I think it was a little bit of both,” Campbell said. “We just felt like this would suit us a little bit better up to this point, and then be disruptive and get takeaways, which worked well Week 1. We had two (opportunities) last week against Buffalo we weren’t able to get, but they’re there.” I followed up by asking how much the combination of heavy blitzing with the back end playing zone has contributed to some of the early-season coverage woes, since adding extra players to the pass rush means leaving the coverage short-staffed. “I mean, it’s challenging, and that’s why a lot of the things we’ve done in zone, for the most part, have been to reduce that stress level back there,” Campbell said. “But that also requires the front getting there. And if you don’t get there, we already kind of talked about that, but there (has to be) a trust there.” The alternative, Campbell explained is sending four and it taking longer for the rush to get home, which can create different problems for a defense. “You can bleed yards,” Campbell said about the strategy. “It gets a little longer and it’s dink-and-dunk and run after catch. …So, we do what we think is right by what we feel like our personnel (does well). But also the game plan, who you’re going in to play, the matchups, their offense. “We’re not stuck on one way.” Detroit Football Network is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe