SCROLL NEWS / DISCOVERY
Search headlines
Find the stories shaping the conversation.
Results for " competitive " 797 found 🔀 AI-powered Shuffle
Solo Reload Victory Cup in NA West: Event 1 Event 1 Round 1
Battle your way to Platinum in Reload Ranked to be eligible for the first and second Events of the Season, Diamond for the third, and Champion for the final Event of the Season! Compete for the opportunity to win a cash prize! Reach Round 2 (top 1600 in EU; top 800 in NAC; top 320 in OCE, ASIA, ME, BR, and NAW), where every player who earns a Victory Royale will earn $100 USD. Good luck and have fun!
GOP super PAC pauses spending in North Carolina Senate race, shifting money to Kansas
The new moves from the Senate Leadership Fund reflect a difficult landscape for Republicans, with increasingly competitive races in red states.
NASA Selects Projects to Engage Communities Across the US With NASA Science
Science Activation is a nationwide network of competitively-selected, collaborative projects that extend the impact of NASA science by connecting people and
Crain’s event: UChicago president talks Chicago’s research-to-business challenge
The program is part of Crain’s Most Innovative Companies event, which will celebrate Chicago businesses that are using technology, strategy and new approaches to gain a competitive edge.
Steelers may have found what they need to stay competitive
The Pittsburgh Steelers may have found exactly what they need to win.
Business expert says AI literacy will become as essential as knowing basic word processing
Retail Prophet founder and CEO Doug Stephens explains why the competitive edge in artificial intelligence may come down not to he technology itself, but how leaders use it.
Google’s overdue Gemini 4 Argon reaches the frontier with mixed results for science
Google’s Gemini 4 Argon brings competitive AI performance at introductory prices, but independent tests show uneven results against leading rivals.
Time lost to political haggling means lost momentum for research
While it’s not up to universities to set deadlines for EU institutions, “lost time” in the run-up to the launch of the next Horizon Europe would translate into “lost momentum” for universities, according to Dag Rune Olsen, president of the Young European Research Universities Network.“I think it's important to have [the EU budget] in place in order to be able to work on the research funding mechanisms, because we cannot afford to lose more momentum than we already have,” Olsen told Science|Business in an interview in September, just after EU research lobbies gathered in Brussels to push for a €200 billion budget for the next Horizon Europe programme.A funding gap would mean ramping down research activities, said Olsen. “You can do that quite swiftly, that’s not a problem, but ramping up again is much more difficult.”The last-minute push for an ambitious budget, and for a timely adoption of the research programme, comes at a time when the richest EU states have teamed up to call for significant cuts to European Commission’s proposal for the next multiannual budget, which allocates €175 billion for Horizon Europe. At the same gathering of research associations in September, the European Parliament’s budget rapporteur warned that the EU will need to raise its own taxes, otherwise political pressure and tighter national budgets will translate into a limited EU budget with a less ambitious envelope for research. The research sector hopes EU institutions will reach timely agreement on the budget and on Horizon Europe, but progress has been slow. Legislative progress has been delayed, partly because the European Parliament’s budget committee is still haggling over how to apply new EU-wide spending rules, known as the Performance Framework Regulation, and partly because EU governments have yet to agree on the size of the next EU budget. EU research Commissioner Ekaterina Zaharieva told Science|Business in July that she was hoping for an agreement on Horizon Europe by the end of 2026, but the timelines have been pushed back significantly, with the Parliament now aiming to announce its official position on Horizon Europe only in November. Avoid the funding gapAccording to Olsen, delayed EU funds could prompt universities and researchers to move on and do something else, potentially jeopardising years of work building consortia and collaborations. “If funding is interrupted, the networks fall apart in just a few months,” he said. Olsen also noted that an interruption would affect junior researchers first. PhD students and postdocs are on shorter term contracts and universities risk losing them if funding for EU projects is interrupted. Related articlesEU own resources ‘essential’ for future research budget, says leading MEPParliament haggle over EU-wide spending rules delays vote on Horizon EuropeZaharieva hopes for a Horizon Europe deal in 2026Universities usually have more employees, permanent and short-term staff, than they can cover with national funding, and external funding is essential to keep them all on the payroll. In case of an EU funding gap, “there will be a huge number of people that might end up without any contracts,” he said. Apart from the money issue, Olsen said EU projects forces universities to collaborate more which, in turn, increases the quality of teaching and research. In case of a funding dip, people will look around for opportunities elsewhere, in the private sector or abroad. “And then then you have to recruit again, and it's a tedious business,” said Olsen. “A gap is not a good idea, it's actually a waste of money.”According to Olsen, the difficult political context should encourage universities to make a stronger case for the EU increasing research funding, as universities can deliver on competitiveness, technological sovereignty, security and defence. “The reason why we ask for substantial investments in research is exactly what the Commission, what Europe, the Parliament have been discussing,” he said. “You really need to invest in order to thrive in the longer run.”Focus on the member statesBut EU and national R&D expenditure hasn't kept up with the times. EU governments have failed to reach a spending target set almost 25 years ago. Only six EU countries spend 3% or more of their GDP on R&D. Asked whether universities should put more effort into convincing the governments to ramp up their own spending, but also to support a strong budget for Horizon Europe in the ongoing budget negotiations, Olsen said “the answer is yes.”“We are very actively encouraging our members to talk to their ministries in order to enlighten them about the joint effort,” he said. The network is made up of 25 universities from across Europe, all established in the past 60 years or so.Who will call the shots?Budget and timing issues aside, the Parliament’s research committee has been locked in behind-the-scenes negotiations over the future structure of Horizon Europe, with MEPs disagreeing on the degree to which its collaborative research should be governed by councils of experts.The European Parliament’s lead rapporteur on Horizon Europe wants councils of independent experts to decide on the funding agenda, but the Commission, the Council, and parts of the Parliament disagree. For Olsen, it is normal for politicians to point at the big challenges, but when they start detailing how those challenges should be solved, the endeavour “fails utterly.” He does not necessarily think that “bureaucrats who don’t know the field” would be “much better at it” either. “There has to be a combination” of broad political directions and bottom-up implementation, Olsen said.
Newsom signs anti-monopoly bill after bruising legislative battle
California’s new antitrust law will let prosecutors sue businesses for anticompetitive conduct, but not individuals
Beyond Horizon: Science and competitiveness brief
As Brussels debates how to extract more economic value out of its investments in science and technology, this news tracker brings together the latest developments in EU and national R&I policies, as well as updates on how the worlds of research and industry are working together for a more prosperous Europe.If you have any tips, please email them at news@sciencebusiness.net.You can read the full archive of this blog here.
Joelinton Returns To Training After Recovering From Foot Injury
The Brazilian powerhouse brings his physical presence back to Tyneside, handing Matthias Jaissle a vital tactical boost as the midfield linchpin nears a return to competitive action.
Yankees Birthday of the Day: Johnny Allen
Allen was an ultra competitive right handed pitcher for the Yankees in the 1930s.
Steve Kerr Knows the Warriors Can Stay Competitive This Season
Steve Kerr has faith in the Golden State Warriors.
Andrew Garfield got ‘so scared’ playing basketball with Woody Harrelson: ‘He’s fiercely competitive’
The erstwhile Spider-Man actor “fully froze and folded” going up against the “White Men Can’t Jump” star.
Mike Johnson, Bernie Sanders to campaign in Central Valley for 22nd District race
The dueling visits come as Rep. David Valadao and challenger Randy Villegas face off in one of the country’s most competitive congressional races.
Vance takes battleground role as Trump opens midterm push
Vice President JD Vance is heading into competitive races this week as President Donald Trump begins his fall campaign push in Oklahoma and Alabama, two reliably Republican states without marquee contests expected to determine control of Congress. The split screen comes as Vance has emerged as one of the administration’s most prominent campaign surrogates and […]
Health tech's dealmaking boom is back as firms chase scale and profitable growth
Health tech and digital health merger and acquisition activity remains a major force in 2026, driven by strategic expansion and the race for competitive artificial intelligence capabilities. | Health tech and digital health M&A activity remains a major force in 2026, driven by strategic expansion and the race for competitive artificial intelligence capabilities.
GOP doubts about North Carolina have Republicans shifting focus
Republicans haven’t abandoned the Southern battlegrounds, though they're shifting greater resources to states they see as more competitive.
Revisiting Rivalries: Crystal Palace October Preview Part 1
Crystal Palace fans will be looking forward to the return of competitive matches, with three tense fixtures in the first half of October.
Terim: Italy have ‘significant potential’ but no identity
Former Fiorentina and Milan coach Fatih Terim insists Italy must ‘rediscover identity and competitiveness’ and backs the Turkish FA’s decision to confirm Vincenzo Montella in charge despite a di...
Trump to travel to Ohio to stump for Sen. Jon Husted as the Republican faces competitive challenge
President Donald Trump plans to visit Ohio on Saturday in support of Sen. Jon Husted as the Republican tries to fend off a competitive challenge from Democratic former Sen. Sherrod Brown.
Trump to travel to Ohio to stump for Sen. Jon Husted as the Republican faces competitive challenge
President Donald Trump plans to visit Ohio on Saturday in support of Sen. Jon Husted as the Republican tries to fend off a competitive challenge from Democratic former Sen. Sherrod
Trump to travel to Ohio to stump for Sen. Jon Husted as the Republican faces competitive challenge
President Donald Trump plans to visit Ohio on Saturday in support of Sen. Jon Husted as the Republican tries to fend off a competitive challenge from Democratic former Sen. Sherrod Brown.
Trump to travel to Ohio to stump for Sen. Jon Husted as the Republican faces competitive challenge
President Donald Trump plans to visit Ohio on Saturday in support of Sen. Jon Husted as the Republican tries to fend off a competitive challenge from Democratic former Sen. Sherrod Brown.
Trump to Travel to Ohio to Stump for Sen. Jon Husted as the Republican Faces Competitive Challenge
WASHINGTON (AP) — President Donald Trump plans to visit Ohio on Saturday in support of Sen. Jon Husted as the Republican tries to fend off a competitive challenge from Democratic former Sen. Sherrod Brown. The trip to Vandalia, just north of Dayton, is scheduled to come after stops in Oklahoma on ...
12 Of The Best Android Phones You Can Buy In 2026
Choosing a flagship Android phone used to be easy, before the market became more competitive.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. [1] Intel, “Intel Tech Tour 2025 Panther Lake recap,” Doc. 866361, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/866361/ITT_2025_Panther_Lake_Recap1.pdf [2] Intel, “Core Ultra processors Series 3 datasheet, volume 1,” Doc. 872188-001, Jan. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/872188/872188-001.pdf [3] N. Horiguchi and E. Beyne, “Backside power delivery: How to power chips from the backside,” imec Reading Room, Nov. 25, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/how-power-chips-backside [4] W. Hafez et al., “Intel PowerVia technology: Backside power delivery for high density and high-performance computing,” in Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2, doi: 10.23919/vlsitechnologyandcir57934.2023.10185208. [5] K. Fischer et al., “Intel 18A platform technology featuring RibbonFET (GAA) and PowerVia for advanced high-performance computing,” in Proc. Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2025, pp. 1–3, doi: 10.23919/vlsitechnologyandcir65189.2025.11075006. [6] K.-F. Cheng, C.-L. Teng, H.-Y. Huang, and H.-C. Chen, “Metal oxide composite as etch stop layer,” U.S. Patent 12 176 247 B2, Dec. 24, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12176247B2/en [7] S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS J. Solid State Sci. Technol., vol. 4, no. 1, pp. N3029–N3047, 2015, doi: 10.1149/2.0051501jss. [8] A. V. Mule’, D. J. Towner, D. Seghete, C. R. Ryder, and A. A. Gonzalez, “Multi-layer etch stop layers for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20220102343 A1, Mar. 31, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20220102343A1/en [9] C.-C. Wang and J. H. Wang, “Interconnect structure with dielectric cap layer and etch stop layer stack,” U.S. Patent Appl. 20230253247 A1, Aug. 10, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20230253247A1/en [10] Y. J. Wu, K.-F. Cheng, C.-C. Lee, H.-K. Chang, and H.-Y. Huang, “Etch stop layer for interconnect structures,” U.S. Patent Appl. 20240332070 A1, Oct. 3, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240332070A1/en [11] M. G. Rainville, N. Shankar, K. S. Reddy, and D. M. Hausmann, “Deposition of aluminum oxide etch stop layers,” U.S. Patent Appl. 20180197770 A1, Jul. 12, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20180197770 [12] J. S. Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240112951A1/en [16] Applied Materials, “Applied Materials unveils chip wiring innovations for more energy-efficient computing,” Applied Materials Investor Relations, Jul. 8, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy [17] Samsung, “Samsung showcases AI-era vision and latest foundry technologies at SFF 2024,” Samsung Semiconductor, Jun. 13, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/ [18] C. W. Yeung et al., “Channel geometry impact and narrow sheet effect of stacked nanosheet,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2018, pp. 28.6.1–28.6.4, doi: 10.1109/iedm.2018.8614608. [19] S. Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
Historic businesses discuss staying competitive amid massive growth in south St. George
[NAC] Override Series: Persona 5 Royal Cup Reload in NA Central: Session 1
Take their hearts! Compete for a chance to earn Persona 5 Royal cosmetic rewards. Good luck and have fun!
Joe Neguse launches initiative to boost Democrats running statewide
Democratic Rep. Joe Neguse is sending volunteers into competitive Colorado districts, backing candidates challenging Republicans Lauren Boebert and Gabe Evans.
Trump said he would campaign in midterm battlegrounds. He's starting in deep red states instead
President Donald Trump has vowed to campaign in 35 of the most competitive battleground districts in the final sprint to November’s midterm elections.
‘You’re going to see more of it’: Republican candidates increasingly distance themselves from Trump
On issues like the Iran war and the economy, a number of GOP candidates in competitive races are trying to show some separation from the president.
Axios House: Politics complicates U.S. ambitions in energy race
Politics is an obstacle to the country's competitive energy and climate efforts at a critical time, industry leaders say.
Economic development veteran Mike Malone notes value of statewide competitiveness
Mike Malone, partner at Shallotte, N.C.-based economic development firm Economic Leadership, said cities, counties, and states compete to retain and attract residents and businesses. The firm recently worked with the...
Record-Breaking Tech Innovation, Investment, Entry and Business Formation in Recent Years
Critics of the technology sector have asserted as recently as 2020 that digital markets are stagnant, closed to entry, and low on competitive investment and
Calling all current and future scientists: Kiel is the place to be this week
This week, Kiel has become a meeting place for science in Europe. Researchers, school pupils, young scientists and members of the public are coming together through a series of major events led or co-organised by Kiel University.At the centre of it all are around 150 of Europe’s most talented young researchers, aged 14 to 20, who have travelled to Kiel from nearly 40 countries for the 37th European Union Contest for Young Scientists (EUCYS). Running from 22 to 27 September, the European Union’s flagship competition for young scientists brings together winners of national science competitions to present around 100 original research projects across fields ranging from engineering and computer science to medicine, environmental research and the social sciences. The winners will be announced at the Award Ceremony on Saturday.For Kiel University, hosting EUCYS is both an honour and a natural extension of a much longer story. Germany’s northernmost comprehensive university has invested for many years in supporting young scientific talent and bringing research into dialogue with society. The Kiel Science Factory gives school pupils opportunities to experience research first-hand, while programmes such as Rent-a-Scientist send researchers directly into local classrooms. Major annual public events including Kiel Week and the European Researchers’ Night take science beyond the campus through talks, exhibitions and hands-on activities.That long-standing commitment has increasingly taken on a European dimension – and this week, many of those efforts are coming together.One of the foundations for this success is the European Researchers’ Night (ERN), which celebrates its tenth edition in the Kiel region this year. The initiative is funded through the Marie Skłodowska-Curie Actions, with Kiel University developing the successful EU proposals and securing the funding, while regional partner KielRegion coordinates the many activities on the ground. Together with research institutions, schools, companies, local authorities and civil society, they have built ERN into a major platform for public engagement.Over the years, Kiel’s ERN programme has grown far beyond a single evening into a whole “Science Summer”, beginning with “Science Shopping” in spring and culminating tomorrow, 25 September, in Science Day.“We have developed a wide range of public engagement formats, often together with the other research institutions in the region, the city and regional authorities, schools, companies and civil society,” says Eckhard Quandt, Kiel University’s vice president for research, academic infrastructure and transfer. “Over the past decade, we have increasingly taken this commitment to the European level.”That combination of European funding expertise and strong regional partnerships also helped Kiel University take the next step. Drawing on its experience with ERN and its European networks, including the SEA-EU University Alliance, the university brought together Brest in France and Split in Croatia for a successful bid to the EU’s new Science Comes to Town initiative. Throughout 2026, the three cities are serving as Europe’s first Science Ambassadors, with more than one thousand activities bringing science into schools, public spaces, cultural venues and everyday life.EUCYS is perhaps the clearest example of how Kiel University is using Science Comes to Town to create new connections between major European initiatives. From the outset, the university deliberately planned the contest for the week of European Researchers’ Night and opened the EUCYS exhibition to the wider Science Day audience. Tomorrow, that means thousands of visitors can encounter the next generation of scientific talent first-hand, while the young researchers themselves gain a much bigger public stage.“Because we opened EUCYS up for European Researchers’ Night, there will be a lot of people actually visiting the exhibition,” says organiser Stefanie Altemark of Kiel University.“We wanted Europe’s most talented young scientists not only to compete with one another, but also to become visible to the wider public. At the same time, people in Kiel will have the opportunity to see what the next generation of scientists are already capable of,” says Quandt.“We’ve shown over the last years that science is a big part of Kiel, and it’s always been the goal to not only show that to people in Germany, but also to show it to people all over Europe. Thanks to Kiel University’s expertise in European funding programmes, we have been able to turn that ambition into reality,” says Sünje Fock, who is coordinating the Science Summer at KielRegion.The model is characteristic of Kiel University’s approach: combining European funding expertise and international networks with strong regional partnerships to give major initiatives greater reach and visibility.This year also marks the 30th anniversary of the Marie Skłodowska-Curie Actions, giving Kiel University the special opportunity to welcome Vanessa Debiais-Sainton, Head of Department for the Marie Skłodowska-Curie Actions at the European Research Executive Agency, to Kiel tomorrow. Her visit brings together two priorities that have shaped Kiel University’s work over the past decade: supporting researchers and bringing science closer to society. Debiais-Sainton emphasises how closely the two are connected: "For thirty years, the Marie Skłodowska-Curie Actions (MSCA) have given more than 150,000 researchers the chance to pursue their dreams and open up new fields. Doctoral Networks and Postdoctoral Fellowships give them the freedom to move, to connect, to train and to follow their curiosity across borders, sectors and disciplines. But excellence cannot live only in laboratories. Researchers’ Night takes science out of the lab and into the city, to the families, the schoolchildren and the curious minds who will become the next generation. Kiel shows what that looks like at its best. That is the MSCA promise: open science, open borders, open doors."For Kiel University, these activities are not separate endeavours. They are part of a broader understanding of academic excellence in which outstanding research, talent development, international cooperation, knowledge transfer and engagement with society strengthen one another.“For me, one of the most important lessons from the past decade is that scientific excellence, knowledge transfer, talent development and engagement with society cannot be treated as separate tasks,” stresses vice president Quandt. “They reinforce one another.”That philosophy is also reflected in Kiel University’s current bid for Germany’s Excellence University status. The designation is part of Germany’s national Excellence Strategy, which provides substantial long-term funding to selected universities to strengthen internationally competitive research and their overall institutional development. A successful outcome would provide new opportunities to build on what has already been created: deepening international cooperation, creating more opportunities for knowledge exchange and public engagement, and extending the university’s reach across the region and beyond. “If we are successful, it would allow us to take what we have built in Kiel considerably further – including expanding our networks and transfer activities beyond the region and increasingly across the Baltic area,” says Quandt.This week’s events offer a glimpse of what that could mean in practice: a university using its research strength, European expertise and regional partnerships to create opportunities for scientists at every stage of their careers while making science more visible, accessible and exciting to the wider public.
Analysis | One Republican could hold back the party’s candidates in Pennsylvania. And it’s not Trump.
Pennsylvania Republicans are starting to worry that the state’s lopsided race for governor is directly affecting four of the nation’s most competitive House races.
Golf Insider Calls For Presidents Cup Overhaul
John Huggan argues the Presidents Cup is fading like the 1977 Ryder Cup, urging rule changes to make the International team competitive again.
Hands-on science can be cool
After spending many long days conducting experiments to find a new way to combat bacterial infections in crops, Misha Hegde and Mia Soleil Maurer have been rewarded with international recognition and access to top research facilities. But these are not typical scientists. They are 16-year-old German high school students.“Our supervisor told us that in order to start a project, you need to begin with either a question or a problem,” says Misha, adding that she and Mia had read about antibiotic resistance in certain plants being treated for bacterial infections. “We found out that antibiotics overuse is very common in agriculture,” explains Mia. “Our aim was to create an alternative to antibiotics and to try to raise awareness of the problem of overusing antibiotics.”Their subsequent research has focused on harnessing bacteriophages, the natural predators of bacteria, to eliminate pathogens threatening food crops treated with antibiotics. At the Schuldorf Bergstraße Jugend forscht MakerLab in Seeheim-Jugenheim, located in the German state of Hesse, they discovered a novel phage that infects the Rhizobium rhizogenes bacterium, which causes the hairy root disease that can reduce yields of tomatoes, carrots, soya beans and other food staples.The students believe their method could curb antibiotic use, while protecting plants from infections without disturbing the natural soil microbiome. “The application of phages is host-specific, so they would only kill the targeted pathogen or disease-causing bacteria,” explains Mia. It may also offer environmental benefits, since applying antibiotics can contaminate groundwater.Getting to this point has not been easy. The childhood friends admit to feeling frustrated when their trials did not yield the expected results. “We spent six months on our first experiment, just doing the same thing over and over and over again, to the point where we thought, is it even worth it? Why are we doing this?” Misha says. “You just need to be brave enough to take that first step and keep going.”The benefits of inquiry-based learningTheir determination has paid off. In 2025, the pair won first prize in biology at Jugend forscht, Germany’s national competition for young people interested in science, technology, engineering and mathematics. They were also among the winners of the German Research Foundation Europa-Preis, which is awarded to selected national winners at Jugend forscht, and took third place in the 2025 European Union Contest for Young Scientists.The Jugend forscht Foundation opens doors for young people to connect with scientists as well as industry professionals. Jessica Bönsch, executive director of the Foundation, sees Misha and Mia as prime examples of how young people can develop a deeper understanding of science through their own research projects. “The experience of working on your own research question is very important,” she explains, adding that “inquiry-based learning engages with real-life problems in a way that can be more motivating than traditional classroom teaching.”The Jugend forscht Foundation offers financial support through sponsor pools in Germany’s federal states. Some projects are developed in cooperation with student research centres, university labs or informal collaborative learning areas called makerspaces. Other activities start as hands-on “garage projects” and can grow within the Jugend forscht network and infrastructure.The Jugend forscht Foundation is also a partner of Science Comes to Town, an EU initiative to strengthen public awareness about science and create bridges between researchers and communities. The EU-financed project involves universities, research institutions and other stakeholders in three host cities — Brest (France), Kiel (Germany) and Split (Croatia).“It's so important for people not to live in a bubble, because I think science can be very scary if you misunderstand it,” Mia says of SCTT. The initiative’s aim of raising awareness about science is “absolutely amazing,” Misha adds. “I think it's the best way to kind of make science digestible for the public. In a world where misinformation in science is getting more radical, more dangerous, becoming more of a threat to the trust in scientific infrastructure and foundations, we need such programmes.”Misha and Mia also believe that SCTT can help break down gender stereotypes in science by encouraging young women to study and pursue careers in scientific fields. Both students have benefited from female mentors and encouragement they had when they were much younger. Mia’s love of science began with a class trip to a lab, while Misha — with a smile on her face — says she wanted to study history until “a teacher kind of coerced me into joining a school science club.”Recognition beyond EuropeIn May, Misha and Mia were among the finalists at the Regeneron International Science and Engineering Fair held in Phoenix, Arizona, and involving nearly 1,700 pre-university students from over 60 countries. “It was very crazy because there were so many people and so many teenagers interested in science,” Mia recalls. The event was also challenging. “It was eight hours of continuously presenting your project,” adds Misha.Attending the fair was a chance for the young women to see first-hand the value of international collaboration as well as how research cultures differ. “America is a bit more willing to take risks, and I think that's something we can learn about here in Europe,” Misha explains. However, she continues, “I think Europe has the talent, has the innovation and has the resources” to be competitive.Misha and Mia plan to continue their phage experiments in the new school year, inspired by the project’s hands-on nature and the support they receive from their supervisors. They have also attracted the interest of professional scientists and received invitations to leading research facilities, including the Centre for Synthetic Microbiology, jointly run by the University of Marburg and the Max Planck Institute for Terrestrial Microbiology in Germany. “It is so cool that we can do something to try to move the world in our school and at this age,” Mia says.After completing secondary school, Mia plans to study microbiology and pursue a career in medical research, focusing on Ebola and other infectious diseases. “This has been my dream for so long,” she says. Her friend Misha is interested in biological research with a focus on medicine. “I've gotten addicted to the process of going to the lab, planning out experiments, then failing, trying again,” Misha says. “I think there's just so much to be discovered, so much to be done.”The students' names and photos were published with the permission of their parents.Science|Business, which connects policymakers, academics and industry through its news reporting, analysis and events, is an SCTT partner.
Health Care Partnership outlines workforce progress
More local nursing graduates are staying in the region, according to officials offering an update on the progress of the New Hanover Healthcare Career Partnership at a public forum last night. According to Jack Watson, dean of UNCW’s College of Health & Human Services, the number of UNCW nursing graduates choosing to remain in the area after graduation has climbed from 27% to the mid-40% range. The New Hanover Healthcare Career Partnership aims to address the region’s healthcare worker shortage, with a key focus on nursing through strategic partnerships between UNCW, Cape Fear Community College (CFCC), New Hanover County Schools and the Wilmington Chamber of Commerce Foundation. "Each of the partners had pathway programs,” said Watson, “but they were almost at times done in a silo." One of the New Hanover Community Endowment's largest commitments to date, the collaborative received a $22.3 million grant in 2023, to be disbursed over three years, beginning in 2024. At the public forum, leadership addressed the nursing bottleneck created by the pandemic, and Laurie Whalin, president of the Novant Health Coastal Region, acknowledged that Novant Health had relied heavily on travel nurses during that period, with travel nurses making up about 47% of staff and nursing turnover at 35% at the height of the pandemic. "I can say we are in a tremendously different place today,” Whalin said at the forum. The number of travel nurses employed by the Novant Health Coastal Region has dropped to around 100 today, which Whalin says accounts for less than 4% of the workforce. Roughly two years into the grant term, major stakeholders in the collaboration pointed to various accomplishments tied to the initiative. According to Stephen Hill, vice president of talent development with the Greater Wilmington Chamber of Commerce, 250 more nurses live in New Hanover County in 2026 than in 2023. Whalin added that between 2021 and 2025, the Novant Health Coastal Region has hired close to 1,200 registered nurses. Additionally, according to Whalin, over the past two years, hiring and retention of nursing graduates from UNCW increased by 103%, while hiring and retention of nursing graduates from CFCC increased by 70%. Mandy Mills, director of career & technical education at New Hanover County Schools, pointed to the launch of its first Health Sciences Academy program, established across the county's four traditional high schools (Hoggard High School, Laney High School, Ashley High School and New Hanover High School), which started with 38 students last year. Mills also pointed to growth in the district’s Nursing Fundamentals course, which grew from 10 seats in 2023 to 50 in 2025-2026 and is now offered at all four traditional high schools. Watson emphasized the growing nursing class sizes and offered an update on the school’s accelerated nursing degree, which launched last year. Eleven students graduated in the first class, and all passed their boards on the first try, Watson said. This year’s class has 24 students. When the endowment announced its $22.3 million grant for the collaborative in 2023, UNCW and CFCC were each slated to receive the bulk of the funds, at about $10 million each. UNCW’s plans for the grant money included expanding its simulation lab, Watson said. He added that construction is expected to begin on the simulation lab this year and will likely extend through next year. According to Mary Ellen Naylor, dean of Health & Human Services at CFCC, the college has experienced growth in its associate degree nursing retention, rising from 59% in 2023 to 76% for the May 2026 class. CFCC used part of its endowment funding to support wraparound services, including a housing stipend, tuition assistance, exam assistance, emergency assistance, drop-in daycare and clinical and educational supplies. "We have very strong … students, but once they get into the program, there are competing priorities,” Naylor said. “They are working multiple jobs. They have children. They're single parents." According to Naylor, in 2026, 94% of students who used support services are still enrolled or have graduated. Addressing a question from an audience member about an approaching “enrollment cliff,” driven largely by dropping birth rates, Watson and Naylor said demand remains strong at both schools. “Right now … we do have more applicants than we have spots in our nursing program, and it is still a competitive process to get into,” Watson said. “I do not foresee that changing.” "(We've) doubled enrollment in our nursing programs over the last few years, but just as Dean Watson said, we still have very robust applicant pools, so it is still very competitive to get in,” Naylor said. "We have the applicant pool to support that, but again, it's not as easy as just saying, 'Okay … we're going to take another 90 students.' It's making sure all the resources and infrastructure that we need to educate the students outside the classroom is there as well." In response to a question about applying the collaborative model to other healthcare positions besides nursing, Sophie Dagenais, CEO and president of the endowment, said she sees the potential for the model to expand to other healthcare jobs and even other industries, but that the endowment hopes to learn from this model first. “This is a grant that is in year two of three years, and first we wanted to learn what is this going to demonstrate, what will we learn and then how may we scale it possibly,” she said. According to endowment spokesperson Amber Rogerson, funds for the program are set to expire after June 2027. “It's too early to discuss what happens after that,” wrote Rogerson in an email, “though we know the partners are considering the future, and some of the work supported by the grants is now built into their regular operations.”
Health Care Partnership outlines workforce progress
More local nursing graduates are staying in the region, according to officials offering an update on the progress of the New Hanover Healthcare Career Partnership at a public forum last night. According to Jack Watson, dean of UNCW’s College of Health & Human Services, the number of UNCW nursing graduates choosing to remain in the area after graduation has climbed from 27% to the mid-40% range. The New Hanover Healthcare Career Partnership aims to address the region’s healthcare worker shortage, with a key focus on nursing through strategic partnerships between UNCW, Cape Fear Community College (CFCC), New Hanover County Schools and the Wilmington Chamber of Commerce Foundation. "Each of the partners had pathway programs,” said Watson, “but they were almost at times done in a silo." One of the New Hanover Community Endowment's largest commitments to date, the collaborative received a $22.3 million grant in 2023, to be disbursed over three years, beginning in 2024. At the public forum, leadership addressed the nursing bottleneck created by the pandemic, and Laurie Whalin, president of the Novant Health Coastal Region, acknowledged that Novant Health had relied heavily on travel nurses during that period, with travel nurses making up about 47% of staff and nursing turnover at 35% at the height of the pandemic. "I can say we are in a tremendously different place today,” Whalin said at the forum. The number of travel nurses employed by the Novant Health Coastal Region has dropped to around 100 today, which Whalin says accounts for less than 4% of the workforce. Roughly two years into the grant term, major stakeholders in the collaboration pointed to various accomplishments tied to the initiative. According to Stephen Hill, vice president of talent development with the Greater Wilmington Chamber of Commerce, 250 more nurses live in New Hanover County in 2026 than in 2023. Whalin added that between 2021 and 2025, the Novant Health Coastal Region has hired close to 1,200 registered nurses. Additionally, according to Whalin, over the past two years, hiring and retention of nursing graduates from UNCW increased by 103%, while hiring and retention of nursing graduates from CFCC increased by 70%. Mandy Mills, director of career & technical education at New Hanover County Schools, pointed to the launch of its first Health Sciences Academy program, established across the county's four traditional high schools (Hoggard High School, Laney High School, Ashley High School and New Hanover High School), which started with 38 students last year. Mills also pointed to growth in the district’s Nursing Fundamentals course, which grew from 10 seats in 2023 to 50 in 2025-2026 and is now offered at all four traditional high schools. Watson emphasized the growing nursing class sizes and offered an update on the school’s accelerated nursing degree, which launched last year. Eleven students graduated in the first class, and all passed their boards on the first try, Watson said. This year’s class has 24 students. When the endowment announced its $22.3 million grant for the collaborative in 2023, UNCW and CFCC were each slated to receive the bulk of the funds, at about $10 million each. UNCW’s plans for the grant money included expanding its simulation lab, Watson said. He added that construction is expected to begin on the simulation lab this year and will likely extend through next year. According to Mary Ellen Naylor, dean of Health & Human Services at CFCC, the college has experienced growth in its associate degree nursing retention, rising from 59% in 2023 to 76% for the May 2026 class. CFCC used part of its endowment funding to support wraparound services, including a housing stipend, tuition assistance, exam assistance, emergency assistance, drop-in daycare and clinical and educational supplies. "We have very strong … students, but once they get into the program, there are competing priorities,” Naylor said. “They are working multiple jobs. They have children. They're single parents." According to Naylor, in 2026, 94% of students who used support services are still enrolled or have graduated. Addressing a question from an audience member about an approaching “enrollment cliff,” driven largely by dropping birth rates, Watson and Naylor said demand remains strong at both schools. “Right now … we do have more applicants than we have spots in our nursing program, and it is still a competitive process to get into,” Watson said. “I do not foresee that changing.” "(We've) doubled enrollment in our nursing programs over the last few years, but just as Dean Watson said, we still have very robust applicant pools, so it is still very competitive to get in,” Naylor said. "We have the applicant pool to support that, but again, it's not as easy as just saying, 'Okay … we're going to take another 90 students.' It's making sure all the resources and infrastructure that we need to educate the students outside the classroom is there as well." In response to a question about applying the collaborative model to other healthcare positions besides nursing, Sophie Dagenais, CEO and president of the endowment, said she sees the potential for the model to expand to other healthcare jobs and even other industries, but that the endowment hopes to learn from this model first. “This is a grant that is in year two of three years, and first we wanted to learn what is this going to demonstrate, what will we learn and then how may we scale it possibly,” she said. According to endowment spokesperson Amber Rogerson, funds for the program are set to expire after June 2027. “It's too early to discuss what happens after that,” wrote Rogerson in an email, “though we know the partners are considering the future, and some of the work supported by the grants is now built into their regular operations.”
Logitech G Unveils Fifteen New Products at Logitech G PLAY 2026
There has never been a more exciting time to be a gamer. Today at Logitech G PLAY 2026, Logitech G unveiled fifteen new products, along with new software experiences and breakthrough designs created to elevate how competitive players, creators, and everyday gamers play. As blockbuster releases,...
Georgia university opens new competitive science lab, engineering center
Kennesaw State University announced what it called a major milestone with the opening of the Hornet Hub, a dedicated 12,000-square-foot facility for student competition teams.
Citi jumps into the ad business, enters a competitive market
The banking giant is letting brands target ads to its more than 70 million customers based on their spending habits.
Buffalo Sabres hungry for more a season after ending playoff drought
It won’t be easy in a highly competitive Atlantic Division, but the Sabres are leaning on their youthful core to take yet another step after the team closed last year on a 39-9-5 surge to win its first Atlantic title.
Medicine goes global: How international students break into pre-health fields
With changing immigration policies and growing uncertainty over work authorization for foreign nationals, one student organization on campus hopes to help pre-health international students gain a competitive edge.
Oregon's competitiveness ranks fall as business group urges policy reforms
Bend, Ore. (KTVZ) --- Oregon Business and Industry released its 2027-28 Oregon Competitiveness Agenda today, urging state lawmakers to reform tax and regulatory policies to address ongoing economic stagnation. The statewide business group highlighted several indicators showing Oregon trailing national growth and employment averages over consecutive years. Data cited in the report shows Oregon's economy
Europe has the science. Now it needs a clinical trials system to match.
Europe has the scientific expertise to lead the next generation of cancer research, but slow and fragmented clinical trial processes, particularly in the case of multinational trials, are not allowing it to reach its full potential. The EU Biotech Act can address the existing bottlenecks to turn this excellence into faster research, stronger competitiveness and earlier opportunities for patients.
The Best Competitive Cards from Pokémon TCG: 30th Celebration -...
Pokémon has officially reached its 30th anniversary, and with that comes another special anniversary set in 30th Celebration. As you would probably
Poll: Most voters say Trump has hurt the economy as competitive midterm election looms
Trump’s approval and economic ratings point to a gloomy environment for the GOP, but the race for Congress is closer than in his first midterm, with the Democratic Party still unpopular.
California Republicans walk tightrope as Trump jumps into campaigning
California Republicans running in the state's most competitive House races are appearing to keep some measure of public distance from Trump ahead of the Nov. 3 election.
I reckon Red Bull will definitely give Newcastle wings
NEWCASTLE finally have a squad that could make the Prem competitive from top to bottom. It will likely take them some time to hit full stride given there are 25 new faces at Kingston Park, but their Prem Cup win over Leicester last week showed their direction of travel. Red Bull’s takeover can only be […] The post I reckon Red Bull will definitely give Newcastle wings appeared first on The Rugby Paper .
Override Series: Cyberpunk: Edgerunners Cup Zero Build in Europe: Session 1
Keep running on the edge. Chase the win. Team up as a trio and compete for a chance to earn Cyberpunk: Edgerunners cosmetic rewards. Good luck and have fun!
Vance campaigns in red Iowa but barely mentions competitive Senate race
(CNN) — Vice President JD Vance hit the trail in Iowa Friday — a state his boss won by double digits that’s now home to competitive Senate and gubernatorial contests
UA Trustees seek review of athletic program competitiveness
With Razorback football program failure becoming an obvious concern debated with varying degrees of vigor in many breakfast diners statewide, a member of the University of Arkansas Board of Trustees...
As pyramid scheme past is challenged, Democrat Woodson Bradley says she was victim, not perpetrator
A key issue in a competitive race for a Mecklenburg County state Senate seat is Democrat Woodson Bradley's time in sales for a company that was shut down for being a pyramid scheme.
WATCH LIVE: Vance speaks at rally in Iowa as competitive midterm races heat up
A view from DC: A sudden shift in gravity for AI politics
Instead of asking whether to regulate AI, Congress is asking how to build accountability without surrendering U.S. competitiveness.
Democrats aim to flip Iowa's U.S. Senate seat in an increasingly competitive race
The race for U.S. Sen. Joni Ernst's open seat is getting increasingly competitive. Democrats hope it's one of the Senate seats they can flip to gain control of the chamber.
Burlington’s headquarters move to Philadelphia puts spotlight on New Jersey’s difficult business climate, experts say
Gov. Mikie Sherrill has defended her growth strategy, but advocates say the state must do more to boost competitiveness.
Sticker Shock at the Doctor's Office Could Motivate Midterm Voters
Steep jumps in health insurance premiums and deductibles are top of mind for many voters heading into midterm elections. KFF Health News chief Washington correspondent Julie Rovner explains how rising costs may shape competitive races. She also distills plans from candidates on both sides of the aisle to bring costs down.
Republican 'cavalry' arrives with a Trump-backed $150 million ad blitz in key races
To counter a difficult political environment, two Trump-aligned super PACs have reserved more than $150 million in ads — primarily in deep red House and Senate races that have now become competitive.
Did the Kings Get Better Despite a Quiet Offseason?
Sacramento’s addition-by-subtraction strategy swaps aging stars for defensive versatility to spark a postseason surge in the competitive West.
In Arizona's most competitive district, Ciscomani and Mendoza spar over healthcare policies
The future of insurance, hospitals and healthcare is a major issues in the race between Juan Ciscomani and JoAnna Mendoza
Presidents Cup Stars Get Final Tuneup Before Medinah Showdown
Jackson Koivun and six other Presidents Cup players use the Biltmore Championship as their final competitive tuneup before next week's showdown at Medinah.
Canada looks to deepen research and education links with the EU
Canada is looking for deeper research and education links with the EU, according to its prime minister, Mark Carney. His comments followed hard on the heels of an offer from European Commission President Ursula von der Leyen to give his nation associate membership of the EU, a status that currently has no legal status or definition. Both sides have yet to detail how this newfound political enthusiasm will translate into concrete action.Addressing the European Parliament on September 17, Carney cited both the Horizon Europe research and innovation programme and the Erasmus+ student mobility scheme as areas for future collaboration.Association with the next iteration of Horizon Europe “would allow us to pool resources, cooperate on frontier technology, leverage our world-class research institutes and universities,” he told MEPs. Canada joined the present programme in 2024, but only takes part in Pillar 2, which supports collaborative research projects. Carney also said that young people should be allowed to work, study and live where they want, on either side of the Atlantic. “Canadian membership of Erasmus+ would give your students and ours more opportunity to learn at some of the world’s top universities, to broaden their horizon and to build those lasting ties that will sustain our alliance,” he said.Limited exchanges with Canada are already possible, for example in the Erasmus Mundus strand of the scheme, which supports joint master’s programmes. This would be considerably increased if the country became a full associate member, a club currently limited to nations neighbouring the EU.Most favoured nation?As for the offer of associate membership of the EU, the aim would be to build “an alliance for the future to create a common prosperity and economic security base,” von der Leyen said during her state of the European Union address, also in the European Parliament in Strasbourg, on September 16.“We will work on intelligent manufacturing,” she went on. “We will create a tech alliance. We will integrate defence industrial bases. We will make the Arctic a flagship joint project. We will work on energy-critical minerals and batteries, on [artificial intelligence], quantum, cyber and economic security.”Mona Nemer, Canada’s chief science advisor, told Science|Business that the political speeches by Carney and Von der Leyen will open the door to even more scientific cooperation between Canada and the EU. She even attributed the broader political partnership to the scientific diplomacy of Horizon Europe association. “The science and research collaborations have predated this political rapprochement,” she said.While she is not part of the government decision-making process, Nemer thinks Carney’s speech in the European Parliament is more than “political posturing” and the Canadian government is likely to come up with more practical ideas for how to boost collaboration in the near future. “The prime minister mentioned Horizon [Europe] and Erasmus+, maybe there is something more concrete around this,” she said.She went on to suggest that Canada and Europe could also work more closely together on setting international standards for emerging technologies, AI safety, data sovereignty and joint research infrastructures, such as particle accelerators and marine research fleets.Nemer confirmed that science cooperation will be on the agenda at an upcoming EU-Canada summit in October. She met recently with EU ambassadors to Canada to "see where the possibilities are, to signal that there is interest."Room for expansionLike other countries outside Europe that are associated to Horizon Europe, such as South Korea, Australia or Japan, Canada is not allowed to host European Research Council (ERC) grantees. However, Canadian universities hint they would like re-open that discussion. “Canada’s participation in Horizon Europe, the world's largest research funding programme, has been a big success,” said Robert Asselin, the chief executive of U15 Canada, an umbrella body for some of the country’s biggest research universities, in a statement. “Ensuring swift re-association to the next research programme, will be vital to maintain this momentum. We would welcome efforts to explore further opportunities to collaborate with European partners, such as through the European Research Council,” he said. Related articlesHow a new multilateral defence bank could boost innovationEurope’s independence hinges on innovation, von der Leyen saysBut so far, there are no details from the Commission on how von der Leyen’s proposal would boost Canadian access to the ERC or other sensitive research calls in Horizon Europe. And it is unclear how other non-European associated countries, such as New Zealand or Australia, would react if Canada was given better access than them. The same questions may arise closer to home. “How would a new category of associate member of the EU differ from Norway’s participation in EU programmes through the European Economic Area?” asked Jan Palmowski, secretary general of the Guild of European Research-Intensive Universities. “And how does this proposal for Canada change discussion for the UK, Norway and Switzerland for the next Multiannual Financial Framework?”Another area for discussion is how far Canadian organisations can participate in sensitive projects. “I would expect some of the most crucial issues at hand to be whether Canada can participate more closely and predictably in calls that are deemed sensitive on research security or EU preference grounds, on critical technologies, for instance,” Palmowski said. Canada’s participation in other parts of Horizon Europe, as well as the European Competitiveness Fund, might also be discussed, he added.Whatever the details, closer cooperation between the EU and Canada represents a “substantial” opportunity, according to Mattias Björnmalm, secretary general of the Cesaer university group. “Scientific excellence depends on talented people being able to work together, exchange knowledge and access complementary expertise and infrastructure,” he said. “A closer EU-Canada partnership would strengthen these conditions and provide greater certainty for long-term collaboration.”
'It will be a tricky game'
Manchester City boss Enzo Maresca says he expects a "tricky game" against Championship side Norwich City in the Carabao Cup on Thursday evening, and has hinted at rotating his starting XI. Maresca confirmed he will hand goalkeeper Geronimo Rulli his first competitive appearance for the club since signing from Marseille in the summer.
Pete Buttigieg rallies with Mike Lawler challenger in competitive House race
Cait Conley attacked Mike Lawler over his ties to President Trump.
Healthcare affordability is shaping competitive races ahead of the midterm elections
Healthcare costs are rising at their fastest pace in decades, just as early voting begins in Virginia. KFF Health News' Julie Rovner says the moment echoes the run-up to the Affordable Care Act — and voters are taking notice.
EU membership bid gives boost to Moldova’s fledgling R&D landscape
Moldova’s push to join the EU is having the spillover effect of helping to improve the country’s R&D landscape, which in recent years has suffered from fragmentation, decreasing personnel and a lack of research infrastructure.The country became an EU candidate country in 2022, alongside Ukraine, and officially began accession negotiations in 2024. With a pro-EU government, Moldova has been actively carrying out reforms to align with EU standards. This has helped accelerate the development of R&D, said Igor Chiosa, acting head of the Research and Innovation Policy Directorate at Moldova’s Ministry of Education and Research. “Our R&D landscape is moving up, and we are more and more involved in the European Research Area,” he said. “The support we receive from the EU is very important, not only financially, but also because of incentives, consultation and capacity building.”The R&D landscape in the former Soviet republic is still relatively underdeveloped, despite attempts at improvement going back to a 2004 law on science and innovation and later reforms in 2017 and 2018. But the system remains in a “precarious situation” and “in the process of contraction,” according to an assessment carried out by the government for the current National Programme for Research and Innovation, which runs from 2024 to 2027. The analysis highlights in particular the declining number of researchers and PhDs, which has been continuously falling, as well as limited research funding. This is around 10 times lower than the EU average and “insufficient to maintain a level of research activity that supports higher education and meets the needs of the economy.” The mechanisms for allocating research funds are also described as inefficient, as well as the general fragmentation of the landscape, with research and innovation activities being carried out in 67 different places. The lack of strategic vision for research infrastructure is also noted. The strategy sets out to address these issues and is being fuelled by reforms linked to EU accession. Moldova now has a regulation on open science and gender equality. There is also a new support mechanism for technology transfer offices and a business-academia roadmap. In 2025, the country also became the first Eastern Partnership country to approve a Smart Specialisation strategy, which will coordinate its R&D efforts to focus on strengths, within a European context. “We’ve done a lot in terms of normative acts,” Chiosa said. Horizon Europe successMoldova is also seeing more success in the EU’s flagship R&D programme, Horizon Europe. The country has now won nearly €15 million in funding, already double the amount won under the previous programme, Horizon 2020, and more than the €10 million target set by the government. Chiosa said the priority has shifted now to winning more research-centred projects, rather than those related to support and capacity. Moldova is also targeting further involvement in large European projects. Last year, it joined the EuroHPC Joint Undertaking giving Moldovans access to Europe's supercomputing network. The country is also a member of Danubius-RI, a European research infrastructure focused on river and sea research. Despite these efforts, Moldova’s research capacity is still shackled by its limited R&D budget, which equates to 0.23% of its GDP. This is around half of what its neighbour Romania spends, which is the lowest in the EU. According to Chiosa, the research budget is increasing year-on-year, jumping by €6.34 million between 2024 and 2025. But this doesn’t show up when looking at it as a proportion of GDP. “Of course, it’s difficult,” he said. “That is why we are putting more emphasis on collaboration between business and academia, as well as participation in Horizon Europe, to try to diversify our sources of funding.”A World Bank loan of €30 million, plus a grant of €7.8 million, was agreed in 2025 to support the modernisation of Moldova’s universities. As part of this, a call was launched this year to provide universities grants of up to €900,000 to develop their research infrastructure. Moldova is also collaborating closely with Romania, with which it shares a common language, funding 100 joint projects in 2023 and 2024. This support has been instrumental. “They are helping with sharing their expertise, inviting us into consortia, and lots more,” Chiosa said. Looking forward, Moldova is eagerly anticipating joining the EU. “We are looking closely at what the EU is doing and will shape our future national programme in research innovation accordingly.”EU accession “blocked at a technical level”Moldova is aiming to join the EU by 2028, but despite its swift and eager efforts to meet the accession criteria, there remain obstacles outside of the country’s control. For a country to join the EU, it must have certain legislation in place and meet specific standards in various areas. This is categorised into six thematic clusters containing 33 chapters. Moldova and the EU have so far opened two of the clusters, numbers one and six. The first covers fundamental laws, such as the judiciary, security and financial legislation. The sixth covers external relations. The remaining four clusters are still unopened. This includes the third cluster, on competitiveness and growth, which contains the chapter on science and research.Related articlesQ&A: Albania’s ambition to become a ‘moderate innovator’Data corner: Horizon success rates are droppingThe European Commission has confirmed that these clusters are ready to be opened, with an official saying that the Commission is encouraging EU governments, who have the final say, to move forward on the matter. However, both clusters two and three remain blocked by the EU Council’s working party on enlargement and countries negotiating accession to the EU, a different official, representing the Council, confirmed.This working party is set to meet several times in the coming weeks, with a Council meeting scheduled for mid-October in which enlargement, and Moldova’s bid, will be discussed. But there is no certainty that these talks will lead to progress. According to the Council source, it is “completely impossible to foresee if and when the file will be unblocked,” citing the sensitivity of the matter. Moldova’s situation is particularly complicated. One factor is that it borders Ukraine and is increasingly embroiled in Russia’s war, with drone incursions occurring more often on its territory. Another is Transnistria, a Russian-backed breakaway state that lies within the territory of Moldova. It is unclear how the EU would be able to accept Moldova into the bloc while this situation remains unchanged. While there is no direct reason to delay opening cluster three with Moldova, as it covers matters unrelated to security, it could be that the EU is reluctant to speed through accession negotiations without first resolving broader, geopolitical issues.Chiosa is confident that, if and when the chapter on science and research is opened, Moldova will be able to finalise it quickly. It doesn’t require any legislative changes and is only a matter of proving certain standards, which Chiosa believes Moldova is well prepared to do. “We hope that chapter 25 on science and research will be one of the first chapters opened and closed,” he said.
Analysis | The midterms are over. Sort of.
Most Americans don’t live in competitive House districts, so who will represent them in Congress next year was likely decided in the primary.
New Small Business Alliances Signal Competitive Positioning by 40+ IT and Consulting Leaders Across FedCiv, FedHealth, and DoD
In the GovCon IT and consulting market, some companies react to opportunities. Others shape the board well before the game begins. Mentor-protégé agreements fall squarely into the latter category. These partnerships are not administrative check-the-box exercises. They require sustained commitment, alignment at the leadership level, and a clear view of where the market is heading. […]
Community businesses need to show up in AI search, not just Google
Community businesses need to adapt to AI search to improve local visibility. It helps them connect with nearby customers and stay competitive as search behavior evolves.
As WA’s economy slows, it’s boom times for government task forces
The Partnership for a Competitive Puget Sound is the third high-profile task force this year – and a sign, perhaps, that political consensus is growing for economic solutions.
Sustainability Spotlight: The competitive edge
Small businesses drive New Hampshire’s economy, accounting for roughly 97% of all state enterprises and generating the majority of its jobs, according to the U.S. Small Business Administration.
WA's business ranking drops from 1st to 11th as Puget Sound region loses nearly 7,000 jobs, report finds
A new business report from Challenge Seattle warned the region is losing its competitive edge and identified the factors driving the decline.
Business Leader Briefing with Senator Fischer: What Small Businesses Should Know About the Expanded Paid Leave Tax Credit – September 24 - Small Business & Entrepreneurship Council
11:00 AM ET September 24, 2026 Providing competitive benefits like paid family and medical leave can be challenging for small businesses, but a recently expanded federal tax credit could help make it more affordable. Join Public Private Strategies on September 24 at 11:00 AM ET for a virtual business leader briefing on the newly permanent […]
Former Gov. Gregoire: Puget Sound lost nearly 7,000 jobs, losing competitive edge
European science calls for ambitious investment in research: "Current decisions determine Europe's future. We are falling behind China and the USA"
"To remain global leaders, a competitive economic power, and a sovereign actor, Europe needs strong science and innovation." Seven scientific organizations, representing...
PENN Entertainment holds steady with $18 target amid mixed earnings and debt concerns.
PENN Entertainment maintains a Hold rating with an $18 price target due to mixed Q2 earnings and limited valuation upside compared to peers. The retail segment showed solid growth with a 5.6% increase in adjusted EBITDAR, especially strong in the Midwest and West regions. However, the Interactive segment's revenue growth has slowed sharply despite improving profitability, raising concerns about long-term competitiveness. The company remains highly leveraged with net debt around 5.2x–5.5x, making proactive debt reduction and consistent Interactive profitability key factors to watch going forward.
Carnevali: ‘Juventus built competitive squad, pleasing to see Sassuolo’
Juventus director Giovanni Carnevali admits it’s emotional returning to his old club Sassuolo as an opponent, but they built ‘a competitive squad’ to deal with injury problems.It kicks off at th...
NFL Writer Has Interesting Play-Calling Prediction For Sean Payton
Davis Webb takes the reins in Denver, but experts predict Sean Payton’s competitive fire will lure him back to the headset for at least one critical showdown.
Top Lawmakers Agree A.I.’s Risks Are Rising but Say They Have No Quick Fix
House Speaker Mike Johnson warned on Sunday of competitive risks from China, and Hakeem Jeffries, the minority leader, said Congress should start regulatory talks this week.
Former college athletes: We're not pushing sports on our kids.
We've decided to take a low-pressure approach to competitive youth sports with our two kids.
The White House’s Midterm-Travel Sweepstakes
Cabinet members were rewarded points and praise for appearing in congressional districts and states with competitive midterm elections.
Kenny Dillingham Breaks Silence on Arizona State’s Fourth-Quarter Collapse
The Arizona State Sun Devils are now 1-1 on the 2026 season in year four under Kenny Dillingham.The Sun Devils are fresh off of a 48-20 loss to #10 Texas A&M in a game that happened to be much more competitive than the final box score indicated.The head coach brought light to the mistakes that […] The post Kenny Dillingham Breaks Silence on Arizona State’s Fourth-Quarter Collapse appeared first on HEAVY.
CEOs Are Using AI, but Few Are Planning for What Comes Next
AI should be embedded into business planning to strengthen execution, governance, competitiveness, and long-term growth.
Nets Labeled as ‘Noncompetitive Without Own Pick’ in 2025-26
With Houston controlling their draft fate, Brooklyn pivots toward a veteran-led push for the Play-In, betting on Julius Randle and new depth to defy low expectations.
The Prescription for Better Health Insurance? Competition.
Anticompetitive behavior, such as consolidation, in the health-insurance industry has allowed a small group of insurers to dominate the market. One of the main drivers of this behavior is “adverse selection,” where individuals know more about how sick they are than insurance companies do. To mitigate the risk of paying out more claims than they can cover, insurers often raise their premiums. Kellogg’s Amanda Starc and her colleague argue that, to create a truly healthy health-insurance marketplace, regulators and policymakers need a framework for rethinking the complex interactions between adverse selection and regulatory guardrails.
With pace and real finesse – fans vote for Michael Olise
Explosive acceleration, irresistible dribbling and a clinical finish with real finesse! In his first competitive match following the summer break, Michael Olise impressively demonstrated that he had l...
UK Business Calls For Scrapping Taxes on Electricity Bills
UK business groups urge Chancellor John Healey to scrap electricity levies, warning high energy costs threaten industry competitiveness.
How Jeremy Gosch is refocusing Hy-Vee
Jeremy Gosch, in his fourth year as Hy-Vee’s CEO, is steering the large, Midwest regional grocery chain through a competitive landscape unlike any faced by his predecessors. The four Hy-Vee CEOs who preceded Gosch helped transform a small Iowa grocery chain into a regional retailer with more than $14 billion in annual sales. Along the…
Mousinho forecast close Championship season
Portsmouth head coach John Mousinho says that the Championship has already shown to be "really competitive" at both ends of the table this season.
Empty seats, socialism and Trump dominate the Republican midterm convention
The two day Republican convention in Dallas showcased the party's biggest asset in trying to win competitive midterm races and its greatest obstacle: President Trump.
Empty seats, socialism and Trump dominate the Republican midterm convention
The two day Republican convention in Dallas showcased the party's biggest asset in trying to win competitive midterm races and its greatest obstacle: President Trump.
Score Prediction: Does Michigan Have What It Takes Against Oklahoma?
Michigan will host Oklahoma on Saturday as the underdog and will need to be much better than they were last week to even be competitive.
NFC West should remain the NFL’s best division in 2026
If the Rams, Seahawks and 49ers remain competitive, the division could field three playoff teams again
Gyokeres shows again why he should not start for Arsenal
Viktor Gyokeres has sat on the bench in Arsenal’s first four competitive matches of the season, failing to come on in their opening two league games as Kai Havertz was preferred.The decision was baf...
McInnes on 'fire and ice', derby first & 'godsend' Miovski
Rangers manager Derek McInnes has been speaking to the media before the League Cup quarter-final against Celtic on Sunday at Ibrox. The Ibrox boss emphasised the importance of striking the first blow against a good Celtic team to deliver the chance to "be relevant domestically again in terms of winning trophies". McInnes stressed the need for discipline alongside being competitive and aggressive, adding a "bit of fire and ice at the right times can help matters".
Arsenal advances in talks over new deal for three players
This is a really good time for Arsenal as a football club as they look to ensure they have the best possible season by the end of this campaign.They have won all their competitive matches so far, and ...