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Tony Fadell on why the first wave of AI gadgets failed — and what comes next
The “father of the iPod” says the first generation of AI gadgets failed to solve real problems — and the next wave will need to earn consumers’ trust.
The Politics of Sustainability Have Changed. The Business Case Hasn’t.
Corporate sustainability may have fallen out of favor in some executive and political circles, but the business case remains strong: Companies continue to invest because sustainability initiatives can deliver measurable gains in profitability, resilience, and growth. Drawing on research from NYU Stern’s Center for Sustainable Business and other recent studies, the article shows how four areas in particular—circularity, decarbonization, sustainable sourcing, and employee well-being—can lower costs, reduce risk, strengthen supply chains, improve productivity, and create new revenue opportunities. Examples from industries including automotive, healthcare, apparel, energy, consumer goods, and manufacturing illustrate how companies are capturing value through resource reuse, energy efficiency, resilient sourcing strategies, and investments in frontline workers. While the language of ESG may be losing momentum, the underlying business fundamentals have not changed: organizations that systematically address material environmental and social challenges, quantify the financial impact of their efforts, and embed sustainability into core decision-making are better positioned to improve operational performance and create long-term enterprise value.
The Politics of Sustainability Have Changed. The Business Case Hasn’t.
Corporate sustainability may have fallen out of favor in some executive and political circles, but the business case remains strong: Companies continue to invest because sustainability initiatives can deliver measurable gains in profitability, resilience, and growth. Drawing on research from NYU Stern’s Center for Sustainable Business and other recent studies, the article shows how four areas in particular—circularity, decarbonization, sustainable sourcing, and employee well-being—can lower costs, reduce risk, strengthen supply chains, improve productivity, and create new revenue opportunities. Examples from industries including automotive, healthcare, apparel, energy, consumer goods, and manufacturing illustrate how companies are capturing value through resource reuse, energy efficiency, resilient sourcing strategies, and investments in frontline workers. While the language of ESG may be losing momentum, the underlying business fundamentals have not changed: organizations that systematically address material environmental and social challenges, quantify the financial impact of their efforts, and embed sustainability into core decision-making are better positioned to improve operational performance and create long-term enterprise value.
Truckers thought the worst was over. Then diesel prices doubled
The trucking industry and the consumer-driven US economy have ridden out energy shocks before. But the timing of this one stings.
Scientists Urge Consumers to Stop Buying Products Made From Antarctic Krill
A new global boycott comes as major retailers withdraw krill products from their shelves to protect whales and other marine life.
Massie files bill to let small farmers process their own livestock
The bipartisan Red Meat Inspection Exemption Act would cut red tape and costs at a time consumers are looking for lower food prices, Massie said in a news release.
Starbucks sued over ‘sugar-free’ claims for protein beverages
Starbucks has been sued by consumers who said the coffee chain falsely advertised eight protein beverages as “sugar-free” because they contain lactose, a naturally occurring sugar in milk.
Indian jeweller Titan reports 25% growth in quarterly consumer business sales
India's Titan on Tuesday reported a 25% rise in sales in its consumer business in the second quarter, driven by demand for jewellery, watches and eyewear.
Films and streaming prices - how the Warner Bros deal could affect you
The deal is expected to alter the entertainment and news industries but could it mean higher prices for consumers?
Paramount-Warner Bros merger: Four ways the deal could affect you
The deal is expected to alter the entertainment and news industries but could it mean higher prices for consumers?
Industry Insights: Q&A with Estée Lauder’s SVP of Global Clinical, Consumer Sciences on One-of-a-Kind Complexion Research
“A shade can be technically close to a person’s skin tone and still not look completely natural in every situation.”
Wall Street is booming. Surging yields could shake things up
The boon comes at a time when consumer sentiment is at historic lows and with heightened concerns about the cost of living, from rising energy prices to stubborn food inflation.
Before Saying Yes to the Medical Test, Know the Risks and Benefits
Tests like full-body scans marketed directly to consumers are pitched as a way to detect diseases early and establish a baseline of health markers. But there are financial, physical, and psychological risks to all medical tests — and in some cases, not getting a test could be better for your health.
Mamdani Backs Bill to Let Consumers Sue Over Unfair Business Practices
The proposed New York City legislation would also allow nonprofits, including tenants’ unions, to sue companies directly rather than relying on agency enforcement.
How consumer healthcare brands are adapting FMCG media strategies
Can Opella adapt FMCG marketing without also importing the issues facing that category?
RFK Jr. moves to reveal health care costs
HHS Secretary Robert F. Kennedy Jr. announced a new initiative requiring the health care industry to publish clear pricing data for consumers.
How the Trump administration's revamped healthcare price transparency rules could impact patients
Consumer advocates say the rules are an important step, but stress there's more work today to ensure full transparency.
How the Trump administration's revamped healthcare price transparency rules could impact patients
Consumer advocates say the rules are an important step, but stress there's more work today to ensure full transparency.
A lawsuit accuses Starbucks of mislabeling 8 'sugar-free' protein drinks
Starbucks is facing a consumer lawsuit over claims that the protein drinks labeled as “sugar-free” on its cafe menus may actually contain more sugar than a Reese’s peanut butter cup.
Chip City closes all locations amid economic challenges
Chip City, a New York City-based gourmet cookie chain, has closed all 22 remaining locations nationwide due to tough consumer spending and evolving preferences.
GloRilla expands her business brand with 'glam on demand' GloVerse
Memphis rapper GloRilla is expanding her business portfolio with GloVerse, which aims to help connect consumers with verified beauty professionals.
Livelong Women’s Health Summit Builds Momentum for 2027 Expansion
The Livelong Women's Health Summit brought together consumers, clinicians, researchers, and health experts for conversations spanning menopause, strength and performance, brain health, nutrition, hormones, and the science of aging. The Health & Fitness Association (HFA) served as a sponsor for the event.
Heartland Catfish Unveils New Website
Heartland Catfish Company recently launched a new website in celebration of its 30th anniversary. The site has been refreshed to focus on retail and food service partnerships, give a detailed look at the company’s products and processes and emphasize consumer education about the benefits of U.S. Farm-Raised Catfish as a versatile and healthy protein source. […]
From floating saunas to clinical trials: How heat might help mental health
Many people are turning to sauna because of its benefits for their mental health. While scientists have a decent understanding of how sauna — and other forms of heat exposure — exercises our cardiovascular system, they know relatively little about its impact on depression, anxiety and mood. But more studies are being done to understand this connection and why heat appears to act as a powerful antidepressant. NPR's Will Stone visits a "floating sauna village" in Oslo where a husband-wife team are conducting one of the first trials on the link between sauna and mental health — and talks to one of the leading researchers in the U.S about her efforts to study this. Morning Edition consumer health segment for October 5
Strawberries in February: The Cyclospora outbreak and the cost of convenience
The 2026 outbreak reveals strains on farmworkers, food inspections and disease tracking in a system where consumers demand fresh produce year-round.
The Supply Side: Consumers want fewer digital distractions in stores
A new report from JLL Design reveals that 60% of consumers say a store’s atmosphere influences whether they would recommend it, even if they did not make a purchase. At...
Hassett blames ‘partisan pollsters’ for pessimistic consumer sentiment and says ‘the economy is booming’
Campbell County health and food inspections (9/25/26–10/1/26)
GILLETTE, Wyo. — The Consumer Health Services Division of the Wyoming Department of Agriculture conducts inspections of retail food establishments throughout Wyoming (where there is not a local health department that does inspections) to help ensure safety of Wyoming residents. Campbell County establishments are inspected at least once a year by the WDA. All of […]
How Americans’ Financial Health Is Faring In The “K-Shaped” Economy
Hey all, Jason here. Money20/20 is still two weeks away, but I’ve already started packing (not procrastinating for once!). My calendar is already filling up with various sessions I want to catch, meetings, and of course happy hours, dinners, and other side events. If you’ll be in Vegas and want to catch up, let me know by replying to this email, and we can try to find a time amidst the chaos of the Venetian. A big if not totally unexpected piece of news dropped on Friday: the Independent Community Bankers of America, a trade group that represents smaller U.S. banks, filed a lawsuit against the OCC and Comptroller Jonathan Gould, arguing that the regulator’s move to grant trust bank charters to firms seeking to use them to conduct substantial non-fiduciary activities exceeds the authorities granted to the OCC by Congress. I haven’t had time to fully digest the legal filing or speak to folks in my network about it, but you can expect to see coverage and analysis on it in next week’s newsletter. Subscribe or Support by Upgrading The NerdCon agenda just dropped. It’s stacked. Partner content: Nubank built an AI-first bank. Chime built its own banking core. Figure and Valon are rebuilding the mortgage stack. At NerdCon, you’ll hear from the people behind those bets: what they chose, what they learned, and what they’re still figuring out. The agenda is live, with leaders from Nubank, Chime, OpenAI, Remitly, Mercury, Figure, Valon and more. Follow the mainstage conversations, bring the problem your team is wrestling with to a hands-on workshop, or pull up a chair at a roundtable. Pick your quests. Meet us in San Diego, November 18–20. Fintech Business Weekly readers save 20% with code FBW20. Explore the Agenda Things To Know & Other Good Reads Federal Reserve Board finalizes changes to enhance the transparency and public accountability of its stress test and reduce volatility in its stress test-related capital requirements (Federal Reserve Board of Governors) FDIC Announces Conclusion of Independent Monitorship (FDIC) Modernizing Financial Regulation: Initial Observations from eSLR (Fed Vice Chair for Supervision Michelle Bowman) The Data Version of Godzilla versus Kong: FRED Takes on AI (Fed Governor Christopher Waller) Financing the AI buildout (Brookings) Q3’26: Rules for Banks but Not for Crypto (Fintech Takes Banking) The Inevitability of Local Stablecoins (Lombard Notes) Delusions of AI Governance: The Human-in-the-Loop Comfort Blanket (Fintech Snark Tank) Stripe agrees to acquire Parafin to expand revenue opportunities for platforms and help small businesses grow (Stripe) Listen: Fighting Fraud in the Age of AI, with SEON’s Tamas Kadar (Fintech Business Weekly) How Americans’ Financial Health Is Faring In The “K-Shaped” Economy If there is one overarching theme across the economy and politics in the U.S. at the moment, it’s “affordability.” The term is vague enough to encompass a panoply of factors shaping Americans’ day-to-day lives: rising costs for the hallmarks of being “middle class,” including healthcare, housing, childcare, and education, inflation and rising interest rates, and a job market with the specter of AI hovering over it. At the same time, policy shifts under the Trump administration have resulted in reduced subsidies to those who get health insurance under the Affordable Care Act and new restrictions on qualifying for Medicaid and SNAP, the impacts of which have yet to be fully felt. These factors are contributing to declining consumer confidence and general dissatisfaction with the economy, despite continuing GDP growth and stock market records. This divergence is encapsulated in the idea of the “K-shaped” economy, in which a small proportion of Americans have seen their wealth balloon, while the majority of American households struggle to preserve the lifestyle they have. Perhaps the greatest determinant of which branch of the “K” a household is on is whether their wealth and income are primarily derived from employment vs. from assets. Nearly two decades of low interest rates and, more recently, elevated rates of inflation have benefited asset owners, while those whose income is primarily or solely derived from labor have largely seen real purchasing power stagnate or decline. This is reflected in recent Bureau of Labor Statistics data showing that labor share of U.S. GDP — the fraction of economic output that accrues to workers as compensation in exchange for their labor — dropped to just 52.8% in Q2 2026, the lowest since the BLS began keeping records. In 1947, approximately 2/3rds of economic output accrued to workers; even as recently as 2001, labor’s share of GDP was 64.1%. Against this backdrop, we’ve seen the rise of more credit and credit-like products: cash advance apps, “no-fee” overdraft, earned wage access, and buy now pay later, which are often used as small-dollar short-term borrowing mechanisms to meet immediate consumption needs or pay other bills (eg utilities, cell phone, other debt payments). With the markers of a middle class existence and, increasingly, basic financial stability seemingly out of reach for many, it should be no surprise there’s been an increase in “financial nihilism,” something industry peers like Alex Johnson and Frank Rotman have discussed and analyzed the roots of. The explosion of gambling and gambling-adjacent products and services — often marketed under the guise of being an “investment” — is inextricably intertwined with the rise of financial nihilism. Crypto, sports betting, and, more recently, prediction markets offer an escape or even hope of sorts, like a contemporary, digital version of a scratch-off lottery ticket, while leaving the overwhelming number of people who use such products worse off. Share of Households That Are Financially “Vulnerable” Ticks Up The Financial Health Network’s 2026 Financial Health Pulse® report adds context on how American households are faring. (I linked to this report in last week’s newsletter, but wanted to take time to further unpack the data in the report this week.) The Financial Health Network publishes the report annually, providing insight into how Americans’ financial circumstances are changing over time. The 2026 report is derived from a survey fielded in April and May 2026. The report leverages survey responses to assess indicators of financial health across spending, saving, borrowing, and planning/protecting and to determine a zero to 100 “FinHealth” score. Those with scores between 0 and 39 are considered “Financially Vulnerable,” consumers with scores ranging between 40 and 79 are defined as “Financially Coping,” and those with scores of 80 to 100 are “Financially Healthy.” The report found that moderate improvements in 2025 were reversed, with the share of respondents considered financially “vulnerable” rebounding to 17%. The longitudinal data reflect the impact of pandemic-era programs, like expanded unemployment, cash stimulus payments, and pauses of federal student loan payments. The positive impacts of those programs, as reflected in the Financial Health Pulse reports, had largely disappeared by 2023. While pandemic-era inflation — to be fair, in part caused by the various support and stimulus measures — had come down from as high as 9% in 2022, it has rebounded since the start of Trump’s second term, with tariffs and energy market disruptions owing to the war in Iran pushing prices back up. Specific indicators in the survey that deteriorated from 2025 to 2026 include the share of respondents spending less than their income over the past 12 months, the share paying all bills on time over the past 12 months, the share that have a manageable amount or no debt, the share that are “moderately” or “very” confident their insurance is adequate to cover them in an emergency, and the share that “somewhat” or “strongly” agree that their household plans ahead financially. Unsurprisingly, lower- and moderate-income households are more likely to struggle to pay their bills on time and have any funds leftover to save. The share of low-income households whose income exceeded their spending dropped from 35% in 2025 to 31% in 2026, while the share of upper-income households whose income exceeded expenses remained unchanged at 63%. Households with student loans or revolving credit card debt reported having “a bit more” or “far more” debt than was manageable at rates far higher than those not carrying these types of debts. The share of those with student loan debt indicating their debt load was too high to manage increased from 50% in 2025 to 55% in 2026, while the share of those with revolving credit card debt saying the same ticked up from 51% in 2025 to 54% in 2026. Households that had student loans were markedly more likely to be financially “coping” or “vulnerable” vs. those without student loans. In 2026, 27% of households with student loans were considered financially vulnerable, a jump of 6% points vs. 2025. Households without student loans saw just a 1% point increase (not statistically significant) in those considered financially vulnerable. Households’ perception of the affordability of categories of goods and services paints a stark picture, with less than one-fourth considering higher education affordable, about a third deeming childcare affordable, and less than half viewing healthcare as affordable. Fintech Business Weekly is made possible by the generous support of paying subscribers — bringing you independent analysis of banking, fintech, and crypto without fear or favor. You can support my work by becoming a paying subscriber if you aren’t already. Paying subscribers enjoy: access to the entire archive of nearly six years of newsletters extended versions of the weekly newsletter, with additional content and analysis and (for founding member tier) quarterly personal 1:1 fintech Q&A / strategy calls with me, tapping into my unparalleled knowledge of the intersection of banking and fintech and experience working in the sector, including helping to launch Goldman Sachs’ retail bank Marcus Support Fintech Business Weekly You can also support Fintech Business Weekly by sponsoring a newsletter or podcast, putting you in front of 93,000+ of the most influential decision makers in banking, fintech, and crypto. Learn more about sponsor opportunities or request a media kit by dropping me an email. Democratic Senate Report Highlights How Iran Uses Tether to Evade U.S. Sanctions Iran uses stablecoins, specifically Tether, to evade sanctions, fund regional proxies, and to purchase military drones, a report released last week by the Senate Permanent Subcommittee on Investigations says. The report was authored by committee ranking member Senator Richard Blumenthal (D-CT) and the minority staff. Crypto and stablecoin proponents will often push back on criticism that criminals make use of these assets by arguing that, on an absolute dollar basis, far more illicit funds flow through traditional banking systems and payment rails than via crypto and stablecoins. And while that is likely true, it elides the reality presented in news story after news story: whether state actors — Russia, Iran, North Korea — or criminal groups, those looking to engage in illicit transactions increasingly favor stablecoins and, specifically, Tether (USDT). The report from the Senate Permanent Subcommittee on Investigations released last week adds context to how Iran uses Tether has a lynchpin in its shadow banking system. The report analyzed 846 wallets that have been sanctioned or targeted for seizure, finding that 84% of them transacted exclusively or primarily in Tether. The ability to create near limitless, anonymous wallets and to move funds effectively instantaneously and irreversibly have made crypto a favored financial mechanism for bad actors. Stablecoins solved key drawbacks of bitcoin, namely, the original cryptocurrency’s highly volatile value in dollars. And while Tether (the company) has the technical ability to “freeze” or destroy funds, the company is often limited and reactive in its approach to doing so, the Senate report argues. Tether, which is nominally based in crypto-friendly El Salvador, “has stated that its compliance with OFAC sanctions is ‘voluntary’ and that it follows ‘OFAC guidelines,’” the Senate report says. Owing to these favorable attributes, Tether “became a primary cryptocurrency for Iran, Hamas, Hizballah, and the Houthis beginning in 2023 and has expanded in scale since,” according to the report. Tether’s role in Iran’s shadow banking system, the report says, is enhanced by crypto exchanges like Bybit, Kyrrex, OKX, Gate, and Binance, and through “over the counter” exchanges and hawala networks. The consequences of these financial flows aren’t hypothetical. The Senate report links Tether as a funds transfer mechanism to Iranian proxies in the region, including Hizballah, the Houthis, and Hamas. Tether has also been used to make payments to secure components necessary to manufacture drones, the report says. The report concludes by arguing that “[s]tablecoin issuers with a significant nexus to the United States, particularly those that offer dollar-denominated stablecoins, should be subject to American sanctions law rather than being allowed to hide behind foreign jurisdictions.” Stablecoin issuers like Tether must be held accountable for repeated failures to prevent illicit finance and sanctions violations by law enforcement, the Department of Justice, the Securities and Exchange Commission, and OFAC, the report argues. [Paying Subscriber Exclusive] OUSD Goes Live, Make Your Own Neobank, U.S. Sanctions Russia’s A7 Network As “Transnational Criminal Organization” OpenUSD, the stablecoin issued by the Open Standard consortium that includes Stripe, Visa, Mastercard, core providers, crypto firms, and numerous banks, went live last week. Social commerce platform Whop raised eyebrows in fintech by offering creators on its platform the ability to launch their own neobanks, which the company describes as “great businesses that are easy to run,” in just 15 minutes. And OFAC and FinCEN target Russia’s “shadow banking” A7 Network — more on these stories after the paywall.
Jodi's Journal: A sign of the consumer spending times?
Gas prices are climbing as the crucial fourth quarter begins for businesses. In this week's column, Jodi takes a look at how the consumer could be responding.
Irish Sea Moss Is Making Waves. The Science is Actually Pretty Murky.
Irish Sea moss supplements are all the rage with a billion-dollar industry that expects consumer demand to continue rising. While the superfood is packed with different nutrients, there is a high risk of ingesting heavy metals.
Your health insurance premiums may take a big jump in 2027
Many consumers are likely on the hook for an increase of about 10% or more in 2027, experts said.
Analysis-Vance's fraud crackdown may raise costs for US health insurers, enrollees
NEW YORK, Oct 2 (Reuters) - A crackdown on Obamacare health insurance could raise prices for US consumers and insurers by removing healthy, low-cost enrollees, adding pressure to a shrinking marketplace.
Vance's fraud crackdown may raise costs for US health insurers, enrollees
A crackdown on Obamacare health insurance could raise prices for US consumers and insurers by removing healthy, low-cost enrollees, adding pressure to a shrinking marketplace.
From Unicorn Frappuccinos to VIP meet-and-greets: How 3 brands are turning buzz into business
As companies fight harder for consumers' attention, marketing is becoming an increasingly important tool for driving growth.
Is Trump too focused on political content creators as midterms approach?
With Republicans deeply worried about the looming midterms, is President Trump focusing too much on politically obsessed content creators and consumers instead of ordinary voters? Join The Hill’s s…
YouTube sports strategy targets more live rights -- but not necessarily events
YouTube is targeting more live sports rights. But it's more likely to buy games in bulk if there's a clear consumer proposition underlying the rights.
Online holiday sales expected to top $275 billion in 2026
With the Christmas holidays approaching and the shopping season underway, Adobe Analytics predicts more consumers will shop online, especially during the aggressive promotional period between Thanksgiving and Cyber Monday. Adobe...
Senate Majority Leader Erin Murphy Responds to Health Insurance Rate Increases
SAINT PAUL, Minn. – On Thursday, the Minnesota Department of Commerce announced the health insurance rate increases facing Minnesotans next year. For 203,000 consumers who purchase insurance on the individual market, rates will increase between 9.9 and 21.1 percent; for 184,000 Minnesotans who are insured on small group market plans, rates will increase between 10.6
Expert reveals US business owners set to bear brunt of Canadian tariff fallout as trade war uncertainty looms
Karan Ramchandani says Trump's import bans on Canadian dairy, alcohol and automobiles could trigger inflation as production costs hit consumers.
How are higher interest rates and rising prices affecting you?
Last month, the Federal Reserve raised interest rates for the first time in more than three years, as it tries to bring inflation under control. But higher rates make borrowing more expensive for consumers and businesses — one reason mortgage rates have climbed to a three-year high in recent weeks.
Minnesotans face another year of steep health insurance hikes
All approved insurers will raise rates by at least 10 percent in Minnesota’s individual and small-group markets, as higher healthcare costs and expiring ACA tax credits put pressure on consumers.
Refunds From the Trump Administration’s Unlawful Tariffs Are a Windfall for Corporate America, Not for Small Businesses or Consumers
New state-by-state CAP analysis finds that the Trump administration’s tariffs cost small-business importers in all 50 states and Washington, D.C., an average of $426,000 more over 18 months—damage that refunds cannot fully undo.
Apple's smart hub shows its new view of the tech consumer
A home hub showcasing Siri AI gives the company another reason to envelop new and familiar categories of connected products.
September Monthly Review: Health MCP Guy?
For all the time I spend talking about APIs and data exchange, this newsletter has had embarrassingly little interoperability of its own. It’s old-school SaaS, baby - UI or bust. Not all of that is my fault! Substack, for all its popularity, is (as mentioned before) really frustrating as my system of record. The primary user it optimizes towards is the reader, whose attention feeds the app, the Notes feed, and the recommendation network that Substack is actually selling. Health API Guy is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe They’re falling into the same trap that Medium once sprinted into, albeit at a much more glacial speed. Younger generations may not remember (or never knew) it, but Medium once lured publications like The Ringer and Signal v. Noise onto its platform, only to lose them as it rebuilt itself around a paywall and an algorithmic feed. Substack’s original pitch circa 2020 was the antidote (you own your list), but every new feed feature chips away at it. I get it: writers are generic supply in the eyes of the Substack product team. Generic supply follows demand, so the consistent pressure on the PMs is to generate demand, which leads to every product cycle going toward discovery (Notes, recommendations, the app, live video). The end result lackluster author tools (laggy and broken analytics are truly crippling) all despite the premium price point. The archive is where it crosses from authorial gripes to actual reader impact, though. Across Substack and LinkedIn, I’ve published 1,218 posts and nearly 900,000 words since 2018. Substack’s native search can see only the 464 posts that live on Substack, and even there it’s woefully inadequate at surfacing relevant content (even for the guy who wrote it)! Readers have the same problem, writ large. Ask the Archive Fixing search (for both my readers and my own use) turned out to be extremely non-trivial, unfortunately: There’s no public API for readers to access content RSS exists for new content notification, but it only carries the 20 most recent posts and cuts paid ones off at the preview The only Substack MCP is an admin tool for analytics The export exists for authors, but it’s painfully awkward and slow. So I built something to work around that: the Health API Guy MCP. It’s a private MCP server holding the full text of everything I’ve written across Substack and LinkedIn. Add it to Claude or ChatGPT as a connector and you can ask things like: It pairs keyword search (for acronyms and case names, of which we have many) with semantic search. Every post is also labeled by topic, form, and court case, so you can pull a lawsuit’s (or multiple cases’) entire docket across Substack and LinkedIn in one query: Hail, Healthapiguyhydra This is also a bit of me eating my own cooking. I’ve spent the year arguing that headless healthcare is arriving and that developers want primitives over abstractions. Last week in Hail, Benihydra, I watched Salesforce plug its platform into Claude and bet that the records underneath outlive whatever interface sits on top: Salesforce must believe that the Hydra’s immortal head is the records, permissions, and business logic (in that they will survive whatever happens to the interface). It felt a bit hypocritical to keep my own archive behind a Substack search bar. The archive is the body. Substack is one head, and now whatever tool you might use is another. Will the EHRs follow my lead? Probably not imminently, but one can hope! Why Founding Members Only The MCP is available to Founding Member subscribers. A few reasons: It costs money and time to run. Hosting, the database, Clerk usage and AI compute for search and labeling are significant operational costs (that increase with usage). Substack gives me no way to automate access. There’s no API to check whether someone is a paid subscriber, so every user is manual operations for now. It’s a beta. We’ll need to improve things and parts will break. I’d rather they break for a small group of dedicated readers who will tell me about it. The Founding tier deserved a real benefit. Until now it was mostly a generous tip. Now it comes with something. If you’re already a Founding Member, reply to this email with the address you’d like provisioned. If you’re not and want in, upgrade here. Larger teams (such as companies) can get access too: group subscriptions at the Founding tier come with the group discount. The admin for the subscription can reply with the list of addresses to provision. Get 20% off a group subscription Pricing Founding membership is now a flat $200 a year, replacing the old suggested $150 that readers could adjust. Existing Founding Members will have access grandfathered in at their previous rate. Month in Review Articles Published Make Networks Dumb Again (Sep 11): AI is making old analog networks cheaper to use and flooding them with machine traffic in the process. A plea for agent-native rails with the intelligence at the endpoints, and for Washington to drag them to ubiquity. Interoperability, Unbuttoned (Sep 29): Interoperability is a series of workflows in a trenchcoat, and this post finally takes the trenchcoat off. A color-coded map shows which provider workflows went digital, which are fragmented, and which still run on fax. Video Content Antitrust’s System of Record Problem (Sep 3): The FTC’s investigation into Epic prompted a ninety-minute webinar, now posted with chapters and a smoothed transcript. We get into why market definition, missing B2B share data, and the SSNIP test leave antitrust poorly suited to systems of record, plus why information blocking may be doing more than any pending lawsuit. The Information Exchange: Cerner Milking Edition (Sep 18): This was so fucking fun. Ryan Tucker, Ryan Brickner, Brad Thorson, and I try an Around the Horn format, complete with points, penalties, and a mute button. We debate whether Oracle Health is dead, who would actually buy Cerner (IBM enters the chat), p(Doom), and why the front desk still hands you a clipboard. Regulatory Ask Not What Your Network Can Do (Sep 23): CDC’s RFI on public health data intermediaries lists use cases already served, unevenly, by eCR, lab reporting, IZ Gateway, and syndromic surveillance. The real opportunity sits in one question about AI: a network that can handle the next emergency without another interface project. Court cases Particle v. Epic: The Naughty Schoolteacher (Sep 4): After a summer-long vigil, the answer on Epic’s early summary judgment bid is two paragraphs and a remedial assignment. Particle advances to the next grade, and market definition gets another year of discovery. The Epic Discovery Files (Sep 8): Texas’s motions to compel arrive with a 251-page appendix of requests, objections, and meet-and-confer letters with Cravath. Inside: Epic using generative AI for document review, denied interoperability requests in scope, and Noerr-Pennington raised against lobbying discovery. Epic v. Health Gorilla: “Working as Designed” (Sep 9): Epic wants nothing to do with the data breach MDL, and explaining why puts fresh discovery on the public docket. The spiciest allegation: Health Gorilla told GuardDog to scrub its law firm business from its website instead of cutting off access. Veeva v. Epic: Legal Bypass Surgery (Sep 15): Veeva asks the Wisconsin Supreme Court to skip the Court of Appeals, while law professors and three policy groups line up as amici. Meanwhile, Epic’s lawyers apologize for another round of citation errors, including a quote that never existed. Texas v. Epic: Behind the Black Bars (Sep 17): The court portal served up Epic’s unredacted filings, revealing a $5 million document review budget and the AI workflow behind it. Also inside: the 200-plus company names Texas wants searched, and one very expensive Zoom invitation. OpenEvidence v. Doximity: Consequences Will Follow (Sep 25): OpenEvidence tells the court it will not comply with a discovery order, and its own lawyers at Quinn Emanuel say they won’t defend the choice. Add years of Slack reported unrecoverable, and Rule 37 sanctions come into view. Health Tech Keeps Choosing Violence (Sep 28): Doximity moves to end OpenEvidence’s case, Epic asks Texas to show its work, and a sleepy Audacious Inquiry patent fight sprouts antitrust and information blocking counterclaims. The main event is a long-sealed Cognizant v. Infosys ruling that hints where system of record antitrust claims can survive. EHRs One Verb for Oracle Health (Sep 14): Oracle’s earnings call quantifies every data center to the decimal point, while Oracle Health gets a single verb: “accelerate.” Panning the few healthcare mentions turns up an agentic care management system, a research-to-care ledger play, and the question of whether healthcare gets Larry’s patience. Epic’s Forretress Under Siege (Sep 30): Judy Faulkner tells a panel Epic paused hundreds of projects to harden its software and calls it a “shame,” while a spokesperson insists the roadmap hasn’t changed. Project Glasswing, a Pokémon-branded QAN sprint, and a trove of Jodel grievances reconcile the two Epics and preview the Jevons paradox coming for all software. Industry Analysis Scanning for a Network (Sep 1): Scan.com raises $220M to build the imaging network labs never got, speedrunning Zocdoc’s consumer-to-B2B pivot. Its wedge to network density may be the most American one available: personal injury litigation. The Front Desk Wants the Damn Whole Building (Sep 16): Hello Patient buys Converse Health, pushing its AI front desk into referrals, chart work, and prior auth. The copilot categories keep blurring, and your distribution partner is still your final boss. Cross-industry Comparisons A Different Patchwork Quilt (Sep 10): Healthcare loves to envy open banking, but the US version has no mandate, a toll booth at Chase, and data quality problems of its own. The grass isn’t greener; it’s another American patchwork quilt, and perhaps a worse one. Hail, Benihydra (Sep 21): Salesforce brings its platform into Claude, Slack, and its own agent, inviting the interfaces that might replace it. Cut off one head and more grow back, so long as the records underneath stay put. Living on A Trade Secret Prayer (Sep 22): Six credit unions are suing Fiserv, the Epic of core banking, by claiming their own member records as trade secrets. Banking has no Cures Act, so its lawyers reach for legal alchemy that healthcare has already tried. Other News None this month External Media Nabla Accelerate NYC: I kicked off fall conference season at Nabla’s Accelerate event in New York, where Delphine Groll opened by asking the room to picture the company it wants to become and the one it doesn’t. I liked her framework of bureaucracy, fear, and ego as the blockers. I also love vendor conferences/events in general - different vibe than industry biggies. Healthcare 101 with Nikhil Krishnan: I briefly guest lectured Out-Of-Pocket’s Healthcare 101 class. Appreciated Nikhil’s takeaways cover whether AI doctors can query HIEs, why healthcare’s data-liberation rules beat most industries’, and the hi-res graphic is in the comments. HCN: Epic Probed by the FTC: I joined the HCN guys to talk through the FTC’s investigation into Epic. Cedric’s new hairdo was an unexpected plot twist. The episode also covers MFN drug pricing, healthcare M&A and Eli Lilly’s acquisition streak. Fall Conferences: At eHealth Exchange’s Annual Meeting in Austin on Oct 27, I’ll moderate a panel on the tensions between AI, HIEs, and timely patient access with Jean Ross (Primary Record), Therasa Bell (Kno2), Byron Crowe (Doctronic), and Michael Marchant (Freenome). Here’s the rest of my schedule if you want to meet up: CommonWell (Redwood Shores, CA): Oct 13-14 Will be participating in a fun Jeopardy event Open@Epic (Madison, WI): Oct 20-23 Will be enjoying Verona, Willy Street, and other local adventures eHealth Exchange and Sequoia Project (Austin, TX): Oct 27-29 Yeehaw HLTH (Vegas): Nov 15-18 Groundhog Day, Venetian Edition RSNA (Chicago): Nov 30-Dec 2 See me at “Governing AI in Breast Imaging: What Health Systems Are Actually Doing” Digital Health Counsel 2026 AI Summit (Seattle): December 2-3 Will likely be speaking to a bunch of lawyers about information blocking Posts I Liked ChatGPT’s Epic integration: game changer or nothing burger?: Joshua Liu, MD offers five thoughts on OpenAI’s Epic launch, starting from the point that it rides the same open APIs available to anyone. He argues read-only access leaves ordering to Art and the ambient startups, and asks why HCA is piloting it alongside Commure. He’s sorta a must-follow at this point - consistently excellent, thought-provoking takes. Epic, Lilly, and the Discovery pass: Seth Chaney reads Epic’s first major Discovery deal (with Eli Lilly), as well as its revised developer terms on commercial displays, as the pipe finally opening between EHRs and pharma. Life sciences and health continue to collide. Scott Rossignol on EHR payer platforms and ePA fees: Scott argues the top ambulatory EHR vendors are turning the prior auth mandate into a per-member-per-year toll on payers, for an API whose operating cost has nothing to do with covered lives. His fix is two lines of regulatory text: put the CRD/DTR/PAS certification criteria in the Base EHR definition, and bring payer-facing ePA connectivity under § 170.404’s cost-based fee rules. It’s a good solution. Health API Guy is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
Congress Set to Leave Washington for the Midterms With No A.I. Progress
Senate Democrats were expected on Wednesday to block a measure that would encourage, but not require, states to protect consumers from power rate hikes as a result of data center growth.
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Newsom vetoes insurance-claim bills: Is it ‘petty’ politics?
This story was originally published by CalMatters. Sign up for their newsletters. Gov. Gavin Newsom vetoed two bills that would have helped improve the insurance-claims process for consumers but signed one that also addresses claims-related issues, leaving Los Angeles County fire survivors and others wondering whether the vetoes were retaliatory. One bill, Senate Bill 877, […]
Newsom vetoes insurance-claim bills: Is it ‘petty’ politics?
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Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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