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Delaware details still slim as Penn Medicine plans new surgery centers
Penn Medicine unveiled a new plan to bring 18 ambulatory surgical centers to the region. Details remain slim on what's coming to Delaware.
Israelis scarred by Oct. 7 attack weigh Netanyahu’s political future
Some survivors of the deadliest day in Israel’s history see this month’s election as a long-delayed reckoning for the officials in charge when the country dropped its guard.
Kofane Delays Leverkusen Deal As Premier League Interest Grows
Negotiations for the striker’s bumper extension have stalled over signing bonus demands, leaving the door ajar for circling English giants to hijack the Bundesliga star’s long-term future.
Jessica Chastain doubles down on criticism of Apple delaying “The Savant” after Charlie Kirk murder: ‘Had to go on record’
The actress previously said she and the streamer were “not aligned” on postponing the extremist series’ debut.
Delaware or Texas? Business Court Dismisses Coinbase Shareholder Suit
The decision turned on a key difference between the two states. Because the company reincorporated in Texas, shareholders must follow Texas’ stricter requirement to demand board action and wait 90 days before filing a derivative suit, even when the alleged misconduct occurred while Coinbase was incorporated in Delaware.
South Texas races could determine control of Congress
The nonpartisan Cook Political Report recently moved Texas’ Congressional District 15 from “Lean Republican” to “Toss-up.”
New agriculture scouting business takes off
Delmarva farmer Nichole Krambeck uses drones and soil DNA testing at Insight Ag Scouting to cut costs and boost crop yields.
Demand Change: Homer G. Phillips Sale Delay Endangers Vulnerable Seniors
Homer G. Phillips residents endure neglect, safety risks, and maintenance failures. Uncover the story behind Alderwoman Tyus's 'bullet in the head,' comment | 104.1 FM KMOX
A ‘telenovela of US politics on a two-year delay’: Expert reacts to Brazil election results
Patient Dies By Suicide After 'Insurance Issue' Delayed Medicine For Lung Disease Flare-Ups
By Lauren Sausser and KFF Health News HealthDay ReportersTUESDAY, Oct. 6, 2026 (HealthDay News) — Kenney Blewett was diagnosed with lung disease more than a decade ago but started experiencing flare-ups this year that made him feel like he couldn’t breathe. Blewett, of Kyle, Texas, described those ...
DHS buys 2 more detention centers in California for $950 million
WASHINGTON — The Department of Homeland Security has purchased two immigrant detention facilities in Adelanto for $950 million, according to the private prison corporation that sold them. The sale by
Darko Rajakovic Reveals What’s Behind Kawhi Leonard’s Delayed Raptors Return
Toronto prioritizes long-term health over preseason minutes as the superstar ramps up his reconditioning process.
Why I Don’t Think Ride Or Die Should Have Been Cancelled (And What Company Should Save It...)
(Welcome to my weekly streaming ratings report, the single best guide to what’s popular in streaming TV and what isn’t. I’m the Entertainment Strategy Guy, a former streaming executive who now analyzes business strategy in the entertainment industry. If you were forwarded this email, please subscribe to get these insights each week.) So…I recently came across a Reddit thread, talking about films on streaming, wondering why there are no reliable sources out there for streaming ratings data. Sigh. Honestly, as annoyed as I am that so many still don’t realize that we have streaming ratings, I somewhat get it. Until now, there was such a long delay between when a show or film came to streaming and when we got its viewership data; I understand why people were confused. (But, as you know, this just changed.) Also, even back in the day, how many people knew how well films did on television? Luckily, as a reader, you’re in the know. Okay, on to this week’s issue. I want to take a look at Prime Video cancelling Ride or Die and whether I agree with that decision. Overall, we didn’t have any breakout hits (no TV shows landed over 20 million hours according to Nielsen) but we have a lot of steady performers on the streaming charts. Plus, we’ll look at where $50 million in missing box office dollars went. (Spoiler: straight-to-streaming.) All that, plus new episodes of The Secret Lives of Mormon Wives, Supergirl heads to streaming, a new YA show does well on Netflix, the viewership for the Daily Wire’s $50 million fantasy show, what TV show hit-maker can’t make streaming hits, CD sales, all the flops, bombs and misses, and a whole lot more. Let’s dive right in! (Reminder: The streaming ratings report focuses on the U.S. market and compiles data from Nielsen’s weekly top ten viewership ranks, Luminate’s Top Ten Data, JustWatch and Reelgood interest data, Samba TV household viewership, company datecdotes, Netflix hours viewed data, Google Trends, and IMDb to determine the most popular content. While most data points are current, Nielsen’s data covers the weeks of September 7th to September 13th, 2026. You can find a link to my terminology here.) Subscribe Television - Ride or Die Is a Hit…But It Got Cancelled? What The Data “Says” I hate the phrase “here’s what the data says”, even though sometimes I find myself using it. If data just told us everything, we data folks would be out of a job! Data is often messy, complicated and nuanced. When it comes to strategy, many of the best decisions can’t actually use “data”, since it’s vastly too complicated to model. Anyways, I’ve been singing the praises of Prime Video’s Ride Or Die this summer, a show that did very well for them. And yet…it got cancelled. Now, usually when a show gets cancelled, a bunch of websites say “a hit show got cancelled”... Here’s the thing, though: in this case, they’re right! The data “says” that this show was a hit. Specifically, out of 522 first seasons to make a week on the Nielsen charts since 2020, it’s the 75th biggest. On Amazon, Ride or Die is eighth out of 41 first seasons: That’s top 15th percentile all time, almost exactly, which is my definition of a “hit”! I mean, outside of Reacher, Amazon needed a hit this summer! (Admittedly, Off Campus did well for Amazon in the spring, but Ride or Die performed even better.) So what happened? Why did Amazon cancel one of their rare 2026 bright spots? Well, Deadline reported a reason—which I’ll get to—but I’d break it down into three relevant questions: What is a given streamer’s reasoning? Is that reasoning sound? Could the stated reason not be the real reason? According to Deadline, Amazon felt the show “over-indexed” in middle-aged women. (This was based on leaks from within Amazon.) The logic is this: Amazon already reaches this demographic because of unlimited two-day shipping bundled with Prime, so they don’t really need more shows like this. Now, it’s my job to ask if that’s a good reason, and I’ll be honest, in this case, I don’t think it is. Sure, this show may “over-index” in middle-aged women—I’ll just assume that’s the case here—but I think folks often oversell how important over-indexing actually is. When a show is a “hit”, it isn’t a bit bigger than its rivals; it’s usually multiples bigger. For example, Elle only made the charts for two weeks at 8.3 million hours each. So Ride or Die was 80% bigger in its first two weeks, and likely had a much stronger hold, with its terrific 13 million hours in week three. Ride or Die was nearly three times bigger than Sterling Point through three weeks too. And that means that _Elle, Sterling Point a_nd other Amazon YA shows need to not just over-index a little with younger women (assuming that’s who Amazon prefers over middle-aged women), but massively over-index. Otherwise, more people in that demo (and a bunch more besides) likely watched Ride or Die. (I’ll try to explore this concept more in a future article.) And don’t get me started on how Ride or Die did compared to a certain (very, very popular, possibly the world’s most popular) YouTuber’s reality show…which didn’t make the charts after its first week and likely cost much, much more than Ride or Die. All to say, Amazon-MGM Studios/Prime Video can tell reporters that this show didn’t reach the right audience, but that excuse feels weak to me. So this leads to the third question: could other reasons have come into play? Yes! Renewal or cancellation decisions rarely (I’m tempted to say “never”) boil down to one variable. At its simplest, it’s two things: budget versus viewership. But often factors like critical acclaim, ownership and, yes, personal opinion come into play. In this case, Amazon has a new executive running things, and this show isn’t owned by Amazon-MGM Studios (unlike Elle). And yes, it may not have indexed with the right target viewers, too. Likely all of those factors came into play.1 My guess is ownership ended up mattering most. Amazon doesn’t own Ride or Die. It’s actually produced by another major studio. Fortunately/allegedly, this show is being shopped around. I can think of one brand new CEO who should consider it for one of his two major streamers…especially if he wants to rebuild goodwill in Hollywood. His name is on this list of exec producers of Ride or Die… If David Ellison needs some goodwill—and he does—rescue this female-led show tomorrow and grab some good headlines for a day. The data justifies it. Quick Notes on TV We’re just getting started with this issue, but the rest is for paid subscribers of the Entertainment Strategy Guy, so if you’d like to find out… How The Secret Lives of Mormon Wives latest season did on Hulu, post-controversy... Whether Supergirl soared on HBO Max... Why the box office is losing money due to the streamers... The viewership for the Daily Wire’s $50 million fantasy show... Updates on The Gentlemen, Lanterns, Outer Banks, King of the Hill and more... What former hit-maker has three streaming flops in a row... Whether The Mandalorian and Grogu popped in week two... All the flops, bombs and misses... And a whole lot more... ...please subscribe! We can only keep doing this great work with your support. If you want an idea of just how much content you’d get in a full issue, check out this older issue. Coming Soon! Oh man, we’re almost caught up! We just have two more issues, then the streaming Ratings Report will be coming out just two weeks after a TV show premieres! Next issue, I’ll be looking at the first two weeks of the NFL Thursday night games on streaming, a huge new spinoff, Reacher’s Neagly on Prime Video, and the latest edition of Monster: The Lizzie Borden Story on Netflix, the return of Slow Horses on Apple and MobLand (quietly one of their biggest shows) on Paramount+, and Dancing with the Stars on both ABC and Disney+. Plus I’ll take a look at animation for adults in 2026. The week after, a ton of movies are coming to streaming: Toy Story 5 on Disney+, Backrooms on HBO Max, Jackass: Best and Last on Paramount+ and The Breadwinner on Netflix, plus a Unabomber film on Netflix and a romcom on Prime Video. Woody Harrelson and Matthew McConaughey have a show on Apple, along with a game show inspired by Willy Wonka that everyone seems to hate. Long term, some crazy (but hopefully crazy like a fox) IP news. FX ordered a new Sons of Anarchy show from Charlie Hunnam, but it’s not about the biker gang. No, it features the show’s cast playing themselves in a new “meta-thriller”. Huh. And a lot of the cast is coming back. Next, Ryan Gosling is producing a Flintstones movie about a “grown-up Bamm-Bamm Rubble”. Also, huh. This one is in “early development” so we’ll see what happens. Both projects are based on IP, but also seem to have crazy takes on the IP, which I like.
‘The Batman Part II’ halts production as director Matt Reeves steps away for personal reasons
After years of delays, ‘The Batman Part II’ has ‘temporarily paused’ production as director Matt Reeves ‘focuses on a family matter.’
Texas AG investigating second health insurer over delayed, denied care
The Texas attorney general's office has launched an investigation into UnitedHealth Group, citing reports of nursing home bribes and revoked coverage.
DHS buys three detention centers in California for $950 million
The GEO Group, a Florida-based private prison corporation, announced Monday that it had sold the detention facilities, including the Adelanto ICE Processing Center, totaling 2,644 Beds.
Eyes on Growth: TD Survey Finds Small Businesses Confident About Growth Despite Economic Headwinds and Delayed Investments
TD Bank U.S. survey finds 85% of small business owners expect stronger revenue through year-end, despite economic uncertainty and preparedness gaps.
DV students win at FBLA National Leadership Conference
Students from Delaware Valley School District won top prizes at Future Business Leaders of America Inc.’s National Leadership Conference. The event, held in San Antonio from June 29 to July 2, attracted more than 16,000 middle school and h…
'All INdiana Politics': Albright and Forrestal battle for closely divided seat in Senate District 31
INDIANAPOLIS — One of Indiana’s most competitive Senate districts is the site of a high-stakes showdown as a family physician and a former sheriff vie for the seat vacated by Republican Sen. Kyle Walker. Senate District 31 covers Delaware and Fall Creek townships in Hamilton County, including most of Fishers, along with Lawrence and parts […]
From nearsightedness to self-harm: Meta-review looks at how digital media impacts young people’s health
The authors of an expansive new series in ‘The Lancet’ argue that gaps in our understanding about digital harms shouldn’t delay urgent policy action.
Eagles fans react to new parking and tailgating rules
The Philadelphia Eagles announced new parking and tailgating rules, and some fans are not on board.
All INdiana Politics: Albright and Forrestal battle for closely divided seat in Senate District 31
INDIANAPOLIS — One of Indiana’s most competitive Senate districts is the site of a high-stakes showdown as a family physician and a former sheriff vie for the seat vacated by Republican Sen. Kyle Walker. Senate District 31 covers Delaware and Fall Creek townships in Hamilton County, including most of Fishers, along with Lawrence and parts […]
Why hasn’t the Trump administration decided the fate of TPS for Salvadorans?
The Trump administration still hasn't reached a decision, plunging the Salvadoran community into uncertainty and raising questions about what has prompted the delay.
$28B hemp THC industry fighting to save itself from looming federal ban
A government-funding bill last month delayed the effective date of a hemp THC ban to Dec. 11 to give Congress time to consider regulations.
Wolff: “It’s difficult to cope” for Russell seeing Antonelli pace
The Bahrain GP in Malaysia represents a crucial moment in the Championship for Mercedes, who introduce a series of long-awaited upgrades to the W17. These updates are the first major aerodynamic changes for Mercedes in several months, who are finally responding to the developments from other teams - most notably McLaren. Despite the relative delay …
New Alfred I. duPont Charitable Fund to support children's health
A new fund has been created in the name of Alfred I. duPont to support Delaware children's health with nearly $1 billion over the next 11 years.
Last redistricting hearing comes to Jackson, MS. What happens next?
The statewide tour of redistricting hearings ended in Jackson with boos, accusations of racism and calls to delay redistricting until the 2030 census.
A Delaware County estate with a par-three golf hole and an entertaining space is on the market for $4M
The house also has a sports court and pool.
Ken Welch's thorny Thursday showed exactly why he's about to join the club of one-timers
Projects delayed for retribution. Hiding from the press. Misuse of city resources. It wasn't just a bad day — it was a terrible one.
Former NFL great DeSean Jackson comes to UAlbany on Saturday
With no college coaching experience, Jackson took over a Delaware State program that went 1-11 in 2024. Jackson is 11-6 with the Hornets of the Mid-Eastern Athletic Conference,
Colorectal Cancer Is Rising Among Kids and Teens—and It's Not the Same Disease Adults Get
Colorectal cancers in people 20 and under are often aggressive and delayed in diagnosis, new research shows.
Newark Charter girls volleyball standout wins Athlete of the Week
The poll, presented by Delaware Orthopaedic Specialists, runs Monday through Thursday each week.
MD Health Department fined $4.7M so far for delayed psychiatric care
Maryland is scheduled to approve a six-figure payment after the Department of Health failed to provide prompt psychiatric care to criminal defendants, an ongoing issue that has racked up a cost of $4.7 million.
Patient Dies by Suicide After ‘Insurance Issue’ Delayed Medicine for Lung Disease Flare-Ups
Hours after experiencing a flare-up related to chronic obstructive pulmonary disease, Kenney Blewett of Kyle, Texas, died by suicide in June. A medication his doctor prescribed days earlier to ease his breathing problems hadn’t been filled due to an “insurance issue,” his pharmacy explained via email.
Supreme Court denies Arizona’s bid to delay start of takeover of healthcare in state prisons
The U.S. Supreme Court rejected a bid by Arizona to block the start of a court-ordered takeover of healthcare operations in its prisons after the state was found to have provided inadequate care to incarcerated people and dragged its feet...
$46.8 million townhome development planned in Ankeny
Hubbell Realty Co. plans to develop a $46.8 million rental townhome community on Ankeny’s northeast side, adding 200 units to one of the Des Moines area’s fastest-growing communities. The 16-acre development, called Marlow 35, is planned for the northeast corner of Northeast Delaware Avenue and Northeast Ninth Street. The community will include one- and two-story…
Kena: Scars of Kosmora delayed to 2027
Publisher Sony Interactive Entertainment and developer Ember Lab have delayed Kena: Bridge of Spirits sequel Kena: Scars of Kosmora from its previously planned 2026 release window to 2027. It will …
This diet may slow brain aging by 2.5 years
People who followed the MIND diet more closely showed slower brain shrinkage and less grey matter loss over time, with the strongest differences equivalent to about 2.5 years of delayed brain aging. Berries and poultry were linked with healthier brain changes, while sweets and fried fast foods were associated with greater tissue loss.
Time lost to political haggling means lost momentum for research
While it’s not up to universities to set deadlines for EU institutions, “lost time” in the run-up to the launch of the next Horizon Europe would translate into “lost momentum” for universities, according to Dag Rune Olsen, president of the Young European Research Universities Network.“I think it's important to have [the EU budget] in place in order to be able to work on the research funding mechanisms, because we cannot afford to lose more momentum than we already have,” Olsen told Science|Business in an interview in September, just after EU research lobbies gathered in Brussels to push for a €200 billion budget for the next Horizon Europe programme.A funding gap would mean ramping down research activities, said Olsen. “You can do that quite swiftly, that’s not a problem, but ramping up again is much more difficult.”The last-minute push for an ambitious budget, and for a timely adoption of the research programme, comes at a time when the richest EU states have teamed up to call for significant cuts to European Commission’s proposal for the next multiannual budget, which allocates €175 billion for Horizon Europe. At the same gathering of research associations in September, the European Parliament’s budget rapporteur warned that the EU will need to raise its own taxes, otherwise political pressure and tighter national budgets will translate into a limited EU budget with a less ambitious envelope for research. The research sector hopes EU institutions will reach timely agreement on the budget and on Horizon Europe, but progress has been slow. Legislative progress has been delayed, partly because the European Parliament’s budget committee is still haggling over how to apply new EU-wide spending rules, known as the Performance Framework Regulation, and partly because EU governments have yet to agree on the size of the next EU budget. EU research Commissioner Ekaterina Zaharieva told Science|Business in July that she was hoping for an agreement on Horizon Europe by the end of 2026, but the timelines have been pushed back significantly, with the Parliament now aiming to announce its official position on Horizon Europe only in November. Avoid the funding gapAccording to Olsen, delayed EU funds could prompt universities and researchers to move on and do something else, potentially jeopardising years of work building consortia and collaborations. “If funding is interrupted, the networks fall apart in just a few months,” he said. Olsen also noted that an interruption would affect junior researchers first. PhD students and postdocs are on shorter term contracts and universities risk losing them if funding for EU projects is interrupted. Related articlesEU own resources ‘essential’ for future research budget, says leading MEPParliament haggle over EU-wide spending rules delays vote on Horizon EuropeZaharieva hopes for a Horizon Europe deal in 2026Universities usually have more employees, permanent and short-term staff, than they can cover with national funding, and external funding is essential to keep them all on the payroll. In case of an EU funding gap, “there will be a huge number of people that might end up without any contracts,” he said. Apart from the money issue, Olsen said EU projects forces universities to collaborate more which, in turn, increases the quality of teaching and research. In case of a funding dip, people will look around for opportunities elsewhere, in the private sector or abroad. “And then then you have to recruit again, and it's a tedious business,” said Olsen. “A gap is not a good idea, it's actually a waste of money.”According to Olsen, the difficult political context should encourage universities to make a stronger case for the EU increasing research funding, as universities can deliver on competitiveness, technological sovereignty, security and defence. “The reason why we ask for substantial investments in research is exactly what the Commission, what Europe, the Parliament have been discussing,” he said. “You really need to invest in order to thrive in the longer run.”Focus on the member statesBut EU and national R&D expenditure hasn't kept up with the times. EU governments have failed to reach a spending target set almost 25 years ago. Only six EU countries spend 3% or more of their GDP on R&D. Asked whether universities should put more effort into convincing the governments to ramp up their own spending, but also to support a strong budget for Horizon Europe in the ongoing budget negotiations, Olsen said “the answer is yes.”“We are very actively encouraging our members to talk to their ministries in order to enlighten them about the joint effort,” he said. The network is made up of 25 universities from across Europe, all established in the past 60 years or so.Who will call the shots?Budget and timing issues aside, the Parliament’s research committee has been locked in behind-the-scenes negotiations over the future structure of Horizon Europe, with MEPs disagreeing on the degree to which its collaborative research should be governed by councils of experts.The European Parliament’s lead rapporteur on Horizon Europe wants councils of independent experts to decide on the funding agenda, but the Commission, the Council, and parts of the Parliament disagree. For Olsen, it is normal for politicians to point at the big challenges, but when they start detailing how those challenges should be solved, the endeavour “fails utterly.” He does not necessarily think that “bureaucrats who don’t know the field” would be “much better at it” either. “There has to be a combination” of broad political directions and bottom-up implementation, Olsen said.
Light Science Technologies Lowers 2026 Revenue Outlook Following Project Delays
Light Science Technologies Holdings (LSE:LST) expects full-year 2026 revenue of between £9. 0 million and £9.
Liberty-Delaware Preview
Liberty(3-1 overall, 0-0 CUSA) at Delaware(2-2 overall, 0-0 CUSA)Friday 7 pmDelaware StadiumNewark, Delaware
Senate reaches bipartisan deal on permitting bill to speed approvals of new energy projects
Senators from both parties said Wednesday they have reached a bipartisan deal on legislation aimed at speeding up permitting reviews for new energy and infrastructure projects that now face yearslong delays as lawmakers seek to meet growing demand for electricity and other forms of energy.
Livingston Parish president says release of unredacted checks was political, not criminal
Parish President Randy Delatte told WAFB Wednesday that he does not believe there was criminal intent behind a political flyer that exposed the parish’s government checking account.
VIDEO | Plot Twist: Making Delaware a film and entertainment hub through tax credits
Now that Delaware's film tax credit is up and running, what is the actual potential for making The First State a hub for creators?
De La Cruz Office Helps Edinburg Agriculture Business Resolve H-2A Visa Delay
The office of U.S. Rep. Monica De La Cruz helped an Edinburg agriculture business resolve delayed H-2A visas after the company sought congressional casework assistance, according to De La Cruz’s office and the business owners.
6 PS5 Games Releasing in October You Officially Cannot Miss
Too many games, never enough time
Exclusive: N.Y. House Democrats push for delay of state SNAP cost share
The law establishes an up to 15% state contribution rate, depending on the state’s error rate.
Proposed aircraft carrier redesign could delay NNS construction
The Trump administration is considering a potential redesign of the nation's aircraft carriers that could cost billions more dollars.
Anthropic joins ARPA-H clinical AI moonshot, will hold closed-door health care event
In this edition of STAT Health Tech: Oura delays IPO plans, Anthropic joins an clinical AI effort by ARPA-H, and MAHA's health data goals.
Samsung’s Android 17 floodgates are open – updates rolling out for Galaxy S26, S25, more
The floodgates are open. After a delay and staggered starts, Samsung is widely rolling out its Android 17-based One UI...
Eagles' Jalen Hurts fuming over medical delay in Bears loss
Philadelphia Eagles quarterback Jalen Hurts wasn't happy about being out of the Chicago Bears game for a period of time.
Chicago renter ordinance votes delayed as Johnson, opponents seek compromise
Neither Mayor Brandon Johnson’s proposal nor a competing measure has enough support to become law as the two sides continue negotiations.
Newsom vetoes bills aimed at insurance reform sought by wildfire survivors
Supporters of the bills said would give policyholders greater transparency and accountability when insurance companies delay or underpay claims
Senate Health Panel Delays Bill as Nominees Await Vote
Senate Health Committee recesses HHS markup as measles cases rise. Surgeon General nominee delayed. See why this matters for public health policy.
Delaware health centers receive nearly $23M for technology, mobile care
Gov. Matt Meyer and other Delaware officials announced nearly $23 million in federal funding to upgrade patient records, expand care coordination and improve access to services in rural communities between three federally qualified health centers.
Scientists solve 1840s space weather mystery
19th century Nature account of 1841 train delayed by geomagnetic storm got year wrong—thanks to a typo.
University of Delaware cancels political debates, prompting pushback
UD will not be hosting its debate for the first time in decades, citing expenses and a change in mission for its Center for Political Communication.
Counties urge action on state voter registration system amid backlog
The request comes as county election officials are working overtime to rectify the problem with the delayed voter registration applications.
Millions Of Galaxy S25 And S26 Phones Get New Samsung Features Today
Samsung is finally rolling out its free feature upgrade to millions of Galaxy phones after a delay with the One UI 9 release. Here's who's getting it.
Bayern's training ground continues to be developed despite slight delays
Sports BILD understands that construction work is ongoing at Bayern Munich's Säbener Straße during the international break.The first-team section has been expanded towards the training pitches. A su...
Arizona prison health care issue heads to U.S. Supreme Court
PHOENIX - Attorneys for inmates in Arizona prison are telling the U.S. Supreme Court it should reject a last-ditch bid by the state to delay wresting away control of its health care system. In a …
Mental health stabilization center opens in Upper Darby
Operated by MVP Recovery, this is the second STAR Center in Delaware County.
ICE enforcement around healthcare facilities in Pa. leads to fears for immigrants of seeking care
Advocates warn that as word of raids near hospitals and medical centers spreads, so can fears of seeking healthcare services in immigrant communities. Medical workers too have warned that more aggressive immigration enforcement has led to immigrants delaying or refusing necessary care.
US Supreme Court receives arguments about fate of prison healthcare system
Attorneys for Arizona prison inmates are telling the U.S. Supreme Court to reject a last-ditch bid by the state to delay the takeover of its healthcare system.
Taylor Swift turned up, Madonna let loose and everybody smoked: The 2026 MTV VMAs, from every angle
The 2026 VMAs gave us a Madonna and Sabrina Carpenter collab, a football-related delay and ... smoking rock stars.
I-5 southbound project on track as pressure builds for local businesses
Portland’s southbound I-5 Rose Quarter shutdown hits the halfway point, with ODOT saying repairs remain on track for Oct. 16. But delays are worsening and nearby businesses report steep losses as traffic patterns shift.
Here’s why the 2026 MTV VMAs were delayed
The annual awards show was set to start at 7:30 p.m. ET/4:30 p.m. PT with a performance by Madonna.
Here’s why the 2026 MTV VMAs were delayed
Here’s why the 2026 MTV VMAs aren’t on yet, and why the annual MTV awards show is delayed on the network and CBS.
TX maternal health report delay is political, puts pregnant women at risk, lawmakers say
Editor's note: Headlined shorted for character length requirements
TX maternal health report delay is political, puts pregnant women at risk, lawmakers say
Editor's note: Headlined shorted for character length requirements
Start of Mets-Nationals game delayed due to inclement weather
The start of Sunday's season finale between the Mets and Washington Nationals has been delayed due to inclement weather.
Attorney General Rob Bonta defends settlement with Paramount as judge delays merger
A federal judge has delayed approval of the settlement in the Paramount-Warner merger case, following concerns raised by critics and New Jersey Sen. Cory Booker about its potential impact on competition, jobs, and media independence.
Xbox is reportedly paying a "fraction" of the $400 million Kojima quoted Sony for Physint
Xbox is reportedly paying far less than the $400 million Kojima quoted Sony for Physint, after Sony dropped it over cost and delays.
Virginia bounces back, takes care of business against Delaware with 42-3 win
Quarterback Beau Pribula scored five touchdowns, helping Virginia jump out to a two-score lead on its way to a 42-3 win over Delaware on Saturday night at Scott Stadium.
Virginia bounces back, takes care of business against Delaware with 42-3 win
Quarterback Beau Pribula scored five touchdowns
Rangers 6, Twins 2: Ober and Out
Well, in their quest to aid major-league history and prevent a sub-.500 team from winning their division, the Texas Rangers knocked the Twins around in a rain-delayed, 6-2 victory on Saturday afternoon. With the Houston Astros just underway, the Rangers improve to 80-81, and give themselves a fighting chance of claiming the West with another […]
Virginia bounces back, takes care of business against Delaware with 42-3 win
CHARLOTTESVILLE, Va. (AP) — Quarterback Beau Pribula scored five touchdowns, helping Virginia jump out to a two-score lead on its way to a 42-3 win over Delaware on Saturday night
Virginia bounces back, takes care of business against Delaware with 42-3 win
Quarterback Beau Pribula scored five touchdowns, helping Virginia jump out to a two-score lead on its way to a 42-3 win over Delaware at Scott Stadium.
Trump administration awards $23M to boost rural healthcare in Delaware
A major infusion of federal money is headed to Delaware health centers, with nearly $23 million aimed at expanding care and modernizing services.
Trump administration awards $23M to boost rural healthcare in Delaware
A major infusion of federal money is headed to Delaware health centers, with nearly $23 million aimed at expanding care and modernizing services.
Trump administration awards $23M to boost rural healthcare in Delaware
A major infusion of federal money is headed to Delaware health centers, with nearly $23 million aimed at expanding care and modernizing services.
Trump administration awards $23M to boost rural healthcare in Delaware
A major infusion of federal money is headed to Delaware health centers, with nearly $23 million aimed at expanding care and modernizing services.
Samsung Galaxy S26 Users, Check Your Phone For This Free Upgrade Now
Samsung is finally rolling out its free feature upgrade to millions of Galaxy phones after a delay with the One UI 9 release. Here's who's getting it.
Pakistan’s Political Standoff Deepens as Imran Khan’s PTI Delays Islamabad March
Just twenty-four hours before a nationwide protest march […]
This seasonal habit promotes healthy aging and may reduce dementia risk in older people
Aging is inevitable, but there’s increasing evidence that it may be possible to prevent, or at least delay, age-related diseases, including cardiovascular disease and Alzheimer’s.
Delaware high school football scores, highlights, analysis from Week 3
Follow along for live coverage of the top high school football games in Delaware.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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