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Diamondbacks expected to get Corbin Burnes back during Royals series
PHOENIX — The Arizona Diamondbacks are expected to get reinforcements in their starting rotation during their next road trip, and the return of a former National League Cy Young Award winner. Arizona Sports’ John Gambadoro expects right-hander Corbin Burnes to join the rotation and make his first start of 2026 against the Kansas City Royals on Tuesday.
Health insurance premiums in New Mexico could rise up to 30%
New Mexico expects health insurance premiums to rise by up to 30% and says 89,000 Medicaid recipients could lose coverage under new rules.
MLB insider 'expects' Yankees to keep Aaron Boone as manager
This is Boone's ninth season as Yankees manager.
Tyson Foods lowers earnings guidance for beef segment
Tyson Foods lowered its full-year earnings guidance on Thursday (Sept. 3) after reporting larger beef losses than expected. The Springdale-based company now expects to lose between $775 million and $625...
GOP lawmaker says he expects McConnell will return to Capitol Hill later this month after lengthy absence
House Oversight Chair James Comer of Kentucky said Thursday that Sen. Mitch McConnell’s staff have told him they are hoping the senator – who has had an extended absence from Washington due to health issues – will return when the Senate comes back into session on September 14.
AI boom through 2050 hinges on power supply, politics, PwC says
PwC expects global data center capex will hit $31.6 trillion by 2050 in a base case scenario, with spe | AI may unleash a $31.6 trillion data center buildout by 2050, but PwC says the real race isn’t just for capital — it’s for power, chips and political advantages.
AI boom through 2050 hinges on power supply, politics, PwC says
PwC expects global data center capex will hit $31.6 trillion by 2050 in a base case scenario, with spe | AI may unleash a $31.6 trillion data center buildout by 2050, but PwC says the real race isn’t just for capital — it’s for power, chips and political advantages.
Penguins May Be Better Than Anyone Expects This Season
The Pittsburgh Penguins could pull off one more surprise in 2026-27, even if the risk of everything falling apart is very much there. The post Penguins May Be Better Than Anyone Expects This Season appeared first on HEAVY.
Packers' Matt LaFleur says Josh Jacobs will be on roster during legal process
Packers coach Matt LaFleur wouldn't say whether running back Josh Jacobs will be available for the Sept. 13 opener, but he expects him to be on roster
Retired political science professor discusses Michigan primary and the road to the November Election
Kulisheck expects the U.S. Senate and Michigan Gubernatorial race to be close.
Mullins expecting another stern test against Tranmere
Newport County manager Hayden Mullins expects another demanding afternoon when his side host Tranmere Rovers on Saturday
Surprise Eastern Conference Teams Predicted To Finish With Better Record Than 76ers
Everyone expects the 76ers to be near the top of the list, but you may be surprised who ESPN has ranked above them.
Here’s how many foldable iPhones IDC expects Apple to ship
Bloomberg notes that IDC has a bullish outlook on the device’s performance during its first year. Here are the details.
Philadelphia DA says he'll keep piece of Trump's White House ballroom 'after we all blow it up'
Philadelphia District Attorney Larry Krasner said Tuesday he expects President Donald Trump’s White House ballroom to one day be blown up in an “official ceremony."
Boston Scientific hit by cyberattack causing ‘disruptions’ to parts of its business
This year has seen a growing number of medtechs hit by cyberattacks, and now Boston Scientific has become the latest victim. In an SEC filing posted Aug. 26, the medtech giant said it had detected a “cybersecurity incident” the day before. The incident has affected certain parts of its information technology systems, something that “has resulted in a global disruption to the company’s operations.” The incident has hit not just its information systems but also its business applications, which “support aspects of the Company’s operations,” it said in the filing. This includes its ability to process and ship customer orders. Boston Scientific said it is working to restore the systems, but the timeline remains unknown. Related Baylor Genetics hit by cybersecurity attack targeting patient, staff information As the company investigates the incident, it remains unclear how significantly its business will be affected. “Accordingly, the Company has not yet determined whether the incident is reasonably likely to have a material impact.” The company’s shares were down 3.5% in premarket trading as the news broke. This adds another layer of pressure for the medtech, which last month revealed a new global restructuring program that starts this year and is slated to be completed by 2029. The company said at the time that it “does expect some headcount reductions to result from these restructuring activities,” but did not provide any numbers or specify areas where the cuts may be made. It added, however, that new jobs are also set to be “created in areas of growth.” It was also forced to cut its sales guidance in Q2, saying in late July that it now expects full-year 2026 organic revenue growth of 5% to 6%, down from its previous guidance of 6.5% to 8%. Boston Scientific is one of a growing number of life sciences companies, notably medtechs, that have been hit by cyberattacks this year. These include Abbott, iRhythm, Medtronic and Stryker, as well as Big Pharmas Amgen and Novo Nordisk.
Exclusive: Onos Health raises $17M Series A for clinical intelligence
The company expects to raise $25 million to $40 million in a Series B round in the next 18 months.
Veterans Affairs to open clinic in South Burlington
The VA White River Junction Healthcare System expects the new clinic to open by 2030. It will replace and expand on the services the VA currently offers at its clinic in Burlington.
FDA digital health leader promises generative AI regulatory guidance is coming
FDA expects to issue guidance on policies regarding generative AI devices, according to Rick Abramson, the agency’s head of digital health policy.
Avalanche news: Joe Sakic delivers confident Cale Makar contract update
Colorado Avalanche president and general manager Joe Sakic provided another positive indication Sunday that the team expects to secure a long-term contract extension with defenseman Cale Makar before the start of the 2026-27 season. Makar is entering the final season of his current contract, which carries a $9 million salary-cap hit. He became […] The post Avalanche news: Joe Sakic delivers confident Cale Makar contract update appeared first on ClutchPoints.
Oxford traders count cost of extended congestion charge
Business owners warn of lost trade as a council expects to earn £7.7m from a charge on motorists.
Roundup: Partnership CEO search / Broadband expansion / Tariff negotiations
Time frame: The Greater Baton Rouge Economic Partnership tells Daily Report it expects to have a new CEO in place in three to four months. The organization launched its national search for a new CEO on Aug. 4. While internal milestones won’t be shared, the Partnership says it remains committed to moving thoughtfully and steadily […]
Trump says he expects to meet with North Korea’s Kim Jong Un later this year
In an impromptu White House meeting with reporters, the president touted his relationship with Kim and said North Korea has “57 very powerful nuclear weapons.”
Baker Mayfield expects Buccaneers to surprise NFL in 2026
Tampa Bay enters 2026 with a new offensive coordinator.
Macau’s Paradise Entertainment warns of likely US$10.5 million loss in 1H26 on satellite casino closure, lower gaming machine sales
Macau’s Paradise Entertainment has warned that it expects to record a HK$82.6 million (US$10.5 million) loss in the six months
UNT Health Fort Worth expects nearly flat revenue, higher spending in 2027
The university expects a small revenue increase and raises expenditures $8.2 million as it pursues enrollment, research and clinical growth.
Bills DC Leonhard expects defensive starters to play in preseason opener
Jim Leonhard expects his defensive starters to play in the Buffalo Bills’ preseason opener against Carolina on Saturday.
Scientists Release Biggest 2D Map of the Universe
Key Takeaways The DESI Legacy Imaging Surveys combined more than 263,000 telescope exposures to make the largest 2D map of the universe in visible and near-infrared light. Astronomers can pair the Legacy Surveys map with their own observations to explore our universe and search for rare phenomena. The 2D map serves as the foundation for the Dark Energy Spectroscopic Instrument survey to measure the universe in 3D and investigate dark energy. Hold on to your telescopes: the DESI Legacy Imaging Surveys team has released the largest-ever 2D color map of the universe. The 5.6-trillion-pixel map contains nearly 4 billion celestial objects, primarily stars and galaxies. The data is available for all to use and publicly viewable through the Legacy Survey Sky Viewer. Astronomers and citizen scientists can explore the map or combine it with their own observations to better understand our universe. Researchers can search for rare phenomena like gravitational lenses, observe fleeting events like supernovae, and investigate two of physics’ biggest mysteries: dark matter, the invisible substance that accounts for most of the mass in our universe, and dark energy, the force driving our universe’s accelerating expansion. The new map builds on earlier versions from the DESI Legacy Imaging Surveys that have already proved invaluable. To date, more than 1,800 science papers that reference the Legacy Surveys data have been published. “It’s part of the fabric of astronomy research now,” said David Schlegel, a co-lead of the Legacy Surveys and scientist at the Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab). “When you’re working with astronomical objects today, you often start by pulling up the Legacy Imaging Viewer to see what you’re looking at.” Covering roughly 75% of the sky in visible and near-infrared light, the updated map provides a deep view of the extragalactic universe not blocked by the dust and stars of our own Milky Way. Researchers expect it will remain the most comprehensive 2D map of our universe for years to come. More than 160 scientists contributed to data collection for the project, and a team of 20 produced the final dataset released today. It was built by combining 263,407 telescope exposures from three ground-based sky surveys: the Dark Energy Camera Legacy Survey (DECaLS) at NSF Cerro Tololo Inter-American Observatory, the Mayall z-band Legacy Survey (MzLS) at NSF Kitt Peak National Observatory, and the Beijing-Arizona Sky Survey (BASS) at the University of Arizona’s Steward Observatory. That was supplemented by years of data from NASA’s Wide-field Infrared Survey Explorer (WISE) satellite mission and additional public data. “For our team, these data are fundamental to our investigation of the expansion history of the universe and the formation of our galaxy,” said Arjun Dey, co-lead of the Legacy Surveys and an astronomer at NSF NOIRLab. “But the skies belong to everyone, and this survey gives everyone the chance to explore the sky and marvel at its wonders.” Here be galaxies The DESI Legacy Imaging Surveys were originally conducted to prepare for the Dark Energy Spectroscopic Instrument (DESI) survey. The Legacy Surveys’ 2D map is essentially a deep photograph of the sky; it records where galaxies and stars appear and how bright they appear. This crucial step enables DESI to select objects and measure their light in different wavelengths to determine their distances, building the largest high-resolution 3D map ever made. Scientists study the way galaxies have clustered at different ages of the universe to track dark energy over time. In April 2026, DESI completed its original five-year survey ahead of schedule and with vastly more objects than expected. The early results have shown surprising hints that dark energy’s impact may be weakening over time — a paradigm shift that could potentially shape the predicted fate of our universe. DESI expects to publish improved results using their first five years of data in 2027 and is continuing observations into 2028. DESI was so efficient at observing galaxies, the Legacy Surveys map needed to expand. Early on, “it became clear we might run out of galaxies to look at and run out of sky, and we better start doing something about that,” said Schlegel, who also works on DESI. The new Legacy Surveys map has been used to select DESI targets since June 2026 and will guide the telescope’s operations over the coming years. Computing the cosmos Merging hundreds of thousands of images taken on 2,285 nights, each with unique atmospheric and telescope conditions, was a massive computational effort. It took about a year to develop the computer code and eight weeks to process all the images at the Perlmutter supercomputer at the National Energy Research Scientific Computing Center (NERSC) at Berkeley Lab. Beyond supporting DESI, the Legacy Surveys will be a foundational reference for the next generation of telescopes. As new observatories like the NSF-DOE Vera C. Rubin Observatory (jointly funded by NSF and DOE’s Office of Science) and NASA’s Nancy Grace Roman Space Telescope come online, researchers can compare their observations with one of the deepest and most comprehensive views of the sky ever assembled. The Legacy Surveys data will also help scientists train artificial intelligence tools to analyze petabytes of astronomical data and accelerate new discoveries. It will be among the datasets used in an astrophysics pilot project within the American Science Cloud, part of the DOE’s Genesis Mission. The DESI Legacy Imaging Surveys are supported by the U.S. Department of Energy’s Office of High Energy Physics; the National Energy Research Scientific Computing Center, a DOE Office of Science user facility; the U.S. National Science Foundation, Division of Astronomical Sciences; and the partner institutions. DESI is supported by the DOE Office of Science and NERSC. Additional support for DESI is provided by the NSF; the Science and Technology Facilities Council of the United Kingdom; the Gordon and Betty Moore Foundation; the Heising-Simons Foundation; the French Alternative Energies and Atomic Energy Commission (CEA); the Secretariat of Science, Humanities, Technology and Innovation (SECIHTI) of Mexico; the Ministry of Science and Innovation of Spain; and by the DESI member institutions. ### Lawrence Berkeley National Laboratory (Berkeley Lab) is committed to groundbreaking research focused on discovery science and solutions for abundant and reliable energy supplies. The lab’s expertise spans materials, chemistry, physics, biology, earth and environmental science, mathematics, and computing. Researchers from around the world rely on the lab’s world-class scientific facilities for their own pioneering research. Founded in 1931 on the belief that the biggest problems are best addressed by teams, Berkeley Lab and its scientists have been recognized with 17 Nobel Prizes. Berkeley Lab is a multiprogram national laboratory managed by the University of California for the U.S. Department of Energy’s Office of Science. DOE’s Office of Science is the single largest supporter of basic research in the physical sciences in the United States, and is working to address some of the most pressing challenges of our time. For more information, please visit energy.gov/science.
Treasury Wine announces $395 million charge tied to US supply chain revamp
Australia's Treasury Wine Estates said on Monday it expects to take an additional A$558.4 million ($394.5 million) post-tax charge in 2026 related to the write-down of U.S.-based assets and brands.
Cruisin’ the Coast turns 30 with new events, expanded entertainment
Classic car event expects nearly 11,000 vehicles for milestone October run.
Sean Payton shares encouraging update after Jaylen Waddle injury scare
Sean Payton said Jaylen Waddle had some muscle tightness, and he expects the Broncos wide receiver to be fine.
Cowboys OLB Donovan Ezeiruaku expects more sacks than last season
"We will not live on past successes or be trapped by past failures" – Xbox CEO outlines priorities to turn platform around in FY27
Asha Sharma expects growth to return to Xbox by "investing in what players value"
Salt Lake County Health Department reports first human West Nile Virus case of 2026
The Salt Lake County Health Department reported the area's first human West Nile Virus case of the year.The health department expects the infected adult, who wa
Amazon CEO: AWS could be a ‘trillion-dollar’ business
Amazon (AMZN) CEO Andy Jassy explained on the company's earnings call that while the company expects to spend approximately '$220 billion in cash capex in 2026' to meet soaring demand, he believes AWS could "very possibly be a trillion-dollar annual revenue business for us in time.'
FTSE 100 to fall from record high after Fed holds interest rates and Iran attacks; Rolls-Royce expects higher profits
Live, rolling coverage of business, economics and financial markets as global stock markets drop after US central bank keeps interest rates steady
ArcelorMittal Posts Fall in Net Profit But Sees Improved Outlook for European Business
The steelmaker said supportive trade measures had improved the prospects for its European business and expects second-half sales to outperform those of the first.
Steam Machine gets AMD FSR 4.1 support and official external CAD files
Valve expects every Steam Machine reservation holder to receive a purchase option before the end of 2026. FSR 4.1 support and external CAD files are also available.
Town Square looks to bring new health care model to Rochester
The primary care practice catering to seniors expects to begin accepting patients this month, and to open in September.
Fertitta Entertainment counsel doubts Texas will legalize gaming, expects SCOTUS to favor state regulation
The general counsel and executive vice president of Houston-based Fertitta Entertainment cast doubt on Texas getting legalized gaming anytime soon and told Neva
'MacBook Ultra' Coming Soon With These 12 New Features
Apple's first high-end MacBook redesign in five years is expected to arrive in the near future, bringing a run of firsts to the Mac. Bloomberg's Mark Gurman expects the laptop to arrive between late 2026 and early 2027, with the later window now looking more likely owing to the global memory chip shortage. Analyst Ming-Chi Kuo expects mass production to begin by late 2026.
Freeport McMoRan eyes $4.5B expansion of Arizona mine as investment decision looms
Freeport-McMoRan Inc. is moving forward with the expansion of its Arizona mine operation and expects to make an investment decision by the end of the year.
Nestle to raise €3 billion from spin off of its water business
Nestle said on Thursday it expects to raise around €3 billion ($3.43 billion) from spinning off its water business into a 50-50 joint venture with U.S. investment firm Platinum Equity.
Hospital opens ‘1st of its kind’ new interventional radiology suite
The University of Wisconsin expects to double the number of IR procedures performed annually at American Family Children’s Hospital.
Ohio's top health leader expects increase in cases of explosive diarrhea bug
Dr. Bruce Vanderhoff, leader of the Ohio Department of Health, says while Ohio has had 364 cases so far, Michigan has had thousands of cases.
Emergent CEO shares what he looks for in developers
Mukund Jha said he expects demand for software to "exponentially increase."
Cutting GLP-1 coverage may cost UVM Health more than it saves
UVM Health expects to save $19 million a year by cutting GLP-1 coverage for employees. But does that figure account for the medical costs patients avoid once the treatment works?
One small pen for one giant fee: Buzz Aldrin’s mission-saving felt-tip up for auction
Sotheby’s expects second man on moon’s marker, crucial to Apollo 11 return, to reach astronomical sum
Here's How Big Wall Street Expects SpaceX's Business to Get in 5 Years
If analysts are right, SpaceX could be on the cusp of some tremendous revenue growth.
BP Flags $1 Billion Writedown From Gas and Low Carbon Business
BP Plc said it expects to book impairments of $1 billion related to its gas and low carbon energy business in the second quarter, as the energy giant refocuses on oil and gas.
US health watchdog expects $5.56 billion in recoveries and savings
The federal watchdog for the U.S. health department generated $5.56 billion in expected recoveries and projected savings over six months and barred 1,212 individuals and companies from federal programs, it said on Monday, even as its overall enforcement activity fell to the lowest level in two years.
US Health Watchdog Expects $5.56 Billion in Recoveries and Savings
By Ahmed Aboulenein WASHINGTON, July 13 (Reuters) - The federal watchdog for the U.S. health department generated $5.56 billion in expected recoveries and projected savings over six months and barred 1,212 individuals and companies from federal programs, it said on Monday, even as its overall ...
Cboe expects SK Hynix options to trade two business days after Nasdaq debut, source says
Derivatives exchange Cboe Global Markets expects to list options on SK Hynix's U.S.-listed shares two business days after the stock's trading debut, a source familiar with the matter told Reuters on Friday.
Cboe expects SK Hynix options to trade two business days after Nasdaq debut, source says
Derivatives exchange Cboe Global Markets expects to list options on SK Hynix's U.S.-listed shares two business days after the stock's trading debut, a source familiar with the matter told Reuters on Friday. The South Korean chipmaker, which raised $26.5 billion in share sale, is set to make its Wall Street entry later in the day. SK Hynix, which is valued at about $1.03 trillion based on its South Korea-listed shares, did not immediately respond to a Reuters request for comment.
Microsoft expects more Windows security updates from AI-discovered flaws
Microsoft says Windows users should expect to see an increase in security updates as the company increasingly relies on artificial intelligence to discover vulnerabilities in its codebase.
A Business Owner Paid Himself a Low Salary for Decades to Save on Taxes. The Trade-Off Shows Up Now, in a Smaller Social Security Check, and Selling the Company Won’t Fix It.
A 66-year-old business owner running an S-corporation for decades is planning his exit. A buyer is circling, and he expects the sale to fund retirement. When it came time for him to request his Social Security statement, the projected monthly benefit was lower than expected. Friends with W-2 careers and similar lifestyles were getting noticeably ... A Business Owner Paid Himself a Low Salary for Decades to Save on Taxes. The Trade-Off Shows Up Now, in a Smaller Social Security Check, and Selling
NCAA president expects no changes to trans athlete rules after US supreme court ruling
Collegiate sports organization led by Charlie Baker banned trans athletes from women’s sports after 2025 Trump order
Continental Agrees to Sell ContiTech Business to Lone Star Funds
Continental expects the deal to generate cash proceeds of approximately 3.1 billion euros, some of which will be used to cut debt, with around 2.5 billion euros distributed to shareholders.
Jimmy Butler believes he’ll return better than ever
Jimmy Butler is confident his comeback from ACL surgery will be a successful one. The Warriors star says he expects to return as one of the NBA’s top players while revealing his desire to finish his Hall of Fame-caliber career in Golden State.
Claude Fable 5 isn’t permanently leaving subscriptions, Anthropic says
Anthropic says Claude Fable 5 won't be accessible via Claude subscriptions after July 7, but it's not a permanent change, and the company expects the model to return outside the usage-based plan soon.
Rich Eisen belives he’s done doing play-by-play
Rich Eisen built a second career on NFL Network almost by accident, stepping into the play-by-play chair years after he’d already made his name as a host. It appears that part of his career is now over, as he told Sports Illustrated’s Jimmy Traina that he no longer expects to call games. “No, it is…
Rivian boosts delivery outlook as EV sales top estimates
The company now expects to deliver between 65,000 and 70,000 vehicles this year, exceeding the roughly 63,000 deliveries expected by Wall Street analysts.
Everett water main break forces business closures
Water service along a section of West Marine View Drive was shut off around 1 p.m. Tuesday. The city expects to restore it Wednesday afternoon.
Lindsey Graham expects housing package to become law despite Trump's election bill demands
"We need the housing bill." U.S. Sen. Lindsey Graham says President Trump shouldn't let Tim Scott's bipartisan housing bill become collateral damage in the fight over the SAVE America Act.
FMOL Health pegs Cancer Institute investment at $70M, shares timeline
FMOL Health expects to invest roughly $70 million to transform the former Bone & Joint Clinic of Baton Rouge building into a new home for the Our Lady of the Lake Cancer Institute, according to E.… Already an INSIDER? Sign in. Already an INSIDER? Sign in
Xbox Expects The 'Component Crisis' To Get Worse For Consoles In 2027
Specifically for console storage and memory prices
Comcast Announces Plan To Split Tech And Media Businesses With NBCUniversal Spinoff
The company said it expects the split to be completed within a year, with Comcast’s shareholders owning shares in both companies.
3 million Americans have dropped Obamacare health coverage over past year, after Republicans let federal subsidies expire
KFF expects the total number of people in the government healthcare program to continue to decline throughout the year, potentially to a low of about 17.5 million from 19.2 million now.
Andy Burnham distanced himself from UK Prime Minister Starmer, but may be stuck with his policies
Andy Burnham has set himself apart from the man he expects to replace as British prime minister
Microsoft is raising Xbox prices yet again — this time by up to $150
Microsoft said memory and storage prices have increased by "more than 2.5x" and it expects "another doubling by the fall of 2027."
Rush CEO to step down, take health equity mission to national stage
Dr. Omar Lateef said he is handing off a health system at the top of its game and expects healthcare leaders from around the nation will be clamoring to fill the role.
Flutter Entertainment (NYSE:FLUT) To Leave London And Trade Only In New York
Flutter Entertainment plans to delist from the London Stock Exchange and keep its ordinary shares trading only on the New York Stock Exchange. The company expects its stock to remain listed under ticker NYSE:FLUT, concentrating liquidity in the US market. The change alters how existing London holders access the stock and could reshape the shareholder base over time. Flutter Entertainment enters this shift with its stock trading at $97.85 and a mixed recent performance profile. The share...
OpenAI Touts Progress in 19-Week-Old Ad Business
OpenAI is promoting progress in what it expects to become a $100 billion ad business. The artificial intelligence (AI) startup is making its inaugural
Jim Cramer Says McCormick “Is Still Reeling From Their Deal to Buy Unilever’s Food Business”
McCormick & Company, Incorporated (NYSE:MKC) was among the stocks Jim Cramer discussed as he said that the Iran peace negotiations could trigger an oil glut, cool inflation, and pull interest rates down. Cramer expects to hear a Unilever deal justification from the management, as he remarked: Also, on Thursday, we hear from McCormick. This is […]
BofA forecasts 75 bps of rate hikes in 2026 on labour market resilience, new Fed chair
BofA Global Research expects the Federal Reserve to hike interest rates by 75 basis points in 2026, it said on Monday, citing resilient economic data and rising expectations of a hawkish Fed under new Chair Kevin Warsh.
Apple to Release These 20 New Products Across Rest of 2026 and 2027
Apple's annual WWDC developers conference is in the rearview mirror, but there is still a lot to look forward to over the next year and beyond. In his Power On newsletter today, Bloomberg's Mark Gurman listed around 20 products that he expects Apple to release across the remainder of 2026 and 2027.
WHO expects stronger focus on link between climate crisis and human health at COP31
'Health is one of the strongest and most tangible arguments for climate action because people experience climate change first through its impact on their lives, wellbeing, and communities,' WHO head of office in Türkiye tells Anadolu | Anadolu
Registration open for 2026 HousingIowa Conference in Des Moines
Registration is now open for the 2026 HousingIowa Conference, hosted by the Iowa Finance Authority and scheduled for Sept. 9-10 in Des Moines. The conference expects to bring together nearly 1,000 professionals from housing, development, lending, government and community sectors. The event will feature national speakers, policy experts, and industry leaders addressing key issues in…
Sony drops “PC”, adds “AI” to official PlayStation business strategy summary
Sony had made some conspicuous edits and updates to its description of PlayStation’s “business environment and strategy,” in a new annual report filed to the U.S. Securities and Exchange Commission today. These changes are part of a 379-word overview of Sony’s strategy for its Game & Network Services (G&NS) division, which is another name for PlayStation. The chunk about PlayStation strategy is part of a voluminous financial report filed by Sony each June. This year’s is 229 pages long. Differences to any part of the filing—word changes made from year to year, as Sony provides a breakdown of its business for investors—can be illuminating. For example: A line from 2025 about how the PlayStation team “aims to achieve sustainable and profitable business growth” has been changed in the 2026 version to “aims to achieve sustainable business growth.” Notice which word they cut? That’s a pretty clear tell about how Sony expects its profit margins to be squeezed this year, due to rising chip costs for its hardware, among other things. A line from 2025 that stated “Sony plans to continue its efforts to deploy its first-party titles to multiple platforms such as PC” had been cut from the 2026 version. That appears to be Sony’s admission by omission that it has backed off releasing its biggest games on PC. Bloomberg’s Jason Schreier reported in March and again in May that Sony’s big single-player marquee games are no longer planned for time-delayed release on PC.1 A whole new chunk has also been added about how “Sony is utilizing AI to unleash the creativity of studios and further enhance the PlayStation experience.” A full breakdown of the changes made from the 2025 version to the 2026 version is below. I’ve redlined them for you…
Kustom Entertainment Announces Major Ticket Inventory Updates for Country Stampede Kansas 2026 in Bonner Springs, Kansas
Thursday single-day GA and Party Pit inventory is SOLD OUT; 3-day inventory is moving fast Overland Park, KS., June 15, 2026 (GLOBE NEWSWIRE) -- Kustom Entertainment, Inc. (NASDAQ: KUST) today announced strong ticket demand for Country Stampede Kansas 2026, taking place June 25–27, 2026, at Azura Amphitheater in Bonner Springs, Kansas. Ticket demand has spiked following the recent Kustom Entertainment Inc. and Gilley’s Gambling Hall Park City, KS announcement. Kustom expects a strong presence fr
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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