SCROLL NEWS / DISCOVERY
Search headlines
Find the stories shaping the conversation.
Results for " leak " 1,683 found 🔀 AI-powered Shuffle
Wolverines Zack Marshall Releases Statement after leaked text messages
On Monday night, there were leaked text messages surfacing across the internet about Michigan Wolverines tight end Zack Marshall being critical of offensive coordinator Jason Beck. Well, Marshall released a statement on his Twitter on Tuesday afternoon and said, What…
Michigan tight end Zack Marshall apologizes after he ripped OC Jason Beck in leaked texts
Report: Leaked Michigan Texts Rip Jason Beck’s Offense
Leaked group chat messages have Michigan's tight ends turning on Jason Beck's offense during the bye week. #GoBlue
Apple TV 4K Rumored to Support Four HomePods for Surround Sound
Last month, a proven leaker revealed that Apple has tested the ability to connect four HomePods to an Apple TV 4K for surround sound, with the HomePods intended to be arranged in front-left, front-right, rear-left, and rear-right positions. Now further evidence of this functionality has surfaced ahead of an announcement from Apple.
New leaks reveal more details about the Fitbit Edge including its price
Google’s next fitness tracker with a screen could arrive soon.
Leaks reveal new Apple TV 4K and HomePod features coming next week
Leaks in the latest Apple software reveal several new Apple TV and HomePod features expected to be unveiled.
Google ‘Fitbit Edge’ reportedly costs around $180 as specs & features leak
A new leak reveals that Google’s upcoming Fitbit Edge tracker will probably have a price somewhere around $180 and offer...
Xbox Elite Series 3 Controller Leaked Via Microsoft's Own Design Lab
Is an announcement imminent?
Xbox Elite Controller 3 Specs Leak Via Xbox's Own Design Lab
Xbox's long awaited Elite Controller 3 may finally offer drift-free joysticks.
The Xbox Elite Controller (Series 3) specs might've leaked — here's what's new (and the main thing you'll want to know remains unanswered)
Although I was unable to verify the sources (as they've been removed), users suggest that this leak is most likely legit. The Xbox Elite Controller Series 3 is likely imminent.
GTA 6 Could Finally Fix Gaming's Huge Drug Problem
Just because you can doesn’t mean you should
The Googlebook era is here: some first impressions of the hardware and a whole new OS
Today is the day. After months of tracking code commits, dissecting leaks, and getting that unforgettable first taste at Google’s media showcase in New York City, Googlebooks are officially landing...
Why I Don’t Think Ride Or Die Should Have Been Cancelled (And What Company Should Save It...)
(Welcome to my weekly streaming ratings report, the single best guide to what’s popular in streaming TV and what isn’t. I’m the Entertainment Strategy Guy, a former streaming executive who now analyzes business strategy in the entertainment industry. If you were forwarded this email, please subscribe to get these insights each week.) So…I recently came across a Reddit thread, talking about films on streaming, wondering why there are no reliable sources out there for streaming ratings data. Sigh. Honestly, as annoyed as I am that so many still don’t realize that we have streaming ratings, I somewhat get it. Until now, there was such a long delay between when a show or film came to streaming and when we got its viewership data; I understand why people were confused. (But, as you know, this just changed.) Also, even back in the day, how many people knew how well films did on television? Luckily, as a reader, you’re in the know. Okay, on to this week’s issue. I want to take a look at Prime Video cancelling Ride or Die and whether I agree with that decision. Overall, we didn’t have any breakout hits (no TV shows landed over 20 million hours according to Nielsen) but we have a lot of steady performers on the streaming charts. Plus, we’ll look at where $50 million in missing box office dollars went. (Spoiler: straight-to-streaming.) All that, plus new episodes of The Secret Lives of Mormon Wives, Supergirl heads to streaming, a new YA show does well on Netflix, the viewership for the Daily Wire’s $50 million fantasy show, what TV show hit-maker can’t make streaming hits, CD sales, all the flops, bombs and misses, and a whole lot more. Let’s dive right in! (Reminder: The streaming ratings report focuses on the U.S. market and compiles data from Nielsen’s weekly top ten viewership ranks, Luminate’s Top Ten Data, JustWatch and Reelgood interest data, Samba TV household viewership, company datecdotes, Netflix hours viewed data, Google Trends, and IMDb to determine the most popular content. While most data points are current, Nielsen’s data covers the weeks of September 7th to September 13th, 2026. You can find a link to my terminology here.) Subscribe Television - Ride or Die Is a Hit…But It Got Cancelled? What The Data “Says” I hate the phrase “here’s what the data says”, even though sometimes I find myself using it. If data just told us everything, we data folks would be out of a job! Data is often messy, complicated and nuanced. When it comes to strategy, many of the best decisions can’t actually use “data”, since it’s vastly too complicated to model. Anyways, I’ve been singing the praises of Prime Video’s Ride Or Die this summer, a show that did very well for them. And yet…it got cancelled. Now, usually when a show gets cancelled, a bunch of websites say “a hit show got cancelled”... Here’s the thing, though: in this case, they’re right! The data “says” that this show was a hit. Specifically, out of 522 first seasons to make a week on the Nielsen charts since 2020, it’s the 75th biggest. On Amazon, Ride or Die is eighth out of 41 first seasons: That’s top 15th percentile all time, almost exactly, which is my definition of a “hit”! I mean, outside of Reacher, Amazon needed a hit this summer! (Admittedly, Off Campus did well for Amazon in the spring, but Ride or Die performed even better.) So what happened? Why did Amazon cancel one of their rare 2026 bright spots? Well, Deadline reported a reason—which I’ll get to—but I’d break it down into three relevant questions: What is a given streamer’s reasoning? Is that reasoning sound? Could the stated reason not be the real reason? According to Deadline, Amazon felt the show “over-indexed” in middle-aged women. (This was based on leaks from within Amazon.) The logic is this: Amazon already reaches this demographic because of unlimited two-day shipping bundled with Prime, so they don’t really need more shows like this. Now, it’s my job to ask if that’s a good reason, and I’ll be honest, in this case, I don’t think it is. Sure, this show may “over-index” in middle-aged women—I’ll just assume that’s the case here—but I think folks often oversell how important over-indexing actually is. When a show is a “hit”, it isn’t a bit bigger than its rivals; it’s usually multiples bigger. For example, Elle only made the charts for two weeks at 8.3 million hours each. So Ride or Die was 80% bigger in its first two weeks, and likely had a much stronger hold, with its terrific 13 million hours in week three. Ride or Die was nearly three times bigger than Sterling Point through three weeks too. And that means that _Elle, Sterling Point a_nd other Amazon YA shows need to not just over-index a little with younger women (assuming that’s who Amazon prefers over middle-aged women), but massively over-index. Otherwise, more people in that demo (and a bunch more besides) likely watched Ride or Die. (I’ll try to explore this concept more in a future article.) And don’t get me started on how Ride or Die did compared to a certain (very, very popular, possibly the world’s most popular) YouTuber’s reality show…which didn’t make the charts after its first week and likely cost much, much more than Ride or Die. All to say, Amazon-MGM Studios/Prime Video can tell reporters that this show didn’t reach the right audience, but that excuse feels weak to me. So this leads to the third question: could other reasons have come into play? Yes! Renewal or cancellation decisions rarely (I’m tempted to say “never”) boil down to one variable. At its simplest, it’s two things: budget versus viewership. But often factors like critical acclaim, ownership and, yes, personal opinion come into play. In this case, Amazon has a new executive running things, and this show isn’t owned by Amazon-MGM Studios (unlike Elle). And yes, it may not have indexed with the right target viewers, too. Likely all of those factors came into play.1 My guess is ownership ended up mattering most. Amazon doesn’t own Ride or Die. It’s actually produced by another major studio. Fortunately/allegedly, this show is being shopped around. I can think of one brand new CEO who should consider it for one of his two major streamers…especially if he wants to rebuild goodwill in Hollywood. His name is on this list of exec producers of Ride or Die… If David Ellison needs some goodwill—and he does—rescue this female-led show tomorrow and grab some good headlines for a day. The data justifies it. Quick Notes on TV We’re just getting started with this issue, but the rest is for paid subscribers of the Entertainment Strategy Guy, so if you’d like to find out… How The Secret Lives of Mormon Wives latest season did on Hulu, post-controversy... Whether Supergirl soared on HBO Max... Why the box office is losing money due to the streamers... The viewership for the Daily Wire’s $50 million fantasy show... Updates on The Gentlemen, Lanterns, Outer Banks, King of the Hill and more... What former hit-maker has three streaming flops in a row... Whether The Mandalorian and Grogu popped in week two... All the flops, bombs and misses... And a whole lot more... ...please subscribe! We can only keep doing this great work with your support. If you want an idea of just how much content you’d get in a full issue, check out this older issue. Coming Soon! Oh man, we’re almost caught up! We just have two more issues, then the streaming Ratings Report will be coming out just two weeks after a TV show premieres! Next issue, I’ll be looking at the first two weeks of the NFL Thursday night games on streaming, a huge new spinoff, Reacher’s Neagly on Prime Video, and the latest edition of Monster: The Lizzie Borden Story on Netflix, the return of Slow Horses on Apple and MobLand (quietly one of their biggest shows) on Paramount+, and Dancing with the Stars on both ABC and Disney+. Plus I’ll take a look at animation for adults in 2026. The week after, a ton of movies are coming to streaming: Toy Story 5 on Disney+, Backrooms on HBO Max, Jackass: Best and Last on Paramount+ and The Breadwinner on Netflix, plus a Unabomber film on Netflix and a romcom on Prime Video. Woody Harrelson and Matthew McConaughey have a show on Apple, along with a game show inspired by Willy Wonka that everyone seems to hate. Long term, some crazy (but hopefully crazy like a fox) IP news. FX ordered a new Sons of Anarchy show from Charlie Hunnam, but it’s not about the biker gang. No, it features the show’s cast playing themselves in a new “meta-thriller”. Huh. And a lot of the cast is coming back. Next, Ryan Gosling is producing a Flintstones movie about a “grown-up Bamm-Bamm Rubble”. Also, huh. This one is in “early development” so we’ll see what happens. Both projects are based on IP, but also seem to have crazy takes on the IP, which I like.
Google's Mysterious New Fitbit Just Got a Lot More Real
The Fitbit Edge has a screen and a similar collection of sensors to the company's recent screenless wearable, according to new leaks.
[LEAKED] Dream Harvard Business School Invitee List
[LEAKED] Dream Harvard Business School Invitee List
Pixel 12 series leak allegedly reveals model numbers, display specs, no wide Fold
A new leak allegedly reveals Pixel 12 display specs, model numbers, and helps confirm Google isn't launching a wide Fold.
Marvel's 'Project COMET' First Gameplay Trailer Allegedly Leaks
We've heard rumors and talk of Project COMET for weeks, and the new Marvel game has reportedly had its first footage leaked.
Galaxy S27 Ultra colors leak, and Samsung could be breaking up with purple
Leaked Galaxy S27 Ultra colors suggest Samsung is retiring Deep Purple for another, surprising shade of color.
This is the Fitbit Edge: Google's next fitness tracker finally spills its secrets
Google is reportedly getting ready to launch a new fitness tracker called the Fitbit Edge, and the device has leaked in full!
China develops plant to extract hydrogen, fresh water and uranium from the sea
Scientists improve on existing technology, plugging an overlooked energy leak to achieve a potentially profitable green solution.
2TB MicroSD Express card leaks, providing Switch 2 storage for 100+ games
With some Switch 2 games creating a storage dilemma, help is on the way. Suneast is marketing a 2TB MicroSD Express card without a release date or price. Amid the memory shortage, 1TB cards already cost Nintendo supporters over $300.
The new Fitbit Edge leaks
Google’s midrange Fitbit Edge shows off is many sides and colors in leaked images.
‘Fitbit Edge’ leaks as Google’s next fitness tracker with ‘Apps’ & ‘Notifications’
Following an accidental marketing leak in August and FCC listing last month, retail listings for the “Fitbit Edge” have now emerged.
Samsung Galaxy S27 Ultra: (Slightly) faster charging and potentially fewer camera artifacts
While industry insiders are currently focused on the starting mass production of some Galaxy S27 series components like the Exynos 2700, leakers are sharing more details about battery and camera improvements that could matter to end users.
Exclusive: This Is the Fitbit Edge, Google's Next Fitness Tracker
Exclusive Fitbit Edge images show Google's new screened fitness tracker in three colors, sitting between the Fitbit Air and Pixel Watch 5.
📸 This week's kit news 👕
Official announcements, leaks... it’s been another week full of news in the world of football kits.On the agenda: PSG’s likely next kit, as well as Liverpool’s surprising kits for next season.��...
Amid bleak financial forecast, Brown Health announces buyouts, executive layoffs
Brown University Health announced a series of cost-cutting measures Thursday on the first day of its fiscal year, including executive layoffs and non-clinical buyouts. The hospital operator projects a $64 million deficit due mostly to federal budget cuts.
Leaked Anthropic IPO prospectus: The US government could hurt our business
Anthropic (ANTH.PVT) understands that the US government could affect how customers of all kinds view their business.
Intel Core Ultra 4000 Nova Lake-S lineup leaks, Core Ultra 9 4970K BFC appears above 4950K
Intel Nova Lake-S leak lists seven Core Ultra 4000 processors, led by the Core Ultra 9 4970K BFC. The chip has 28 cores, bLLC and a 125W rating.
Nebraska’s Dan Osborn responds to leaked audio commenting on Trump supporters
Osborn, an independent running for Senate, answered rapid-fire questions.
‘HomePad’ could launch in these four colors, per leaker
Apple’s long-rumored ‘HomePad’ product is reportedly launching October 13, and a new leak reveals the colors it might launch in.
Cops Can Bypass iPhone’s Automatic Reboot to Get Into Locked Phones, Leaked Video Claims
Magent Forensics, the owner of the GrayKey phone unlocking tool, says it can bypass an iPhone rebooting feature that was locking cops out.
Man City guilty: Premier League rivals demanding sanctions imposed before end of season
Plus: Man City are expected to owe the Premier League tens of millions of pounds in compensation for legal costs; Rui Pinto, whose leaks of private documents helped to trigger the Premier Leagues investigation, will no longer be protected as a witness by Portuguese authorities
Trump deflects on leaked audio of Ken Paxton calling Texas midterm convention a drag on his poll numbers
Republican Senate candidate Ken Paxton reportedly told donors that "everybody's numbers are down" after a midterm convention in Dallas that touted both Paxton's campaign and President Trump's record.
How Could Black, Newton Stand Out in Kings Training Camp?
Leaky Black and Tristen Newton battle to bolster Sacramento’s struggling perimeter rotation to accelerate the Kings' rebuild.
NRL Grand Final entertainment leaked
The NRL’s pre-game entertainment plan will reportedly centre on a touching tribute for Rabbitohs great Jai Arrow.
Leaked photos reveal an unreleased Fire TV Stick 4K and all-new remote
Image Source: WinFuture There have been a few signs of a new Fire TV Stick 4K being released soon, but nothing concrete until now. Several leaked photos of an unreleased Fire TV Stick 4K and a completely new remote have been acquired by German site WinFuture from independent retailer sources.
What smart people say about Anthropic's leaked IPO prospectus
Anthropic is planning its massive IPO after the November midterms, Reuters reported. Market watchers and techies are weighing in.
Pixel 11a looks mostly unchanged in first leak, reportedly brings purple color back [Gallery]
The first leak of Google’s upcoming Pixel 11a just hit the web, revealing a virtually unchanged design, as well as...
Leaked images reveal new colors for Amazon’s next entry-level Kindle
Amazon’s next basic Kindle is getting one very welcome upgrade.
Exclusive: Google Pixel 11a Official CAD Renders Leak
Our exclusive first look at the Google Pixel 11a: design, colors, size, what's new inside, and when it's expected to launch and at what price.
Leaked: Roma’s possible third Centenary kit
Roma’s centenary is also starting to take shape through the jerseys. FootyHeadlines has published the first previews of the third kit the club is expected to wear in the 2027-2028 season, the centen...
Samsung Galaxy S27 Ultra camera leak points to warmer photos and cleaner night shots
Leaker Ice Universe says the Samsung Galaxy S27 Ultra moves from the Galaxy S26 Ultra's cool color profile to warmer tones, holds back small bright light sources on both its main camera and 50MP 5x telephoto, and shows less shadow noise at night.
Galaxy S27 Ultra camera could solve two major issues seen on Samsung phones
The launch of the Galaxy S27 series is still four months away, but most details about the lineup's phones have already leaked. While the Galaxy S27 Ultra's basi
iPhone Duo StandBy Leak Reveals Five Unannounced Faces
We've seen previews of iOS 27 running on the iPhone Duo, including a new StandBy mode that activates even when the iPhone isn't charging. Apple showed the mode in press materials, but leaker pdfu today shared a more in-depth look at some of the options. There are multiple StandBy faces available on the iPhone Duo, five of which we weren't aware of. A Home Camera view will show a single camera feed or a grid of up to nine camera feeds.
Motorola's wide foldable now has a name and its specs are out
We also get two concept shots of its colors to look at. Earlier this month, some sketches leaked purporting to show Motorola’s upcoming wide foldable,...
Kindle rumors: A new basic Kindle might be coming, according to leaked pictures
Amazon finally moved the power button on the Kindle.
New 'Pokémon Winds and Waves' Leaks Fill Major Gap Left by Game Freak's Silence
Including gameplay, maps, and Elite Four character models
Motorola’s wide Razr looks small, chunky, and powerful in detailed new leaks
Motorola’s Razr Wide Fold could pack a 165Hz display, 5,000mAh battery, and dual 50MP cameras in a compact design.
Next entry-level Kindle may get rounded screen corners and new colors
Leaked images show a possible new entry-level Kindle with flatter edges, rounded display corners and a side power button. Amazon has not announced it yet.
It really is bleak out there, and list prices matter
Health insurance premiums are skyrocketing, private equity hospital chain goes nonprofit, and more from STAT's Health Care Inc.
Leak reveals new iPhone Duo features not yet announced
iPhone Duo is coming soon, and there are several unannounced features coming to its StandBy mode that were just discovered in Apple code.
3 business risks of AI-assisted coding executives can’t ignore
Without oversight, AI coding assistants can leak secrets, act sans accountability and spike spend.
Siloam Springs business owner raises concern over water leaking into basement of historic structure
SILOAM SPRINGS -- When a leak was noticed in the basement of Park House Kitchen + Bar, staff checked for plumbing leaks, drainage issues, air-conditioning runoff and anything else they could think of that might be causing the issue, according to business owner Alma Sanchez.
First Samsung Galaxy S27 Ultra cases reveal new details of the revamped camera design
Leaked CAD models have already provided a rough idea of what the Galaxy S27 Ultra and Galaxy S27 Pro will look like. The first real-world photos of very early protective cases now offer more details, particularly about the new and somewhat controversial camera design, suggesting that previous renders may not be entirely accurate.
PlayStation Plus Free Games October 2026: Reveal Date, Rumors, Predictions And More
he PS Plus October 2026 free games are coming soon. Here’s when Sony will reveal the Essential lineup, when the games release, plus leaks, rumors and predictions.
📸 This week’s kit news 👕
Official releases, leaks and great finds: OneFootball rounds up all the kit news of the week.This week, we begin our overview with Ecuadorian club Deportivo El Nacional, which has pinned around sixty ...
Pokémon Winds & Waves Full Region Map Leaked Alongside Gameplay Footage
Pokémon Winds & Waves full map has leaked online alongside a ton of gameplay details and beta footage.
New Pokemon Winds and Waves leaks have emerged, including the map, possible look at the Champion, more
Just when you may have thought that the major Pokemon Winds and Waves leaks were over, a new batch falls into our laps. The latest round of leaks comes from X user @grubbinscrubbin. A number of different images were posted online from the game’s beta, including what might be a look at the Champion. Note that everything is based on...
Texts link Justin Baldoni’s crisis PR pro to 'smear' sites, complaint alleges
Top Hollywood publicist Melissa Nathan faces allegations of playing a key role in running 'smear' sites for embattled celebrities amid the Justin Baldoni legal saga. In a deposition, Nathan denied she was the mastermind behind the now-defunct stephaniejonesleaks.com.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. [1] Intel, “Intel Tech Tour 2025 Panther Lake recap,” Doc. 866361, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/866361/ITT_2025_Panther_Lake_Recap1.pdf [2] Intel, “Core Ultra processors Series 3 datasheet, volume 1,” Doc. 872188-001, Jan. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/872188/872188-001.pdf [3] N. Horiguchi and E. Beyne, “Backside power delivery: How to power chips from the backside,” imec Reading Room, Nov. 25, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/how-power-chips-backside [4] W. Hafez et al., “Intel PowerVia technology: Backside power delivery for high density and high-performance computing,” in Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2, doi: 10.23919/vlsitechnologyandcir57934.2023.10185208. [5] K. Fischer et al., “Intel 18A platform technology featuring RibbonFET (GAA) and PowerVia for advanced high-performance computing,” in Proc. Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2025, pp. 1–3, doi: 10.23919/vlsitechnologyandcir65189.2025.11075006. [6] K.-F. Cheng, C.-L. Teng, H.-Y. Huang, and H.-C. Chen, “Metal oxide composite as etch stop layer,” U.S. Patent 12 176 247 B2, Dec. 24, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12176247B2/en [7] S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS J. Solid State Sci. Technol., vol. 4, no. 1, pp. N3029–N3047, 2015, doi: 10.1149/2.0051501jss. [8] A. V. Mule’, D. J. Towner, D. Seghete, C. R. Ryder, and A. A. Gonzalez, “Multi-layer etch stop layers for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20220102343 A1, Mar. 31, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20220102343A1/en [9] C.-C. Wang and J. H. Wang, “Interconnect structure with dielectric cap layer and etch stop layer stack,” U.S. Patent Appl. 20230253247 A1, Aug. 10, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20230253247A1/en [10] Y. J. Wu, K.-F. Cheng, C.-C. Lee, H.-K. Chang, and H.-Y. Huang, “Etch stop layer for interconnect structures,” U.S. Patent Appl. 20240332070 A1, Oct. 3, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240332070A1/en [11] M. G. Rainville, N. Shankar, K. S. Reddy, and D. M. Hausmann, “Deposition of aluminum oxide etch stop layers,” U.S. Patent Appl. 20180197770 A1, Jul. 12, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20180197770 [12] J. S. Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240112951A1/en [16] Applied Materials, “Applied Materials unveils chip wiring innovations for more energy-efficient computing,” Applied Materials Investor Relations, Jul. 8, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy [17] Samsung, “Samsung showcases AI-era vision and latest foundry technologies at SFF 2024,” Samsung Semiconductor, Jun. 13, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/ [18] C. W. Yeung et al., “Channel geometry impact and narrow sheet effect of stacked nanosheet,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2018, pp. 28.6.1–28.6.4, doi: 10.1109/iedm.2018.8614608. [19] S. Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
Top Stories: Apple Leaks, Siri AI Settlement, and More
The Apple rumor mill never stops, and this week MacRumors was able to break the news of details on several upcoming products.
Long-Time PlayStation Publisher Says "The Discussion May Change" Around Physical Media
Rumors recently appeared about Sony potentially delaying its digital-only future due to pressure from Microsoft's Xbox Helix, although they were promptly shot down by industry insiders and frequent leakers who said that Sony was dead-set on killing its physical media production—despite data...
Whistleblowers accuse Kennedy Center officials of halting planned repairs later used to justify closure
Whistleblowers are alleging that Kennedy Center officials halted plans earlier this year to repair leaks in the building, which the Trump administration has highlighted as its reason to close the storied arts institution.
Vacant South Philadelphia property pipe leak creates 8-inch deep "pond" in nearby business lot
Yearlong water leak at vacant South Philly property ruins nearby business lot
Health Wagon in Wise closes Friday due to possible gas leak in the area
The Health Wagon closed its facility on Patriot Drive in Wise on Friday due to a possible gas leak in the area.
Apple Code Confirms iPad 12 Specs: A19, 8GB RAM, N1, C1X Modem
The next low-cost iPad will be equipped with an A19 chip, C1X modem, N1 networking chip, and 8GB RAM, according to details found in Apple's code by MacRumors contributor Aaron Perris. We've heard some of these same specifications in prior rumors, so this is more of a confirmation than a new leak. The iPad 11 has an A16 chip, so the upgrade to the A19 in the 12th-generation iPad will bring a noticeable improvement in performance.
Leaks reveal a new Apple HomePod mini, iPad mini, and Apple TV 4K
Apple’s not done with hardware announcements this year.
iPad Mini With A20 Pro, New HomePod Mini Colors, and New Apple TV 4K All Just Leaked
MacRumors has just leaked the next iPad mini, HomePod mini, and Apple TV 4K models, all of which are likely to be announced this October. The most notable iPad mini details revealed in the leaks include an A20 Pro chip, a new speaker design, and a landscape front camera, while images have revealed that the next HomePod mini will be available in new colors like green and pink.
iPad Mini 8 Leaked: A20 Pro Chip, Landscape Camera, and More
Apple's next-generation iPad mini will feature the A20 Pro chip, a rearranged front-facing camera, and a new speaker system, leaked code reveals. The information originates from Apple's own code (spotted by MacRumors contributor Aaron Perris) and also shows clear product images of the new iPad mini. Although images of the device only show the front, leaving any design changes of the rear or side profile unknown, there are still visible changes.
New Apple TV 4K Leaked
MacRumors contributor Aaron Perris has uncovered an image file for an unreleased Apple TV 4K, suggesting that a new model will finally be released soon. The image is specifically for an "Apple TV 4K (4th generation)" model. Apple TV 4K (4th generation) image (on a gradient) The image reveals that the Apple TV will have the same external design as the current model, with all of its upgrades expected to be internal.
Pioneer of China NewCo model sued in US over trade secret misuse, double-dealing
A legal feud unfolding in New York is putting a spotlight on the work of a business development veteran who is credited for pioneering one of biopharma’s hottest dealmaking mechanism: the China “NewCo” model. In a lawsuit originally filed in New York state court and recently moved to federal court, China’s Lepu Medical Technology has alleged that biopharma business development consultant Su Zhang, who was hired to help shop its GLP-1 weight-loss candidates to Western partners, engaged in corporate double-dealing and trade secret leaks. According to the complaint, while acting as Lepu’s primary dealmaking liaison for a group of obesity and metabolic disease drug candidates, Zhang was secretly double-dipping as the acting chief business officer for a direct competitor, BrightGene Pharmaceutical. “She never adequately disclosed the role, never sought Lepu’s consent, and never proposed any safeguard,” Lepu alleged in its complaint, which was filed in July after Zhang’s consulting firm, CoDevCo, sought certain transaction-based success fees from its angry customer through an arbitration process in Singapore. Lepu, the parent company of Lepu Biopharma, has asked Zhang to pay back its $500,000 retainer and disgorge all benefits she received during the alleged breaches of fiduciary duty, plus other damages and relief. The company has also requested the court grant injunctions to protect Lepu’s trade secrets. The ill-fated partnership officially kicked off in December 2024, when Lepu tapped CoDevCo as its “exclusive business development mechanism” to identify collaborators for the company’s drug candidates. According to Lepu’s complaint, Zhang personally negotiated and signed the agreement as managing director for CoDevCo, which used her home address. Before the Lepu deal, Zhang made a name following a short stint as the global head of business development for Hengrui Pharmaceuticals. It was during her tenure that Hengrui signed a landmark deal granting exclusive rights for a portfolio of GLP-1 assets to Hercules, which was at that time newly established by a group of private equity and venture capital firms. In addition to the regular upfront and milestone payments, Hengrui also gained an equity stake in Hercules, which later became Kailera Therapeutics. The Hengrui-Hercules deal opened a new paradigm, where a Chinese biopharma company spins off certain early-stage assets to investors for further development through the creation of a new company abroad. The “NewCo” model quickly came into vogue as it allows Western investors to access high-potential assets originating from China at an early stage while giving the Chinese licensors an opportunity to reap long-term benefits through equity stakes in the new firms. The NewCo model proved its value when Kailera staged a record-breaking $625 million IPO on Nasdaq this April, merely two years into the Hengrui deal. Related Kailera CEO 'knew we were in a good spot' before obesity biotech's record-breaking $625M IPO On her LinkedIn page, Zhang described her work at Hengrui as “[b]uilding team and capability from the ground up,” forming NewCo and major pharma partnerships worth billions of dollars. Lepu clearly wanted that kind of track record to help boost its own cardiometabolic portfolio, which includes a range of assets for obesity, Type 2 diabetes, fatty liver disease and muscle preservation during weight loss treatment. “Lepu’s pipeline is very valuable, but only if Lepu could secure the right international partner to expand into the overseas market during the available commercial window,” the company argued in its complaint. The Chinese biotech said it had little knowledge of U.S. laws, customs or business practices in the business development field, and therefore “needed to rely entirely” on the expertise of Zhang and her team as the firm’s first engagement of a U.S.-based BD consultant. “Zhang’s dominating influence on the business development strategy is further evidenced by the fact that she personally controlled the business-development communications on behalf of Lepu with potential partners,” Lepu said in its complaint. After entering the deal, Zhang introduced Lepu to her four associates. According to Lepu’s version of events, all of them were allegedly employed at different time points to perform similar jobs at other Chinese companies that Lepu described as its competitors, while having access to Lepu’s confidential information. As such, Lepu described Zhang’s team as “a roster of individuals whose primary professional loyalty, by virtue of their concurrent full-time employment, ran to Lepu’s competitors.” As well as the specific examples set out in the case, a look at Lepu’s deals over the period suggests Zhang may have been involved in at least one transaction. During their partnership, Lepu, through its subsidiary Shanghai Minwei Biotechnology, also out-licensed its GLP-1/GIP/FGF21 agonist MWN105 to a NewCo called Sidera Bio in the fall of 2025. The deal included an upfront and near-term payment of $35 million, up to $1.01 billion in milestones, and a 9.99% stake in the Danish startup. It seems likely that Zhang facilitated the Minwei deal given that Lepu is on record as having used CoDevCo as its “exclusive business development mechanism.” The big shock for Lepu came in the form of a news article on June 25, 2025. The article, reporting on phase 2 data for BrightGene’s GLP-1/GIP receptor agonist BGM0504, identified Zhang as acting chief business officer of the Lepu rival. Blindsided by her association with BrightGene, Lepu confronted Zhang in July 2025. “Lepu was given assurances that there was nothing to be concerned about and told that Zhang would explain the matter to Lepu,” Lepu alleged in its complaint. “Zhang never did.” Lepu claimed that Zhang had the motive and opportunity to steer potential prospective partners toward BrightGene or other competitors. Later, in February 2026, one of Zhang’s associates joined BrightGene as the vice president for global business development, according to the complaint. Around the same time, Lepu sent written demand letters asking Zhang to account for her BrightGene role, identify what confidential data were shared with the rival firm, and provide any conflict-of-interest or firewall policies during the engagement. According to Lepu, neither CoDevCo nor Zhang answered the questions in their responses. Related Novo vs. KBP: How a $1.3B deal turned into a fraud accusation and an international legal fight In a motion to dismiss filed with the U.S. District Court in the Eastern District of New York on Sept. 4, Zhang’s legal team argued that Lepu’s agreement was signed with CoDevCo, and that an employee of the contractor does not owe fiduciary duties to the client. In its complaint, Lepu said: “That CoDevCo was the contracting entity does not insulate Zhang from personal liability for duties she personally undertook and personally breached.” Taking the argument one step further, the defending party argued that the consulting agreement “does not create a fiduciary relationship even between CoDevCo and Lepu; instead, it identifies CoDevCo as an independent contractor retained to market Lepu’s business to potential western partners.” Although CoDevCo was Lepu’s exclusive business-development contractor, there were no terms stipulating that the consulting firm should serve only Lepu, Zhang’s lawyer noted. As to Lepu’s claims that Zhang misappropriated trade secrets, the defendant argued that Lepu authorized the use of the information so Zhang’s team could perform their service per the agreement. In a rebuttal filed on Sept. 11, Lepu’s lawyer set out why they believe the Chinese biotech satisfied New York law’s misappropriation definition by alleging that the defendant used a trade secret “in breach of a duty or through improper means.” As an alternative to dismissing the suit, the defendant suggested the action should be stayed pending outcomes from the arbitration of a separate case in Singapore. While NewCo pioneer Zhang is defending her business arrangements, momentum behind the NewCo trend has continued unabated into 2026. Through August, Chinese biotech assets have spurred 15 NewCo deals this year, according to local trade publication PharmaDJ.
watchOS 27.2 includes hidden overhaul for Apple Watch screenshots
watchOS 27.2 is coming next month with new Apple Watch features, and leaker pdfu just found a big change in the works for screenshots too.
GTA 6 Datamine Reveals 'The Goodtime State
A mysterious new GTA 6 product has been leaked to be coming to the Rockstar Store called the Vice City Collection.
Sony Allegedly Surveyed Game Developers on its Disc-Killing Plan for 2028, Hinting at a Possible Reversal amid Fan Boycotts
According to leaker MLID, Sony has surveyed game developers on its disc-killing plan, suggesting they may consider a shocking reversal.
Here’s what Siri AI looks like on HomePod, per leak
Siri AI is likely coming to HomePod soon, and leaker pdfu today shared evidence of what the new Siri could look like on a HomePod.
Galaxy Tab S12+ and S12 Ultra specs leak - here's what will be upgraded
As we've seen before, both slates will be powered by the Dimensity 9500. The "plus" model is getting a new battery too, but it loses a camera.
PC version ControlResonant leaked a day before its official release.
A computer version of a sci-fi action film Control: Resonant from Finnish studio Remedy Entertainment has become freely available on...
Trump’s midterm woes deepen amid worsened economic backdrop: CNN poll
With President Donald Trump at record unpopularity, Republicans are facing an even bleaker midterm political landscape than they did eight years ago, a new CNN poll conducted by SSRS finds.
Seattle mayor tries to ‘right the ship’ in her first city budget
The city has faced consistently bleak revenue projections for years, and, as was the case last year, city spending continued to outpace revenue this year.
New 'Injustice 3' Leak Teases Highly Anticipated DC Characters
A new 'Injustice 3' leak seemingly confirms two beloved characters are on the way for the unannounced game.
Xbox Is Merging Its Two Forza Teams Into One Studio Focused On Forza Horizon And Fable
Playground Games and Turn 10 are merging
Beats 360 Deliver Customizability and a Revamped Over-Ear Headphone Design
After months of teases and leaks, Beats is officially announcing its new Beats 360 headphone today. Priced at $349.99, Beats 360 represents a rethinking of the Beats over-ear headphone design, with an emphasis on sound quality, comfort, and customizability. Subscribe to the MacRumors YouTube channel for more videos.
Another Injustice 3 leak reveals two characters in the rumoured DC fighting game - one that's expected and one that's a big surprise
Two new characters from the unannounced DC fighting game Injustice 3 have been revealed in a new leak.
Jürgen Klopp’s leaked email reveals message to former Germany internationals
Ahead of his debut as Germany head coach against the Netherlands on Thursday, Jürgen Klopp has reportedly sent an email to all former Germany internationals, asking for their support.“I would be ve...
Injustice 3 Leak Reportedly Reveals 2 Playable Characters
Injustice 3 will feature one character fans will expect and one who perhaps comes as a surprise, according to a fresh leak.
Injustice 3 Leak Reveals Two Fighters That Might Be In The Sequel
Supergirl is a predictable inclusion in the yet-to-be-confirmed game's roster, but the other name is intriguing...
BU students displaced after health officials condemn Brookline apartment building
A Brookline apartment building housing some Boston University students has been condemned after health inspectors discovered what they say is an active sewage leak and other health and safety violatio...
Report: Injustice 3 Leak Reveals New and Returning Characters for Roster
It’s an open secret by now that a new entry in the DC fighting series Injustice is in the works at NetherRealm Studios. A few months ago, we spotted the…
Dyson Won't Say What's Wrong With Its CameraJet Toothbrush
Despite admitting to a “component issue,” the company refuses to say what went wrong, how many units are affected in how many countries, and why it won't recall its $500 AI toothbrush.
iPhone 20 display leak teases massive upgrade over iPhone 18 Pro
Remember: We're pretty sure Apple is skipping iPhone 19.
iPhone 20 Pro Display Sizes Leak Ahead of 2027 Launch
Apple's 20th-anniversary iPhone lineup could feature slightly larger displays than the iPhone 18 Pro models, if a new leak shared on Weibo is accurate. Prolific Chinese leaker Digital Chat Station claims that early iPhone 20 Pro display specifications include a 6.41-inch screen with a resolution of approximately 2,686 × 1,236 pixels, while the iPhone 20 Pro Max is said to have a 6.96-inch display with a resolution of around 2,912 × 1,340 pixels.
Nike stock struggles: Kylian Mbappe's On move signals deeper problems
Losing the soccer superstar caps a long streak of issues, including weak China sales and bleak guidance.
Snapdragon 8 Elite Extreme Gen 6’s Engineering Prototype Video Surfaces Before Official Launch, Showing A New Packaging, Improved Benchmark Scores & More
An engineering prototype of Qualcomm's Snapdragon 8 Elite Extreme Gen 6 has leaked ahead of launch, revealing a new SoC packaging design, higher benchmark scores, and key hardware upgrades
Marvel Tōkon: Fighting Souls' Future Already Looks Bleak
Marvel Tōkon: Fighting Souls' has dipped into three-figure player counts on Steam, and it's less-than-impressive sales numbers are likely to blame
The Rams will continue running tons of 13 personnel sets
It was the one shining light in a bleak Week 1 performance
Fatal Fury: City of the Wolves datamine potentially leaks future DLC characters
Fans have been datamining the latest update for Fatal Fury: City of the Wolves, which may have leaked future characters with a potential Season 4 of DLC. We’ll be getting into the details below, so keep that in mind before proceeding. All information comes from heavenstardrive. First up, new win quote dialogue from Rick points to Xiangfei joining the game...
Olid's Man Utd take big step forward after 'intense week'
A week ago, the picture at Manchester United looked bleak. Then on Saturday, victory was snatched away from them at Arsenal. But have we seen signs of improvement from Eva Olid's side?
Official Galaxy Tab S12+ Keyboards Leak Online Ahead of Expected October Launch
Leaked renders from a retail listing reveal Samsung's official Book Cover Keyboard Slim and Pro Keyboard for the upcoming Galaxy Tab S12+.