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Assistant Professor Thomas Rose, an expert in archaeometallurgy, dies at 37
Assistant Professor Thomas Rose, an expert in ancient metallurgy, has died of injuries from a bicycle accident. He was 37.
Heavy Metal Sausage was forced to stop serving dinner. It may shutter the acclaimed South Philly restaurant
The South Philly butcher shop's acclaimed trattoria dinners are on pause after a health inspector found Heavy Metal Sausage Co.'s layout inadequate for indoor seating.
‘Metal Gear Solid: Master Collection Vol.2’ Is Worth It For ‘Ghost Babel’
Now that the second volume of the 'Metal Gear Solid: Master Collection' is finally here, the real star of the show is the Game Boy Color game, 'Ghost Babel'.
A new recipe unlocks “impossible” nanocrystals for LEDs, implants, and superconductors
Scientists have cracked a long-standing chemistry problem, creating nanocrystals from tough metal nitrides that were previously extremely difficult to produce at this scale. The breakthrough could turn familiar materials used in LEDs, implants, and superconductors into building blocks for flexible electronics, printable devices, and other technologies.
Status of The Lions Bay Resources Barbrook Business Rescue Plan
Victoria, South Africa--(Newsfile Corp. - August 28, 2026) - On 25th August 2026, Vantage Goldfields released a press statement, wherein they claimed that the "Lions Bay Resources Proposed Transaction to Acquire the Barbrook Mine Has Failed" and further that "Confirmation provided by the South African Mining Regulator means that Lions Bay Resources, owned by Metals One Plc (AIM: MET1) (LSE: MET1) and Lions Bay Capital Inc. (TSXV: LBI), cannot obtain mining regulatory approval, so that the...
The Hiroshima Atomic Blast Forged a Metal Never Seen Before on Earth
Discovery from tragedy.
Metal Gear Solid Fan Community Makes Unexpected Appearance In Master Collection Vol. 2 Executable
"The original DLC might only exist today because SaveMGO kept it available"
AI searched 100 million possibilities and found a cheaper way to 3D-print a NASA rocket alloy
Researchers used AI to search through more than 100 million possible settings for 3D-printing a high-performance NASA alloy. After only 40 experiments, the system identified six successful configurations, including one that worked at a record-low 500 watts. That could allow GRCop-42, currently difficult and expensive to print, to be made with much more widely available equipment.
Blood spatter, bats, beer: This metal bar’s ‘Science Time’ happy hour a hit on St. Claude Ave.
What do you get when you combine science, drink deals and goths? That’s Science Time, baby. Here’s an inside look.
Amiga-Inspired AROS Goes Bare Metal On Raspberry Pi
There’s no actual data, but if we had to guess the least-favourite Disney movie of former Amiga owners would have to be Frozen, because none of them will ever be able to “Let it Go̶…
Video: Metal Gear Solid 4 Side-By-Side Graphics Comparison (Switch 2, PS5, PS3)
Master Collection Vol. 2 launches next week
Video: Metal Gear Solid 4 Nintendo Switch 2 vs. PS5 vs. PS3 graphics comparison
New Metal Gear Solid 4 Nintendo Switch 2 vs. PS5 vs. PS3 graphics comparison video released as MGS: Master Collection Vol. 2 approaches.
Metal Gear Solid: Master Collection Vol. 2 updates MGS4 joke, even brings back original voice actor
Following hands-on verdicts of Metal Gear Solid: Master Collection Vol. 2, an interesting tidbit has come to light about a joke that’s been updated in Metal Gear Solid 4. In the original release, after reaching Shadow Moses Island, the game referenced changing the discs of the first Metal Gear Solid when you reach this same location. Otacon says: “Hold it,...
Metal Gear Solid: Master Collection Vol. 2 Is An Exciting Return To Metal Gear's Past
The new compilation of Metal Gear Solid games is a great time capsule of classic Solid Snake adventures.
Metal Gear Solid: Master Collection Vol. 2 review – 18 years later, MGS4 still feels like an event
We don't really get games this gloriously excessive anymore, while Peace Maker and Ghost Babel make it a deep-cut collection worth playing.
Scientists crushed diamond beyond Neptune-like pressures—and solved a 20-year mystery
Extreme experiments have revealed how diamond behaves at crushing pressures beyond those inside Neptune and Uranus, resolving a decades-old conflict between theory and observation. The results could help scientists boost fusion energy output while revealing more about the exotic diamond rain hidden inside ice giant planets.
Christian metal band sues Netflix over ‘KPop Demon Hunters’
Demon Hunter, a metal band formed in 2000, is suing Netflix over ‘KPop Demon Hunters’ for trademark infringement, false designation of origin, and unfair competition.
Ardagh considers sale of metal beverage can business
The company’s beverage can sales and global volumes were down 1% year over year in its most recent quarter.
Scientists Melted Diamond at Temperatures Hotter Than the Sun. It Behaved Very Strangely
Under crushing pressure, diamond stays diamond until it suddenly becomes a metallic carbon liquid.
‘He had magnetism’: Lula returns to site of political origins to launch fourth-term campaign
Brazil’s president was union chief who led metalworkers’ strikes of 1979-80 that paved the way for return of democracy
Best Pixel 11 cases: Pixelsnap-ready, metal, protective, customizable, deals, more
The Pixel 11, 11 Pro, 11 Pro XL, and 11 Pro Fold pre-order deals are still flying but many of our favorite case...
How Wonderskin Turned TikTok Fame Into a $200 Million Beauty Business
With $50 million in Series A funding and 1,500 new US retail doors through Sephora, the brand behind the ubiquitous metallic blue lip stain has turned virality into lasting growth.
Ardagh considers selling off metal packaging business after restructuring
Ardagh Holdings, which has a 76% stake in Ardagh Metal Packaging, disclosed Thursday it may take steps to facilitate a sale to a third-party buyer. AMP’s revenues totaled $5.5 billion last year.
MIT selected to lead new NSF materials research center
The National Science Foundation selected MIT to establish a Materials Research Science and Engineering Center to develop materials for medical imaging, sustainable metals production, and next-generation electronics. MRSEC will also launch outreach programs exploring the role of materials in society and the lessons learned from materials failures.
Republic Business Credit Partners with Family Office on $2.5MM Credit Facility
Republic Business Credit partnered with a family office to provide a $2.5 million receivables financing facility for its precision metal coating company. The
I Just Had My Mind Blown By A Car Museum In The Middle Of Nowhere Built By A Scrap-Metal Magnate
Having lived in Detroit, LA, and Bavaria, and having a brother who lives in Hong Kong, I’ve been lucky enough to see some of the greatest car museums/collections this world has to offer. This past weekend, while on vacation with my family in Iowa, I saw one that surprised me and that I feel compelled […]
Life On Earth Appeared Not Once But Twice, Both Times Evolving From A Common Genetic Code
For life to get started it may have depended on one of the rarest, and currently most expensive, metals on Earth.
Scientists discover a hidden switch inside silver nanocatalysts
Silver nanocatalysts have been found to switch where they perform their most important reactions depending on whether a solid oxide cell is making electricity or hydrogen. The discovery could enable smarter catalyst designs that boost clean power generation while making green hydrogen more energy-efficient.
How hospital monopolies are driving up the cost of your health care
More than a million times a year, a U.S. surgeon slices open a knee, strips out worn cartilage, caps the leg bones with metal and drops in a plastic spacer to allow the new joint to glide. But while these knee-replacement procedures have become standard, the prices charged have not.Subscribe to The Post Most newsletter for the most important and interesting stories from The Washington Post. At Catawba Valley Medical Center in Hickory, North Carolina, for example, the cost of the procedure under
What Is J-B Weld Used For And What Should It Not Be Used On?
J-B Weld is an epoxy for bonding wood, metal, and concrete, but it's not ideal for softer materials like some plastics, leather, vinyl, and flexible rubber.
Scientists Catch a Hidden Electronic State Forming Almost Instantly
Researchers observed a hidden state triggered by light forming within 30 femtoseconds. A pulse of light sent a metal-organic framework into a hidden electronic state in just 30 femtoseconds. By watching the transformation almost as it happened, researchers uncovered a fleeting intermediate stage that appears to guide the material into its new state. The work
Grants Boost New Waynesboro Businesses
Heading into Waynesboro on Route 250 past the Rockfish Gap entrance of Shenandoah National Park and the Blue Ridge Tunnel’s western portal, signs of an entrepreneurial wave are easy to spot. The Virginia Metalcrafters Marketplace, a cavernous industrial space where metalworkers forged iron and brass products for more than a century before sitting vacant for
Tough Tek Metals turns window safety into global business
The work of Lansing Housing Products to improve child safety after a toddler’s death in 2006 resulted in the Tough Tek window screen, a stainless steel woven screen set in
Google's AI told people Flock cameras were full of gold. They weren't.
The story starts with a meme: privacy advocates joking online that Flock's surveillance cameras are secretly loaded with valuable metals, worth cracking open for scrap. AI Overviews...
German factory orders rise faster than expected; Asian shares fall on tech pullback
Germany’s biggest arms maker Rheinmetall slashes outlook after cancelled government contract; crude oil prices hold below $80 a barrel
Freezing fire: UT San Antonio scientists discover breakthrough for green energy
A novel approach borrowed from metallurgy breaks down ceramics into powerful clean-energy building blocks.
Scientists just 3D printed one of the hardest metals on Earth
A new 3D printing technique can produce exceptionally hard tungsten carbide cobalt while using less of its expensive raw materials. By softening rather than fully melting the material, researchers created defect-free samples with industrial-grade hardness and opened the door to more efficient manufacturing.
If Not AOC, Then Who?
What do we do if Alexandria Ocasio-Cortez decides not to run for president in 2028? It makes sense that many leftists are currently focused on calling on her to take the plunge. But the absence of a Plan B, or even much discussion about one, is worrisome. The US Left can’t afford to sit out the 2028 Democratic primary. Doing so in 2024 was a disaster: our abstention self-marginalized anti-billionaire politics from the national conversation and thereby gave space for Harris to pivot to the “center” (i.e. the policy preferences of corporate donors, establishment hacks, and AIPAC). Abstaining again in 2028 would be especially counterproductive since democratic socialists now have so much wind in our sails after our big electoral wins in NYC and across the country. It’s time to deepen our momentum, organization, and profile — not to retreat to the margins during America’s single most important political battle. Even more urgently, keeping Trump’s heir out of the White House may depend on whether leftists and the party’s unprecedentedly disenchanted base can force the Democrats in 2028 to take meaningful steps towards a very angry electorate and away from the corporate-consultant blob that has helped get us into this mess. If AOC (or Abdul El-Sayed) decides to run, we should enthusiastically go all in — DSA, fighting unions, progressive organizations, anybody who wants to see a better country and world. But, as far as I can tell from the outside, there’s a real chance that she doesn’t run. And we can’t just wait and see where she lands before discussing alternatives, since AOC’s decision might not come for quite a while, giving us little time to scramble at the last minute for an alternative. So we should start working now on getting a Plan B into motion, and recruiting a good candidate for the role. Here’s one idea. A Worker Candidate — Healthcare Not Warfare 2028 Run a union worker Leftists don’t need to always run experienced, well-known socialist politicians for high-profile contests. Lula, the current president of Brazil, began his political career as a metalworker militant who ran for governor of São Paulo in 1982. Especially in an era of institutional distrust, it’s possible to lean hard into making a virtue out of a working-class comrade’s distance from traditional politics. Experience abroad shows this clearly. Rachel Kéké — an immigrant hotel housekeeper — ran as the candidate of the leftist La France Insoumise for the National Assembly in 2022, defeating a former minister in the Macron government. The Belgian Workers’ Party in 2024 won its first Flemish seat in the European Parliament by running Rudi Kennes, a three-decade veteran of the Opel Antwerp auto factory. And the South Korean left in 2024 elected auto factory militant Yoon Jong-oh to the National Assembly. If a tiny French Trotskyist organization could make such a big splash in 2002 and 2007 by running a well-spoken postal worker cadre for office — the LCR’s Olivier Besancenot received about 1.5 million first-round votes — it’s not far-fetched to expect that a much larger organization like DSA, together with a broader coalition of the willing, could run this playbook to much greater effect. This is especially the case now that almost everything DSA does immediately becomes a national news story. We don’t need someone famous. We just need a charismatic, well-vetted comrade who works in a relatable working-class occupation — e.g. a nurse, or a worker in auto or construction, or at Amazon. Ideally, they have a compelling personal story or have been part of a significant strike or organizing campaign, but even those criteria don’t necessarily have to be deal-breakers. The main lesson of the Graham Platner fiasco isn’t that we should never run outsiders for office (the momentum he generated proves the exact opposite), but that they need proper vetting and roots in democratic membership organizations like DSA or a union. In any case, there are plenty of ways to signal working-class authenticity without resorting to Platner’s or Fetterman’s performative macho white dude affect. Better to have someone of any gender or race who is actually working class, with firm socialist politics, who can speak from experience about the day-to-day realities of trying to make it in America. There are surely at least a dozen such worker leaders in our movement nationwide; we just need to sit down and convince one that their personal sacrifice for the greater good (i.e. running for president) will be worth it. If we don’t have a frontrunner with a clear path to victory like AOC (or El-Sayed, were he to win Michigan), it’s better to embrace someone whose decision to run in itself tells an important story about US politics: workers have been iced out of our political system and are now fighting hard to break back in. The novelty factor, in itself, would generate press. And it would help democratic socialists signal to the American public that our movement’s defining characteristic is that we represent workers vs. bosses, not that we’re “the furthest left” force in American politics — a framework that suggests we’re extremists and that helps our opponents isolate us from non-college-educated voters by highlighting extremely minoritarian (and misguided) stances included in DSA’s platform like prison abolition. We don’t get many opportunities to speak to tens of millions of Americans; we need to use these opportunities to broaden our appeal beyond those already in our orbit. Run to polarize the 2028 primary and general election around “Medicare for All” and “End All Aid to Israel” Why should democratic socialists use our scarce time and volunteer energy to run in a race we’re unlikely to win? Running in the 2028 primary will not only recruit us scores of members (imagine having a DSA member intervening in eleven nationally televised primary debates!), but — more importantly — it has the potential to be a decisive leap forward towards an America that finally starts meeting the needs of working people instead of HMO and AIPAC billionaire donors. Polarizing litmus tests are good, actually — as long as they’re fought for around popular demands in a thoughtful and strategic way. Democratic socialists have an opportunity and responsibility to make the 2028 primary about two of the most widely and deeply felt issues of our moment: domestically, America’s unaffordable, family-breaking private healthcare system; internationally, America’s bankrolling of the genocidal Israeli government. A candidacy relentlessly demanding Medicare for All and No Aid to Israel would pose a sharp question to the American public, the Democratic Party, and other 2028 contenders: Why can’t working-class Americans afford their healthcare bills at the same time that our government is spending at least $3.8 billion yearly to fund an Israeli regime eager to keep dragging us and the world into more forever wars? Our candidate can agitate around a clear message: I’m running to give voice to all those working-class Americans who are struggling to get by. No matter what state you live in, who you voted for in 2024, or your background, it’s just plain common sense that we should make healthcare more affordable instead of spending billions to enable the Israeli government’s crimes against humanity. Every American who agrees with me when I say ‘Medicare for All — Not a Dime for Israel’ should make their voice heard through our campaign. Racking up a high number of votes for this agenda is a crucial way to show the Democratic Party and the country as a whole that we can’t keep supporting a life-destroying status quo in our healthcare system and in the Middle East. If we want to defeat Trump’s handpicked crony this coming November, we need to speak to ordinary people’s frustrations with the status quo — we can’t keep running the same tired establishment playbook and expecting a different result. For those highly engaged voters (or skeptical media pundits) who raise concerns about wasting votes, the candidate can take the time to explain why this isn’t the case: It's true I'm a long shot. But Zohran showed anything can happen — and voting for me is a pragmatic decision, not a wasted vote. In a heavily divided primary with a large number of candidates and a very discredited establishment, my campaign and the democratic socialist movement I’m part of are positioned to be the balance of power if we can get a large enough number of voters to loudly demand Healthcare Not Warfare. Since there’s a high chance no candidate will get to 50% in the 2028 primaries, the Democrats could very well be heading towards a brokered convention, where a disciplined, principled current committed to breaking from corporate donors can play an outsized role in making sure whoever ends up with the nomination raises the banner of single-payer healthcare and cutting aid to Israel. How exactly could running this sort of primary campaign be translated into actual leverage? The candidate replies: I’m aiming to win the nomination, but if I don’t achieve that goal, my delegates and I will pledge our support in the primary only for a candidate who agrees in the general election to call for ending US aid to Israel and establishing Medicare for All at home. These are both winning planks for November against the Republicans, and the only reason I can see that other candidates haven’t yet raised these is that they’re still more scared of the donor class than they are of the people. That needs to change. If Democratic leaders want young people, workers, and those sick of the status quo to show up in big numbers this November, they need to meet us halfway. In this way, whether or not we win the nomination, democratic socialists could still play a decisive role in 2028. The approach outlined here is similar to what radical left parties periodically do in parliamentary democracies like Denmark or Sweden when they find themselves as a junior partner electorally: they dictate to center-left allies what their terms would be for enabling, from the outside, the formation of a new government. Running a Healthcare Not Warfare candidate will make it significantly more likely that the 2028 Democratic candidate stands with ordinary people instead of donors on these two pivotal planks — a shift that will, in turn, make it easier to achieve the existentially important task of defeating MAGA’s heir in November. Look at how much popular traction the Uncommitted movement got with a similar strategy in 2024 with so little on-the-ground organization — surely we can go much further with a working-class candidate, a much bigger DSA, and a Democratic Party base that has turned against Israel, billionaires, and the hacks in the party who prop them up. Objections and Responses There are quite a few objections to this proposal, many of which are very reasonable. Let me briefly address each here. Socialists shouldn’t waste their scarce time and resources on a candidate unlikely to win. This is a good rule in general, but there are important exceptions, and presidential elections are the main one. There’s no other political contest that gets anything like this level of attention and engagement in the US, so if you want to be a serious force in nationwide politics, you basically can’t afford not to have a candidate. Far from being an overall drain on our resources, running a dynamic 2028 campaign would likely result in a major net increase in members and capacity. In that spirit, the very pragmatic Milwaukee sewer socialists — who mostly ran to win at home in Wisconsin — supported Eugene Debs’s propagandistic presidential campaigns, which they correctly saw as a crucial means of recruiting to the Socialist Party. And now that the (post-1972) Democratic Party gives more weight to voters than party operatives in determining its presidential nomination, it’s become feasible to run as a socialist in primaries without risking a split in the vote against the Republicans in November. We should just support Ro Khanna, who also supports M4A and ending aid to Israel. I like Ro Khanna and would enthusiastically vote and canvass for him for president were he to get the nomination. But there’s a real chance that Khanna’s bid for office doesn’t catch on; he lacks the grassroots organizational apparatus of DSA, and, because he’s not really of the Left or labor (despite his current very good positions), he’s unlikely to generate the type of buy-in and enthusiasm that a DSA candidate would. Moreover, Khanna would be running as an individual, not as someone emerging from and building an organized movement — his campaign would not likely focus on building sustained power from below, nor would it likely polarize the 2028 primary around M4A and Israel aid. Also, and not inconsequentially, the poor electoral results for Tom Steyer and Saikat Chakrabarti this spring suggest that there’s perhaps not much of a popular appetite in the Democrats’ base to support multi-millionaire class traitors. Much better, then, to run a democratic socialist worker. If by Super Tuesday it’s clear that our campaign has captured the main left lane in the primary, Khanna should drop out and endorse us; conversely, if he’s managed to capture this lane, DSA could at that point transform its Healthcare Not Warfare campaign into an independent campaign to elect Ro Khanna focused on winning (and holding him accountable to) those two critical planks. An openness to consolidating an anti-corporate candidate by Super Tuesday is a necessary component of the strategy I’m proposing, because otherwise we risk splitting the primary votes (per DNC rules, you need at least 15% to get any delegates to convention). We should convince Shawn Fain or Sara Nelson to run for president instead. I agree it’d be great if either ran for president, but my impression is that there’s basically no chance that will happen in 2028, because both are firmly focused on their union leadership duties (and, in the case of Fain, beating back a federal witch-hunt). This plan could have DSA end up endorsing a non-socialist, non-DSAer for president. That’s against our principles. It’s a myth, and bad politics, that socialists can’t ever support candidates who aren’t members of their organization and/or who don’t call themselves socialists. Bernie, after all, was not a DSAer. And socialists abroad regularly make tactical decisions about if and when supporting a non-socialist candidate makes sense from the standpoint of promoting working-class interests, defending democracy, and building a socialist current in the process. If your “principles” prevent you and DSA from helping achieve the momentous stride forward of having a Democratic candidate in 2028 run on Medicare for All and ending aid to Israel, those “principles” are not very good. In fact, they actively undermine the causes they’re aiming to support. We shouldn’t confuse principles (working-class independence) with tactics (the best way to advance this in a given context). In my recent article in Catalyst on Milwaukee sewer socialism (I’ve uploaded the full text here), I have a section showing how similarly rigid rules about endorsements had to be eventually discarded in the old Socialist Party nationwide after WWI because they tended to lead socialists towards a sectarian abstention from broader anti-corporate electoral insurgencies beyond their party’s control. For what it’s worth, Lenin’s current under Tsarism frequently backed bourgeois candidates in the second round of elections and Lenin himself advocated that British Communists support Labour Party candidates; for his part, Kautsky in 1912 defended the German Social Democracy’s electoral pact with the Progressives in the runoffs. If our predecessors could be that tactically flexible in an era before the limits of their underlying strategic assumptions about intransigent class politics in capitalist democracies were made clear, then there’s no need to insist on being more tactically rigid today, after a century’s worth of accumulated experience. As long as you maintain your own political profile and organization while engaging in broader coalitional efforts, there’s zero inherent contradiction with the principle of political independence. More specifically: DSA and allied organizations should enthusiastically back Michigan’s Abdul El-Sayed if AOC declines to run and he throws his hat in the presidential ring. (I have no idea whether he’s even considering this path, but there’ll surely be chatter about it if he wins his Senate race this November.) Though he doesn’t call himself a socialist, El-Sayed is a principled Berniecrat, a consistent fighter for Palestine, and would have a clear path to victory. Using the “s” word is far less important than whether a campaign fights for the interests of working people at home and abroad — and whether actively participating in it can grow the organized working class and the Left. And the same holds true if a less anti-corporate candidate were, under pressure, to adopt our two Healthcare Not Warfare planks. Why focus only on M4A and ending US aid to Israel? There are so many other important issues to fight for! Obviously there are many pivotal issues beyond healthcare and Israel, and our candidate — and especially our organizations involved in the campaign — should be prepared to speak on all of these. But one of the crucial lessons of the Zohran campaign is that you have to relentlessly stay on message if you want to cut through the noise. CNN and Fox News will want to talk about DSA’s views on Venezuela and abolishing the police; we need to polarize the debate on the widely and deeply felt issues that are most favorable for growing the Left, isolating our opponents, and winning urgently needed changes. One recent poll found 63% of Americans support M4A, even after respondents were told it would raise taxes and eliminate most private insurance. Another found that 74% of Democrats opposed “providing additional economic and military support to Israel.” And focusing on two demands sets the campaign up to be able to leverage its mandate to make clear demands upon other candidates (which we can’t do if we run with a laundry list of demands). Talking about a Plan B is a distraction from the more urgent work of building a groundswell of calls on AOC to run. It’s good for DSAers, fightback unionists, and progressive organizations to try to convince AOC to run. This proposal is meant as an addendum to pushes to get AOC to run and to line DSA up for that eventuality, not as a substitute for those efforts. But I’m worried that, like in 2024, we might eventually find ourselves with no time to find a viable alternative unless we start now. DSA, with its abundant deliberative processes, moves slowly. The approach you’re suggesting seems risky. If a DSA candidate runs but doesn’t receive a lot of votes, it’ll undercut our current national momentum. This is a reasonable worry. All big initiatives always carry risks, and the path I’m advocating is certainly not free of these. That said, if a Healthcare Not Warfare campaign doesn’t catch on like we envisioned, it’s a pretty simple pivot in March 2028 to explain that in the future we really need our standard-bearers like AOC, or our growing bench of national electeds, to step up in presidential primaries. Moreover, it’s worth noting that the risk of my Plan B proposal is on the whole significantly less than the risk entailed by an AOC run. We should all back her if she runs, since she’d fire up the base, provide huge openings for organizing, have a real shot at defeating a Republican (especially given MAGA’s unpopularity), be a great standard-bearer for our issues, particularly M4A and ending aid to Israel, and be less willing than mainstream candidates to capitulate to any anti-democratic machinations from Trump and co. But it’s also true that AOC could lose, which would be a devastating setback to the country and the Left. Or she could win and find herself unable to pass much, if any, of her (and our) program, a demoralizing prospect. So if we’re willing to take these risks with AOC (and we should), it follows that we should be able to take lower-level risks if she doesn’t throw her hat in the ring. What’s Your Plan B? The US Left is facing its biggest opening for growth and influence since the 1930s. Initiatives that would have been impossible a few months ago are now potentially feasible. A President AOC is now easier to imagine, but if she ultimately assesses that the risks aren’t worth the potential reward in 2028, we can’t be left flat-footed. So even if you’re not convinced by the specifics of my Plan B, I hope you can at least agree that it’d be a disaster for us not to have one — and not to start getting a Plan B into motion. Hopefully other organizers and political currents will put forward their responses and alternative ideas ASAP. The stakes are too high to just wait and see. More As always, please share this article widely. This newsletter depends on all you lovely people to get the word out. Thank you! I uploaded the full text of my Catalyst article on Milwaukee sewer socialism here (it’s updated and 3x as long as the version published earlier on this substack). If you haven’t yet, please make sure to subscribe to Catalyst here; I read every issue front to back, highly recommend. 🌹🎵 Ivan Lins (arranged by Arthur Verocai) — “General da Banda” 🌹🎵
Nearly 23,000 pounds of Ukrop's baked spaghetti and chicken cobbler recalled over metal sliver concerns
A consumer complaint about metal found in a fully cooked product triggered the Ukrop's Homestyle Foods recall of baked spaghetti and chicken cobbler.
A look at new construction projects and property deals in Ascension Parish
Ascension Parish recently announced new construction projects, property transactions and upcoming business events, Ascension Business Report writes. The parish issued permits for two major projects, including a $3 million, 10,483-square-foot building at The Church International on La. 42 in Prairieville, with Living Solutions Construction as the contractor, and a $400,000, 11,840-square-foot pre-engineered mixed-use metal building […]
Sheet metal, Plainview dentist, data leak make Lubbock business news
Business Reporter Alana Edgin reviews recent Lubbock area businesses news and hints at upcoming articles in the Around the Hub column.
A tiny molecular basket unlocks a powerful new kind of chemistry
Rice University chemists have found a new way to make neodymium, a rare-earth metal, interact with oxygen. Using a specially designed molecular structure described as a “basket,” the team positioned the atoms so they could form a bond once thought unlikely. The breakthrough produced highly reactive compounds that could eventually give chemists alternatives to iron-based molecules used in biological reactions and chemical manufacturing.
NASA’s Psyche spacecraft aces Mars flyby capturing stunning timelapse video
NASA’s Psyche spacecraft aced its Mars flyby, using the planet’s gravity to speed toward its 2029 encounter with a metal-rich asteroid. The spacecraft tested its cameras, magnetometer, and particle-detecting instruments, capturing unusual views of Mars and measuring its magnetic environment. It also detected neutrons from the planet and spotted the tiny moons Phobos and Deimos.
Texas investigates major tampon, cosmetics manufacturers for alleged deceptive health claims
The Texas Attorney General's office has launched sweeping, industry-wide investigations into major manufacturers of feminine care and cosmetic products over concerns that companies may be misleading consumers about the presence of toxic chemicals and heavy metals.
Texas investigates major tampon, cosmetics manufacturers for alleged deceptive health claims
The Texas Attorney General's office has launched sweeping, industry-wide investigations into major manufacturers of feminine care and cosmetic products over concerns that companies may be misleading consumers about the presence of toxic chemicals and heavy metals.
New study reveals additional health risks from Great Salt Lake dust
New research shows two additional routes that toxic metals in dust from the Great Salt Lake could move into soils, plants, and human bodies.
Lead pollution poses health risk, says review sparked by FT investigation
Animals reared near ex-mining sites ‘can have high, potentially toxic concentrations of metals’, academics find
Lubbock business news includes best jerky, sheet metal, AI flyers
Business Reporter Alana Edgin reviews recent Lubbock area businesses news and hints at upcoming articles in the Around the Hub column.
When It Comes to Fusion, Materials Matter
Fusion at high temperatures powers the sun and, if harnessed, could provide a potential source of energy here on Earth. But controlling fusion reactions has other benefits. The process also generates subatomic particles called neutrons that are used in a range of applications spanning medicine, research, and national security. Now, scientists at the University of California, Davis (UC Davis), and the Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab) have found that the materials surrounding a fusion reaction can dramatically increase how often it occurs, particularly at low energies where fusion is rare. The study was published July 18 in Nature Communications. Their approach sets up a way to study and engineer nuclear reactions within solid materials, opening a new field of “materials-driven fusion.” Instead of designing materials just to survive the harsh conditions of fusion, researchers might be able to design materials that boost the reaction in specific conditions, similar to the way catalysts speed up chemical processes. “It gives you a new knob to turn that you didn’t have before,” said Arun Persaud, head of the Fusion Science & Ion Beam Technology group in Berkeley Lab’s Accelerator Technology & Applied Physics (ATAP) Division. “If we understand this effect better, it opens the door to engineering new materials that would affect the fusion rate under certain conditions. Someday future progress might enable more compact and efficient neutron generators, which have all kinds of applications, like cargo screening, planetary science, and medical therapy and imaging.” In the experiment, researchers used two different methods to pack deuterium, a heavy form of hydrogen atoms that is often used in fusion, into thin foils of palladium and titanium. They then fired a beam of deuterium ions at the foils at different energies and measured how often fusion happened. Then they compared the rates from the different materials and methods with the “bare” fusion reaction (not in a material). The team found that fusion rates depended on how the deuterium was loaded into the metal foils. The biggest effect was at the lowest energies, below 2.5 kiloelectronvolts (keV), where theory predicts fusion rates drop off sharply. Instead, researchers found a surprising plateau: Some samples showed elevated fusion rates roughly a quintillion times higher than bare fusion reactions. (A quintillion is a 1 followed by 18 zeroes.) Researchers are not exactly sure why that’s happening, though they have some ideas and ways to test them. The electrons and defects within the material might partially shield repulsive electrostatic forces between deuterium nuclei, making it easier for them to get close together and fuse. Tuning the electronic structure, defects, and composition of materials could help make nuclear reactions happen more readily. “It comes down to better understanding the mechanism so that we can try to enhance it,” said corresponding author Jeremy Munday, a professor at UC Davis. “We’ve seen that we can increase fusion rates, but what is the limit? Can we bring it to lower temperatures or energies? There’s obviously a lot of interest and excitement about fusion, so if there’s something we can learn about the physics at these lower energy scales, maybe there’s something we can translate to other areas of nuclear science.” The team plans to explore a wider range of materials and continue probing the unexpected fusion plateau at lower energies. Their work establishes a reproducible experimental platform to study how solid materials influence nuclear reactions, creating a new area of research that links fusion science with materials science and chemistry. “The work shows conclusively that the material environment where fusion occurs at low temperatures is an active participant rather than a passive container,” said Cameron Geddes, director of ATAP. “That adds a new dimension to fusion research.” This work was funded by the U.S. Department of Energy’s Advanced Research Projects Agency-Energy (ARPA-E). ### Lawrence Berkeley National Laboratory (Berkeley Lab) is committed to groundbreaking research focused on discovery science and solutions for abundant and reliable energy supplies. The lab’s expertise spans materials, chemistry, physics, biology, earth and environmental science, mathematics, and computing. Researchers from around the world rely on the lab’s world-class scientific facilities for their own pioneering research. Founded in 1931 on the belief that the biggest problems are best addressed by teams, Berkeley Lab and its scientists have been recognized with 17 Nobel Prizes. Berkeley Lab is a multiprogram national laboratory managed by the University of California for the U.S. Department of Energy’s Office of Science. DOE’s Office of Science is the single largest supporter of basic research in the physical sciences in the United States, and is working to address some of the most pressing challenges of our time. For more information, please visit energy.gov/science.
Metal Gear Solid: Master Collection Vol. 2 reveals Nintendo Switch 2 and Switch frame rate, resolution
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Scientists have found an ancient sea worm with jaws made from a mysterious 'bio-metal' never encountered before, a discovery that could rewrite what we know about nature
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William Shatner — yes, “that” William Shatner — to debut his heavy metal band The *uckers
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Entertainment Business Grad José Aparicio Marquez Helps Bring the World's Biggest Artists to Mexico
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AARP reporter Stacey Colino interviewed Milam Brantley, MD, Associate Professor of Ophthalmology and Visual Sciences, in 2020 for a story about whether eating carrots can improve vision. Sacramento Bee reporter Samantha Agate has now used Brantley’s comments in an AI-curated story created by content specialists on the same topic that has been picked up by MSN and others. Prevention magazine interviewed Heidi Silver, RD, PhD, Founding Director of the Vanderbilt Diet, Body Composition, and Human Metabolism Core, for a story about the importance of fiber and how people can get more of it in their diet. William Schaffner, MD, Professor of Preventive Medicine, was quoted by several news outlets about public health issues, including: Women’s Health (tick bites and alpha-gal syndrome); The Washington Post (tetanus); and Healthline (why mosquitoes prefer to bite some people and leave others alone). A visit to Monroe Carell Jr. Children’s Hospital at Vanderbilt by some Banana Ball baseball players was covered by The Tennessean and WZTV Fox 17 News, and The Tennessean’s story was also picked up by Yahoo! Sports. Clarksville Now published a story written by the Montgomery County Economic Development Team, whointerviewed Bradley Stancombe, MD, professor of Clinical Pediatrics, Vanderbilt Neonatology, about the new energy of Vanderbilt Clarksville Hospital and how the facility is recruiting physicians. Healio Allergy/Asthma group editorial director Richard Gawel interviewed Mark Rolfsen, MD, Clinical Fellow in the Division of Allergy, Pulmonary and Critical Care Medicine, for a story about his presentation at the American Thoracic Society meeting on metal health outcomes following ICU discharge. Nashville Scene reporter Hannah Herner interviewed James Crowe, MD, Director of the Vanderbilt Center for Antibody Therapeutics, for a story about his efforts to prepare for the next pandemic by isolating antibodies that can neutralize dangerous viruses. Medscape reporter Kathleen Doheny interviewed Neesha Choma, Associate Chief of Staff of Vanderbilt University Hospital, for a story about how hospitals can reduce readmissions.
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Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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