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'iPhone Ultra' Screen Protectors Reveal Asymmetric Corners
The leaker known as "Ice Universe" today shared images and a hands on video of screen protectors for Apple's rumored "iPhone Ultra," and the leak appears to confirm two of the most discussed details about the foldable's front design. The leaked accessory has square corners on the side that would sit next to the hinge, and rounded corners on the opposite edge.
Gates Foundation gives $540 million to UW health institute, the largest gift in university history
The Gates Foundation is giving $540.2 million over 10 years to the University of Washington's Institute for Health Metrics and Evaluation, the largest charitable gift in UW history. The grant will expand the institute's Global Burden of Disease study and comes as global health funding falls sharply.
Gates Foundation to give historic $540 million to UW health institute
The Gates Foundation is donating over half a billion dollars to UW's Institute of Health Metrics and Evaluation, whose research informs policies around the world.
A Monday with Brad Pitt
The 62-year-old has lived a singular life. He resides in the top 1 percent of the top 1 percent of all movie stars, not only today but ever, as measured by any metric you like, including intrigue. What does he have to say about all of it?
60,000-year-old ostrich eggshell engravings reveal a surprisingly sophisticated human mind
More than 60,000 years ago, humans in southern Africa were engraving ostrich eggshells with intricate geometric patterns that appear far more organized than previously realized. Researchers found recurring grids, parallel lines, right angles, and repeated shapes, suggesting the designs followed deliberate rules rather than being improvised. The engravers may even have planned entire patterns in their minds before carving them.
Vikings QB Race Heating Up With One Name Pulling Away
The Minnesota Vikings quarterback battle has been one of the biggest stories for training camp to this point. Friday gave another chance for the quarterbacks to showcase their skills. J.J. McCarthy had the better day on Friday according to statistics, but SKOR’s Judd Zulgad pointed to one metric that worked in Murray’s favor.McCarthy had a […] The post Vikings QB Race Heating Up With One Name Pulling Away appeared first on HEAVY.
PENN Entertainment (PENN) Reports Q2 Earnings: What Key Metrics Have to Say
The headline numbers for PENN Entertainment (PENN) give insight into how the company performed in the quarter ended June 2026, but it may be worthwhile to compare some of its key metrics to Wall Street estimates and the year-ago actuals.
Digital Science Brings Real-World Research Impact Data Into AI Workflows with New Altmetric MCP
Digital Science has announced the launch of its Altmetric MCP, a new Model Context Protocol server that connects AI agents to Altmetric’s research attention tracking data.
Digital Science brings real-world research impact data into AI workflows with new Altmetric MCP
Digital Science has announced the launch of its Altmetric MCP, a new Model Context Protocol server that connects AI agents to Altmetric’s research attention tracking data.
Digital Science launches Altmetric MCP
Launch is intended to help organisations move beyond traditional citation-based measures of research impact
Texas Shows Strengths and Gaps in Multi-Metric Business Rankings
We are accustomed to Texas topping virtually every ranking relating to the economy—most major corporate locations and expansions, top CEO perceptions, highest investment, and many others.
Chartbook 464 The"China squeeze" - the politics of development counterfactuals.
There are three types of China shock discourse. Each has a distinct temporal register. China shock 1.0 was a phrase coined by US academics in the 2010s to retrospectively summarize the impact on particular US labour markets, which they identified through painstaking empirical investigation. China shock 2.0 on everyone’s lips in Europe in the mid 2020s is an alarm raised by trans-Atlantic policy thinkers warning of a coming disaster which they project onto Europe’s ailing car industry. The third type of China shock discourse - commonly known as the “China squeeze” launched most recently by Indian economists Shoumitro Chatterjee and Arvind Subramanian in the pages of Foreign Affairs - mobilizes a different, more speculative temporal register: the counterfactual realm of alternate history. The China squeeze argument asks not what has happened, or what is going to happen, but what might have been. Specifically, what options for economic development might have been open to Global South economies like India or the economies of sub-Saharan Africa, had it not been for China’s spectacular industrialization since the late 1990s and the persistent competitiveness of China’s manufacture in low-skilled segments. Chatterjee and Subramanian’s argument is that whilst China has built a powerful position in electrical machinery and other high-skill manufacturing, which is now delivering China Shock 2.0, it also continues to run a trade surplus in low-skill, labour-intensive manufacturing. This surplus is large and has remained largely unchanged in fifteen years. Indeed, in the 2010s, in trade with low-income countries, China’s surplus rapidly increased. On their reading, this squeezes low-income producers in low-skill sectors in which they “should” be able to compete. Source: “China’s Mercantilist Squeeze on Developing Countries” Shoumitro Chatterjee and Arvind Subramanian. Peterson Institute for International Economics 26-7 May 2026 Chatterjee and Subramanian’s wording is telling: (emphasis mine) The canonical trajectory of economic development in the post-World War II period is for countries to transition from agriculture to manufacturing, first in low-skilled manufacturing and then later on to high-skill manufacturing (Herrendorf, Rogerson, and Valentinyi 2013). At the global level, this implies that high-income countries (HICs) that once specialized in low-skilled activities cede manufacturing export space to poorer countries that come along to occupy that space. In 1965, advanced economies accounted for about 60 percent of global value-added exports in four key low-skilled manufacturing sectors, i.e., apparel, leather, textiles, and footwear. Over time this share declined and began to be occupied first by the East Asian tigers and, beginning in the late 1990s, by China. Today China accounts for about 50 percent of the global market. The question is whether China, with its rising prosperity, is continuing to behave like its richer counterparts and ceding export space to poorer followers or to behave unlike them and continuing to occupy space. In terms of the conceptual maneuvers it performs, of the three China shock discourses, the “China squeeze” argument is by far the most ambitious. After all, it bases its critique of China on a counterfactual imagining of the world. Like any counterfactual argument, to construct this alternative reality it must rely on a heuristic model. To make their argument Chatterjee and Subramanian mobilize two key claims. The first reference point is the actual history of rich-country industrialization, what they refer to as the “canonical path”. The idea is that countries transition from agriculture to light industry and low-skilled manufacturing and from there up the value chain. To make this useful as a standard of comparison and a means to construct a normative standard, they adjust sectoral export shares for two factors: 1. the underlying level of economic development of the exporting country, as measured by national income and 2. the degree to which the sector in question is internationalized. The idea being that for a high income country to have a high export share in low-skill sectors is anomalous and even more so if that particular product is highly internationalized and thus suitable for being “conceded” to lower-income competitors. Where should this process end? Here Chatterjee and Subramanian introduce their second benchmark. Their normative idea of a global development path is one in which, in due course, low-skill manufacturing exports are distributed in proportion to a country’s share in the global labour force. They imagine, in other words, a world of proportional, polycentric global development without much national specialization in low-skill manufacturing. A useful benchmark is that, in labor-intensive manufacturing sectors, a country’s share of world exports should be broadly commensurate with its share of the world’s low-skilled labor endowment. … In the Heckscher-Ohlin model, this would be true if value added per worker and export propensities, i.e., fraction of output that is exported, are the same across countries. It is this pleasant liberal vista of orderly global development, progressing towards a general distribution of low-skilled manufacturing against which they judge reality and conclude that the low-income countries are suffering a “China squeeze”. China is not exiting low-skill sectors fast enough Allowing for its gdp level and the degree of globalization, China’s share of low-skill manufacturing exports is far higher than it “should” be. Relative to population, its low-skill share of exports is far too high. That in turn yields the conclusion that huge numbers of jobs - the authors suggest tens of millions - are being hoarded by China. For the four sectors captured in figure 4, this excess in value-added exports is $110 billion in 2022. For all low-skilled sectors overall captured in appendix figure D.1, excess value-added exports amount to $365 billion. The crowding out of LMIC exports by China is therefore substantial. Both these claims have in common that they are strong structuralisms. The first is that development paths ought to resemble each other. The second is that broadly speaking as far as low-skilled manufacturing is concerned, all countries are alike. If the world currently diverges from the distribution of trade implied by these assumptions, if China is not following the advanced economy path and has huge exports, this must be the result of “policy”, which the authors then put in question as illegitimate or unfair. Thus the naturalistic construction of a canonical path leading to a “level” distribution of low-skilled manufacturing reveals itself to be a polemical tool. From the point of view of China shock polemics, this discourse is no doubt welcome. But as an account of economic history, it must surely be regarded as nothing short of bamboozling. Development paths do not follow a regular, natural sequence. As David Fishman put it aptly, “development is not a queue”. They are always and everywhere, through and through political. Development is not so much a process, as a project. Each such project is more or less well adjusted to its context. As Gerschenkron taught uneven and combined development implies differentiation rather than simple imitation on a single parth. It may be true that Europe and the US exited relatively early from low-skill work. But clearly technology has changed. As C&S themselves point out, China no longer enjoys a low wage environment. Do they really believe that such huge differences can be accounted for either by industrial policy, which as they admit does not operate powerfully in low-skill sectors, or by exchange rate manipulation? What is overwhelmingly dominant in explaining the persistence of “low-skill” manufacturing in China are surely the network effects of complex supply chains. Indeed the label of “low-skill” may miss the point. The degree of globalization which Chatterjee and Subramanian decide to conjure away in their model of the development path - to allow for the fact that Europe and American textiles exporters did not enjoy just-in-time logistics in the 1950s - obscures the point that the networks through which Chinese factories supply the world are themselves key parts of the low-skill industrialization project. China isn’t knocking out 1970s style “cheap”. It has redefined the entire product cycle. C&S’s casual reference to “T-shirts” is telling. In today’s “fast fashion”, there is weight on both terms. Fashion and fast. China’s success in delivering on both at unprecedentedly high speed and at unprecedentedly low cost, isn’t a low-skill operation at all. If we see development trajectories not as the serial repetition of the same, but as distinctive, crafted projects that cumulate in complex agglomerations of skill, technology and labor, then this explains why the assumption that low-skilled manufacturing should follow the distribution of population flies in the face of all experience. As countless cases attest, low-wage, low-income developed economies are not by themselves the makings of a competitive production base. As Leon Liao puts it quite fairly: “International trade has never been allocated according to population. A country’s population gives it no natural claim to an equivalent share of global exports." And the remarkable fact is that Subramanian alone and with co-authors has long been making this point, not to pillory China, as is the case of the tendentious _Foreign Affair_s and Peterson pieces, but to highlight the great counterpart to China’s industrial success, namely India’s relative failure. The much-quoted Foreign Affairs piece showed low-skill export shares only for China, not for India. If you put both countries in the picture as Chaterjee and Subramanian have done on other occasions, the picture looks like this. China is far above the line, but India, almost as large in terms of population, is no less anomalous, just in the opposite direction. As far as global populations are concerned, and the imagining of tens of millions of “squeezed” jobs, it is this Sino-Indian pair that account for a huge share of the action. What this graph reveals is not China’s cheating, but India’s “greatest development failure”, at least this is the argument made Arvind Subramanian, this time in co-authorship with Devesh Kapur, in their major book, A Sixth of Humanity. Independent India’s Development Odyssey which appeared with Oxford University Press earlier this year. In this highly critical work on India’s development, China is repeatedly evoked, not to criticize but as a benchmark against which to illuminate what India’s political economy has not delivered i.e. large-scale formal employment for hundreds of millions of citizens. Kapur and Subramanian leave no doubt, if you want to understand why China, not India was the main driver of manufacturing globalization from the 1980s, don’t look to slots opening up in the division of labour thanks to the liberal mindedness of advanced economies, look to the contrasting political economy of the Maoist PRC and India’s post-independence political economy. As Kapur and Subramian note: The great divergence between China and India did not begin in 1978 with the Deng reforms—it was well underway by then. In one of the great ironies of modern history, the conditions created by Maoism turned out to be a great launching pad for industrial globalization. As the comparison of India and China in 1980 makes clear, to imagine manufacturing would be equally distributed when populations are so differently endowed in terms of educational and nutritional is fanciful. Here is the data from Kapur and Subramanian, data which I explored back at the very beginning of Chartbook. As Kapur and Subramanian insist, the striking fact is that even as India’s growth accelerated from the 1980s, structural change has not. Formal employment in India lags woefully behind. Why? As Kapur and Subramanian note, the path-dependent impact of India’s poor early start was devastating. The list of factors they mention is long and weighty: We argue for a new five-fold explanation applicable at different stages of Indian history: in the initial stages, the legacy of two key pre-1980s policies, the neglect of agriculture and the strangling of the domestic private sector, were critical. The failure of broad-based agricultural growth militated against rural industrialization, which would have been devoted to satisfying local needs that would have necessarily been labour intensive. Then, when the boom came after 1980, the thicket of regulation and broader labour protections that were legislated prematurely in a nascent democracy, underpinned by a deep ideological aversion to private capital in general and big capital specifically, became a barrier to attaining the size that would be necessary to compete globally. Similarly, the reforms after 1991, while wide-ranging, did not quite encompass non-tradeable inputs critical to manufacturing, namely, land, logistics infrastructure and power. A combination of low investment (logistics infrastructure), regulation (land) and the continued monopoly supply by state governments (power), combined with residual socialism, kept costs at 75–100 per cent above efficient supply. These factors were compounded on the supply side by the government, which dominated the formal labour market and established exorbitantly high wages at the lower end of the skill spectrum. This made their employment in the labour-intensive sector by the private sector less attractive. Finally, when the services sector and its exports boomed, wages soared even further via a Dutch Disease effect: one successful tradeable sector killed and cannibalized another less-skilled tradable sector, namely, manufacturing. Thus, scarcity-inducing policies of the planning era, precocious democracy and a Gandhian aversion to size; inefficient, monopolistic supply of critical non-tradable inputs; the behemoth of government; and super-successful skill-intensive services successively undermined India’s unskilled labour employment opportunities. The employment failure seems to have been over-determined. … Less quantifiable but no less important are some of the sociological factors that have undermined manufacturing and factory jobs. Take the impact of the success of the IT sector—located in urban areas with better working conditions, such as air-conditioned offices, good schools for children and attractive entertainment options. It became a more attractive place for engineering and management graduates to flock to. … Consider manufacturing and female employment. Indian society makes it difficult for women to work, reflected in India’s unusually low female labour force participation (elaborated in Chapter XIII). Indian society, in particular the routine harassment of women in public spaces, makes it even more difficult for them to travel long distances to take up work.37 Combined with onerous regulations on creating hostels and dormitories for women—which, in turn, prevents multiple shifts of operation—factories need to be located in areas with a large female labour pool. While firms can take apparel plants to female labour or bring them to the plants by building large-scale dormitories, this raises costs. If there was a case for subsidies to encourage labour-intensive manufacturing, housing subsidies to build dormitories for women workers would be a good place to start. All of this meant, that when opportunities did open up, in part thanks to adjustments in China, India was in no position to take advantage. Here is the account of the 2020s from Kapur and Subramanian. It stands in dizzying contrast to the one-sided, “China squeeze” argument delivered in the Peterson and Foreign Affairs pieces: In 2022, for example, India’s share of global exports in clothing (the canonical labour-intensive sector) was 3.1 per cent compared to 32 per cent for China. This is extremely disappointing because China started vacating export space in this sector after the Global Financial Crisis as its wages started rising; it then vacated further space in the aftermath of geopolitical developments that led investors to seek alternative investment locations. Between its peak and today, China lost about 7.5 percentage points of global export share (worth about $43 billion in 2022); over this period, India’s export share remained stagnant at 3 per cent, while that of Vietnam and Bangladesh rose by 3.5 to 4 percentage points. China’s loss did not translate into any gain for India in terms of low-skill exports and employment. Put differently, when the conditions for dynamism and prosperity were established after 1991, and even more tantalizingly when the global export opportunities opened up, it was as if India was a high-wage economy and only skilled labour could benefit from the dynamism. It had converted its physically abundant unskilled workforce into an economically expensive resource, penalizing its use. It is not my mission here to argue for or against Kapur and Subramanian’s interpretation of India’s development trajectory. The point in this context is simply that the “China squeeze” such as it is can only be understood, in relation to the heavy burden of domestic constraints that Kapur and Subramanian so unsparingly enumerate. I am concentrating here on India because it is the great counterpart to China and the unspoken reference point of the “China squeeze” discourse. But the point is more general. Can anyone with a straight face suggest that the main problems afflicting the development of South Africa or Nigeria, the great centers of mass underemployment in sub-saharan Africa, are cheap competition from China driven by Beijing’s industrial policy and an undervalued RMB? Likewise, is the main problem of the American working-class the threat of Chinese competition or the manifest crisis of social reproduction in the United States itself? The point here, as in the discourse around China shock 2.0 in Europe, is to insist that we should not normalize the world and pathologize China, without actually investigating what is going on in America’s industrial wastelands, the German car industry, or India’s lopsided labour market. One-sided pathologization should be understood for what it is, a polemical gesture. Concepts like China shock and China squeeze are, what Reinhart Koselleck, following Carl Schmitt, would have described as “asymmetrische Kampfbegriffe”, or “asymmetrical counter-concepts” or “asymmetrical combat concepts”. If the function of arguments like the “China squeeze” is to alert elites in the rest of the world of the need to rejuvenate and energize their development projects, so be it. But let us see the resulting discourses as the mobilizing interventions that they are. Interestingly, a significant slice of China’s public sphere - the so-called industrial party - have been obsessed for the last twenty years with precisely these questions of counterfactual economic history. Since the mid 2000s, a massive online discourse developed around an alternative history in which Chinese techno-patriots were asked to imagine how they would proceed if they had the possibility of traveling back in time to transport modern technology into the Ming dynasty (1368-1644) thus averting the “great divergence” of the 18th and 19th centuries. It is a fantasy of course, but also a goad. The point was not directed at Westerners. The alternate history is dramatically nationalist, but few n the West had even heard of it until recently. The adherents of the industrial party are not liberal moralists. They don’t project natural ladders of international development and ask why others don’t cede space. They take the Realpolitik of global economic development for granted. Their pointe was directed against fellow Chinese. The rallying cry of the alternative narrative was this: Now that we are beginning to gain steam and push forward on our national development path, now that we are breaking out of the inferior position assigned to us even in the early years following WTO accession, do not lose yourself in humanistic imaginings about better futures. In the spirit of Deng, they called on China to embrace the hard truth of development. Perhaps one might of the Industrial Party as a cultural trend born out of desire for symbolic revenge against those who had inflicted the century of humiliation. In terms of the various temporalities of the “China shock” - retrospective, prospective and counterfactual - one might think of the Industrial Policy discourse as truly speculative, conjuring up the China shock that never was. Or perhaps one might better think of it as imagining a world in which a powerful China was no shock at all, but simply a defining fact of modern history. I love putting out Chartbook. I am particularly pleased that it goes out for free to thousands of subscribers around the world. But, writing this newsletter takes a lot of work. If you are enjoying it and would like to support the project, sign up for one of the subscription options here. It is the equivalent of a fancy cup of coffee per month! Subscribe
NEC Transfers Overseas Network Equipment Resale Business and Other IT Businesses
NEC Corporation (NEC; TSE: 6701) today announced that it has entered into an agreement with a consortium led by Assist Group S.r.l. with business leaders who have extensive experience across a wide range of industries to transfer its overseas network equipment resale business—which involves building systems for overseas telecommunications operators and enterprises using network equipment from partner companies—as well as its IT services business for governments and local authorities in certain countries, which includes system development for biometric authentication and smart cities.
Amid trend in health optimization, Berkeley scientists focus on brain optimization
What’s a healthy body without a healthy brain? Neurologists, neuroscientists and psychologists unite to find metrics for brain health and effective training to improve it.
Huge blankets of seaweed are smothering coastlines from the Caribbean to Mexico
Some 27 million metric tons of self-sustaining sargassum have been recorded in the Atlantic, Caribbean and Gulf of Mexico in July, according to a report released Friday by the University of South Florida’s Optical Oceanography Lab.
California school dashboard adds science as a full metric
Short of dropping a dead weight copy of the state Education Code on your foot, a State Board of Education agenda item on the California School Dashboard normally wouldn’t evoke
casio turns its ring watch into smart wearable with health tracking and notifications
the CRW-H001 combines digital timekeeping with biometric sensors and smartphone connectivity in a finger-sized device available exclusively in china.
Compared to Estimates, Sphere Entertainment (SPHR) Q2 Earnings: A Look at Key Metrics
Although the revenue and EPS for Sphere Entertainment (SPHR) give a sense of how its business performed in the quarter ended June 2026, it might be worth considering how some key metrics compare with Wall Street estimates and the year-ago numbers.
Zacks.com featured highlights include PENN Entertainment, Carriage Services, General Motors and AMN Healthcare Services
PENN Entertainment, Carriage Services, General Motors and AMN Healthcare are highlighted as value stocks with strong cash flow metrics for the second half of 2026.
National Survey on Drug Use and Health shows promising trends for youth mental health and drug use
A key U.S. government report on mental health, substance use and addiction shows continued improvements in several metrics, especially among young people
Federal survey shows promising trends for youth mental health and drug use
A key U.S. government report on mental health, substance use and addiction shows continued improvements in several metrics, especially among young people.
Federal survey shows promising trends for youth mental health and drug use
A key U.S. government report on mental health, substance use and addiction shows continued improvements in several metrics, especially among young people
Federal survey shows promising trends for youth mental health and drug use
A key U.S. government report on mental health, substance use and addiction shows continued improvements in several metrics, especially among young people
New Allegheny County Jail devices track incarcerated peoples’ health, with an eye on early intervention
Medically vulnerable groups going through the intake area of the Allegheny County Jail will now have the chance to wear a biometric monitoring device that...
Breaking Down the Hard Business of Measuring Security Culture
By understanding the types of data available and how they can be meaningful, security professionals can develop metrics that are useful in describing and enhancing security culture.
LSU's National Championship Odds May Depend on One Overlooked Metric
The LSU Tigers have their eyes set on the ultimate goal this season.
Red Sox trust in the breakout in trade for Nats’ Curtis Mead: MLB trade grades
Curtis Mead was traded for Connelly Early, who has shown flashes of No. 2-3 starter stuff, but his underlying metrics look more like a 4-5.
Monkeys Understand Shapes in Almost the Same Way as Humans
Our geometric intuition, long considered something that sets us apart, seems to be shared with other primates.
Samsung Debuts AI-Powered Health Assistant, Joining Packed Market
Samsung Electronics Co. is rolling out a new AI-powered assistant that acts as a virtual health companion, joining a growing number of tech companies using chatbots to deliver personalized wellness insights to its users.Samsung Health Assistant pulls in data from the user’s Galaxy smartphone, smartwatch or smart ring, the company said Tuesday. The firm also announced a series of other features coming to its health platform, particularly around heart metrics.
AMC Entertainment (AMC) Stock Trades Up, Here Is Why
Shares of theater company AMC Entertainment (NYSE:AMC) jumped 17.3% in the morning session after the company reported impressive Q2 2026 earnings results with revenue and Adjusted EBITDA crushing expectations.The cinema chain delivered a blowout second quarter, posting total revenues of $1.60 billion—representing 14.2% year-over-year growth and easily surpassing analyst estimates of $1.47 billion. Profitability metrics were particularly strong, with Adjusted EBITDA soaring to $321.4 million comp
AMC Entertainment (AMC) Q2 Earnings: Taking a Look at Key Metrics Versus Estimates
The headline numbers for AMC Entertainment (AMC) give insight into how the company performed in the quarter ended June 2026, but it may be worthwhile to compare some of its key metrics to Wall Street estimates and the year-ago actuals.
Snapdragon 8 Gen 5 phones compared: Which one is right for you?
Motorola recently introduced the Motorola Edge 70 Max, a phone powered by the Snapdragon 8 Gen 5. In terms of compute metrics, this system-on-chip represents the absolute pinnacle of high-end value engineering, serving as the next best sub-flagship silicon right after the ultra-premium Snapdragon 8 Elite Gen 5. It delivers sustained frame rates and high […]
AMC (AMC) Stock Trades At A Discount On Its 99% Five Year Slump
AMC Entertainment Holdings stock now trades around US$1.94 after a long slide in which shareholders have seen the value of their investment fall about 99% over five years, while some valuation checks still suggest the shares are not clearly expensive on current metrics. Over the past five years, AMC Entertainment Holdings has declined about 99%, which means any fresh move in the share price carries outsized importance for existing holders. Recent balance sheet moves to refinance high...
Eversource, Blumenthal, data centers: CT politics news
Plus: Stacey Abrams in CT, a federal investigation into sexual assault handling, and education accountability metrics.
Is the stock market a good measure of Trump’s success?
It’s a metric that leaves out small businesses, not to mention many Americans
Google Pixel 11 devices to have the first 2nm smartphone SoC, new modem
The Tensor G6 is expected to leapfrog the competition in one very specific metric and probably not much more. According to a new report from China,...
Lunarium launches July 29
Hand-drawn isometric action RPG Lunarium will launch for PC via Steam on July 29 for $17.99 / €17.99 / £15.99, publisher Imperfect Games and developer Lunarium Game Studio announced. It will suppor…
Google's SensorFM Reveals Where AI Takes Wearable Health
Google's trillion-minute SensorFM data shows wearables shifting from raw metrics to AI health agents, a trend already reshaping Whoop and Oura.
Health trackers offer a ton of data. Here are the metrics doctors want you to pay attention to
We’re all wearing Apple Watches, Oura Rings, and FitBits now. Are they doing us any good?
Health trackers offer a ton of data. Here are the metrics doctors want you to pay attention to
We’re all wearing Apple Watches, Oura Rings, and FitBits now. Are they doing us any good?
How to Bring More Data Science to YouTube and Creator Media
I am constantly writing about the challenge facing agencies and brands when in comes to YouTube. Is it TV? Social video? Search? Commerce? Do you fund it from all of those respective budgets, and measure it using all their respective metrics? Sean Odlum, Chief Product Officer at Tinuiti, says it may not make sense to try and “bucket'“ YouTube. “You kinda gotta treat it as its own thing,” he said. “Years ago, we had debates [along the lines of] ‘what is this?’ Ultimately we decided, it’s YouTube. It is hard to categorize because it is so protean.” Which ultimately means that almost every part of a media department or marketing group will likely touch YouTube in some fashion. And that it probably needs its own sets of metrics and measurement tools. At Tinuiti, that need has led the agency to develop the YouTube Intelligence Suite, which aims to help brands optimize YouTube campaigns while using all the traditional marketing tools they are used to, such as MMMs. “I wouldn’t say there is a YouTube playbook,” Odlum said. “[For media planners] there is this vast bubbling ocean, so where do you start?’ A lot of brands and agencies struggle.” “You don’t want to just brute-force it—spray dollars everywhere and eventually learn. You want to start intelligently and then learn iteratively.” The problem, Odlum and his team have found, is that “brands have largely defaulted into demand generation campaigns because they’re easier to measure.” However, “you can really build your own content ecosystem around these trusted experts.” Check out the full interview here: Thanks for reading Next in Media! Subscribe for free to receive new posts and support my work. Subscribe
America's Top States for Business 2026: See the full rankings and where your state finished
CNBC's annual study puts all 50 states to the test across 138 metrics and 10 categories of competitiveness. These are America's Top States for Business.
Carbon capture continues to expand globally despite mounting opposition
Carbon capture continues to expand globally despite mounting opposition Global energy and research consulting firm Wood Mackenzie reports that carbon capture, utilization and storage, or CCUS, is expected to expand significantly, with global capacity projected to grow from roughly 91 million metric tons per year today to about 3 billion metric tons annually by 2060, […]
New Google Health App Update 5.03: More Metrics, Sleep Improvements
Google pushed a new Google Health app update today on Android and iOS as version 5.03. This new update begins rolling out today and will continue in phases over the next week, so try not to worry...
Dumbo Health Launches SleepLongevityAge, Bringing Clinical Care to the World’s Most Overlooked Health Metric
Introducing Sleep Longevity: a new category of care that turns the world’s most overlooked health metric into action. Sleep better. Live longer.Miami, Florida, July 08, 2026 (GLOBE NEWSWIRE) -- Millions of people wake up tired every morning, and most never find out why. Americans have never known more about how they sleep: Apple Watch, Oura, Whoop, Garmin, and other wearables generate millions of sleep scores every morning. Yet for most people, those scores never lead to action. Today, Dumbo Hea
Why cardiology leaders should be careful about the quality metrics they focus on
"Data should simply be a measure of a broader organizational objective," one expert explained. "When the data becomes the goal, that's where organizations can get into trouble."
This Toilet Attachment Helps You Understand Your Gut Health, Hydration And More
Kohler Health's easy-to-install bathroom appliance provides key wellness metrics and personalized health insights.
Make the Business Case for Your Sustainability Initiative
Sustainability proposals often stall not because they lack merit, but because they are framed in a language that does not match how senior leaders allocate capital. While CSOs tend to emphasize impact, materiality, and disclosure, CFOs and CEOs need to understand cash flow, risk, and return. External reporting frameworks are useful for accountability, but they are poorly suited to internal investment decisions, which require project-level comparisons rather than aggregated enterprise metrics. Sustainability investments should therefore be evaluated like any other investment: by showing how they reduce current costs, avoid future costs, generate new revenue, or protect existing revenue. Strong cases begin with a clear business story that links the proposed action to a specific business impact and cash-flow outcome, then quantify what can credibly be quantified while treating harder-to-measure benefits as either upside or an explicit strategic bet.
Deutsche Bank, Lufthansa invest in SAF to cut business travel emissions
The deal between the German lender and the aviation company is estimated to enable up to 5,500 metric tons of carbon dioxide emissions reductions compared to conventional jet fuel.
Jaguars’ QB Lawrence Outperformed His Salary Last Season
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Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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Semiconductor decoupling. Powell's politics. Industrializing Ogaden. Free trade and the Magna Carta.
Thank you for opening your Chartbook email. Feliks Topolski, 1907-1989 8th Army’s Front, Italy 1944 Semiconductor decoupling Source: FT One thing that Jerome Powell deeply understood is that chairing the Fed under current conditions is a deeply political job. “Powell has successes and mistakes to his name. But he stands out as having thought more carefully about the Fed’s democratic legitimacy than any chair since Paul Volcker,” said Paul Tucker, a former deputy governor at the Bank of England, referring to the Fed chair who successfully fought the great inflation of the 1970s and early 1980s. … While Powell was at the Treasury in the early 1990s, he watched Alan Greenspan build relationships within the government. That convinced Powell he needed to follow the former Fed chair’s lead and spend more time in Congress than his predecessors Yellen and Bernanke. “The accountability for the Fed runs through Congress,” said Claudia Sahm, a former Fed official who is now chief economist at New Century Advisors. “That’s not just about having people on speed dial — it’s answering questions, explaining policy and getting feedback.” Source: FT Ethiopia’s PM Abiy and Nigerian business tycoon, with Chinese engineering, are driving industrialization in Ogaden/Somali region of Ethiopia. - Michael Masri’s reporting for Africa Report if fascinating. Ethiopia has launched a cluster of large industrial schemes in the Somali region, laying foundation stones for a urea plant and an oil refinery in Gode while opening the first two phases of the Ogaden LNG project. Abiy Ahmed framed the push as part of a broader strategy to link energy, agriculture and industry. “These projects embody more than industrial growth,” he said. “They represent our shared responsibility to harness opportunities, strengthen co-operation and promote peace.” The Gode urea plant, backed by Dangote Group and Ethiopian Investment Holdings (EIH), is designed for 3m tonnes a year. Dangote owns 60%, while EIH holds 40%. Officials say Dangote’s equity totals about $2.5bn, while the state provides land and implementation oversight. Gas from the Calub fields will be piped 108km to the site. Construction is slated for 40 months, with operations targeted for 2028. Ethiopia imports most of its fertiliser, spending more than $1.2bn a year for 1.5m–2m tonnes. Usage was roughly 1.7m tonnes in 2023, almost half of it urea, and demand for 2024–25 is put above 2.4m tonnes. If delivered on time, the Gode plant could cover domestic needs and allow exports to neighbours. Brook Taye, chief executive of EIH, called the venture “a significant milestone in the journey toward industrial self-sufficiency”. Dangote told the groundbreaking crowd that the complex would be integrated with gas supply and a polypropylene unit to support local inputs. He pointed to Ethiopia’s Grand Ethiopian Renaissance Dam (GERD), with a capacity of more than 5,000MW, and noted his group’s cement operations and expansion plans. The Gode refinery is being developed by Golden Concord Group of China. It is designed to process 3.5m tonnes a year of crude and condensate from the Hilala field, with associated storage. Backers say it will ease foreign-exchange pressure from fuel imports and anchor further industrial activity, including a proposed steel smelting site in Dire Dawa. GCL’s chair, Zhu Gongshan, cast the project as “a key step in Ethiopia’s path to energy sovereignty”, underscoring the Beijing–Addis ties. Financing details are still being finalised, but the refinery is central to the government’s energy-security narrative. Source: The Africa Report Dangote’s Ethiopian vision: Dangote began with cement. His crown jewel, Dangote Cement, dominates Nigeria’s market and has 10 operations in other nations in Africa. The formula has been consistent: identify sectors with chronic shortages – cement, fertiliser, sugar – commit massive local investments, and scale up to serve regional demand. Ethiopia was a natural extension of that model. In 2015, Dangote launched the Mugher Cement Plant outside Addis Ababa at a cost of $600m, with an annual capacity of 2.5 million tonnes. The investment gave him a firm foothold in one of Africa’s fastest-growing construction markets. But success came with risks. In May 2018, violent unrest led to the killing of Dangote’s country manager and temporary shutdowns at Mugher. While other investors might have retreated, Dangote doubled down. Today, he is preparing to spend $400m to expand Mugher’s capacity to 5 million tonnes, alongside a new grinding unit near Addis Ababa. Cement is just one market Dangote is targeting. Ethiopia’s enormous state-controlled sugar industry, long plagued by inefficiency and debt, has struggled for years to reform. Its Omo Kuraz Sugar Development Project, touted as one of the continent’s largest initiatives, continues to face delays and mismanagement. … The most ambitious venture of all is the planned fertiliser production complex in Gode, Somali region. Publicised on 28 August 2025, the Dangote Group and Ethiopian Investment Holdings (EIH) deal plans one of the world’s largest single-site urea manufacturing plants. The project costs an estimated $2.5bn and has an estimated capacity of 3 million metric tonnes annually, a rate that would not only render Ethiopia independent, but even a net exporter of fertiliser. EIH, the state wealth fund of Ethiopia, will hold 40%, while 60% is held by Dangote Group. … For Dangote, Ethiopia is a trifecta: Cement demand is projected to grow by 10% annually, its sugar consumption is growing with rapid urbanisation, and fertiliser demand is all but insatiable, given that farming supports the livelihood of 70% of Ethiopians. Source: The Africa Report The stakes for Abiy are high: For Addis Ababa, the $4bn fertiliser project in Ethiopia’s Somali region is no longer simply a manufacturing investment. It is increasingly being framed as a strategic state project tied to food sovereignty, import substitution and the government’s broader attempt to build economic resilience under mounting fiscal pressure. “Becoming self-sufficient in food is our main agenda,” Abiy says during the visit. “Land is needed; we have it. Water is needed; we have it. Human resources are needed; we have it.” The scale is enormous even by African industrial standards. Once operational, the plant is expected to produce three million metric tonnes of urea annually, potentially making it one of the continent’s largest fertiliser complexes. Ethiopian officials say the project now includes a 110km gas pipeline, a 120MW power plant, a polypropylene packaging facility and a two-million-tonne NPK blending plant. For a government grappling with chronic foreign exchange shortages, ballooning import bills and pressure on agricultural productivity, the numbers matter politically as much as they do economically. The decision to anchor the project in Gode is deliberate. Long viewed as peripheral to Ethiopia’s industrial economy, the Somali region is now being repositioned by the federal government as a future irrigation and agro-industrial corridor. Officials argue that the area’s vast land reserves and access to water could eventually support large-scale commercial farming capable of reshaping Ethiopia’s food economy. The government is simultaneously building housing infrastructure for about 5,000 residents near the plant, while officials project broader industrial expansion along the corridor. Abiy goes further, comparing the long-term revenue potential of the Gode development zone with Ethiopia’s flagship state enterprise. “The investments we are making in this Gode area, combined, will generate high revenue for Ethiopia, at par with Ethiopian Airlines,” he says. Source: The Africa Report Feliks Topolski 1907-1982 Topolski’s Chronicle, ‘Nazi Revival’, Vol. 8, Is. 1-2, 1960 HEY READERS, THANK YOU for opening the Chartbook email. I hope it brightens your day. I enjoy putting out the newsletter, but tbh, what keeps this flow going is the generosity of those readers who clicked the subscription button. Photo by Jakub Dziubak on Unsplash If you are persuaded to click, please consider the annual subscription of $50. It is both better value for you and a much better deal for me, as it involves only one credit card charge. Why feed the payments companies if we don’t have to. Subscribe Grim vision of drone warfare by Sylvie Kaufmann For contributing subscribers only. Subscribe The state of the art in Colbert-studies. Jean-Baptiste Colbert was Louis XIV chief minister from 1661 to 1683 and traditionally seen as an architect of absolutism and mercantilism. Alexander Hamilton later cited him as an inspiration in 1782. Now his legacy is disputed. Daniel Dessert, the chief critic, sees Colbert as the orchestrator not so much of an absolutist state as of an elite cabal. Would be great to have a good English-language review of this important debate. Source: lhistoire Didn’t know that the Magna Carta included free trade provisions Fighting for the right to the beach in Oregon in 1967: Source: Research Gate RAF Station – British and Polish Flags, c. 1940-45, The Ingram Collection Feliks Topolski, 1907-1989 ink and wash If you’ve scrolled this far, you know you want to click: Subscribe
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Corporate executives highlighted a few asks of their boards in a new survey: focus more on the country’s political environment, incorporate AI, and link their pay to non-financial metrics.
The Latino Electorate: Shaping Texas Politics
Abstract Excerpted From: Armand J. Avila, The Latino Electorate: Shaping Texas Politics, 41 Chicana/o-Latina/o Law Review 1 (2025) (134 Footnotes) (Full Document). Texas is incredibly diverse, with one survey ranking the state second in diversity among all states in the country based on various racial, socioeconomic, cultural, and household metrics....
Wellgistics Health and Datavault AI to Form DelivMeds AI via PharmacyChain™ License Expansion and Acquisitions of QOLPOM Biometric Health Data and Drone Logistics IP and Majority of Tollo Health
Formation of DelivMeds AI, Inc. (ticker reserved: NASDAQ:MEDS), with an expected approximate combined asset value of $4 billion, is subject to…...
NYC Health and Hospitals says hackers stole medical data and fingerprints during breach affecting at least 1.8 million people
The New York public healthcare system said hackers stole personal and medical data, and scans of biometrics — including fingerprints — in one of the largest recorded breaches of 2026.
Syracuse Council to vote soon on biometric identity technology restrictions
Biometric data encompasses a whole host of information.
Scientists discover hidden math secret inside Chinese money plant leaves
Scientists have uncovered a hidden mathematical secret inside the leaves of the Chinese money plant: a naturally occurring geometric pattern known as a Voronoi diagram, something typically associated with city planning, computer science, and network design. By mapping tiny pores and looping veins in the plant’s leaves, researchers discovered that the plant organizes itself using the same kind of elegant spatial logic humans use to solve complex distance problems — without ever “measuring” anything.
UIndy Captures GLVC All-Sports Trophy for 14th Straight Year
UIndy Athletics continued its dominance in the department-wide metric, winning the GLVC All-Sports Trophy by 23 points over second-place Maryville.
Find Hub ‘Mark as lost’ will require biometric unlock & hide Quick Settings, more
At The Android Show, Google today announced the latest security and privacy features for the mobile operating system.
Why 57% of business leaders say their metrics will fail
Companies are investing billions in AI-powered dashboards, predictive analytics and real-time reporting. Yet there's a widening gap between data availability and decision quality.