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Can the so-called nanobubbler save the Reflecting Pool?
The $1.7 million “ozone nanobubbler” being used in an effort to make the Lincoln Memorial Reflecting Pool water crystal clear has a unique ability to shoot 500 million microscopic bubbles into every teaspoon of water. The injected oxygen is supposed to oxidize — or, unscientifically speaking, smash through — algae, bacteria and other chemicals.
What science tells us about the algae bloom in the Lincoln Memorial Reflecting Pool
Algal blooms are not maintenance failures requiring paint or treatment with hydrogen peroxide and nanobubbles. They are ecological warning signs.
International Business Machines (IBM) Is A Top Stock In Billionaire Richard Chilton’s Filings
International Business Machines Corporation (NYSE:IBM) is one of the 10 Best Stocks to Buy According to Billionaire Richard Chilton. Technology giant International Business Machines Corporation (NYSE:IBM) made a key announcement recently when it announced its 0.7-nanometer chip manufacturing technology. This technology is the most advanced chip manufacturing technology in the world. International Business Machines Corporation […]
The Science Of Speed: How Mizuno’s Nanoalloy Face Changes What’s Possible In Driver Design
Mizuno is the first company to put a functional polymer layer in front of a driver face. The implications go well beyond ball speed. For most of the
'This is the next jump in technology': World's first sub-1nm chip keeps Moore's Law alive a little longer
IBM's NanoStack architecture has helped scientists cram 100 billion transistors onto a computer chip, delivering 50% better performance and consuming 70% less energy than the current generation.
19 great Prime Day deals on our favorite charging gear
Keep all of your devices powered with Prime Day discounts.
Meet the doctor building tiny tools for big science breakthroughs
UCLA's Steven Jonas uses nanotechnology in his lab to explore cancer and other disease-fighting tools.
Advances in materials science are helping unlock secrets of nanomaterials
New instruments on the horizon promise the most precise tools yet to study and experiment on the smallest and most complex materials ever manufactured. In a paper published in the journal Nature Materials, ...
Anker 2026 Prime Day sale kicks off with up to 50% off Nano chargers, Qi2.2 stands, power banks, and more from just $16
As part of the ongoing Prime Day sale, Anker’s official Amazon storefront is offering notable discounts across a wide range...
Watching water nanodrops spread themselves thin
Researchers at the Institute of Industrial Science, The University of Tokyo, have determined the molecular origin of line tension for a water nanodroplet on a surface. This tension is the force along the droplet edge where liquid, solid, and gas phases meet. Computational studies showed that at complete wetting, collapse of tetrahedral order in liquid water causes the line tension to change sign. An ice bilayer did not wet a hydrophilic surface, showing that local order can outweigh surface chemistry.
Scientists Made a Car Paint So Black It Looks Like a Hole in Reality
Researchers with Singapore-based Nipsea have created a new “ultra-black coating” that absorbs an average of 99.9% of all visible light wavelengths.
Superconductivity breakthrough could unlock ultra-efficient electronics
A clever nanoscale redesign may have solved one of superconductivity’s biggest problems. Researchers in Sweden discovered that by subtly sculpting the surface beneath an ultrathin superconducting material, they could make it stay superconducting at higher temperatures and under much stronger magnetic fields.
Apple's 2028 iPhones to Use 1.4nm A22 Pro Chips
Apple will transition from 2-nanometer chips to 1.4-nanometer chips with the high-end 2028 iPhone models, reports Bloomberg. Chip supplier Taiwan Semiconductor Manufacturing Co. (TSMC) will make the majority of Apple's A22 Pro chips, but Apple is also considering having Intel make some of them. The current iPhone 17 models use a third-generation N3P 3-nanometer process.
Class action lawsuit claims radiology vendor Nano-X Imaging misled investors
The Israel-based manufacturer allegedly made “misleading statements” regarding its business operations and prospects, attorneys charge in the complaint, filed June 12.
Fluorescent nanosensor enables rapid, first-of-its-kind detection of key gut health biomarker
Researchers developed an optical nanosensor to rapidly detect a key gut biomarker, enabling faster, accessible screening for conditions such as inflammatory bowel disease, Type 2 diabetes, and liver disease.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
UT Austin researchers create nanoscale Longhorn using DNA origami
UT Austin researchers folded DNA into a nanoscale Longhorn, demonstrating a breakthrough that could help deliver cancer drugs more precisely and speed up the production of advanced materials.
Allan MacDonald Wins Kavli Prize in Nanoscience
MacDonald and two colleagues were honored for “foundational work that established the field of twistronics.”
Five Americans Are Among The Ten Scientists Awarded Kavli Prizes For 2026
The Norwegian Academy of Science and Letters has announced the 10 recipients of the 2026 Kavli Prize in the fields of astrophysics, nanoscience, and neuroscience.
Lighter X-ray aprons could spare health-care workers from chronic pain
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Helene-hit Swannanoa businesses say state rules block access to federal recovery funds
Swannanoa business owners who lost everything after Helene are speaking out about not being able to apply for federal disaster recovery funds.
A tiny atomic shift gives scientists powerful control over metals
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New light-powered chip could accelerate AI and quantum computing
Scientists have created a tiny chip that can generate, steer, and read light-based information all in one device, marking a major leap toward ultra-fast, energy-efficient computing. The breakthrough uses atomically thin materials and nanoscale structures to control a unique quantum property of light called the “valley” degree of freedom, allowing information to be encoded in new ways.
UC researcher secures $3.3M grant to study microplastics’ impact on heart
The National Institute of Environmental Health Sciences awarded a $3.3M grant to University of Cincinnati researcher Hong‑Sheng Wang, PhD, to study how microplastics and nanoplastics affect cardiovascular health.
AMD Bundles Carbice Ice Pad with Ryzen 7 5800X3D
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This strange new phase of matter could transform quantum technology
By stacking custom-designed silver nanoparticles like nanoscale LEGO bricks, scientists stabilized a mysterious crystal phase that had never been observed before. The material not only solves a longstanding puzzle in materials science but also exhibits promising quantum properties at room temperature.
Scientists develop 'smart paint' that reflects 97% of sunlight and could reduce AC use during heatwaves
As heatwaves become more frequent and intense around the world, scientists are exploring new ways to keep buildings cool without increasing energy consumption. Researchers at the University of Sydney, working with startup Dewpoint Innovations, have developed a nano-engineered coating that reflects up to 97% of sunlight and stays significantly cooler than conventional surfaces.
How a health clinic in South Africa is navigating Trump's cuts to HIV funding
Community health programs in South Africa have been heavily impacted by U.S. cuts to global aid. Which means there are fewer community and health workers to support low-income people with HIV and AIDS.We recently visited one of those programs, called We Care, to learn more about the experiences of the few employees who still remain.For sponsor-free episodes of Consider This, sign up for Consider This+ via Apple Podcasts or at plus.npr.org. Email us at considerthis@npr.org.This story was supported by the Pulitzer Center.This episode was produced by Matt Ozug, Karen Zamora and Elena Burnett, with audio engineering by Peter Ellena.It was edited by Patrick Jarenwattananon and William Troop.Our executive producer is Sami Yenigun.
Nanoparticles genetically modify several human cell types
In a demonstration that helps pave the way for gene therapies with fewer side effects, several human cell types were genetically modified with protein nanoparticles designed at University of Michigan Engineering and Michigan Medicine.
Visiting students explore sustainability through physics REU program
Students visiting Penn State for its Physics Research Experiences for Undergraduates program not only conduct hands-on research, but also explore the environmental, social and global impacts of that research. The program, hosted by the Department of Physics in the Eberly College of Science and the Center for Nanoscale Science, supports students from across the country who may not otherwise have access to research opportunities.
Why interdisciplinary science is needed more than ever
Solving today’s complex problems requires teams of scientists from a range of disciplines
Anker Clears Out 10000mAh Nano Portable Charger at Its Lowest Price of the Year for Memorial Day, Selling Out Fast on Amazon
Keep all your important devices charged through the day with ease.
UNCG Graduate Student Excels in Science and Leadership
UNCG graduate student Nooshin KianvashRad is advancing nanoscience research while leading campus initiatives and inspiring others.
Two brothers raised $12m for an OpenClaw competitor
NanoClaw's enthusiastic users include AI researcher Andrej Karpathy and Singapore's foreign minister.
Aerobic exercise may lessen the health effects of exposure to nanoplastics
Using female zebrafish as a model, researchers have found that aerobic exercise may influence various connections in the body to lessen the damaging health impacts of environmental nanoplastics. In the ...
Call for a standard framework for triboelectric nanogenerators
Research to boost TENG performance cannot move forward without a standard way to test these devices and report the results.
This popular fermented food may help flush microplastics from the body
Scientists in South Korea have discovered that a probiotic bacterium found in kimchi may help the body flush out tiny plastic particles before they can build up in organs. In lab tests, the kimchi-derived microbe clung tightly to nanoplastics even under conditions designed to mimic the human intestine, where other bacteria quickly lost their grip.
The “impossible” LED that could change everything
Scientists at the University of Cambridge have achieved what was once considered impossible by electrically powering insulating nanoparticles to create a completely new kind of LED. Using tiny organic “molecular antennas,” the team found a way to funnel energy into materials that normally cannot conduct electricity, producing ultra pure near infrared light with remarkable efficiency.
Decoding chirality at the nanoscale with momentum-space polarimetry
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Scientists reverse Alzheimer’s in mice with breakthrough nanotechnology
A new nanotechnology treatment reversed Alzheimer’s symptoms in mice by restoring the brain’s natural cleanup system. The specially engineered nanoparticles helped clear toxic amyloid proteins from the brain and repair the blood-brain barrier, which normally protects and regulates the brain’s environment. In one striking experiment, elderly mice treated with the therapy later behaved like healthy younger mice.
NANO Nuclear Reports Q2 FY 2026 Financial Results and Provides Business Update
Management to hold webcast today at 5:00 pm Eastern
Microplastics absorb heat in the atmosphere and contribute to global warming — as if they weren't bad enough
Climate scientists have discovered that microplastics and nanoplastics are helping to drive global warming by absorbing sunlight and radiation in the atmosphere.
MSOE students share nanoscience with St. Joan Antida High Schoolers
Students became the teachers in SCI 3750 Nanoscience and Nanotechnology course thanks to a unique partnership that has been fostered for more than a decade. Dr. Anne-Marie Nickel, professor in the Physics and Chemistry Department, has partnered with St…
2026 National Defense Science and Engineering Graduate (NDSEG) Fellowship Award
First year Materials and Nanoscience graduate student Stéphane Miaule (Tolbert group) has been awarded the 2026 National Defense Science and Engineering Graduate (NDSEG) Fellowship, one of the country’s most prestigious honors for graduate students in the fields of Science, Technology, Engineering and Math (STEM). The program, jointly sponsored by the U.S. Army, Navy, and Air Force, supports doctoral students across a broad range of scientific and technological fields of strategic importance. This highly competitive fellowship provides full tuition, fees, and a monthly stipend for three years. In 2026, only 102 fellowships were awarded nationwide, and Stéphane is the sole recipient from UCLA. Before transferring from Santa Monica College to UCLA, Stéphane interned at NASA’s Kennedy Space Center and Marshall Space Flight Center, where he researched the mechanical and thermodynamic properties of lunar regolith, as well as radiation shielding materials for lunar habitation development. At UCLA, he joined the Soft Materials Research Laboratory under Professor Qibing Pei, focusing on the synthesis and characterization of hafnium oxide nanocomposite scintillators. After earning his bachelor’s degree in chemistry, he remained in the Soft Materials Research Laboratory as a post-baccalaureate researcher for one year before joining Professor Sarah Tolbert’s group as a Ph.D. student. Stéphane’s Ph.D. research is focused on improving the properties of conjugated polymers, which are a family of plastic materials that can conduct electricity. Stéphane is specifically looking at self-assembling polymers that can be processed in water to create light-weight, flexible, high-conductivity polymer devices without the need for toxic or volatile organic solvents. After completing his Ph.D., Stéphane hopes to work in a national laboratory, researching semiconducting polymers for applications in new electronic devices. “The Graduate (1967) featured a memorable scene in which the protagonist was told that ‘there’s a great future in plastics.’ We know this still holds true today, as polymer research has expanded rapidly due to the wide variety of applications these materials enable. Through my work on semiconducting polymers, I hope to contribute to the continued development of plastic electronics,” Stéphane said. Penny Jennings, UCLA Department of Chemistry & Biochemistry, penjen@g.ucla.edu.
How to remove Gemini Nano from Chrome (and free up 4GB of storage)
Here's how to delete Chrome's weights.bin file and disable Gemini Nano to reclaim your storage space on Windows and macOS.
Quantum topology emerges at near field
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Google Chrome Is Silently Downloading a 4GB Gemini Nano AI Model to User Devices Without Consent
Google Chrome has been automatically downloading a 4GB folder of Gemini Nano AI weights to user devices without notification, and redownloads it if deleted.
U.S. Embassy Supports Tunisian Business Delegation at 2026 SelectUSA Investment Summit - U.S. Embassy in Tunisia
U.S. EMBASSY SUPPORTS TUNISIAN BUSINESS DELEGATION AT 2026 SELECTUSA INVESTMENT SUMMIT The SelectUSA Investment Summit is the premier U.S. investment event, connecting thousands of investors, companies, economic development organizations, and industry experts to make deals happen. Media Note TUNIS, May 5, 2026 – U.S. Embassy Tunis is pleased to support a delegation of 11 Tunisian companies traveling to the United States to participate in the 2026 SelectUSA Investment Summit at National Harbor, Maryland, May 3-6, 2026. The Summit is an opportunity for these dynamic entrepreneurs to establish new connections and explore business and investment opportunities in the United States. This year, three Tunisian women entrepreneurs and members of the delegation representing Spiraw and Sotetel were accepted into the Select Global Women in Tech year-long mentoring program which will kick off at the summit. Since 2022, more than 50 Tunisian entrepreneurs in fields ranging from e-gaming, robotics, software engineering, coding, online fashion, and green tech have participated in SelectUSA Investment Summits, where they have taken their businesses to the next level. Hosted by the U.S. Department of Commerce, the SelectUSA Investment Summit is a one-stop shop for companies considering expanding to the United States and provides economic development organizations (EDOs) with the opportunity to meet directly with international companies to facilitate investment deals. Since inception, the SelectUSA Investment Summit has attracted tens of thousands of companies and economic development representatives, generating over $250 billion in new investment projects that support more than 125,000 jobs across the United States and its territories. The previous SelectUSA Investment Summit saw record-breaking numbers with more than 5,500 participants, including EDOs from 54 U.S. states and territories and over 2,700 business investors from 100+ countries, including Tunisia. The following Tunisian businesses will take part in this year’s SelectUSA delegation: AquaDeep – Revolutionizes aquaculture with AI-powered monitoring solutions, including a real-time larva counting system and a SaaS platform for environmental monitoring. The company is expanding operations across Tunisia, Europe, Africa, and the United States. Bouraoui Group – Specializes in event venues, hospitality experiences, innovative real estate development, and technology driven customer solutions. The business develops experience- focused and tech enabled lifestyle destinations that combine entertainment, culture, retail, and smart services, and is seeking international partners to co-develop hospitality, PropTech, smart retail, and experiential digital projects. Digital Cook – Builds HR and recruitment software solutions, including HRMS, ATS, and custom tools that streamline hiring, employee management, and talent development. It provides custom software, system integration, and scalable HR platforms for SMEs, large enterprises, and recruitment agencies seeking efficient, user-friendly ways to manage their workforce and improve recruitment. El Kanaouet – Provides high-quality and low-cost hydraulic infrastructure for the supply and distribution of drinking water. The company manufactures prestressed concrete structures based on current technological developments in the field and trends in integrated and digitalized management. El Kanaouet aims to enter the U.S. market with its production of centrifugal prestressed concrete pipes and other technical products and services. Fluoink Nanotechnologies – A deep‑tech startup developing next‑generation antimicrobial additives for paints, coatings, and industrial materials, enabling everyday surfaces to act as long‑lasting barriers against harmful bacteria and pathogens without changing their appearance or performance. Mare Custos – A subsea robotics company specializing in ROV-based underwater inspection services for offshore energy, ports, and marine infrastructure, using high-precision imaging, PAUT, and NDT to inspect structures in challenging conditions. SmartMed SA – A fast-growing digital health company operating in Tunisia, Algeria, and Morocco, offering an integrated ecosystem that helps patients book appointments (MedPro), enables clinics to digitize workflows and EMRs (MedLink), and supports targeted digital marketing for healthcare and pharma (MedAds). With millions of appointments and users, SmartMed has become a leading e-health platform in North Africa. Sototel – Builds telecommunications networks and services, including fixed, radio, and mobile networks. Sototel focuses on technological innovation and continuous improvement, providing high-value-added digital solutions. SOTUPRIN HGE – Specializes in manufacturing household electrical appliances under the brand HGE and OEM. Expanded from the local market to North Africa, Central Africa, the Middle East, and Europe. Spiraw by Food4Future – Designs and manufactures smart, AI-powered cultivation systems allowing individuals and businesses to grow fresh, highly nutritious food – starting with spirulina – directly at the point of consumption. Combining patented hardware, controlled-environment agriculture, and a connected app with an AI assistant, Spiraw aims to decentralize food production and create a new category at the intersection of agri-tech, consumer health, and smart home ecosystems. WaterSec (Istidama) – A climate-tech startup that uses IoT, AI, and smart sensors to help high consumption facilities (such as industries, hotels, and commercial buildings) monitor water use in real time, detect leaks, and optimize consumption. The company’s digital platform turns raw water data into alerts and actionable insights, making water management more transparent, proactive, and sustainable. Learn more about the SelectUSA Investment Summit at https://www.selectusasummit.us/. Follow live developments from the summit on X at https://x.com/SelectUSA.
MIT scientists finally reveal the hidden structure of a mysterious high-tech material
For decades, relaxor ferroelectrics have powered everything from medical ultrasounds to sonar systems, yet their inner atomic structure remained a mystery—until now. Researchers have finally mapped their three-dimensional structure in unprecedented detail, uncovering hidden patterns in how electric charges are arranged at the nanoscale. The breakthrough not only challenges long-standing assumptions about how these materials behave but also allows scientists to refine the models used to design them.
InFocus Clinical Research names Elizabeth Nanouris Vice President of Business Operations
InFocus Clinical Research, the only global, full-service retina specialty contract research organization, announced today that Elizabeth Nanouris has joined InFocus as vice president of business operations.
Trump has targeted universities and science. But RIT is thriving
“I don't want to diminish the turmoil that we've all had to live through in the last year, and the consequences of that,” says the university's VP of research. But really? For RIT it's been a non-event.
Viewpoint: A career in science is possible, and worth it
Starting a career in science is exciting, but also demanding, with researchers often faced with intense competition, long working hours and high levels of stress. A pioneer in the field of mass spectrometry, Carol Robinson has been there. She speaks with Science|Business on the importance of creating a supportive environment, particularly for women.Robinson did not wake up one day thinking that she would become a scientist. It was only late in school that she developed an interest in chemistry. “The more you work at something, the more you think, actually, this is fascinating. So, I went much further and deeper than I ever needed to pass the exam. And then I loved it,” she says. “I thought, I’m going to give it my all. I’m going to enjoy it while I’m here. But I didn’t think this would be my career for 50 odd years.”She left school at 16 to become a lab technician with the drug company Pfizer, which is where she first worked with mass spectrometry. Fascinated, she was encouraged to take a part-time degree and then a PhD. She went on to do pioneering work in native mass spectrometry, a technique that is used to study protein structures in their natural state, paving the way for breakthroughs in drug discovery. She also broke new ground by becoming the first female professor of chemistry at the University of Cambridge, and then the first female professor of chemistry at the University of Oxford, her current home.She now wants to show young researchers that a career in science is worth it. “Sometimes, I believe the culture isn’t very encouraging, and that’s something I have worked on,” Robinson says.In 2021, she launched the Kavli Institute for Nanoscience Discovery at Oxford, whose acronym gives a sense of what she hopes it will achieve. “Maybe it is corny,” she says. “It’s just a reminder that I would like it if we could all be kind to each other and supportive, especially for early-career researchers of either gender, because there’s quite a big attrition rate in science, and maybe it just doesn’t feel like a very friendly place to work.”And yet, a career in science comes with a lot of flexibility. “There are few careers where you have that amount of freedom, to go to conferences, to the library. Just because you didn’t see me didn’t mean I wasn’t working,” she says. “And I’m excited to come in every day. So, I don’t want people to think it’s a terrible place.”Gender equality is also important when it comes to the quality of science as a career. “The more women we have, the better it becomes,” Robinson adds.Imposter syndromeAccording to EU data, women outnumber men in university education but account for just about a third of graduates in science, technology, engineering and mathematics (Stem). And while the number of women working as scientists and engineers in the 27-member bloc is on the rise, their representation remains below that of men, at 41%. This discrepancy is even more pronounced in top-tier functions across these fields, where women fill just 20% of positions.Having supervised many young scientists, Robinson sees that women continue to have a greater propensity than men to doubt their abilities, a feeling she once shared. “When I was doing my PhD at the University at Cambridge, I really felt like an imposter,” she says. “I don’t think I ever felt I deserved to be there or owned it and was proud. I just thought I was lucky.” Later on, she adds, “I was always that person who said, I can’t apply yet because my CV is not strong enough.”She has now made it her job to encourage women to break with this imposter syndrome. For example, rather than calling for volunteers to give a lecture in the groups that she mentors or teaches, which nearly always results in men stepping forward, she goes straight to the women, “because I know they won’t push themselves forward.”But the gender gap in science is not just down to imposter syndrome. The “obvious” reason, Robinson says, and the reason that is on everybody’s mind when discussing workplace gender equality, is the balance between work and raising a family. Her own path was to choose between the two, taking an eight-year break after completing a postdoctoral training fellowship to bring up three children. And she continues to advise women not to work part-time while they raise a family. “You’ll just get half the pay and continue to work full-time because you are not able to fit everything in,” she says. “You should be able to have a family and come back to have the career that you want.”The solution is for men to also take career breaks. “That kind of evens it up, so that it’s not such a big thing for women,” Robinson says. “I always encourage men in my groups to do that. I think it’s important to take your share of the duties.”Support produces resultsAccording to the Women in Stem Network, a UK advocacy group, countries with strong childcare systems and equal pay policies retain more women in technical careers. In Europe, these are primarily found in the Nordic region and parts of central Europe.At the EU level, the European Commission asks all Horizon Europe applicant organisations to have a gender action plan in place. Since this criterion was introduced in 2021, the share of women leading consortia has increased to 31%, against 23% in Horizon 2020. Their overall participation, however, has risen just 1%, to 38%. After trying to weaken the requirement for gender action plans in 2025, the Commission now intends to adopt a plan for supporting women in research and innovation.Related articlesCommission scraps plan to water down gender requirements in HorizonHow gender balance can swing who wins Horizon Europe fundingRobinson herself has benefited from three Advanced Grants from the European Research Council. “I was extremely honoured and privileged to get those, because they really allowed me to fuel my passion,” she says. “Without that, it would have been a much harder slog.”Beyond applying gender rules, she says that more work is needed on translational enterprise, where women are, once again, largely underrepresented. The European Patent Office found that only 13.8% of applications were filed by women in 2022. “We have so many more women doing amazing science; why do they feel it’s not a thing to have a company?” she asks.She founded her own spin-out company, OMass Technologies, in 2016, and remains chair of its scientific advisory board now that it trades as OMass Therapeutics. As for research, Robinson is now studying how changes in the brain may be linked to depression, using port-mortem tissue. “We’re hoping to publish soon,” she says. “We had to consult with a lot of people who knew a lot more about the brain than we did. So, we’ve learnt a lot, and that’s always a lot of fun to learn a new thing. That’s what keeps you going.”
More Gemini features are coming to Google TV
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I tested ChatGPT Images 2.0 vs. Gemini Nano Banana to see which is better
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Stratospheric nanoparticles’ surprising abundance is a game changer
Another discovery from NOAA's high-altitude research
New “optical tornado” technology could transform quantum communication
Scientists have created tiny “optical tornadoes” — swirling beams of light that twist like miniature whirlwinds — using a surprisingly simple setup based on liquid crystals. Instead of relying on complex nanotechnology, the team used self-organizing structures called torons to trap and manipulate light, causing it to spiral and rotate in intricate ways. Even more impressively, they achieved this effect in light’s most stable, lowest-energy state, making it far easier to generate laser-like beams with these unusual properties.
Scientists just found where airborne microplastics really come from
Microplastics are floating through the atmosphere and spreading across the globe, but their true origins have been misunderstood. New research shows land sources emit over 20 times more microplastic particles into the air than the ocean, challenging earlier beliefs. Scientists also discovered that previous models dramatically overestimated how much plastic is in the atmosphere.
Twisted nanoparticles sorted by light
Chiral objects are important in fields like drug development because their interactions with biological systems depend on handedness. Researchers from Tokyo University of Science, Institute for Molecular Science, and Seoul National University used light to selectively manipulate nanosized chiral objects. By confining circularly polarized light in an ultra-thin optical fiber, they transported metallic chiral nanoparticles based on handedness, thereby enabling chirality control at near-molecular scales, opening possibilities for applications involving chiral systems, including drug development.
This new brain-like chip could slash AI energy use by 70%
A breakthrough in brain-inspired computing could make today’s energy-hungry AI systems far more efficient. Researchers have engineered a new nanoelectronic device using a modified form of hafnium oxide that mimics how neurons process and store information at the same time. Unlike conventional chips that waste energy moving data back and forth, this device operates with ultra-low power—potentially slashing energy use by up to 70%.
How can scientists visualize cellular life with greater precision? - Salk Institute for Biological Studies
Highlights Salk researchers collaborated with scientists at Albert Einstein College of Medicine to develop a new class of probes for imaging living cells The probes, called visible-spectrum antigen-stabilizable fluorescent nanobodies (VIS-Fbs), generate high-contrast images with minimal disruption to normal cellular activity The technology enables more precise investigation of complex biological processes, including cell signaling, development, and disease progression LA JOLLA—Fluorescent proteins have revolutionized science, enabling researchers to tag and visualize individual molecules in living cells, tissues, and animals. Using these tools, researchers have watched viruses infect cells in real time, observed cellular trash collection, and tracked the signaling that spurs tumor growth.
Scientists sculpt Einstein onto a crystal using only light
A light-sensitive crystal is opening the door to a new era of “light-written” technology. Arsenic trisulfide can be reshaped and permanently altered using simple light, creating ultra-fine optical patterns without expensive manufacturing tools. Scientists even etched a nanoscale portrait of Einstein and high-density patterns that could act as secure optical signatures. This breakthrough could power everything from advanced sensors to next-generation AR devices.
Multifunctional ligand engineering for pure-blue halide perovskite nanocrystal LEDs
Light: Science & Applications - Passivation with a bifunctional fluorinated ligand stabilizes mixed-halide perovskite nanocrystals, enabling high-color-purity deep-blue emission...
PAID POST: CSCU and State Officials Launch Connecticut’s Quantum Science Center
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Nancy Guthrie Update: Sheriff Speaks Out Amid Reports of ‘Bombshell’ Development
Nanos’ comment came after Nancy Grace shared reports that a person of interest had been detained.
Nancy Guthrie Update: Sheriff Speaks Out Amid Reports of ‘Bombshell’ Development
Nanos’ comment came after Nancy Grace shared reports that a person of interest had been detained.
Gemini can now create personalized AI images by digging around in Google Photos
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Google adds Nano Banana-powered image generation to Gemini's Personal Intelligence
The feature will be initially available to paid users in the U.S.
Gemini app using Personal Intelligence, Photos for tailored Nano Banana generation
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WATCH LIVE: It's Tax Day. IRS chief is testifying on tax filing season
IRS CEO Frank Bisignano is set to testify in front of the Senate Finance Committee on Wednesday.
Adobe's Firefly AI Assistant works across Photoshop, Premiere and other apps
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Scientists Break Optical Limits With Quantum Dot-Powered Nanoscopy
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SCORE Offers Free Business Mentoring Sessions
Local entrepreneurs and small business owners in Pasadena have a valuable resource at their fingertips with the ongoing SCORE One-on-One Mentoring Sessions. These free and confidential appointments provide individuals with expert guidance on starting, running, or growing a small business, courtesy of SCORE, the nation’s largest network of volunteer business mentors. The sessions are designed to offer personalized advice and strategic insights from experienced professionals. SCORE, which stands for Service Corps of Retired Executives, is a non-profit organization and a key resource partner of the U.S. Small Business Administration (SBA). Its mission is to foster vibrant small business communities through dedicated mentoring and education. The organization comprises a network of seasoned business owners and executives who generously volunteer their time to support the next generation of entrepreneurs. As SCORE states, their mentoring is a “free, confidential service for anyone starting, running, or growing a U.S.-based small business.” These one-hour mentoring sessions are held every other Tuesday from 1 to 5 p.m. at two branches of the Pasadena Public Library: the Lamanda Park Branch Library and the Santa Catalina Branch Library. Appointments can be conveniently reserved up to 14 days in advance, ensuring that individuals can schedule a time that best suits their needs. This recurring service underscores SCORE’s commitment to continuous support for the local business community, helping them to plan, launch, and grow successfully. Need to Know: The SCORE One-on-One Mentoring Session offers free business guidance. These one-hour appointments are available every other Tuesday from 1 to 5 p.m. at the Pasadena Public Library’s Lamanda Park Branch (140 S Altadena Drive, Pasadena, CA 91107) and Santa Catalina Branch (999 E Washington Blvd., Pasadena, CA 91104). The service is free. For more information or to book an appointment, visit [https://www.score.org/].
Making light spin with a gold nanorod
Controlling photon spin, or the handedness of light, is useful for storing and transmitting information. However, generating circularly polarized light typically requires complex or chiral structures. Researchers from the Tokyo University of Science show that hitting a gold nanorod slightly off-center with an electron beam causes the light around it to rotate. This method offers a simpler way to control photon spin and could accelerate the development of smaller, more efficient optical and quantum devices.
Hidden weak spots in HIV and Ebola revealed with breakthrough nanodisc technology
A new nanodisc-based platform lets scientists study viral proteins in a form that closely mimics real viruses, revealing how antibodies truly recognize them. This approach uncovered hidden interactions in viruses like HIV and Ebola that traditional methods missed. By recreating the virus’s membrane environment, researchers can better understand how immune defenses work. The technique could speed up the development of more effective vaccines.
Scientists trap light in a layer 1,000x thinner than hair
Researchers have created a nanoscale structure that traps infrared light in a layer just 40 nanometers thick—over 1,000 times thinner than a human hair. By using a unique material with exceptional light-bending properties, they can confine and intensify light far beyond previous limits. This setup also dramatically boosts light conversion effects, turning infrared into visible blue light. The advance could pave the way for smaller, faster photonic technologies.
Google previews Gemini Nano 4 for Android AICore, coming this year
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Google's $20 per month AI Pro plan just got a big storage boost
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Hands-on: Anker's new Nano Power Strip will be a perfect fit in your desk setup
Today, Anker is releasing its new Nano Power Strip, initially unveiled at CES 2026. It clamps onto the side of...
Apple Adjusts Studio Display XDR Pricing Weeks After Launch
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Scientists turn MXene into tiny nanoscrolls that supercharge batteries and sensors
Scientists have transformed a groundbreaking 2D nanomaterial called MXene into an even more powerful 1D form—tiny scroll-like tubes that are incredibly thin yet highly conductive. By rolling flat sheets into hollow nanoscrolls, they’ve created structures that act like fast “highways” for ions, boosting performance in batteries, sensors, and wearable electronics.
Stanford scientists create shape-shifting material that changes color and texture like an octopus
A new shape-shifting material can change both its texture and color in seconds, inspired by the camouflage abilities of octopuses. By precisely controlling how a polymer swells with water, researchers can create detailed, reversible patterns at the nanoscale. The material can even mimic realistic surfaces and dynamically adjust how it reflects light. In the future, AI could allow it to automatically blend into its surroundings.
This new “phonon laser” could measure gravity more precisely than ever before
Scientists have taken lasers beyond light and into the realm of sound, creating a breakthrough “phonon laser” that manipulates tiny vibrations at the quantum level. By dramatically reducing noise in these systems, researchers can now measure motion and forces with unprecedented precision. This advance could unlock new ways to study gravity, probe quantum physics, and even revolutionize navigation with ultra-accurate, satellite-free systems.
Best charger deal: Pick up this Anker Nano charger for its lowest price yet in Amazon's spring sale
It features fast charging and Care Mode for better battery health.
Ruby Ridge Book Explores Roots of American Conspiracy Politics at Vroman’s Tonight
Author Chris Jennings will discuss his critically acclaimed book “End of Days: Ruby Ridge, the Apocalypse, and the Unmaking of America” at Vroman’s Bookstore on Monday, March 30, in a 7 p.m. conversation with journalist and author Jim Newton, a Pasadena resident. The book, published in February by Little, Brown and Company, examines the 1992 Ruby Ridge standoff — in which federal agents surveilled a cabin in Boundary County, Idaho, as part of an operation to arrest white separatist Randy Weaver — and traces a line from that 11-day siege to the conspiratorial politics that now mark American public life. By the time Weaver surrendered, his wife, his son, and a U.S. Marshal were dead. Jennings, a former editorial staffer at The New Yorker and the author of “Paradise Now: The Story of American Utopianism,” argues that the strain of apocalyptic Christianity that gripped the Weaver family can be traced to biblical prophecy readings dating to the 1870s and through the rise of 20th-century fundamentalism, according to the publisher’s description. The events at Ruby Ridge, Jennings contends, acted as an accelerant for this worldview. The New York Times Book Review called the book a thoroughly researched chronicle written with precision, according to a review published in February. Kirkus Reviews described it as a vivid reconstruction of a pivotal moment in the history of right-wing extremism. Newton, who will lead the conversation, spent 25 years at the Los Angeles Times as a reporter, editor, bureau chief, and columnist, including a stint as editor of the editorial pages from 2007 through 2010. He is the author of four books, including biographies of Chief Justice Earl Warren and Gov. Jerry Brown. Newton teaches at UCLA, where he founded Blueprint magazine, and is a columnist for CalMatters. He received the American Political Science Association’s
Phonons in Focus
Phonon lasers are used to trap and levitate nanoparticles in the laboratory of Nick Vamivakas, the Marie C. Wilson and Joseph C. Wilson Professor of Optical Physics at the University of Rochester. https://www.doi.org/10.1038/s41467-026-70564-3
Scientists solved the mystery of missing ocean plastic—and the answer is alarming
Scientists have discovered that the ocean’s “missing” plastic hasn’t vanished—it has broken down into trillions of invisible nanoplastics now spread through water, air, and living organisms. These tiny particles may be everywhere, including inside our bodies, raising serious concerns about their impact.
Brad Stevens quickly removes himself from consideration in North Carolina's coaching search
Not even one of the three best jobs in college basketball is moving Stevens out of Boston
Scientists Reinvent a Classic Material To Help Power the Future of Quantum Tech
Researchers have revisited a long-known material and uncovered a way to dramatically enhance its performance by altering its structure at the nanoscale.
My unsung hero of science: Buckminster Fuller, the architect who wanted to redesign the world (and inspired a nanosized one)
Few 20th-century scientific figures are as hard to classify as Buckminster Fuller.
Oscar-Winning Alumnus Returns to Pasadena’s ArtCenter for Entertainment Design Expo
One week after winning the Academy Award for Best Animated Feature, KPop Demon Hunters co-director Chris Appelhans returns today to ArtCenter College of Design, the Pasadena campus where he studied illustration, for the college’s third annual Entertainment Design Expo. The expo, known as ENTX, opens the Hillside Campus to the public for a full day of gallery exhibitions, game playtesting, animation screenings and interactive experiences featuring work from more than 200 ArtCenter students and alumni. General admission is free with advance registration. Two industry panels — including Appelhans’s talk — require $15 tickets. Appelhans, who graduated from ArtCenter with a bachelor of fine arts in 2002, co-directed KPop Demon Hunters with Maggie Kang. The animated film, produced by Sony Pictures Animation and released on Netflix, became the streaming platform’s most-watched film in history, according to Netflix, and swept awards season with wins at the Golden Globes, the Annie Awards and the Grammys before taking the Oscar on March 15. His talk and audience Q&A is scheduled from noon to 1 p.m. in the Ahmanson Auditorium. Doors open at 11:30 a.m. The film’s ArtCenter ties extend beyond its co-director. Art director Angela Sung, cinematographer Gary H. Lee, visual development artist Celine Kim and painter Simon Baek are all ArtCenter graduates who worked on the production, according to the college. The free portions of ENTX include a concept design showcase, a production design gallery, a model gallery, a stop motion studio preview, an alumni gallery and a KPop Demon Hunters fan art gallery. Visitors can also playtest games designed by ArtCenter students. An Animation Shorts Showcase runs from 2 to 3 p.m. and includes “Boy, I’m Scared,” a capstone short by ArtCenter graduate Lindsey Tenaglia that was named a semifinalist for the 2025 Student Academy Awards in the animation category. Also screening
China targets measurement science in tech race with U.S. - Futura-Sciences
The invisible backbone of modern technology Behind every electronic chip, satellite, and medical device sits a system of measurement. Without extreme precision in units, standards, and calibration methods, no technology operates reliably. Metrology ensures that a nanometer is actually a nanometer, that a processor performs exactly as intended at atomic...
Peer review at the service of society
Nature Nanotechnology - The peer review system, as we know it now, is a relatively recent achievement. It will still evolve to better fit the needs of science and society in the future.
Scientists create a new state of matter at room temperature using light and nanostructures
Researchers at Rensselaer Polytechnic Institute (RPI) have created a new and unusual state of matter—known as a supersolid—by engineering how light and matter interact inside a nanoscale device. The ...
M5 Max with inconsistent performance and throttling issues - Apple MacBook Pro 14 Review
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UA Little Rock to Host Hands-On Workshop on the Science of Art Conservation
Students and faculty at the University of Arkansas at Little Rock will have the opportunity to explore how chemistry helps preserve works of art during a hands-on conservation science workshop ... UA Little Rock to Host Hands-On Workshop on the Science of Art Conservation
Scientists discover molecule that stops aggressive breast cancer in its tracks
Scientists at Oregon Health & Science University have developed a new molecule that could open the door to treating triple-negative breast cancer, one of the most aggressive and difficult-to-treat forms of the disease. The compound, called SU212, targets and disables a key enzyme that cancer cells rely on to fuel their growth. In tests using humanized mouse models, the molecule caused tumors to shrink and slowed the spread of cancer by forcing the enzyme to break down.
Tickets Available for 2026 Alaska Nanooks All-Sports Banquet on April 2
FAIRBANKS - The Alaska Nanooks Department of Athletics has announced that a limited number of public tickets are now available for the 2026 All Sports Banquet, set for Thursday, April 2, 2026, at the 8 Star Event Center.
Scientists Spin Molecules Inside a Frictionless Superfluid for the First Time
A newly designed optical centrifuge allows scientists to control molecular rotation inside superfluid helium nano-droplets. Physicists have developed a new version of an optical centrifuge that can control how molecules rotate while they are suspended inside liquid helium nano-droplets. The advan
Poking a nanostring: Scientists uncover energy cascades in tiny resonators
Scientists at TU Delft have designed a nanostring that, when poked, doesn't lose its energy to the environment immediately. Instead, the energy leaks out within the string, triggering a cascade of distinct ...