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Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?

Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.

Jun 14 • 3:14 PM EDT • Technology • newsletter.semianalysis.com

'Meet the Press' host Kristen Welker reveals what Trump told her after he stormed out of interview

'Meet the Press' host Kristen Welker reveals what Donald Trump told her the morning after he stormed out of their interview taped in Wisconsin on Sunday.

Jun 12 • 2:28 PM EDT • Entertainment • ew.com

The deadly tapeworm spreading across America has reached the Pacific Northwest

A potentially dangerous tapeworm linked to severe, cancer-like disease has now been found in the Pacific Northwest, marking its first detection in wild animals along the U.S. West Coast. Researchers discovered the parasite, Echinococcus multilocularis, in 37% of coyotes tested around Puget Sound—a surprisingly high rate for a region where it had never been reported until recently.

Jun 11 • 8:00 AM EDT • Science • sciencedaily.com

Taiwan’s tallest tree found with help of citizen science

Deep in Taiwan’s misty mountains, researchers have confirmed the tallest tree in the country: a thousand-year-old fir tree higher than a 20-story building, which they’ve named “the heaven sword of the Da’an River.” Climbers scaled the tree and dropped a measuring tape from the top to the forest floor during the Lunar New Year holiday […]

Jun 8 • 3:46 PM EDT • Science • news.mongabay.com

I banned smartphones for my kids. They became obsessed with Walkmans.

Ali Hynek says introducing her children to cassette tapes and Walkmans became an unexpected alternative to smartphones and streaming.

Jun 7 • 10:52 AM EDT • Business • businessinsider.com

President Trump touts support for Wisconsin farmers

The president visited Custer Farms near Chippewa Falls, Wis. to highlight how his administration has supported farmers through new trade markets and less red tape.

Jun 5 • 6:50 PM EDT • Politics • spectrumnews1.com

French-Iranian Persepolis author Marjane Satrapi dies of ‘sadness’

Satrapi's autobiographical novel was born from her experiences of Iran's Islamic revolution and war with Iraq.

Jun 5 • 4:28 AM EDT • Entertainment • aljazeera.com

OPINION: Small businesses are backbone of Texas, El Paso, Borderland

State Sen. Cesar Blanco, D-El Paso, is pushing new laws to protect Texas small businesses from cyber threats and red tape.

Jun 4 • 8:01 AM EDT • Business • yahoo.com

Bush focuses on making Maine more business-friendly on the campaign trail

Republican candidate for governor Jonathan Bush is visiting businesses as part of his campaign and talking about the need to cut red tape to make Maine more business-friendly.

Jun 2 • 7:52 PM EDT • Business • wmtw.com

Former NFL QB impressed by Dolphins QB Malik Willis' tape

The Dolphins signed quarterback Malik Willis to be their starter this season, and his tape from his time in Green Bay is already impressing others.

May 30 • 1:22 PM EDT • Sports • sports.yahoo.com

Mamdani launched his own version of DOGE

Mayor Zohran Mamdani is launching his own government efficiency effort to cut red tape and reduce unnecessary spending in NYC.

May 28 • 12:00 PM EDT • Business • businessinsider.com

After Rich Colleges Raid Basketball Team, School Exits D1 Sports

(Bloomberg) -- Saint Francis University was out of its league, and Father Malachi Van Tassell knew it.Most Read from BloombergSingapore Hands Byju's Founder His First Ever Jail TermIran’s Khamenei Says No Going Back for Middle East Rocked by WarTwo More Oil Supertankers Exit Hormuz to Help Push Up FlowsEx-President Biden Sues to Stop DOJ Sharing Interview Tapes‘KPop Demon Hunters’ Studio Draws Tencent Music InvestmentBigger, richer universities were raiding its men’s basketball team, luring away

May 28 • 7:00 AM EDT • Sports • finance.yahoo.com

Biden's ghostwriter tapes lawsuit all about 'politics': Juan Williams

Fox News senior political analyst Juan Williams discusses why former President Joe Biden is suing the Justice Department to block the release of audio recordings on 'Special Report.'

May 27 • 9:08 PM EDT • Politics • foxnews.com

Texas Leads the Nation in Cutting Red Tape for Businesses

At the Texas Association of Business (TAB), we’ve consistently advocated for pro-business policies that strengthen Texas’ competitive edge.

May 25 • 12:20 PM EDT • Business • texasborderbusiness.com

Texas Continues Raising the Bar on Regulatory Efficiency

At the Texas Association of Business (TAB), we’ve consistently advocated for pro-business policies that strengthen Texas’ competitive edge. Cutting red tape, improving government efficiency, and streamlining regulations are essential to keeping Texas the nation’s leader in job creation, business expansion, entrepreneurship, and corporate relocations. Last week, Texas took another meaningful step in advancing our state’s…

May 20 • 3:14 PM EDT • Business • txbiz.org

Band of tech entrepreneurs sounds alarm on Colorado’s business climate

By Vince Bzdek It’s really not a headline you want to see in the national press: “Entrepreneurs Flocked to Colorado. Now Red Tape Is Driving Some Away” warned a recent Wall Street Journal article. “A vocal band of Colorado software engineers and venture capitalists,” wrote the author, “are increasingly grumbling that their tech haven in […]

May 16 • 9:28 AM EDT • Business • gazette.com

Band of tech entrepreneurs sounds alarm on Colorado’s business climate

By Vince Bzdek It’s really not a headline you want to see in the national press: “Entrepreneurs Flocked to Colorado. Now Red Tape Is Driving Some Away” warned a recent Wall Street Journal article. “A vocal band of Colorado software engineers and venture capitalists,” wrote the author, “are increasingly grumbling that their tech haven in […]

May 16 • 9:28 AM EDT • Business • denvergazette.com

NYC restaurateur accuses city officials of bombarding small businesses with red tape

NYC restaurateur Stratis Morfogen joins ‘Varney & Co.’ to sound off on mounting red tape delaying outdoor dining permits and warn how socialist-backed policies could hurt small businesses across New York City.

May 15 • 11:32 AM EDT • Business • foxbusiness.com

Why everyone’s suddenly talking about quitting antidepressants

A new push by Health Secretary Robert F. Kennedy Jr. is putting SSRI tapering — and its risks — into the spotlight.

May 14 • 6:00 AM EDT • Health • washingtonpost.com

Halley’s comet may be named after the wrong person

A medieval monk may have beaten Edmond Halley to one of astronomy’s greatest discoveries by nearly 700 years. Researchers say Eilmer of Malmesbury recognized that the blazing comet seen in 1066 was the same one he had witnessed in 989. At the time, comets were viewed as terrifying omens tied to war and royal deaths, adding even more drama to the famous celestial event shown in the Bayeux Tapestry. The discovery is sparking debate over whether Halley’s Comet deserves a different name.

May 13 • 8:00 AM EDT • Science • sciencedaily.com

Linux bitten by second severe vulnerability in as many weeks

Production-version patches are coming online and should be installed pronto.

May 11 • 6:28 PM EDT • Technology • arstechnica.com

It’s like living a John Hughes movie — and shows the limits of nostalgia

“Mixtape,” an interactive love letter to adolescence, is easy to recommend to almost anyone. It’s also a reminder of the industry’s current limits.

May 9 • 7:00 AM EDT • Entertainment • washingtonpost.com

Reno tests cutting red tape for live entertainment downtown, Midtown

A pilot program will cut the permitting process for new businesses in Midtown and downtown offering indoor live entertainment.

May 8 • 3:01 PM EDT • Entertainment • rgj.com

Coming to Xbox Game Pass: Forza Horizon 6, Mixtape, Subnautica 2, and More

Coming to Xbox Game Pass: Forza Horizon 6, Mixtape, Subnautica 2, and more!

May 5 • 9:00 AM EDT • Technology • news.xbox.com

'Running through the tape': Ron DeSantis addresses future plans, says he has plenty of time to run for President

The future holds possibilities, but DeSantis is playing his cards close to his chest.

May 4 • 7:30 PM EDT • Politics • floridapolitics.com

EDITORIAL: Normalization of misconduct in U.S. politics

President Donald J. Trump's 2016 presidential campaign propelled conversations regarding sexual assault into the national spotlight. A handful of women slowly began coming forward with allegations of unwanted advances and perverse comments over the course of the election cycle, and concerns were further solidified after a secret recording from a 2005 Hollywood Access tape was leaked. Trump had been caught on a hot mic stating he was able to touch women as he pleased, and due to his social status as a "star," they would let him do it. The New York Times published a series of interviews from individuals who had both witnessed and experienced his inappropriate behavior soon after.

May 4 • 9:13 AM EDT • Politics • dailytargum.com

Xbox gets over 20 new games next week

Another 21 new games are coming to Xbox and PC next week, including Mixtape, Motorslice, Froggy Hates Snow, and Will: Follow The Light.

May 3 • 6:00 AM EDT • Technology • trueachievements.com

Next Week on Xbox: New Games for May 4 to 8

Next Week on Xbox: Mixtape, Wax Head, Axe Cop, Froggy Hates Snow, and more coming soon!

May 1 • 10:00 AM EDT • Technology • news.xbox.com

Follow In-Car Entertainment From 1926 to Today

Explore the evolution of in-car entertainment, from early radios and tape decks to CDs, rear-seat screens, and today’s connected infotainment systems.

Apr 29 • 8:00 AM EDT • Entertainment • kbb.com

In pictures: Record entry for cycling's Etape Loch Ness

The event follows a 66-mile (106 km) route, which starts and finishes in Inverness.

Apr 27 • 8:28 AM EDT • Sports • sports.yahoo.com

Officers reportedly injured in shooting at Swedish Hospital in Lincoln Square

Police were en route to what may be an active shooter situation.

Apr 25 • 12:53 PM EDT • Health • chicago.suntimes.com

Small Business Grant recipients announced

ELKINS – Woodlands Development & Lending is proud to announce recipients of its Spring Forward Small Business Grant Opportunity. Officials received more than 80 proposals for this quick-turnaround, $500 grant and were able to make 22 awards to small businesses located throughout the Mon Forest Region of West Virginia. Local food establishments, recreation outfitters, small […]

Apr 23 • 8:00 PM EDT • Business • theintermountain.com

Renner's final NFL Draft big board: Ranking 250 prospects in a wild 2026 class

Tape grades, positional value, age and intangibles shaped Mike Renner's final rankings in a uniquely volatile class

Apr 21 • 9:00 AM EDT • Sports • cbssports.com

Business Buzz: Douglas County’s war on red tape and the $217 million swipe fee debate

Apr 20 • 1:53 PM EDT • Business • 9news.com

Le Pen, Bardella offer to slash red tape in overture to business leaders

French far-right leaders are on a mission to woo the business community ahead of the 2027 presidential election.

Apr 20 • 6:00 AM EDT • Business • politico.eu

The Science Of Taper As Preparation For Swim Performance

After months of research, Cooper Gill found that taper matters more than most people think, and the biggest factor isn’t fitness, it’s fatigue.

Apr 17 • 8:30 AM EDT • Science • swimswam.com

UNC Hussman offers new sports play-by-play class | UNC Hussman School of Journalism and Media

This story, written by UNC Hussman alumna Caroline Daly ’24, was originally published on unc.edu. The UNC Hussman School of Journalism and Media has a new, hands-on class available for students interested in sports careers. Students in “MEJO 390: Sports Commentary and Play-By-Play” can call live radio broadcasts for Carolina sporting events, streamed live on the Go Heels website. This spring, 11 students are calling mostly softball games to gain experience and learn the preparation needed for a successful broadcast. The class is capped at a small number to provide consistent, individual feedback. Matt Krause, the radio voice of Carolina women’s basketball, teaches the class to help students sharpen their skills, using his experience with the Tar Heels and calling games for ACC Network and ACC Network Extra. “There is no substitute for live reps, and that is the only way you get better. The classroom component teaches you how to get better, but going about that requires sitting in that chair, making mistakes and being able to know your broadcast is going somewhere,” Krause said. “These students are doing real live games, and they will have tape where if they want to pursue this. They will have ready-made demos to send for jobs. Being able to utilize all the resources of UNC, GoHeels Productions and the Carolina Athletics brand and create these opportunities for students is really impactful.” In the class, students learn fundamentals like how to announce starting lineups for different sports and how to conduct research before games. Krause has led the class in mock preparation exercises, looking at game charts with information about the different teams and players that they can refer to at pivotal moments during the game. Krause and the students then critique each other, listening to clips from the past week to find ways to improve. It’s a rare class without a slew of quizzes or assignments. Their main tasks are calling games and making a portfolio or demo reel of their best calls at the end of the semester, all with the goal of being ready to step into similar roles after graduation. Laible live streams her coverage on the GoHeels website. Calling a live game while broadcasting her coverage allows her to get hands on experience. (Jon Gardiner/UNC-Chapel Hill) Junior Anna Laible ’27 wished for a class just like this. Her first year at Carolina, she interned with the Coastal Plain League, where she was introduced to play-by-play for baseball. “I enjoy the challenge and uncertainty of each game being different because each sport looks a little different,” said Laible. “Each game is different — not just with teams but what could happen with certain records being broken or random trends. That’s what I enjoy most.” She wanted more opportunities for reps during college to prepare for a career after Carolina, so she pitched an idea for the class to Livis Freeman ’99, distinguished associate professor of sports communication. Laible and Freeman reached out to GoHeels Productions for a partnership and then connected with Krause. “This is how at UNC Hussman we separate ourselves: Our students go into the field ready,” said Freeman. “The biggest compliment we get it is when our students start their careers, they don’t need any hand-holding.” Laible calls a Carolina softball game at Kessing Stadium – after pitching the idea to Hussman faculty. Her interest in sports commentary allowed her to apply her interest as she attends Carolina. (Jon Gardiner/UNC-Chapel Hill) Laible is now a student in the class, which has helped her strengthen her skills and deepen her passion for the field. The goal is to expand to other sports like soccer, lacrosse and field hockey. “The hands-on experience I’ve gotten here is invaluable. I’ve loved the classes and professors because they’ve taught me a lot, but it’s also the things outside of class, too, that have helped me grow,” said Laible. “Since being at UNC, I’ve grown a lot in the versatility, from doing writing to production and commentating. UNC Hussman and Carolina have given me the ability to be strong and well rounded.”

Apr 16 • 9:07 AM EDT • Sports • hussman.unc.edu

Politics and the Bayeux Tapestry: the inside story of the blockbuster loan to the British Museum

History’s most famous embroidery has sparked endless fascination and controversy over the circa 950 years since its creation. In the run-up to its arrival in London, David Musgrove spoke to the UK Government’s Envoy for the Bayeux Tapestry Loan, Lord Peter Ricketts

Apr 16 • 6:44 AM EDT • Politics • historyextra.com

He recorded 10,000 concerts on tape, now they’re streaming for free

The music collection of a 59-year-old Chicago man who attended more than 10,000 concerts and recorded each one on cassette tape is slowly being digitized and released online for free. Like many Gen…

Apr 12 • 9:29 PM EDT • Entertainment • ktla.com

Teddy bears to ticker tape: UVA Center for Politics opens new space

The expanded facility opens Friday with an exhibit of historical campaign memorabilia, from Washington to Trump.

Apr 8 • 4:12 PM EDT • Politics • news.virginia.edu

Comptroller Review Finds City's Small Business Forward Program Failed to Cut Red Tape or Limit Fines

New York, NY — A new review conducted by auditors of New York City Comptroller Mark Levine found the Small Business Forward program, aimed at easing regulatory and financial burdens on small businesses across the five boroughs, failed to achieve meaningful change for small businesses in New York City. Vague definitions, a lack...

Apr 8 • 2:56 PM EDT • Business • comptroller.nyc.gov

Mayor Mamdani appoints 'mom and pop czar' to reduce red tape for NYC small business owners

Delia Awusi was hired to reduce the runaround mom and pop small businesses often face in dealing with permits, inspections and fines.

Apr 7 • 11:20 PM EDT • Business • abc7ny.com

Kansas governor warns of Legislature’s ‘political games,’ ‘micro-managing’ in eight-bill veto spree

Kansas Gov. Laura Kelly shot down legislation riddled with “bureaucratic red tape,” “political games” and “micro-managing” as part of her Monday veto spree.

Apr 7 • 5:07 PM EDT • Politics • kansasreflector.com

After howls from clubs, Syracuse cuts the red tape choking music venues

The Syracuse Common Council approved the new rule Monday after an old ordinance was resurrected when violence erupted after a show at the Westcott Theater.

Apr 7 • 6:02 AM EDT • Entertainment • syracuse.com

JPMorgan Chase CEO Jamie Dimon warns of business 'exodus' from NYC as Mamdani, lefty pols push for tax hikes

JPMorgan Chase CEO Jamie Dimon issued a thinly veiled warning to New York City Mayor Zohran Mamdani on Tuesday, saying crushing taxes and red tape are already sparking a “large exodus” of...

Apr 6 • 9:59 AM EDT • Business • nypost.com

Shroud of Turin, claimed to be Jesus' burial cloth, contaminated with carrot and red coral DNA

An analysis of samples taken from the Shroud of Turin, the cloth thought by some to have been wrapped around Jesus, reveals a rich tapestry of animal and plant DNA. But what does it mean?

Apr 5 • 7:00 AM EDT • Science • livescience.com

What Sea Creatures Reveal About How Fast People Age

By Carole Tanzer Miller HealthDay ReporterSUNDAY, April 5, 2026 (HealthDay News) — This is no ordinary fish story. Researchers who videotaped every moment in the lives of 81 African turquoise killfish gleaned intriguing insights into the aging process that may also apply to humans. Though killfish ...

Apr 5 • 6:30 AM EDT • Health • usnews.com

Influencers tout injectable peptides as key to youth and beauty. Scientists say they're 'a giant scam'

Crocodile dung. Tapeworms. Raw meat facials. Yes, at some point in history these wildly popular — and wildly unproven — treatments were how people tried to stay young. Right now, plenty of influencers will tell you that injectable peptides are the answer. But the scientists? Not so much.

Apr 5 • 4:00 AM EDT • Science • cbc.ca

Building a more business-ready Douglas County

If you keep up on state business news, you’ve seen the headlines. Major companies like Palantir are moving out of Colorado, and statewide, there is a sense that it’s getting…

Apr 2 • 4:18 PM EDT • Business • douglas.co.us

Apollo and FC Barcelona just proved legacy markets are losing their grip on business

New York and California built dominance over decades. But costs, regulation and red tape is pushing companies and capital to states like Florida.

Apr 2 • 3:46 PM EDT • Business • fortune.com

States Pay Deloitte, Others Millions To Comply With Trump Law To Cut Medicaid Rolls

The One Big Beautiful Bill Act will add red tape and restrictions for those seeking Medicaid and SNAP benefits. And the costs to update computer systems that determine eligibility for those programs will be steep.

Mar 31 • 5:00 AM EDT • Health • kffhealthnews.org

4 teenagers injured in shooting while leaving a Minneapolis business, suspect still at large

Four teenagers were injured late Friday night when they were shot as they were leaving a Minneapolis business along Lake Street West.

Mar 21 • 9:06 AM EDT • Business • kstp.com

The biggest medieval march in English history never actually happened

A famous detail in the Battle of Hastings is based on a major misunderstanding.

Mar 20 • 8:01 PM EDT • Science • popsci.com

Science explains why removing adhesive tape makes that unbearable squeaky noise

Scientists discover why adhesive tape makes that squeaking noise when peeled off: tiny shock waves produce the high-pitched sound.

Mar 19 • 10:30 AM EDT • Science • earth.com

First MacBook Neo teardown praises 'absolutely amazing' repairability

"No sticky tape, no tricky adhesives, modular parts... it's just super straightforward, elegant design."

Mar 12 • 2:28 PM EDT • Technology • macworld.com

MacBook Neo Teardown: Modular Ports, Glue-Less Battery, Zero Tape

A teardown of the new MacBook Neo by Australian YouTube repair channel Tech Re-Nu reveals what may be the most modular and repair-friendly Mac laptop in recent times. The Neo is shown being taken apart in just six minutes, suggesting Apple has prioritized simplicity across the board, using standard Torx screws (T3, T5, and T8) and a clean cable routing design. To open the aluminum body, eight screws on the bottom are loosened, similar to the MacBook Air and MacBook Pro.

Mar 12 • 9:43 AM EDT • Technology • macrumors.com

Alexander Butterfield, Who Revealed Nixon Tapes in Watergate Scandal, Dies at 99

“There is tape in the Oval Office,” said Mr. Butterfield, a former White House aide, in testimony that rocked the Watergate hearings and led to the president’s resignation.

Mar 9 • 3:29 PM EDT • Politics • nytimes.com

This Overlooked Health Condition Could Raise Your Risk of Death by 83%

A study following more than 5,000 participants for 12 years found that straightforward clinical measurements can help identify sarcopenic obesity without relying on complex imaging methods such as MRI and CT scans. Researchers from the Federal University of São Carlos (UFSCar) in Brazil, working

Mar 8 • 8:38 PM EDT • Health • scitechdaily.com

‘Have I Got News For You ’ comedians roll the tape on Markwayne Mullin

Mar 7 • 8:57 PM EST • Politics • cnn.com

Drew Carey once ignored a heart attack and went back to work

Drew Carrey is looking back at the day in 2001 when he went out to dinner with his girlfriend and then taped his sitcom not knowing he’d just had a heart attack: 'I thought if you had a heart attack, you would go, "Ugh," and fall down like in a cartoon.'

Mar 6 • 2:26 PM EST • Entertainment • ew.com

Kotek signs bill to cut red tape for Oregon behavioral health workers

The bipartisan law streamlines licensing and supervision rules, aiming to get more mental health workers into practice faster.

Mar 5 • 10:13 PM EST • Health • oregonlive.com

Scientists Found a Way to Store All of Our Data on Pieces of Glass Forever (Almost)

A research team figured out a way to write data onto wafers of glass using lasers, and unlike, for example, a magnetic tape, that glass can hold the data for 10,000 years.

Mar 4 • 9:00 AM EST • Science • popularmechanics.com

Galaxy S26 Ultra’s Horizon Lock Feature Was Tested To Its Limits By Being Taped On A Functioning Drill Machine; The Results Were Downright Impressive

The Horizon Lock feature on the Galaxy S26 Ultra was tested to the extreme as Samsung’s flagship was taped to a powered drill machine

Mar 1 • 8:48 PM EST • Technology • wccftech.com

VHS tapes are now worth big bucks. These N.J. shops are cashing in on the retro rewind.

VHS rentals are back and collectors are in search of rare tapes — check your stash!

Mar 1 • 7:00 AM EST • Technology • nj.com

Heli-Skiing in California Seemed Like a Pipe Dream. Then These Two Guys Showed Up.

Two ski industry mavericks believe they’ve discovered the secret of operating a heli-skiing business in the Golden State, where red tape, finicky snowfall, and plenty of danger have torpedoed past operations

Feb 27 • 10:02 PM EST • Business • outsideonline.com

BigXthaPlug And 600 Entertainment Make Noise For Texas With “6WA”

The Dallas rapper and his crew represent their home state and salute the West Coast on the first single from their upcoming mixtape of the same name

Feb 27 • 6:08 PM EST • Entertainment • yahoo.com

BigXthaPlug and 600 Entertainment Make Noise for Texas With ‘6WA’

The Dallas rapper and his crew represent their home state and salute the West Coast on the first single from their upcoming mixtape of the same name

Feb 27 • 12:00 PM EST • Entertainment • yahoo.com

Understanding the science of sports tape

That kinesiology tape you see on elite athletes is more than a joint stabilizer. It plays a much bigger role

Feb 22 • 10:30 PM EST • Science • deseret.com

Eric Dane Taped Final Interview Before His Death From ALS — And Left A Message For His Girls

The "Grey's Anatomy" and "Euphoria" actor, 53, agreed to be interviewed on the condition that the footage be released after his death.

Feb 20 • 1:56 PM EST • Entertainment • huffpost.com

DAV announces new partnership with Solace Health supporting veterans’ care

ERLANGER, Ky. – DAV (Disabled American Veterans) is proud to announce a new partnership with Solace Health as its first new partner in 2026. The partnership is supported by a donation from Solace Health to advance DAV’s mission of empowering veterans to lead high-quality lives. The collaboration brings together two organizations focused on helping veterans receive timely, coordinated, high-quality care, regardless of where they receive it. While many veterans receive care through the VA, which offers an integrated and coordinated whole-health model, others receive some or all of their care through private health systems using Medicare or other insurance benefits. These veterans often need help to understand health insurance rules, manage their treatment, and navigate between multiple health care systems. “Disabled veterans often have complex health challenges, and DAV’s advocacy work strives to minimize barriers to timely, high-quality care, primarily within VA., but increasingly between VA and private providers,” said DAV CEO and National Adjutant Barry Jesinoski. “Our partnership with Solace Health can offer support for veterans who are eligible for VA care and Medicare, particularly those who split their care between the VA and private health systems. Veterans who don’t use VA at all can also benefit from the care coordination services that Solace Health provides, usually with little or no out-of-pocket cost to them.” Solace Health provides professional health care advocacy services, connecting patients with experienced advocates who help schedule appointments, explain benefits, coordinate care among providers, and manage administrative burdens with private health care systems, thereby allowing veterans and their families to focus on health and recovery. “For many veterans, the fight doesn’t end when service does,” said Jeremy Gurewitz, CEO and co-founder of Solace Health. “Veterans living with serious medical conditions often encounter a private health care system outside of the VA that is fragmented and difficult to navigate. Through this partnership with DAV, Solace Health advocates can help cut through red tape, improve care coordination, and simplify scheduling of medical appointments. We’re proud to support DAV in helping veterans to successfully navigate health care systems so that veterans, particularly disabled veterans, receive the care they have earned.” DAV provides a lifetime of support for veterans of all generations, their families, caregivers, and survivors. Each year, DAV’s no-cost programs and services help more than 1 million veterans access the benefits and health care they have earned, connect with meaningful employment, and ensure their voices are heard on Capitol Hill. About DAV DAV is dedicated to ensuring our promise is kept to America’s veterans. DAV does this by helping veterans and their families access the full range of benefits available to them, fighting for the interests of America’s injured heroes on Capitol Hill, providing employment resources to veterans and their families, offering programs and services to empower them, and educating the public about the great sacrifices and needs of veterans transitioning back to civilian life. A nonprofit organization with nearly 1 million members, DAV was founded in 1920 and chartered by the U.S. Congress in 1932. About Solace Health Veterans face complex health challenges, and the path to care is far harder than it should be. They deal with fragmented services and providers, each with unique requirements and paperwork. Solace Health advocates—healthcare experts with 16 years’ experience on average—help veterans navigate this landscape when they need it most. Advocates schedule appointments, explain benefits and keep doctors aligned. They take the lead on calls and documentation, and their no-homework ethos eases burdens on veterans and their families. Solace Health is covered by Medicare and Medicare Advantage, and most veterans pay little or nothing out of pocket. We’re honored to support DAV members.

Feb 18 • 1:37 PM EST • Health • dav.org

Stone, parchment or laser-etched glass? Scientists find new way to preserve data

Hard disks and magnetic tape have a limited lifespan, but storage developed by Microsoft could last for millennia

Feb 18 • 11:00 AM EST • Science • theguardian.com

New on DVD: Prepare for frights when 'Man Finds Tape'

A found footage horror film tops the DVD releases for the week of Feb. 24. "Man Finds Tape": A brother and sister return to their Texas hometown to investigate surveillance

Feb 17 • 11:56 AM EST • Entertainment • recorderonline.com

Ray J performs with bleeding eyes weeks after revealing he has months to live

Singer Ray J performed a concert on Saturday with what appeared to be bleeding eyes and something taped to his chest, weeks after claiming he only has months to live: 'I'm putting my life on the line for this show!'

Feb 16 • 5:03 PM EST • Entertainment • ew.com

After deaths, protests and political backlash, ICE surge set to end in Minnesota

Feb 12 • 6:55 PM EST • Politics • pbs.org

Louisville Takes Down Syracuse 84-65

Louisville must’ve watched the tape from the Duke game Thursday night and thought “oh hey coming out high energy and smothering the other team is a great way to start the game let’s try that!” The Cards literally held Syracuse scoreless from the field for the entire first quarter and went into the 2nd up […]

Feb 8 • 3:11 PM EST • Sports • cardchronicle.com

AI is now part of Coach and Kate Spade designers' workflow

Tapestry's CEO said the initial sketches of bags and shoes are done by hand, but AI tools help tweak designs and test different colorways.

Feb 6 • 12:07 AM EST • Business • businessinsider.com

Marine biologists discover 28 new deep sea species—and an old VHS tape

The level of ocean biodiversity near Argentina staggered researchers.

Feb 4 • 3:03 PM EST • Science • popsci.com

Sports on the Air for Tuesday, February 3: TV, radio schedule in Kansas City

See the television and radio listings for live and same-day taped sporting events in the Kansas City area for Tuesday, February 3.

Feb 2 • 5:39 PM EST • Sports • sports.yahoo.com