SCROLL NEWS / DISCOVERY
Search headlines
Find the stories shaping the conversation.
Results for " device " 1,721 found 🔀 AI-powered Shuffle
Navigating the American Dream: How Integrated Financial Tools, Credit and Rewards Can Help Small Businesses Succeed
(Feature Impact) Owning a small business has been a cornerstone of the “American Dream” for generations. It represents the chance to transform a passion into a livelihood and legacy. However, turning dreams into reality is rarely a smooth or easy process and requires more than ambition alone. Today’s business owners need support and access to tools that enable them to overcome challenges and keep growing.#placement_678081_0_i{width:100%;margin:0 auto;}var rnd = window.rnd || Math.floor(Math.random()*10e6);var pid678081 = window.pid678081 || rnd;var plc678081 = window.plc678081 || 0;var abkw = window.abkw || '';var absrc = 'https://ads.empowerlocal.co/adserve/;ID=181918;size=0x0;setID=678081;type=js;sw='+screen.width+';sh='+screen.height+';spr='+window.devicePixelRatio+';kw='+abkw+';pid='+pid678081+';place='+(plc678081++)+';rnd='+rnd+';click=CLICK_MACRO_PLACEHOLDER';var _absrc = absrc.split("type=js"); absrc = _absrc[0] + 'type=js;referrer=' + encodeURIComponent(document.location.href) + _absrc[1];document.write('');Recent research conducted by the Capital One Insights Center shows 75% of more than 1,000 surveyed small business owners with more than one employee and annual revenues of up to $20 million are confident about the future, and 69% believe their business is actively primed for growth.While this optimism is promising, 47% of business owners still said their operations either stayed the same or became less efficient over the past year, citing issues like back-office friction and fragmented financial systems that make it difficult to get a clear picture of the health of their businesses.If you’re a small business owner eager to grow but not sure how to get there, start with this advice from real small business owners and experts at Capital One.Identify Sources of FrictionBefore you can pour effort into growth, you must understand what barriers are holding you back. Take time to look under the hood of your business to identify where time and energy is being lost.For example, you may be among the 78% of small business owners who feel stressed and uncertain about expense management – think hours spent hunting for receipts, manually entering numbers into software and reconciling accounts. Operational challenges aren’t just a hassle; they also pull attention away from important priorities like serving your customers and planning for growth. “We were focused on making as many candles as possible, especially during the busy season,” said Katie Roering, co-owner of Fontana Candle Co. “A lot of the back-office tasks like procurement, raw material purchasing, forecasting – all the really important things – were done at 3 a.m., 8 p.m. or on Saturday and Sunday, and there really just was not enough time in the day to get everything done that we needed to. We just knew as we continued to grow, we needed to streamline our processes, build out our team and keep moving forward.”Use Integrated Tools to Manage FinancesInstead of balancing 10 different tracking and analysis tools, you can turn to one-stop solutions to improve efficiency. Time gets lost when you’re forced to manually gather and interpret relevant data before you’re able to act. You need a platform that handles the busywork for you.Integrated, or “all-in-one,” financial tools – like accounting and bookkeeping platforms with automation capabilities or business credit cards featuring built-in analytical tools – allow you to easily stay on top of cash flow and day-to-day operations. For small businesses where every hour and dollar makes a difference, consolidating and automating systems can have an immediate impact. In fact, 51% of survey respondents said integrated tools have already fueled their growth.Leverage Credit Access and Rewards WiselyGrowth requires capital, so access to credit is a game-changer for many business owners, with 77% describing it as a key factor in achieving business resilience. Having funds accessible when you need them makes your business more capable of weathering storms such as equipment failures and seasonal slowdowns. It also puts the power in your hands to act when an exciting opportunity presents itself, like an inventory flash sale or the chance to advertise in a new market.Access to credit comes with another advantage: rewards. By using credit cards for your daily business expenses, you can earn cash back, points or travel rewards. Whether you redeem these to cover everyday expenses, book business trips or reinvest in the business, they can act as a bonus source of income. Learn to maximize rewards like the 84% of small business cardholders surveyed so you aren’t leaving money on the table.To learn more about how small business owners can identify obstacles, employ integrated financial tools and use credit as a tool for growth, read the full report at capitalone.com/about/insights-center.Photos courtesy of Shutterstock
The iPhone 18 Pro Max Has One Downside Almost Nobody Is Talking About
Reviews of the iPhone 18 Pro Max have been largely positive, but there is one major flaw with the device that is largely being ignored.
The GL.iNet Mango 2 Is A Pocket-Sized Wi-Fi Travel Router With VPN
With its slim design, easy setup, VPN support and multi-device connectivity, the Mango 2 is made for travelers who need reliable connectivity in a portable form factor.
Colorado recalls marijuana vape company's products sold at more than 400 stores
Colorado public health and marijuana regulation authorities issued on Friday a recall of marijuana vape devices believed to be contaminated with a volatile industrial solvent.
UCLA receives $75 million in NSF grants for quantum technology
Two UCLA quantum computing institutes received grants from the National Science Foundation worth a combined $75 million Aug. 25. The institutes – Fault-Tolerant Quantum Systems, Architectures and Applications and Challenge Institute for Quantum Computation – aim to advance quantum technologies, which function faster than classical computers or standard digital devices.
This External GPU Uses Wi-Fi To Transform Any Device Into A Gaming Rig
The WiCi One is available for preorders starting at $1,999.
How Long Does The New Siri AI Take To Activate On iOS 27?
Apple users say they waited anywhere from a few hours to nearly a week before the revamped Siri AI finally arrived on their devices.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. [1] Intel, “Intel Tech Tour 2025 Panther Lake recap,” Doc. 866361, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/866361/ITT_2025_Panther_Lake_Recap1.pdf [2] Intel, “Core Ultra processors Series 3 datasheet, volume 1,” Doc. 872188-001, Jan. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/872188/872188-001.pdf [3] N. Horiguchi and E. Beyne, “Backside power delivery: How to power chips from the backside,” imec Reading Room, Nov. 25, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/how-power-chips-backside [4] W. Hafez et al., “Intel PowerVia technology: Backside power delivery for high density and high-performance computing,” in Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2, doi: 10.23919/vlsitechnologyandcir57934.2023.10185208. [5] K. Fischer et al., “Intel 18A platform technology featuring RibbonFET (GAA) and PowerVia for advanced high-performance computing,” in Proc. Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2025, pp. 1–3, doi: 10.23919/vlsitechnologyandcir65189.2025.11075006. [6] K.-F. Cheng, C.-L. Teng, H.-Y. Huang, and H.-C. Chen, “Metal oxide composite as etch stop layer,” U.S. Patent 12 176 247 B2, Dec. 24, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12176247B2/en [7] S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS J. Solid State Sci. Technol., vol. 4, no. 1, pp. N3029–N3047, 2015, doi: 10.1149/2.0051501jss. [8] A. V. Mule’, D. J. Towner, D. Seghete, C. R. Ryder, and A. A. Gonzalez, “Multi-layer etch stop layers for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20220102343 A1, Mar. 31, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20220102343A1/en [9] C.-C. Wang and J. H. Wang, “Interconnect structure with dielectric cap layer and etch stop layer stack,” U.S. Patent Appl. 20230253247 A1, Aug. 10, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20230253247A1/en [10] Y. J. Wu, K.-F. Cheng, C.-C. Lee, H.-K. Chang, and H.-Y. Huang, “Etch stop layer for interconnect structures,” U.S. Patent Appl. 20240332070 A1, Oct. 3, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240332070A1/en [11] M. G. Rainville, N. Shankar, K. S. Reddy, and D. M. Hausmann, “Deposition of aluminum oxide etch stop layers,” U.S. Patent Appl. 20180197770 A1, Jul. 12, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20180197770 [12] J. S. Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240112951A1/en [16] Applied Materials, “Applied Materials unveils chip wiring innovations for more energy-efficient computing,” Applied Materials Investor Relations, Jul. 8, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy [17] Samsung, “Samsung showcases AI-era vision and latest foundry technologies at SFF 2024,” Samsung Semiconductor, Jun. 13, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/ [18] C. W. Yeung et al., “Channel geometry impact and narrow sheet effect of stacked nanosheet,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2018, pp. 28.6.1–28.6.4, doi: 10.1109/iedm.2018.8614608. [19] S. Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
Health and Safety Advisory issued after contaminated marijuana vaporizers sold at over 400 stores in Colorado
The Colorado Department of Public Health and Environment (CDPHE) has issued a health and safety advisory after contaminated "Regulated Marijuana Vaporizer Delivery Devices" were sold at 400+ stores
Apple (AAPL) Plans a Health App Overhaul. Can Better Insights Boost Device Sales?
On September 9, 2026, the Wall Street Journal reported that Apple Inc. (NASDAQ:AAPL) is undertaking a major overhaul of its Health app and Apple Watch strategy. It debuts the Apple Watch Series 12 and Ultra 4 with an upgraded Health Sensing System alongside an Apple Intelligence-driven software redesign coming to iOS 27 that introduces a […]
Google Health 5.09 arrives with more than just your new Pixel Watch features
Learn about all the changes present in this week's Google Health 5.09 update, arriving for both Android and iOS devices.
Pokémon card collector used GPS device to track delivery woman
After 30 years, Pokémon remains among the most desirable collectible franchises in fandom and auctions regularly prove the cards' growing value. But one collector went too far in his efforts…
New kind of AI audio chip transforms earbuds into always-on 'intelligent' devices that run without a smartphone. How does it work?
A new AI audio chip will give future headphones on-device apps and sensors that gather data about your daily movements to feed AI "agents" that will speak directly into your ear.
FDA seeks new regulatory science framework for innovative tech
The FDA is taking stock of the regulatory tools it will need for the next decade to keep up with AI and medical device innovation.
iPad Mini 8 Leaked: A20 Pro Chip, Landscape Camera, and More
Apple's next-generation iPad mini will feature the A20 Pro chip, a rearranged front-facing camera, and a new speaker system, leaked code reveals. The information originates from Apple's own code (spotted by MacRumors contributor Aaron Perris) and also shows clear product images of the new iPad mini. Although images of the device only show the front, leaving any design changes of the rear or side profile unknown, there are still visible changes.
iPhone Duo video shows left-handed use for new model
Many prospective iPhone Duo buyers may be wondering how well the device will work in left-handed use, here’s a video that shows one example.
Meta debuts Tamagotchi-style AI agent
Meta is creating a tiny, portable Muse Charm device for carrying around the company's AI agent, CEO Mark Zuckerberg has announced.
Microsoft Copilot+ Branding Disappears from Latest Surface PCs
Microsoft's recent Snapdragon-powered Surface Laptop and Surface Pro launch was surprisingly absent the usual Copilot+ branding, aside from as a callout to the inclusion of the actual AI assistant on the devices. Apparently, this was an intentional branding change, according to Surface Corporate...
WHO announces expansion of prequalification programme for medical devices
WHO) today announced a major expansion of its prequalification programme to include a wider range of life-saving medical devices such as contraceptives and innovative tuberculosis (TB) screening technologies.
What's Gone in macOS Golden Gate and What's Next in macOS 28
With macOS Golden Gate, Apple phased out several legacy features and services, cutting support for older devices and accessories. More cuts are coming in macOS 28 as Apple continues to root out lingering Intel features. Here's everything that's been dropped. Support for Intel Macs - macOS Golden Gate is the first version of macOS that runs only on Apple silicon Macs. Intel Macs can't run it and are limited to macOS Tahoe. Apple still plans to offer security updates through fall 2028.
Meta gets to consumer AI device market before OpenAI, but Zuckerberg's strategy remains unproven
Meta CEO Mark Zuckerberg's new Muse Charm device is intended to put his company ahead of rivals like OpenAI and Google in AI agents and consumer hardware.
Google rolling out Android 17 QPR2 Beta 6 for Pixel
Android 17 QPR2 Beta 6 is now available for Pixel devices, barely a week after Beta 5 launched. Beta 6...
Microsoft’s New Surface Laptops Embody the PC-Phone Marriage Snapdragon Promised Years Ago
Qualcomm's PC chips were developed with the company's phone DNA. Two generations in, we're seeing payoffs.
Chrome now saves scroll position, filled forms when sending tabs between devices
Google today announced new study-focused Chrome features, with the most notable being how the browser will now save scroll position...
Now Google Chrome shares tabs to new devices that save where you were
Pick up where you left off.
Meta's New AI Device Is This Tamagotchi-Like Muse Charm Keychain
Meta says the keychain will be ready to ship by the holiday season, like some kind of bizarre AI stocking stuffer.
Distant time crystals can somehow fall into the same rhythm
Researchers have shown that multiple time crystals inside a semiconductor can synchronize their oscillations, much like pendulum clocks gradually falling into the same rhythm. The coupling is carried by spin-polarized electrons, allowing time crystals separated by up to 40 micrometers to lock to a common frequency. The discovery reveals surprisingly long-range connections between these exotic spin systems and could help researchers develop future spin-based devices.
ECU Health celebrates nine years of ventricular assist device program
GREENVILLE, N.C. — ECU Health marked nine years of its Ventricular Assist Device program at ECU Health Medical Center on Sept. 23.The health system hosted its n
Meta's Charm gadget carries CEO Zuckerberg's big AI ambitions
Mark Zuckerberg took repeated digs at Apple during Meta's annual event on Wednesday, only to borrow a page from Steve Jobs' playbook for a surprise reveal: a pocket-watch-sized device that carries Meta's viral Muse AI agent into the real world.
Meta made a Tamagotchi-like wearable for its Muse AI agent
The tiny hardware device creates another mobile home for its AI agent Muse.
Meta gives Muse more power, teases handheld AI device
Meta is giving Muse more power, will add to handheld device, smart glasses.
Verizon's Pixel 11 Pro Deal Drops $620 Off With No Trickery
The best Pixel 11 Pro deal is at Verizon, where you can save $620 off at full retail, no contract or device payment plan required.
Meta Announces 'VR Glasses' Next-Gen XR Headset, Priced at $1,300
Meta today unveiled its long-awaited next-gen mixed reality headset: Meta VR Glasses. Previously known under the codename ‘Project Phoenix’, Meta VR Glasses was announced today, but isn’t launching just yet; the compute puck-tethered device is slated to go one sale sometime in Spring 2027, priced at $1,300. While we’re still waiting on a precise release […]
Microsoft refreshes its smaller Surface Pro and Laptop with Qualcomm’s X2 Plus
Microsoft’s smaller Surface devices keep the same design with upgraded internals
iOS 27.0.1 is Coming Soon
After releasing iOS 27 last week, Apple is already testing a follow-up iOS 27.0.1 update for iPhones, according to MacRumors logs. iOS 27.0.1 will likely be a minor update with bug fixes and/or security patches. Shortly after Apple launches new iPhone models, some software bugs are usually discovered as the devices get into the hands of millions of customers around the world.
Qualcomm announces Snapdragon Sound Elite Gen 2 for AI ‘hearables,’ even ones with cameras
Qualcomm announced the Snapdragon Sound Elite Gen 2 as a substantial chipset for upcoming audio devices, with a massive focus...
Kennedy announces an investigation into EMF and radiofrequency radiation
Health Secretary Robert F. Kennedy Jr. said in a video, “Wireless technology touches nearly every part of American life: cell phones, Wi-Fi, smart meters, wearable devices, wireless medical devices, 5G and emerging technologies like…
AT&T Responds to iOS 27's New iPhone Handoff Feature
Apple added a new iPhone Handoff feature to iOS 27 that allows you to switch between two iPhones while using the same phone number on each device. T-Mobile and Deutsche Telekom are the first carriers to offer iPhone Handoff, and Apple said Verizon and EE will add support later this year, but AT&T is noncommittal about the feature.
China’s next-gen stealth fighters, bad cholesterol drug: 7 science highlights
From oil refining with reduced energy use to a self-powered neural device, here are some highlights from SCMP’s recent science reporting.
'It's a sick act': Kenner business owner accused of mounting hidden camera in bathroom
More cameras and memory devices were found at the man's home and his business, according to Kenner police.
Apple Releases First Public Betas of iOS 27.2 and macOS Golden Gate 27.2
Apple today seeded the first betas of iOS 27.2, iPadOS 27.2, macOS Golden Gate 27.2, tvOS 27.2, and watchOS 27.2. The software comes a day after Apple provided the second betas to developers. To get the new betas, you can sign up on Apple's beta testing website. After you're signed up, the betas can be installed through the Software Update section in the Settings app on each device. iOS 27.2 includes the redesigned Health app that Apple introduced at its September iPhone event.
Apple could take on Whoop with a new fitness tracker, report says
Apple may be developing a new fitness tracker as part of its new generation of hardware devices.
Interoperability roundup: New AI connections, more QHINs
HealthEx enables users to connect medical record data to more applications and devices, including Meta's Muse artificial intelligence assistant, as more health tech companies and HIEs participate in TEFCA.
Motorola's Android 17 rollout is bringing a helpful feature to more devices
As Motorola continues its roll out of Android 17, the brand is also expanding access to this helpful feature.
Kenner business owner arrested, accused of video voyeurism after camera found in bathroom
During a review of the recordings, the business owner, identified as Henry Rios, 57, of Kenner, was seen manipulating the position of the camera and later putting the device in his office, according to police.
Micron reportedly ends production of 2GB GDDR7 used by GeForce RTX 50
Micron appears to be moving away from 2GB GDDR7 as its catalog shifts toward 3GB devices. The older 16Gb parts were already used on RTX 50 cards.
Teal Health raises $22M ahead of expected surge in demand with new coverage mandate
Teal Health, maker of an FDA-approved at-home cervical cancer screening device, has raised $22 million in a Series A funding round. | Starting in 2027, most health plans are required to cover the cost of self-collected tests with no cost to consumers, including follow-up tests. Teal is working to coordinate billing with major commercial payers ahead of that deadline.
I flew 11,000 miles with Sonos' brand-new Ace Ultra headphones, and their noise cancellation wowed me
The Sonos Ace Ultra headphones offer excellent ANC and comfort, while integrating wirelessly with other Sonos devices.
Adobe Premiere for Android launches for free with layered video editing, YouTube templates
Months after it arrived on iPhone, Adobe Premiere’s mobile version is now available on Android devices with layered video editing,...
Teal Health Raises $22 Million Series A to Expand Access to the Most Accurate FDA-Authorized At-Home HPV Cervical Cancer Screening
/PRNewswire/ -- Teal Health, creators of the Teal Wand™, the first and most accurate FDA-authorized self-collection device for at-home HPV cervical cancer...
For the first time, scientists watch sound jump between quantum states
Stanford researchers have recorded the first real-time quantum jumps of sound, watching single phonons abruptly vanish from one energy state to another. The breakthrough could open new paths for quantum computing, error correction, highly sensitive biological sensors, and next-generation sound-based devices.
Sunda Energy, Meridian Mining, Quantum Helium, Light Science Technologies, Foresight Solar, hVIVO
Sunda Energy PLC (AIM:SNDA, FRA:GHA0) has raised £5.25 million to fund completion of its New Zealand acquisition. It's also launching a retail offer for a further £525,000. Meridian Mining Plc (LSE:MNO, TSX:MNO, OTCQX:MRRDF) has delivered a net present value of $2.09 billion for its Cabaçal project in Brazil. The CEO says the economics could make it the next major near-term gold-copper mine. Quantum Helium Ltd (AIM:QHE) is targeting Q4 2026 for a larger fracture stimulation programme at Sagebrush-1 in Colorado. It's also taking a 9% stake in Herencia Resources. Light Science Technologies Holdings PLC (AIM:LST, FRA:9FD) has secured a repeat order from a healthcare devices customer, pushing that contract past £500,000. It's building out higher-margin work in defence and medical sectors. Foresight Solar Fund Ltd (LSE:FSFL, FRA:1F5) says it's considering all strategic options to lift a share price stuck below the value of its assets. The board says it needs to "act decisively" to close that gap. hVIVO PLC (AIM:HVO) has appointed Caroline Shaw as an independent non-executive director. She brings more than 30 years of senior healthcare leadership to the board. Follow us and subscribe on YouTube, our social channels, and on proactiveinvestors.co.uk.
RatHat is a new Android malware that records your screen touches to steal passwords
This malicious software also weaponizes AI to infect the device.
iOS 27.2 beta 2 reveals new details about anti-snatching feature
Apple continues to work on a feature that automatically locks an iPhone when it detects that the device has been snatched from its owner’s hand.
Battery Size Upgrades Inbound for Galaxy S27 Ultra and Pro
Batteries for the upcoming Galaxy S27 Ultra and Galaxy S27 Pro are going through regulatory approvals, and thanks to that, we’re getting an idea for how big Samsung is going for 2027. Things are looking good for Samsung fans. For the Galaxy S27 Ultra, which is the flagship lineup’s flagship device, the size is shown...
Scientists made a paper battery you can swallow to power internal medical devices
A paper-based, ingestible battery powered medical devices inside pigs for up to three days before gradually breaking down, a new study reported.
What to stream: ‘A Different World,’ ‘Toy Story 5’ and Kenny Chesney
The Disney+ debut of “Toy Story 5” and a new album from Kenny Chesney are some of the new television shows, films, music and games headed to a device near you.
‘HomePad’ to launch next month with these new features: report
Apple’s long-awaited home hub device, often called ‘HomePad,’ is now expected to launch in October. Here’s what’s coming per Bloomberg.
iPhone owners can now submit a claim in Apple’s $250 million Siri AI lawsuit
You can receive $25 per eligible device.
KCENNews
KCEN 6 News is the NBC affiliate serving the community of Waco, Temple, Killeen, Bryan-College Station, and beyond. Be sure to download the KCEN 6 News app on your favorite devices to watch us anytime for free. SUBSCRIBE to our channel: http://bit.ly/2Z6mT7N Follow 6 News on social media: https://www.facebook.com/6NewsKCEN/ https://www.instagram.com/kcennews/ https://twitter.com/6NewsCTX https://www.tiktok.com/@kcentv
UVA Health first in world to implant new cardiac mitral valve repair device
The new device adheres more readily to the heart and allows quicker recovery after surgery.
Koning Health secures Australian TGA approval for breast CT system
The platform is designed to provide volumetric images to assist clinicians in evaluating breast tissue.
Artist hacks CitiBike to make NYC affordability crisis hard to ignore
Justin Blinder created a device that makes it harder to pedal a CitiBike in rent-burdened areas.
Scientists claim elastocaloric cooling breakthrough
HONG KONG: Scientists claim to have developed what is said to be the world’s first zero-degradation elastocaloric cooling device....Read More...
Samsung confirms One UI 9 rollout dates for some older Galaxy devices
Samsung confirms the One UI 9 rollout date for Galaxy S25, Galaxy Z7 foldables, and S23 FE. Find out when your Galaxy receives the update.
Culturally Relevant Cardiovascular Disease Prevention and Care Strategies
(Feature Impact) Driven by rising rates of obesity, diabetes, high blood pressure and other risk factors, cardiovascular disease has surpassed cancer as the leading cause of death among Hispanic adults in the United States.Hispanic people represent nearly 1 in 5 of the U.S. population and are the nation’s largest ethnic minority group, yet many continue to face barriers to achieving heart health and accessing high-quality healthcare. A new scientific statement published in the American Heart Association’s flagship journal, “Circulation,” revealed how social, economic, cultural and environmental factors contribute to persistent disparities in cardiovascular health, calling for culturally tailored prevention strategies, equitable access to care and greater representation of Hispanic populations in cardiovascular research.“Hispanic populations in the U.S. are incredibly diverse even within their own communities with differences in genetic ancestry, language, cultural traditions and social experiences that can significantly influence cardiovascular health,” said Johanna Contreras, M.D., M.Sc., FAHA, director of the Division of Heart Failure and medical director of the Hispanic Heart Center within the Mount Sinai Health System. “Yet Hispanic people remain underrepresented overall in the research that guides prevention and treatment strategies… Without better representation and more detailed data, we risk overlooking important differences that can help us improve care and save lives.”Hispanic Cardiovascular Health by the NumbersCardiovascular risk factors – obesity (nearly 46%), type 2 diabetes (15.5%) and high blood pressure (approximately 44%) – are prevalent among Hispanic adults and often emerge at younger ages and occur more frequently among Hispanic adults compared with white adults.According to the report, only about 1 in 5 Hispanic adults achieves ideal cardiovascular health as defined by the American Heart Association’s original Life’s Simple 7 metrics. Updated analyses using the Life’s Essential 8 framework demonstrated persistent disparities for heart and brain health, as well as suboptimal dietary quality, sleep patterns and levels of physical activity.Social and Economic Barriers MatterBiology alone does not explain cardiovascular health disparities. The environments where people live, work and age, along with social and economic challenges, impact heart health. In fact, approximately 17% of Hispanics live below the federal poverty threshold, compared with 8.2% of white adults.#placement_976606_0_i{width:100%;max-width:550px;margin:0 auto;}var rnd = window.rnd || Math.floor(Math.random()*10e6);var pid976606 = window.pid976606 || rnd;var plc976606 = window.plc976606 || 0;var abkw = window.abkw || '';var absrc = 'https://ads.empowerlocal.co/adserve/;ID=181918;size=0x0;setID=976606;type=js;sw='+screen.width+';sh='+screen.height+';spr='+window.devicePixelRatio+';kw='+abkw+';pid='+pid976606+';place='+(plc976606++)+';rnd='+rnd+';click=CLICK_MACRO_PLACEHOLDER';var _absrc = absrc.split("type=js"); absrc = _absrc[0] + 'type=js;referrer=' + encodeURIComponent(document.location.href) + _absrc[1];document.write('');“Many Hispanic adults face obstacles that extend far beyond the doctor’s office,” Contreras said. “Limited health insurance coverage, language differences, food insecurity, environmental exposures and concerns related to immigration status can make it more difficult to prevent disease, manage chronic conditions and receive timely treatment.”Contreras emphasized the cultural values and practices of Hispanic people also influence how they perceive their health and healthcare options.“Family plays a central role in many Hispanic communities and can be an extraordinary source of strength, support and resilience,” Contreras said. “At the same time, family members are often called upon to translate medical information, navigate health systems and help make healthcare decisions for loved ones. Those responsibilities can shape how health information is understood and acted upon.”An Action Plan for Improving Hispanic HealthThere are practical opportunities to achieve equitable cardiovascular health and reduce disparities through community engagement, culturally responsive care, inclusive research and policies that address the underlying drivers of health.“Reducing cardiovascular disease among Hispanic populations demands action at every level,” Contreras said, “from improving access to culturally responsive care and expanding research participation to addressing the social and environmental conditions that shape health.”By addressing both medical risk factors and the social conditions that shape health, experts believe there is an important opportunity to reduce disparities and help more people live longer, healthier lives. Learn more at Heart.org.Photo courtesy of Shutterstock
What to stream: 'A Different World,' 'Toy Story 5' and Kenny Chesney
The Disney+ debut of “Toy Story 5” and a new album from Kenny Chesney are some of the new television shows, films, music and games headed to a device near you.
iFixit Shares iPhone 18 Pro Teardown With Inside Look at New Features
iFixit today published an iPhone 18 Pro and iPhone 18 Pro Max teardown in both article and video formats, providing a closer look inside the new devices. The teardown confirms the battery capacities for the eSIM-only models: iPhone 18 Pro: 4,288 mAh (+0.8% vs. 4,252 mAh for iPhone 17 Pro) iPhone 18 Pro Max: 5,567 mAh (+9.4% vs.
A film thinner than a human hair blocks electromagnetic waves—and hides heat!
CHANGWON, South Korea — A research team led by Dr. Taehoon Kim of the Composites & Convergence Materials Research Division at the Korea Institute of Materials Science (KIMS), headed by President Chul-jin Choi, has collaborated with research teams led by Dr. Seon Joon Kim and Dr. Jaewoo Kim of the Korea Institute of Science and Technology (KIST) to develop an ultrathin composite film that combines electromagnetic interference (EMI) shielding, infrared (IR) stealth, and high mechanical strength. The researchers achieved these multifunctional properties by combining carbon nanotube (CNT) fibers and MXene in a structure resembling “bricks and mortar.” The technology is expected to protect military systems and aerospace electronics while also reducing electromagnetic interference in 5G/6G communication devices and wearable electronics.
Rare, Beloved Super Nintendo JRPGs Receive First Re-Released
After 30 years the first two Lufia games will be ported to modern devices, and while the first may seem rudimentary, fans know the series goes to some amazing heights
Apple’s A20 Pro Demonstrated To Be An On-Device AI Beast, Can Run A 27B Parameter Model At Double The Speed Of The iPhone 17 Pro’s A19 Pro
Apple’s next-gen A20 Pro chip demonstrates groundbreaking on-device AI capabilities, running a massive 27B parameter model at double the speed of the iPhone 17 Pro's A19 Pro
The Big Holes in Wearable Heart Rate Variability And Readiness Scores
On September 9th, Apple announced it was revamping its Apple Watch Health Sensing System, rolling out a Readiness score (0 to 10), and increasing the frequency of heart rate variability (HRV) outputs 24-fold. This can be viewed as upping its competition with various other consumer wearable sensors. These “readiness scores” as a composite of multiple metrics, with heart rate variability (HRV) being front and center for most. The majority of Americans are now using wearable sensors, which equates to well over 100 million adults. HRV and Readiness scores are increasingly being marketed as a measurement of autonomic nervous system health, a digital marker for future disease, a clock for biological age, and a holistic metric to promote healthspan and even longevity. (Apple also introduced a new longevity tab and “Health Age”.) None of this has been proven. In this edition of Ground Truths I am going to review what we know about heart rate variability and readiness scores. Heart Rate Variability HRV is the variation in normal heart cycle timing. The variability of the heart rate, the barely perceptible millisecond changes in time between consecutive heart beats (see R-R intervals in the Figure below, left panel), is due to interplay between the sympathetic and parasympathetic (vagal nerve) inputs. Distinct from heart rate, individuals with the same heart rate can have very different HRVs. It is a rough reflection of the autonomic nervous system (ANS) activity, inadequate to say whether a person’s ANS function is abnormal. For more than three decades, heart rate variability (HRV) has been measured and several studies have found an association of low HRV and clinical outcomes, particularly a link with higher all-cause and cardiovascular mortality. There have also been less well established links of low HRV to risk of early cognitive impairment, dementia, mental illness, Type 2 diabetes and substance abuse. An important reminder is that HRV is a surrogate marker without any established cause-and-effect relationship. If you increase your HRV, that doesn’t mean it will improve health outcomes. In fact, there is no hard evidence for that. All that work linking to health outcomes was done with electrocardiogram (ECG) derived HRV. Now, in the era of consumer wearables, this is getting assessed differently, by optical pulse (yes, the lights you see) plethysmography (PPG) or what is called pulse rate variability (PRV). They are not the same, as shown below (right panel) and only concordant when the delay between the ECG and pulse is kept constant, which basically means at rest. I should mention there’s also what I will call MPV, a mattress mechanical movement sensor, a derived heart rate variability, that companies like Eight Sleep use, even further away from directly measuring HRV. HRV has not one uniform measurement but many different types of quantification, such as RMSSD, the magnitude of difference between successive R-R intervals of normal sinus beats (N-N) or SDNN, the standard deviation of NN intervals, both in milliseconds. SDNN is one of the so-called frequency domain HRVs (others are LF, HF, LF/HF). Different wearable sensors use different metics; Apple has relied on SDNN and nearly all of the others use RMSSD, which is generally considered the more accurate metric. There’s also the different length of time measured, such as for a matter of minutes, all day, or an overnight’s sleep. Short measurements are especially problematic since they don’t capture enough of respiratory modulation and other factors that influence HRV. Share Ground Truths How well does HRV correlate with PRV? There are very limited studies, especially independently done. One that is commonly cited was conducted by Air Force researchers in only 13 healthy adults assessing Oura ring 3 and 4, Whoop 4.0, and Garmin Fenix 6 and showed a correlation coefficient of 0.88 to 0.97 and a mean absolute percentage error from 6 to 10%. The correlation is not a perfect 1.0, but there’s at least a fairly high level of correlation. HRV is supposed to increase during the night due to takeover of the parasympathetic nervous system, and higher during deep sleep. A recent example of my 1 week, all day “HRV,” and one during sleep is shown below. As you can see, the N of 1 data are inconsistent for the same days from different sensors (Oura, AppleWatch, Fitbit Air, and Eight Sleep) by patterns, absolute numbers, and comparison with prior days and weeks. The largest study in over 8 million Fitbit users (the old version, not Google Fitbit Air, introduced in May 2026) gives you a sense of the effect of age, sex, and the 2 different main HRV (here PRV) metrics, with RMSSD on the left and SDRR (=SDNN) on the right below. That study, from data collected in 2018, is a major outlier, since all the more recent ones are tiny with respect to sample size. Many of the companies have not had independent evaluation of their HRV, such as Eight Sleep, but have published a low standard error on their website. There are some other published studies on the correlation between HRV and PRV, but they are all small and only in healthy adults. A scoping review emphasized the lack of study in underrepresented individuals, including the aged, people of color (which affects the PPG signal), and individuals who are underweight or obese. Add the typical adult age 60 plus with one or more chronic diseases. For example, one study in over 900 adults found poor correlation of HRV and PRV, non-uniformly underestimated across many chronic diseases (cardiovascular, endocrine, neurological, respiratory, and others), concluding PRV is “an invalid surrogate for HRV.” A recent systematic review of 43 studies comparing HRV and PRV found reasonable pooled absolute standardized error (HRV as gold standard) but only 10 of the studies provided quantitative synthesis in ideal conditions. Their main conclusion was similarly cautious: “PPG-derived HRV [PRV] should not be regarded as universally interchangeable with ECG-derived HRV across all devices, populations, and recording contexts.” Factors Affecting HRV and PRV That gets me to the long list of factors that affect HRV (and PRV) besides the device, the type of measurement (RMSSD, SDNN or others), the person’s signal, the sensor site, the duration of data capture, if weighting by sleep stage is used, how artifact is processed and corrected. And this list is not complete!: Oura puts out data from their community of users (who input data) on what affects their overnight HRV. The factors currently provided are: no alcohol (increase 8%), melatonin (increase 2%, float tank (increase 2%), wine (decrease 4%), and party (decrease 14%) in overnight HRV. Must be some big parties! Subscribe What is a PRV measurement good for? It has been falsely characterized as an index of “autonomic balance” and a specific indicator of stress. A 2018 review of the studies available for HRV and its relationship to stress, not using any of the current wearables, found that stress can lower HRV. But so can many other factors. The non-specificity of the signal, indexed to the table above, is striking. Evidence from a UK Biobank study of over 46,000 participants with actual HRV looked at genetically predicted HRV, a genetic risk score, that failed to show the expected HRV-mortality link, indicating that _HRV is likely not causa_l, but rather a reflection of person’s physiologic state. A review of consumer wearable HRV data from 5 longitudinal studies showed that nighttime PRV was not associated with perceived stress, and surprisingly higher HRV, in the largest cohort (N=717 participants), was correlated with higher stress. An Oura ring cohort of 525 first-year college students found a link between overnight PRV and perceived stress, but that was also seen with resting heart rate, sleep, and respiratory rate. Several very small studies have examined the relationship of HRV and athletic injuries or guiding training with mixed, and predominantly negative results. HRV biofeedback training with paced breathing had no significant effect on reducing stress or raising HRV, as demonstrated with sham controlled trials. When HRV for multiple days showed a decline in conjunction with body temperature, the Oura ring published data for prediction of Covid. The WHOOP company sponsored an observational study, published in 2026, of 30,000 users for 72 weeks, without a control group, that reported reduced alcohol intake (5.8 % points) by self-report. That doesn’t tell us much, and particularly about the merits of HRV for behavioral change. If you use the same device and conditions as longitudinal trends for multiple (at least 2-3) weeks that may be the one way to get something useful from the measurements. Data for overnight sleep with minimal motion and using RMSSD is the best proxy for real HRV. The reason to look at trends rather than any given night is that it more likely represents something, even though you won’t know with certainty what the “it” is. Keep in mind there are no data, no peer-reviewed evidence, to show that HRV fluctuation in-person has any correlation with health outcomes. Share Readiness Scores These are proprietary scores that integrate different metrics for each of the wearables: no algorithms have been disclosed. They are unvalidated against health outcomes. In a review of 14 composite health scores of readiness and recovery, HRV contributed 86% to the scores, followed by reading heart rate (79%), physical activity and sleep duration (both at 71%). That review noted the substantial variability in measurement protools and lack of standardization. Sleep staging is notoriously inconsistent and inaccurate by these sensors, which adds further to the HRV uncertainties for what the scores, which use sleep stage data, mean. Only resting heart rate has been shown consistently across devices to be extremely accurate. I’ve made a Table to summarize what we know about which metrics are included, the scores, any peer-reviewed studies that compared the readiness score with health outcomes, and the corresponding (if any, NA-not available) citation. You will note that some companies do not use the term “readiness," such as WHOOP for recovery, and Garmin, which has 2 different scores, one of which is Body Battery. Eight Sleep uses the term “Fitness Score.” They all include HRV; Apple includes a new metric they call “Recovery HRV” which among other components uses 7-days of sleep, but it is unclear what this means or how it is differentiated from other scores (there are clearly no data for outcomes). We have no knowledge of how the different components are weighted or whether any of these scores are better than resting heart rate, HRV alone, physical activity, or any other single metric. Since none of these are standardized, they are not interchangeable, so if you get a 90 for Oura that has no relationship to a 90 on a Google Fitbit Air. Notably, the company can update its algorithm for readiness score at any point without notification to device users. Without any useful evidence of actionability for these scores or established relationship with health outcomes, it is hard to make a case for their value. At the Apple recent announcement they showed their Readiness score (0-10) on the watch (Figure below) but there are no published data on this score, not even on their website. It’s available only on their new Watch Series 12 or Ultra 4 [of course, ;-)]. That exemplifies the problems with these scores, lack of data and evidence for being meaningful to promote health. Perhaps the best study (which isn’t saying much) is the WHOOP Recovery for golfer performance, because it did correlate with an objective outcome, even though there was no control group and the authors were all from the company. Among the 389 pro golfers, an absolute 10-per cent point increase in Recovery score was associated with about 0.5 fewer strokes per round. But that’s hardly a health outcome! WHOOP is also conducting a study in over 2,700 runners to see if their recovery score will be linked to less injuries and improved performance, but that is not yet published and has no control group or randomization. Putting This in Context For two decades I’ve been enthusiastic about the potential for digital health and particularly wearable biosensors. Over the years, we’ve seen some great progress for their ability to promote physical activity and accurately detect atrial fibrillation (the first FDA cleared deep learning AI for consumers). That work was the subject of rigorous research. But there are holes in the data and evidence for other metrics. One notable one is the “VO2 max” story that I wrote about earlier this year. At that time many subscribers asked me to cover heart rate variability, which I finally got to here. When I dived into the research and publication for HRV and readiness scores, I expected to find at least some that were of high quality and demonstrated their utility by linkage to health outcomes. To my surprise, I found none. The wearable sensor measurements for HRV (PRV) are, for the most part, accurate, but that validation work has only been done in small studies of healthy adults and does not take into account the long list of factors, from the device, software side, and the user side, that affect HRV measurements. Moreover, this metric chiefly relies on optical sensing and, as we have learned for heart rate PPG sensing, may be less accurate in people of color. Keep in mind that all of the health outcome association evidence comes from ECG-derived HRV; none are from wearable sensor data. I will repeat the key point: there's no peer-reviewed evidence to show that in-person HRV fluctuation—or efforts to raise your HRV— has any correlation with health outcomes. For those of you who look at your HRV on awakening, or even 2+ week trends of it being low, I hope this context helps to relieve any anxiety. Yes, low HRV (not PRV) has been shown to increase risk of some diseases as summarized above. But efforts to raise your HRV—a surrogate metric— has not been established for improving any health outcomes. HRV does not have any evidence of causality (the genetic evidence actually goes against this possibility). In this summary, I have not included data for other wearable sensors such as Polar, Samsung, Withings, Suunto, Amazfit, Coros, Ultrahuman, or additional mattress sensors. These are beyond my first-hand experience, and as far as I know from my in-depth review none have any peer-reviewed published data that differ from the 6 sensors I’ve reviewed here. From the points I’ve gone over above, we’re not ready for readiness scores. Besides being proprietary, they are predominantly based on metrics that have their own issues. It’s compounding the problem, like building a house without a solid foundation that has never undergone a rigorous inspection, and then selling it. Like I mentioned for PRV, you can look at trends over weeks rather than any single day, to get a handle, but even that may not be helpful. There’s simply no evidence that these scores meaningfully relate to health outcomes. I’d emphasize they might, but that requires doing prospective or randomized studies to prove it. None exist. There’s great promise for HRV/PRV utility_. For example**,**_ Prof Maiken Nedergaard, who discovered the brain glymphatics that are essential in eliminating metabolic waste products from the brain during sleep, has posited that HRV could be a non-invasive marker for neuromodulator oscillations, brain-body regulatory circuits, and brain clearance. That would be extremely useful, but like everything else on HRV and readiness scores it requires solid research and validation. The lay media isn’t helping much to get the story straight. Earlier this year The Economist published a piece entitled “The most useful indicator of your overall health” which ordained HRV as an “accumulated stress score.” That’s akin to the false assertion about VO2max: “V02 max is the singular most powerful marker for longevity.” As I’ve summarized here, that is not established. The fact is that so many things can lower HRV, including physical exercise (especially an intense workout), reduced sleep quality, stress, the list above, no less the device, signal, and software. Whatever fluctuations observed have not been correlated with any health outcome. Sadly, “datamaxxers” are widely using HRV and readiness scores that have never been validated to mean anything. We already know that for some people using the sensors for sleep metrics, it can induce “orthosomnia,” an obsession to get high sleep quality, with associated high levels of anxiety. In an experiment done by a company to promote sleep quality for its employees, “For those employees who did use the trackers, many reported feeling perfectly rested until their tracker told them they had had a terrible night. Others were told that they had slept like a baby when they had actually been lying awake worrying about the quality of their sleep. “ The same problem can result from preoccupation with HRV or readiness scores, with anxiety that would lead to further reduction in both. It you are using a wearable like >100 million American adults, it’s OK to look at these data, but contextualized with the major caveats reviewed here. If you are one to require evidence that HRV or readiness scores are linked to health outcomes, you may not even want to look. The companies make it hard to turn them off! Let me end with the companies that make and sell wearables. Apple’s doubling down on HRV (24-fold more reporting and heart rate very 5 seconds) and introduction of a Readiness score tells us that consumers have bought into these metrics and they are joining the club. However, all of this is occurring with a backdrop of tens millions of users, claims about the data that are not backed up by adequate evidence, marketing way out in front of whatever limited data exists, and not being transparent about their readiness score algorithms. The companies can well afford to do the research that is needed to connect these metrics with health outcomes show, once and for all, that increasing HRV or using readiness scores promotes our health. If they believed and invested in the products they are selling, we’d not be in this position of not knowing. That’s essentially where we are with HRV and readiness scores. Perhaps someday this will change and we’ll have good reason to embrace them. NB: I wrote this post. No AI. I have no conflicts of interest with any of its content. Loading... Ground Truths has 215,000 subscribers from every US state and 214 countries. There are over 300,000 followers of Ground Truths so more than 90,000 folks who can easily convert to be free subscribers. Your subscription to these free essays and podcasts makes my work in putting them together worthwhile. If you’re not a subscriber, please join! If you found this interesting PLEASE share it! Share Ground Truths The proceeds from all voluntary paid subscriptions go to support our summer internship program. It enabled us to accept and support a record number of 62 summer interns that joined us in 2026! These are high school, college and medical students selected from thousands of applicants. We couldn’t do this expanded program without the funds coming in through Ground Truths. Thank you!
Five One UI 9 features you should try first
Samsung released the stable One UI 9 update for the Galaxy S26 series in Korea on September 16. A wider rollout should start from September 21, with devices suc
Pa’ La Cancha, Chivas’ Official Video Game
Guadalajara, Jalisco, September 18, 2026.- Chivas announces the launch of its official video game, available for download on mobile devices starting today. It is the first video game created from the ...
Pa’ La Cancha, Chivas’ official video game
Guadalajara, Jalisco, September 18, 2026.- Chivas announces the launch of its official video game, available for download on mobile devices starting today. It is the first video game created from scra...
Hands-On With the Apple Watch Series 12
The Apple Watch Series 12 came out today, and we picked one up to get a look at the new feature set. There are no major external changes, but Apple updated the device's internals and health sensors. Subscribe to the MacRumors YouTube channel for more videos. The Apple Watch Series 12 has the same design as the Series 11, but it does come in different colors.
iPhone 18 Pro Max in U.S. Equipped With Qualcomm's Snapdragon X80 Modem
TechInsights has published an iPhone 18 Pro Max teardown that confirms the U.S. version of the device is equipped with Qualcomm's Snapdragon X80 modem. The device's modem firmware also points towards the Snapdragon X80 modem. The smaller iPhone 18 Pro and the iPhone Duo use Apple's custom-designed C2 modem worldwide, and the iPhone 18 Pro Max uses the C2 modem in every other country, so the U.S. version of the iPhone 18 Pro Max having a Qualcomm modem is unique.
Apple's iPhone 18 goes on sale as customers line up at stores worldwide
Crowds flocked to Apple stores worldwide for the iPhone 18 launch, as the tech giant rolled out advanced camera upgrades, AI photo detection and its new flagship devices.
iPhone 18 Pro Teardown Reveals How Apple Shrunk the Dynamic Island
YouTube channel REWA Technology today shared one of the first iPhone 18 Pro teardown videos, offering a look inside the new device. iPhone 18 Pro and iPhone 18 Pro Max feature a smaller Dynamic Island, which Apple achieved by moving Face ID's infrared camera under the display in the top-left corner. The pixels above the infrared camera have a special pattern that lets infrared light pass through, yet the screen looks completely normal at typical viewing angles.
One UI 9 global release dates for some Galaxy devices revealed
Samsung finally started rolling out the One UI 9.0 update for the Galaxy S26 series a few days ago, following months of beta testing. The update, which debuted
Health-ISAC sets nine-domain MedTech cybersecurity baseline to guide medical device procurement, deployment
Health-ISAC sets nine-domain MedTech cybersecurity baseline to guide medical device procurement, deployment and risk management
Fulton Fall Festival to offer variety of attractions, entertainment
FULTON — The Fulton Fall Festival, presented by the Richard S. Shineman Foundation, will bring a full day of family fun Sept. 26.The free event will be held from 10 a.m. until 4 p.m. throughout the Fulton War Memorial complex. × This page requires Javascript. Javascript is required for you to be able to read premium content. Please enable it in your browser settings. kAmxE H:== :?4=F56 3@F?46 9@FD6D AC@G:565 3J t!xr tG6?ED !2CEJ #6?E2=[ EC242? u@F?52E:@?[ 7246 A2:?E:?8 3J uF=E@? w:89 $49@@= pCED[ 32==@@? 2?:>2=D 3J $E2CCJ $Ajv p?:>2=D[ 2?5 |28:4 |2EE 3J E96 ~DH68@ r@F?EJ *@FE9 qFC62F]k^Am#placement_726068_0_i{width:100%;margin:0 auto;}var rnd = window.rnd || Math.floor(Math.random()*10e6);var pid726068 = window.pid726068 || rnd;var plc726068 = window.plc726068 || 0;var abkw = window.abkw || '';var absrc = 'https://ads.empowerlocal.co/adserve/;ID=181918;size=0x0;setID=726068;type=js;sw='+screen.width+';sh='+screen.height+';spr='+window.devicePixelRatio+';kw='+abkw+';pid='+pid726068+';place='+(plc726068++)+';rnd='+rnd+';click=CLICK_MACRO_PLACEHOLDER';var _absrc = absrc.split("type=js"); absrc = _absrc[0] + 'type=js;referrer=' + encodeURIComponent(document.location.href) + _absrc[1];document.write('');kAmp=D@[ |C] $@?87=@H6C[ A6C7@C>2?46D 3J q6==6 #@J2=6 s2?46 p4256>J 2?5 ~77 qC@25H2J s2?46 r6?E6C[ 2 56>@?DEC2E:@? 3J |2DE6C !CJ@C’D %266C:42[ J2C5 82>6D[ E6>A@C2CJ E2EE@@D[ 2?5 >@C6]k^AmkAm%96C6 H:== 36 5@K6?D @7 G6?5@CD[ =@ED @7 7@@5[ 2?5 =:G6 >FD:4 2?5 6?E6CE2:?>6?E E9C@F89@FE E96 52J]k^Am googletag.cmd.push(function() { googletag.display('yup-rectangle-one'); });
The Booming Business of Hair Loss
As hair loss moves from niche concern to mainstream beauty priority, consumers are spending on products spanning scalp serums to LED devices. Now, brands are racing to turn thinning hair into beauty’s next major growth category.
Australia iPhone 18 launch descends into chaos as line-cutter claims he's first in world to buy device: 'I’m the first!'
Octin Health Wins MN Cup Grand Prize of $76K, Looks Toward FDA Clearance
The prize money will support product development for Octin Health’s device, which is designed to maintain blood flow during surgeries.
Caltech’s tiny new chip can steer light in 74 quadrillionths of a second
A new Caltech device can redirect a beam of light in just 74 femtoseconds using another beam and a nanoscale silicon metasurface. The breakthrough could pave the way for dramatically faster photonic communications, computing, and sensing technologies.
First iPhone 18 Pro, Apple Watch Series 12, Apple Watch Ultra 4 and AirPods 5 Orders Arriving to...
It's Friday, September 18 in Australia and New Zealand, which means customers who pre-ordered are beginning to receive their new devices. The iPhone 18 Pro, iPhone 18 Pro Max, Apple Watch Series 12, Apple Watch Ultra 4, and AirPods 5 are launching today. Apple fans who ordered an iPhone, Apple Watch, or AirPods will soon be sharing first impressions on Instagram, Reddit, the MacRumors forums, and other social networks.
New RatHat Android malware uses AI to automate device control
A new Android malware called RatHat has been discovered, targeting users with an AI-powered subsystem that helps operators remotely navigate compromised devices.
15 Useful Tech Devices You Can Buy for Under $50
There's a lot of cheap tech out there, but not all of it is junk. In fact, you can buy a lot of excellent devices for under $50.
Science Corp. names president as it looks to roll out vision-restoring implant
Former chief strategy officer Darius Shahida will continue leading commercialization efforts as Science rolls out its Prima implant to Europe.
New and returning performers shine with the Oswego Players
OSWEGO — Rehearsals are underway for the Oswego Players’ fall show for the 2026 season, “Old Money, New Habits,” written by local playwright Alexis Martin and directed by Sherri Metz.The play will be performed starting Oct. 9 at the Frances Marion Brown Theater in Fort Ontario Park. × This page requires Javascript. Javascript is required for you to be able to read premium content. Please enable it in your browser settings. kAmyF?:A6C qC:88D 2?5 y6??:76C w:E494@4< A=2J E96 4=2DD:42==J >:D>2E4965 ?6H=JH65D |@?EJ 2?5 u6=:4:EJ s2G:6D :? E9:D 72C46 D6E :? E96 `hb_D :? t?8=2?5] |@?EJ :D 2? 62DJ8@:?8[ 56G@E65 9FD32?5[ H9:=6 u6=:4:EJ :D E96 5@>:?66C:?8 2?5 4@??:G:?8 H:76 H9@ >FDE 86E 6G6CJE9:?8 D96 56D:C6D] q@E9 92G6 D64C6ED 2?5 E96J H@F=5 5@ 2?JE9:?8 E@ 2G@:5 E96:C 6IA@DFC6]k^Am#placement_726068_0_i{width:100%;margin:0 auto;}var rnd = window.rnd || Math.floor(Math.random()*10e6);var pid726068 = window.pid726068 || rnd;var plc726068 = window.plc726068 || 0;var abkw = window.abkw || '';var absrc = 'https://ads.empowerlocal.co/adserve/;ID=181918;size=0x0;setID=726068;type=js;sw='+screen.width+';sh='+screen.height+';spr='+window.devicePixelRatio+';kw='+abkw+';pid='+pid726068+';place='+(plc726068++)+';rnd='+rnd+';click=CLICK_MACRO_PLACEHOLDER';var _absrc = absrc.split("type=js"); absrc = _absrc[0] + 'type=js;referrer=' + encodeURIComponent(document.location.href) + _absrc[1];document.write('');kAmw:E494@4< DE2CE65 H:E9 E96 !=2J6CD :? a__b[ 2?5 E9:D :D 96C 7:CDE E:>6 324< @? DE286 :? 2 7F==\=6?8E9 AC@5F4E:@? D:?46 a_a` 2?5 E96 3:CE9 @7 96C 52F89E6C]k^AmkAm“x’> 92G:?8 E96 E:>6 @7 >J =:76 H:E9 E9:D D9@H[” D96 D2:5] “|J 52F89E6C 5@6D?’E C62==J 8C2DA H9J |@>>J =62G6D 96C E@ 8@ E@ C6962CD2=D 2?5 8:G6D 2 AFKK=65 6IAC6DD:@? H9:=6 x’> C64:E:?8 >J =:?6D 2C@F?5 E96 9@FD6 :? >J A@D9 t?8=:D9 2446?E] x =@G6 5@:?8 72C46[ 2?5 H@C6 324< @? DE286]”k^AmkAmu@C qC:88D[ 2=E9@F89 96 92D D@>6 DE286 6IA6C:6?46 H:E9 @E96C E962E6CD[ E9:D :D 9:D 7:CDE D9@H H:E9 E96 ~DH68@ !=2J6CD]k^AmkAm“x 962C5 23@FE E96 2F5:E:@?D E9C@F89 E96 !=2J6CD’ u2463@@< A286[” 96 D2:5] “x 6[ D@ x 7:8FC65 x’5 8:G6 :E 2 D9@E] x H2D 56=:89E65 H96? $96CC: 42DE >6 2?5 92G6 C62==J 2AAC64:2E65 E96 H6=4@>6 x C646:G65 7C@> 2== 2?5 E96 ECFDE 2?5 C6DA64E 2== E96 24E@CD 2?5 4C6H D9@H E@ 6249 @E96C]”k^AmkAm|6EK 92D 366? A=62D65 H:E9 AC@8C6DD D@ 72C]k^AmkAm“x =@G6 72C46[ 3FE :E :D 2 G6CJ 5:77:4F=E EJA6 @7 E962E6C E@ 5@ H6==] }@E @?=J 5@ E96 42DE >6>36CD ?665 E@ ‘364@>6’ E96:C 492C24E6CD[ 3FE E96J >FDE 56=:G6C DA@E\@? E:>:?8 H:E9 6?EC2?46D[ 6I:ED[ 2?5 :?E6C24E:@?] %9:D H9@=6 4C6H 2C6 5@:?8 C62==J H6== 2?5 x 2> 4@?7:56?E H:== AC@G:56 2 7:CDE\4=2DD D9@H]”k^AmkAm!6C7@C>2?46 52E6D 2?5 E:>6D 7@C U=5BF@j~=5 |@?6J[ }6H w23:EDUC5BF@j 2C6 fib_ A]>] @? uC:52JD 2?5 $2EFC52JD ~4E] h\`_ 2?5 `e\`f[ H:E9 $F?52J >2E:?66D 2E a A]>] @? ~4E] `` 2?5 `g] %:46?E H:E9 ~=5 |@?6J !C@5F4E:@?D WHHH]@=5>@?6JAC@5F4E:@?D]4@>X] %96 ~DH68@ !=2J6CD 24
PSA: watchOS 27 Removes This Useful Feature From Your Apple Watch
Apple released watchOS 27 on September 14, bringing a new Audio Intelligence feature set to its latest Apple Watch models, but as a result, owners of previous models are set to lose out doubly in the process. Apple Watch Series 12 and Ultra 4 models later this year will get Live Rewind, a feature that provides a transcript of any spoken audio that was picked up by the device in the last 15 seconds. To activate the feature, users need to double-click the Digital Crown.
Military blast exposure associated with long-term health conditions
Exposure to high-level blasts from incoming explosive devices or land mines among military veterans is associated with an increased risk of several conditions such as seizures, neuropathy and stroke years later, according to a study published September 16, 2026, in Neurology, the medical journal of the American Academy of Neurology.
Google rolling out Android 17 QPR2 Beta 5 for Pixel
The two-week update cycle continues with Google rolling out Android 17 QPR2 Beta 5 for Pixel devices today...
Google Home app brings battery-efficient widget, reduces gray device tiles
Google today is also rolling out Home app (especially for the homescreen widget) and Gemini for Home voice assistant updates.
Google Home MCP lets Antigravity, Claude, OpenClaw, & more control your smart home
Google today announced “Home MCP” to let your personal AI agent interact with your smart home devices via the Model Context Protocol.
Your AI agents can now control your Google Home devices
Google is launching early access to a new MCP server for Google Home, allowing AI agents like Claude, ChatGPT and others to control connected devices, review camera summaries and access smart home activity using natural language.
Specialties Honor Roll: Health Law
Health care is big business, and it’s constantly changing. New medicines and medical devices enter the market, regulations change and artificial intelligence is quickly changing the health care landscape. Ads for prescription drugs and health products are everywhere, while debates over access to care continue to make headlines. Behind all of it are legal issues. […]
iPhone 18 Pro Reviews: Excellent Yet... Meh?
The first iPhone 18 Pro and iPhone 18 Pro Max reviews have been published today by selected tech websites and YouTube channels, ahead of the devices beginning to arrive to customers and launching in stores this Friday, September 18. While the iPhone 17 Pro models featured a major design overhaul last year, the iPhone 18 Pro models look the same overall and have a set of more incremental year-over-year upgrades related to the cameras, battery life, and performance.