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America’s Homegrown-Parasite Problem
Scientists don’t know why cyclosporiasis, a tropical diarrheal disease, is spreading more and more from domestic sources.
It's not just produce. Where else can 'explosive diarrhea' bug hide?
As cases of cyclosporiasis rise, investigators may be overlooking the true source, experts told USA TODAY.
What Delawareans should know about this diarrhea-causing parasite
Cyclosporiasis cases are rising across the U.S. Here's what Delawareans should know about the illness and how to help prevent infection.
See map tracking spread of ‘explosive' diarrhea illness across US
Cases of cyclosporiasis continue to climb rapidly as 13 new states reported infections. See map tracking the spread.
Senate bill tries to 'fix' college sports
Sens. Maria Cantwell, D-Wash., and Ted Cruz, R-Texas, are spearheading new legislation addressing many of the concerns surrounding college athletics
Metro Detroit businesses concerned as Cyclosporiasis cases reach over 1,200
Cyclospora now has over 1000 cases in the metro Detroit area. Symptoms include nausea, vomiting, fatigue, and explosive diarrhea.
Source of 'explosive diarrhea' illness remains mystery as cases rise
Michigan alone has reported more than 700 cases of the seasonal food poisoning parasite often linked to fresh produce. Why haven't we found the cause?
Does cooking or vinegar kill Cyclospora? How to avoid the diarrhea-causing parasite, according to health officials
Keep these tips in mind as the parasite continues to spread this summer.
An outbreak of diarrhea caused by a parasite has hit at least 1,400 people. Here’s how to stay safe
It’s not clear what’s causing rising cases of cyclosporiasis, but cooking fruits and veggies and washing produce can help reduce your risk.
23 cases of 'explosive diarrhea' parasite in Louisiana, LDH reports. Here's what to know.
Here's what to know about the cyclosporas outbreak, including including case numbers, prevention tips and ongoing investigations.
Ohio Department of Health warning spread of ‘explosive’ diarrhea illness
The Ohio Department of Health (ODH) is warning Ohioans to take precautions as cases of the “explosive” diarrhea illness, Cyclosporiasis, continue to spread throughout the state.
Georgia health officials warn of seasonal Cyclospora risk as parasite cases rise nationwide
The parasite that causes prolonged diarrhea is most common during Georgia's summer months. Here's what residents should know as cases climb across the U.S.
Multistate outbreak of foodborne parasitic illness reaches Virginia and Maryland
An intestinal illness that can cause nausea and watery, sometimes explosive diarrhea that’s been reported in several states has reached Virginia and Maryland.
Arkansas Department of Health answers questions on cyclosporiasis outbreak
KATV reached out to the Arkansas Department of Health to ask about the recent outbreak of cyclosporiasis, an intestinal infection that can cause diarrhea.
Riverhead shopping center back in business after losing power for 3 days due to storm
River Center Shopping Center lost power during Saturday's storms. The electricity wasn't restored until late Tuesday afternoon, costing some businesses thousands of dollars, the center's owner said.
Experts weigh in on Michigan cyclosporiasis outbreak, treatment, tests
If you've had diarrhea and abdominal pain for more than a couple of days, infectious disease doctors say it's important to test for cyclosporiasis.
Robinhood cofounder says he'll buy a 'baby-mobile' Ferrari Luce
During a stop on the TBPN podcast, Baiju Bhatt, a noted gearhead, said he's going to buy the Ferrari Luce. He's planning on giving it to his wife.
Cases of 'explosive’ diarrhea illness top 1K. See states with the most
Cases of cyclosporiasis, which causes explosive diarrhea and other food poisoning symptoms, have topped 1,000. See which states have the most.
Illinois health officials warn of high rate of intestinal illness caused by contaminated foods
The intestinal illness cyclosporiasis is contracted by consuming contaminated foods. The most common symptoms of the illness are diarrhea, nausea and fatigue, according to health officials.
‘Explosive Diarrhea’ Parasite Surges In Michigan, At Least 3 More States As Officials Investigate
Infections with cyclospora, a parasite that spreads through raw produce and causes severe “explosive” diarrhea, are on the rise in multiple states.
Michigan parasitic diarrhea cases swell to 681: How to prevent it
The state health department issued more tips and suggests cooking produce to prevent cyclosporiasis infection as cases in Michigan skyrocket.
‘Explosive’ diarrhea parasite cases surge as health officials seek source
Outbreaks of cyclosporiasis are typically traced back to prepackaged food and fresh produce.
‘Explosive’ diarrhea parasite cases surge as health officials seek source
Outbreaks of cyclosporiasis are typically traced back to prepackaged food and fresh produce.
Explosive diarrhea? Here's what to know about Cyclospora
It's invisible to the naked eye, difficult to trace and can cause weeks of diarrhea. Here's what to know about the parasite, Cyclospora.
How Does The MacBook Air Stay Cool Without A Fan?
The MacBook Air doesn't have a built-in fan, yet it still handles heat efficiently. Find out what keeps it cool and how it's designed to avoid overheating.
YouTuber Builds 25-Foot Rideable RC Battleship for $400, and It Shoots Fireworks
When most gearheads and DIYers get the itch to hit the water, they look into buying a used jet ski, a small john boat, or maybe a kayak. But YouTube creator Julius Perdana had a slightly different vision. He wanted…
Scientists find the “Achilles’ heel” of deadly gut bacteria
Researchers discovered an “Achilles’ heel” shared by E. coli, Shigella, and other diarrhea-causing bacteria: enzymes they use to breach the gut’s protective mucus layer. By targeting this common vulnerability, scientists may be able to develop a single vaccine that prevents several major diarrheal infections before they even begin.
CDC investigates parasite that’s caused cases of ‘explosive’ diarrhea in 18 US states
Parasite cyclospora spreads through produce and water contaminated with feces and causes the intestinal illness cyclosporiasis
Firework chemistry: the science behind firework colors
Different chemical compounds create the brilliant reds, blues, greens and golds you see bursting overhead.
More than 60 North Carolina cases tied to parasite behind 'explosive diarrhea'
North Carolina is dealing with a rise in Cyclospora cases, a microscopic parasite known for unpleasant gastrointestinal symptoms, including "explosive diarrhea."
Diarrhea-causing parasite that can contaminate raw produce causing misery across several states
This 4th of July weekend, you may want to give those raw berries or green salad the side-eye.
Bernie Sanders says US is on the 'verge of a political revolution'
Meet Challenger, the legendary 35-year-old bald eagle making a special appearance to celebrate America's 250th anniversary in Washington, D.C., as military aircraft stage a thunderous dress rehearsal overhead.
‘Explosive Diarrhea Parasite’ Sickens 170 in Michigan, Hospitalizes At Least 20 Nationwide
Cyclosporiasis is a type of food poisoning that can cause severe diarrheal illness, but it is not usually life-threatening. The latest spike in Michigan has health officials on high alert.
‘Explosive’ diarrhea illness reported across US. See map of affected states
Cyclosporiasis can ruin a summery picnic with explosive diarrhea and other food poisoning symptoms, according to the CDC. See the impacted states.
Mystery parasite leaves Americans battling ‘explosive diarrhea’ as CDC investigates
The CDC reports 145 confirmed cyclosporiasis cases across 17 states as the parasitic outbreak season climbs, with 20 patients hospitalized so far.
Parasite outbreak spreads to 21 Michigan counties. See where cases are
Michigan health officials said a gastrointestinal parasite that causes explosive diarrhea has sickened over 225 people. Here's where the cases are.
Stomach bug causing explosive diarrhea. How to reduce your risk
In the past nine days, health officials have diagnosed more than 170 people with cyclosporiasis, a diarrheal illness. It is considered an outbreak.
Tps to prevent cyclospora infection and explosive diarrhea
At least 170 Michiganders have contracted a parasitic gastrointestinal infection called cyclosporiasis. Here are the CDC's tips to prevent illness.
Monroe County Health Department reports multiple cases of parasite-caused intestinal illness
Multiple cases of cyclosporiasis, a diarrheal illness caused by an infection from a parasite, have been reported in Monroe County, according to the county health department.
Rabid raccoon found in Manorville, Suffolk health department says
The Suffolk County Department of Health Services is reporting that a racoon found in Manorville has tested positive for rabies.
Scientists infected a 'vagina on a chip' with gonorrhea — then cured it with a new antibiotic found by AI
To sift through 6 million molecules in pursuit of new gonorrhea treatments, researchers trained AI to select the best drug candidate and then tested it in a "vagina on a chip."
PNC Business Credit Names Brady to Southwest Region Sales Manager
PNC Business Credit promoted Eamonn Brady to Southwest region sales manager. Based in Denver, Brady will spearhead business development efforts across both
Baxter Health Heart and Vascular Clinic Welcomes Brandi Watson, APRN
Baxter Health is proud to welcome Brandi Watson, APRN, to the Baxter Health Heart and Vascular Clinic. Watson joined the team on May 15 and is currently accepting new patients. Watson brings more than 25 years of experience caring for some of the most critically ill patients. Much of her career has been spent in intensive care settings, where she learned to make fast, high-stakes decisions for patients whose lives depended on getting the right care at the right moment. That kind of experience, which is gained through years at the bedside, is exactly what heart and vascular patients need from a provider.
Sister’s Gift Represents Transplant First at Sutter Health
Photo caption: Dr. Eric Miller adjusts the image focus on the da Vinci 5 robot as he performs Sutter’s first fully robotic living-donor kidney transplant. | June 2, 2026 Sutter’s California Pacific Medical Center (Sutter’s CPMC) in San Francisco has performed its first fully robotic living-donor kidney transplant, marking a significant milestone for the system’s […]
Howard Hahn Helps Establish Global Health Nonprofit Following International Funding Reductions | News and Publications
Kutak Rock attorney Howard Hahn recently spearheaded the formation of The GOARN Fund, Inc. (&ld...
From soil to gut: why your gut health depends on the world around you
On this World Microbiome Day, we explore the One Health perspective: the idea that human, animal, and environmental health are not separate concerns but expressions of the same interconnected system.
Warhammer Studio goes super-heavy for an Age of Darkness tank war
Fellblade, Glaive, or Falchion – which is your favourite Warhammer: The Horus Heresy super-heavy tank?
'A smartphone-like user experience' – The Hammerhead Karoo has just hit its best price of the year in this Amazon Prime Day deal
At full price, the Karoo 3 impressed our expert tester with its brilliant touchscreen that made it our top choice for cycling navigation
6 animal fathers who go the distance
From carrying eggs in their mouths to building hidden nests, these animal dads do it all.
Coffee shop confession: California must regulate paid political influencers
“It was more than a little ironic to overhear a shoptalk about transparency in politics discussed so openly in public,” writes columnist Robin Epley.
Health leaders urged to curb aggressive AI spending
This HIMSS26 APAC speaker advises leaders to pace their AI investments despite the technology's rapid development.
Maryland Science Center Launches Harbor Plaza Renovation
Last Saturday, the Maryland Science Center held a ceremonial groundbreaking of the renovation of the Harbor Plaza between the Inner Harbor promenade and the Science Center entrance.
UK in Effort to Improve Construction Workers’ Mental Health Amid Out-of-Work Crisis
The UK’s business department is spearheading a new effort to improve mental health in the construction industry, as the government tries to tackle a labor market crisis that’s been worsened by Britain’s high numbers of people out of work due to mental illness.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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Effective preparedness for high-threat pathogens demands more than technical tools — it requires a coherent strategy, sustained country engagement, and the institutional infrastructure to translate evidence into action. In 2025, the Pandemic and Epidemic Management (PEM) Unit advanced all three, working across the full spectrum of high threat pathogen (HTP) preparedness: from methodology development and evidence generation to country-level technical support, emergency response, and regional workforce strengthening.At the core of the PEM unit's work is building the regional evidence and policy architecture needed to prioritize and respond to HTPs systematically. A major milestone was the development of the HTP Prioritization Methodology — a structured, multi-criteria approach to ranking pathogens by epidemic potential, severity, and national context — and its national pilot in Bangladesh, where SARS-CoV-2, Nipah, dengue, and cholera emerged as the highest-priority threats, informing the PEM unit's contribution to 2026–27 biennium prioritization and workplan development (Access link here).Underpinning this work, the PEM unit advanced the peer-reviewed evidence base for HTP preparedness in the South-East Asia Region (SEAR), with three publications in international journals in 2025: Development of a zoonotic influenza distribution assessment and ranking system (ZIDAR): Technical application in Nepal to support cross-sectoral risk-based surveillance in One Health; Implications for influenza A virus surveillance in Southeast Asian Region countries: a scoping review of approaches for the surveillance of swine influenza viruses at human-swine interfaces in BMJ Public Health; and Operationalizing multisector partnerships: a Theory of Action and Reflection tool for zoonotic influenzas in Health Policy and Planning. Together, these contributions move the Region’s HTP preparedness agenda from practice to science — generating the transferable methodological foundations that will inform evidence-based capacity strengthening in Member States.Country-level engagement in 2025 reflected the breadth of contexts in which HTP preparedness must function. Technical support was provided for Mpox and cholera events across the Region, including coordination of cholera and acute watery diarrhea prevention and control in Myanmar in the wake of the March 2025 earthquake. In Myanmar, the PEM unit contributed technical leadership to the earthquake emergency response — one of the most complex humanitarian emergencies in the SEAR — as Health Operations and Technical Support lead within the Incident Management Support Team. This included strengthening emergency response planning, supporting operational and after-action reviews, and providing monitoring and evaluation support for both acute and protracted crisis response. The breadth of HTP support provided to emergency operations across the SEAR was documented in the PEM unit’s contribution to the regional report for the Health Security Interface Technical Advisory Group.In Sri Lanka, technical collaboration with the WHO Country Office and the Ministry of Health laid the groundwork for the National Steering Committee's 2026 annual meeting, development of Standard Operating Procedures for specialized emergency response, and a national training programme — all structured around evidence-based risk assessment for specialized hazards including HTPs.Across the SEAR, the unit contributed to strengthening the workforce architecture that underpins HTP response. Technical inputs shaped the WHO South-East Asia Regional Health Emergency Workforce Strategy 2025–2030, and the PEM unit supported conceptual development of the health emergency workforce framework for the Pandemic Fund Round 3 proposal.Alongside this, the unit's sustained engagement on the meningitis agenda culminated in the launch of the Regional Implementation Framework to Defeat Meningitis in South-East Asia by 2030 at the Seventy-eighth Session of the Regional Committee, ensuring the Region's priorities were reflected in the Global Technical Task Force and expanding the unit's HTP engagement beyond outbreak-prone zoonotic pathogens (Regional Implementation Framework to Defeat Meningitis in South-East Asia by 2030).Taken together, 2025 demonstrated that meaningful HTP preparedness is built incrementally — through methodology, engagement, and the steady accumulation of institutional capacity across Member States.Bangladesh piloted the HTP Prioritization Methodology and identified the highest-priority pathogens in the country context (Photo credit: WHO Country Office, Bangladesh).
9 Hot Rod Styles Every Gearhead Should Know
There isn't a universal definition of what qualifies as a hot rod, and maybe that's because the culture is built on so many different design styles.
Riverhead Board Unswayed By Public Objections to Taking of Science Center Property
The Riverhead Town Board seemed unmoved by hours of comment at a public hearing Wednesday evening on its plan to take the property adjacent to the Town Square owned by the Long Island Science Center through eminent domain. In 2020, the Science Center had proposed to build a new 24,000-square-foot, $13.5 million attraction at the
Eminent domain hearing on science center property turns contentious
Riverhead officials defended a proposed eminent domain taking of the Long Island Science Center property during a contentious public hearing Wednesday night.
Riverhead board hears pleas to save site for planned Long Island Science Center
Residents questioned the town's plans to use eminent domain to take control of the property.
Sutter Health Recognized in Anthem Blue Cross Annual Care Provider Recognition Program
Not-for-Profit Healthcare System’s Medical Groups Honored Among the Top Healthcare Providers in Anthem’s National Network NORTHERN CALIF. – Sutter Health today announced it earned recognition as one of only four California recipients in Anthem Blue Cross’ Care Provider Recognition Program. Developed in collaboration with Anthem’s affiliated health plans, the program honors top-performing medical groups nationwide […]
Where Data Meets Care: Advancing Medicine Through Research
Research presented at a national healthcare conference this past month may already be shaping the care patients receive today. From safer opioid prescribing after surgery to better understanding cardiovascular risk and the role of mental health support in cancer care, Sutter Health researchers shared studies at the 2026 Health Care Systems Research Network Conference in […]
Beyond the Game: Exploring Sports, Media, and Culture at Notre Dame
Katherine Walden, assistant teaching professor of American…
Sutter, Santa Clara Launch New Medical School
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Jurors struggle to decide Harvey Weinstein's rape retrial
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Women’s Health Services Expanded in Berkeley
Pictured above left to right: Lylia Trieu CMA, Gloria Gomez CMA, Mayte Hernandez CMA, Dr. Isabelle Cohen, Kelly Alvarez CMA, Ania Werynski CMA, Rachel Gonzalez CMA Sutter East Bay Medical Group is expanding women’s health services in Berkeley with the completion of Phase II at the Adeline Care Center, which has been operating since […]
Sacramento Kings and Sutter Health Announce Strategic Partnership
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South Park Youth Gain Increased Sports Access
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Academy of Sciences secures grant to help endangered sea stars, Bay Area's coastal ecosystem
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'Food insecurity is no longer just about low-income countries': Environmental economist explains how climate change is pushing agricultural systems to the brink
As a U.N. report warns that extreme temperature swings are disrupting crops and endangering agricultural workers, we spoke with environmental economist Shouro Dasgupta about farming in an overheating world.
Our Daughter Overheard Some … Bombastic Noises While Staying at Our Friends’ House. Now She’s Traumatized.
I'm not sure if I should tell them.
Global Health & WASH: May 2026 Funding Opportunities (14 new opportunities!)
The May update for Global Health & WASH brings new calls that cluster around three distinct shifts: LMIC research leadership moving from funder encouragement into a hard eligibility constraint, pharmaceutical and corporate-linked funders running structurally independent education and use-inspired research portfolios at substantial scale, and AI adoption shifting decisively from speculative tool to operational capability across health and WASH systems alike. In LMIC Research Leadership as Eligibility, Not Encouragement, Wellcome anchors the dominant signal of the month with three separate major calls that all require or strongly center LMIC leadership in their basic eligibility architecture. Wellcome’s ESIC Hubs (£1.5-£1.9M per hub over 3-5 years) explicitly requires an LMIC-based lead applicant, treating Global South leadership as a design constraint rather than a participation goal. Wellcome’s Infectious Disease Clinical Trial Development Award funds transdisciplinary teams whose lead must be a mid-career or established researcher based at an organization in Africa, South Asia, or Southeast Asia. Wellcome’s larger Infectious Disease Clinical Trial Award (£1M-£8M for optimizing licensed interventions) requires the administering organization to be in eligible LMIC regions and at least 50% of applicants based there. Around Wellcome, the same pattern shows up at smaller scale and across funders: CHINNOVA channels $1M into West and Central African research institutions for climate-health work; IBRO’s Neuroscience Training Grants explicitly tier ceilings by region of residence with Africa receiving the highest amount ($5,000); IHME’s GBD Emerging Researcher Award reserves at least one of its two annual awards for an LMIC researcher; Sidaction’s HIV Cure call funds research teams across France, the Netherlands, and eligible African countries with a minimum two-country collaboration requirement. Taken together, these calls signal a meaningful shift in how research equity is being operationalized — not as encouragement language at the bottom of a call, but as a structural feature of who can lead, where the work must be administered, and what proportion of the team must be regionally rooted. In Pharma-Funded Independent Medical Education and Use-Inspired Research, the lineup this month is unusually deep. Pfizer alone runs four parallel calls under independent education and quality improvement frameworks: a Migraine and Women’s Health RFP (200K x 2-year, $500K pool), Migraine IME ($200K, $1M pool), JAK Inhibitor evidence-based education ($100K), and Maternal Vaccination HCP Education in Saudi Arabia ($75K), plus a separate Pediatric Pneumococcal Surveillance research call in Saudi Arabia ($400K per project). Novo Nordisk Foundation runs four parallel calls of its own at substantial scale: Infectious Diseases Catalyst Grants (DKK 60M pool, up to DKK 7M collaborative), Non-Diabetic Endocrinology Collaborative Grants (DKK 53M pool, DKK 5-10M per project), Pioneer Innovator Grant Health (DKK 1.1M), and Distinguished Innovator Grant Health (DKK 6.8M). LEO Foundation deploys DKK 2-4M per project for dermatology research excellence. Pfizer’s framing across calls deliberately separates the funding from product promotion, emphasizing measurable practice-relevant change and structural distance between scientific outputs and commercial activity. Novo Nordisk’s “use-inspired” hard filter pushes researchers toward a credible translation pathway from mechanism to deployable tool. The pattern: industry-aligned funders are running structurally independent portfolios at meaningful $ that fund implementation evidence, not promotion. In AI as Operational Capability, Not Speculation, several calls this month explicitly treat AI adoption as a near-term operational question with real evidence and governance requirements, rather than a speculative trend to be watched. Wellcome’s ESIC Hubs frames AI as “the accelerator” for evidence synthesis, asking hubs to translate technical innovation into adoption-ready workflows that can match real-world policy timelines. UNICEF Venture Fund’s new Climate Tech for Children’s Health call funds for-profit startups deploying AI, machine learning, and blockchain in low-resource environments, with a strict requirement that solutions must already have a working prototype with promising pilot results. The Water Research Foundation has launched two simultaneous AI calls treating reproducibility, cybersecurity guardrails, and human-in-the-loop deployments as core design constraints rather than nice-to-haves: one on GenAI and Agentic AI in water utilities ($200K), one on alternatives to water shutoffs that explicitly screens for implementation economics evidence. Nordic Innovation’s quantum technology call (NOK 4.5M) extends the same logic into life science and healthcare, demanding consortium-stage projects mature enough to test with real users. TEF-Health offers €300K in subsidized testing infrastructure for European healthcare AI and robotics SMEs. The pattern: funders are converting AI pilots into playbooks, requiring transfer evidence and risk controls before AI can move from experimentation to sector-wide operational practice. For LMIC-based researchers in infectious disease or evidence synthesis, the three Wellcome calls together represent the deepest concentration of LMIC-led research capital in recent memory — pair the Infectious Disease Clinical Trial Development Award (£200K, deadline May 19) as a strategic pipeline feeder into the larger Infectious Disease Clinical Trial Award (£1-£8M, deadline June 2), since the development award functions explicitly as a track into the larger trial scheme. For Nordic researchers, the four Novo Nordisk Foundation calls plus LEO Foundation and Nordic Innovation Quantum represent ~$30M in regional research capital this cycle, all with deadlines clustered in May-August. For WASH practitioners, the three Water Research Foundation calls together (each up to $200K) are a cluster worth reading across — one on AI deployment, one on shutoff alternatives, one rewarding applied innovation — and the strongest applicants will articulate how their work bridges utility operations to policy-relevant evidence. For US-based clinical researchers and educators, the four Pfizer calls plus the APF Portfolio’s 80+ programs form an unusually accessible recurring pipeline; APF’s prohibition on indirect costs is a meaningful structural feature for early-career applicants whose institutions might otherwise absorb significant overhead. Snapshot of New Opportunities Total Estimated Funding Pool: $100 Million+ USD The grants are organized into three categories: Open Calls: Current grant and opportunities with a deadline. Grants are listed by closing date. 39 open opportunities- 14 new! Rolling Applications: current grant and opportunities with rolling applications (but it’s still best to submit as early as possible). 14 rolling opportunities- 1 new opportunity! Long term planning: Grants that have closed their current rounds, but are expected to open new windows. 4 long term opportunities! A quick tip for returning readers: if you want to jump straight to the newest additions, use CTRL F to search for “New!” and navigate quickly to the latest funding opportunities This post is for paid subscribers. This helps support the time and effort it takes to curate and organize these opportunities. Subscribe To keep this accessible to everyone who needs it, we’re happy to offer pay what you can rates. You can find more details here. Open Calls: Migraine Competitive Grant Program: Migraine and Women’s Health (Quality Improvement and/or Research RFP), Pfizer.*Closing soon!* Pfizer, in collaboration with the American Headache Society, is seeking independent quality improvement and research projects that close persistent gaps in migraine care for women across the United States. The funding logic centers on measurable, practice-relevant change: proposals should generate actionable evidence, tools, or system improvements that can be shared and used widely, not just within a single site. Priority areas span menstrual migraine and screening in women’s health settings, the role of hormonal fluctuations across the lifespan, sex-specific risk factors, comorbidities and quality-of-life burden, and disparities in outcomes by race, ethnicity, and socioeconomic status. The call is structured as a two-step competitive process with an initial Letter of Intent, with the strongest concepts expected to translate scientific insight into implementable improvements in diagnosis, management, and equity. Geographies: United States. Who can apply: U.S.-based organizations (not individuals), including professional schools, healthcare institutions, professional organizations, and other entities focused on healthcare improvement. Funding amount: Up to USD $200,000 total over 2 years; total pool USD $500,000. Targeted Sectors / SDGs: Health; Focus areas: migraine, women’s health, quality improvement, clinical research, menstrual migraine, health disparities. Deadline: LOI: May 5, 2026; Full proposal (by invitation): August 28, 2026. Learn more and apply here. This RFP rewards “shareable impact”: the most competitive submissions will pair rigorous methods with a clear plan for system uptake and dissemination beyond the originating institution. ReSSARC: Strengthening the Health Sector and Food Security in the Central African Republic (AID 013381/01/0) Call for Proposals, Italian Agency for Development Cooperation (AICS). *Closing soon!* AICS is seeking a limited set of high-capacity humanitarian partners to deliver an integrated package that stabilizes essential health services while reducing acute malnutrition and strengthening food security resilience in priority areas of the Central African Republic. The funder’s logic is explicitly nexus-based: proposals should meet urgent, life-saving needs while reinforcing local systems, coordination mechanisms, and community-level capacity so results persist beyond the emergency window. AICS emphasizes inclusion and protection outcomes, expecting gender-sensitive design and explicit measures for groups facing compounded vulnerability, including women, children under five, internally displaced people, and people with disabilities. The call also signals a localization pathway, encouraging stronger collaboration with national NGOs and balanced partnerships, alongside clear coordination with existing cluster and humanitarian actors to minimize duplication and improve coverage. Geographies: Central African Republic (Bangui, Ombella-Mpoko, Ouham, Ouham-Pende, Lim-Pende, Lobaye). Who can apply: Non-profit organizations registered with AICS, plus eligible non-profits without an office in Italy that have a pre-existing collaboration agreement with an AICS-listed organization. Funding amount: Total pool EUR €1,800,000; max EUR €800,000 (single applicant) or EUR €1,000,000 (ATS). Targeted Sectors / SDGs: Health; Focus areas: malnutrition prevention and treatment, maternal and child health, community health services, food security and resilience, localization partnerships Deadline: May 5, 2026. Learn more and apply here. This call is structured to reward partners who can link frontline service delivery to system durability and localization, not just short-term coverage gains. Contracts for Innovation in drug and alcohol addiction healthcare, Innovate UK. *Closing soon!* Innovate UK, on behalf of the Office for Life Sciences Addiction Healthcare Goals program, is procuring R&D to accelerate innovations that can improve treatment outcomes, strengthen recovery, and reduce harm and deaths linked to drug and alcohol addiction. The competition is positioned as a market-facing readiness push: selected projects are expected to advance solutions toward later-stage validation, generate evidence of user acceptability and UK market fit, and map credible routes through regulatory and certification requirements. Innovate UK signals a preference for innovations that can be field-tested in relevant UK settings and progressed to TRL 6 or 7, with practical plans for commercialization after contract completion. This structure favors applicants that can execute most work in-house, co-develop with service providers and people with lived experience, and translate technical progress into deployable tools for addiction healthcare delivery. Geographies: United Kingdom. Who can apply: Single organizations of any size (including EU, EEA, or international) leading delivery, with most work and key deliverables carried out in the UK; subcontractors for specialist skills only. Funding amount: GBP £200,000–1.5 million per project (inclusive of VAT); Total pool: GBP £20 million (across two strands). Targeted Sectors / SDGs: Health; Focus areas: Mental Health, Health Systems Strengthening, Research & Development, Technology Access. Deadline: May 6, 2026 (11:00am). Learn more and apply here. This call uses procurement to pull near-market addiction innovations toward operational proof and adoption pathways in UK services.
Inside Empire Entertainment Japan: 30 years of turning ‘Wow’ moments into global hits
As the entertainment industry increasingly blurs the lines between digital narratives and physical reality, Empire Entertainment Japan and SOHO Live are market leaders in redefining how Japanese creativity is exported to the global stage. At the spearhead of this evolution are Ted Miller, president and CEO of Tokyo-based Empire Japan,…
Curing U.S. Health Care, Part II
On March 23, 2010 President Barack Obama signed the Patient Protection and Affordable Care Act — usually referred to either as the Affordable Care Act or as Obamacare — into law. Joe Biden, then the vice president, could be overheard whispering “This is a big fucking deal.” And it was. The ACA, which went into full effect in 2014, created a system of subsidies and regulations designed to make health insurance available to many Americans who had previously been left out. It worked: In 2010 there were 47 million uninsured people in America, but by 2016 this number had dropped to 27 million. This still fell short of the universal health insurance that every other advanced nation has, but it was real progress. In 2017, during his first term, Donald Trump tried to destroy the ACA, replacing it with the American Health Care Act — legislation that would have eliminated most of the provisions that expanded health insurance under Obama. At the time the Congressional Budget Office projected that the G.O.P.’s replacement bill would nearly double the number of Americans without health insurance, increasing the total uninsured population by 23 million and undoing all of the progress achieved under the ACA. However, the attack on Obamacare failed by one vote in the Senate, and the ensuing public backlash against the G.O.P. delivered a large victory in the 2018 midterms to the Democrats. After these developments many observers assumed that the ACA had become a more or less permanent feature of American life. Such assessments, however, failed to take into account the deep hostility of the U.S. right toward policies that expand access to healthcare. As we’ll see, this hostility goes back generations. And the second Trump administration has taken actions that the CBO projects will add 16 million people to the rolls of the uninsured by 2034. How did we get here? And now what? Today’s primer will analyze the political economy of U.S. healthcare since the 1940s and the combination of danger and opportunity created by the current crisis. Beyond the paywall I will discuss the following: US health care on the eve of Trump II 80 years of US health politics The Obamacare story The new assault on healthcare
Scientists built a memory chip that breaks the rules of miniaturization
A new kind of memory device may finally solve the problem of overheating and battery drain in electronics. By shrinking components to an extreme scale and redesigning their structure, researchers found a way to reduce energy loss instead of increasing it. The result is a tiny memory unit that improves as it gets smaller—something once thought impossible. This could pave the way for ultra-efficient smartphones, wearables, and AI systems.
Science news: Return of the river-herring run, Musk vs. Altman and new pancreatic cancer drugs
Under the Radar breaks down the latest science and technology headlines, including communities fighting back against data centers, overheated sharks and more
Intermountain Health Unveils New Nevada Community Health Needs Assessment and Implementation Strategy to Enhance Health of Residents
Intermountain Health has published its new Community Health Needs Assessment (CHNA) and the Community Health Implementation Strategies (CHIS)for Nevada, identifying where the greatest healthcare needs for the communities and the actions that must be taken to enhance community health.The new assessment report found the most significant health nee...
Kansas City sports leaders highlight literacy ahead of World Cup
Rhea LeGrande, Lead to Read executive director, said the connection between sports and education is clear.
Overheard on Capitol Hill: Hospital leaders getting upbraided over ‘charging an insane amount for care’
A handful of health-system CEOs took withering fire this week at a hearing of the House Ways and Means Committee.