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How AI is creating a UK super-museum and revealing our planet's history
More than 70 million specimens from 100 UK collections will be put into an online digital museum
How AI is creating a UK super-museum and revealing our planet's history
More than 70 million specimens from 100 UK collections will be put into an online digital museum
Addenbrooke Classical Academy vs. Aurora Science & Tech: Colorado High School Girls Volleyball, Sept. 30, 2026
Addenbrooke Classical Academy at Aurora Science & Tech, Colorado high school girls volleyball, Sept. 30, 2026, 5:30 PM. Records, rosters and head-to-head.
Digital asset tax reform bill advances with broad business implications
RSM US analyzes a Ways and Means tax bill that would change taxation of digital assets, stablecoins and reporting obligations. Learn more.
Xbox Disc-To-Digital Officially Exits Testing
The Xbox Disc-to-Digital licensing program recently launched to insiders, effectively paving the way to a discless future for Xbox, while still allowing the brand to market its console as backwards compatible. Following just over a month of public testing, Microsoft has just announced that the...
Xbox's Disc-To-Digital Is Rolling Out Now To All Users
Dust off your boxes, folks, it's time to claim those licenses
Inspired Entertainment slides after Brazil's ban on online betting and gambling
Inspired Entertainment (INSE) warns Brazil’s online betting ban may hit digital revenue; outlook may change with Q3 results as Congress reviews.
Countries of the Americas advance a health sector digital highway to connect care across borders
PAHO Directing Council briefing highlights regional progress toward a trusted digital health ecosystem where secure information can accompany people across services and borders.
How Digital Entertainment Is Expanding the Modern Racing Fan Experience
Motorsports fandom has never been limited to what happens when the green flag drops. For decades, race fans have found
Health tech's dealmaking boom is back as firms chase scale and profitable growth
Health tech and digital health merger and acquisition activity remains a major force in 2026, driven by strategic expansion and the race for competitive artificial intelligence capabilities. | Health tech and digital health M&A activity remains a major force in 2026, driven by strategic expansion and the race for competitive artificial intelligence capabilities.
Federal court will hear if Wake schools wrongly suspended GOP candidate from job
Scott Lassiter charges Wake suspended him as an assistant principal in 2024 to help his Democratic opponent running for NC Senate.
UNIVERSAL MUSIC GROUP APPOINTS LIBBY BUSH AS PRESIDENT, GLOBAL BRANDS AND COMMERCIAL PARTNERSHIPS
Entrepreneur and CAA Global Head of Entertainment Partnerships to drive growth for artists and brands and create new experiences for fans across digital...
Scientists discover how excess dietary salt drives 'lean MASH'
Fatty liver disease is commonly associated with obesity, yet a growing number of people with normal body weight develop a severe form of the condition.
The Grand Theft Auto VI Digital Issue Is Now Live
Subscribers can read the digital version of our latest magazine starting today. - Game Informer
Optimi Health Appoints Melanie Pump to Board of Directors
Seasoned finance executive brings more than 25 years of leadership experience across technology, digital infrastructure, software, fintech and emerging growth companiesVANCOUVER, British Columbia, Sept. 29, 2026 (GLOBE NEWSWIRE) -- Optimi Health Corp. (NASDAQ: OPTH) (CSE: OPTI) (FSE: 8BN) ("Optimi" or the “Company"), a commercial-stage manufacturer and clinical-stage developer of regulated psychedelic drug products, today announced the appointment of Melanie Pump to its Board of Directors (the "
Smart ring maker Oura postpones public listing due to 'uncertainty in the IPO market'
The digital health IPO window may be closing, at least for now. | Smart ring maker and health tracking company Oura is postponing its previously announced initial public offering on Nasdaq due to "uncertainty in the IPO market," the company announced Tuesday morning.
Spain’s DeAPlaneta Entertainment hires digital content and channels chief
Spanish kids company DeAPlaneta Entertainment has appointed Daniel Acero Montoya as head of digital content and channels.
Top Democrats Start to Fund James Talarico in Texas Senate Race
The main super PAC for Senate Democrats will begin to run digital ads in the state’s Senate race, in a sign of the party’s growing confidence.
Landlocked Chungcheongbuk-do Welcomes First National Marine Science Museum
Landlocked Chungcheongbuk-do Welcomes First National Marine Science Museum Digital aquarium and experiential exhibits bring ocean science to inland residents after six-year development
How FIBA 3x3 Basketball Went From A Business Case To An Olympic Sport
FIBA 3x3 basketball evolved from a Youth Olympic experiment into a global sport, driven by gender equity, digital engagement and a spectator-first approach ahead of LA28.
IBM is Building a Bigger Software Business. Can Its Balance Sheet Keep Up?
On September 24, International Business Machines Corporation (NYSE:IBM) announced two key capabilities designed to strengthen its digital asset infrastructure for tier-one financial institutions, governments, and regulated entities. In a new beta rollout, IBM Digital Asset Haven clients can connect to SWIFT’s blockchain-based shared ledger, linking into a cooperative network of over 12,500 financial institutions across […]
TTEC Digital Earns Microsoft AI Business Solutions Inner Circle Award for 2026-2027
TTEC Digital has earned the Microsoft AI Business Solutions Inner Circle award for 2026-2027 for sales achievements.Quiver AI SummaryTTEC Digital has been awarded the Microsoft AI Business Solutions Inner Circle award for the eleventh consecutive year, recognizing its position among the top Microsoft partners globally based on sales achievements. The Inner Circle designation highlights TTEC Digital's expertise in leveraging AI and customer experi
Valley Bank Courts Small Businesses With Bluevine Acquisition
Valley Bank is set to acquire Bluevine, a digital banking platform for small businesses. The $340 million deal is designed to help Valley with its efforts
EFI and Agfa’s Digital Printing Solutions Business to Combine
An affiliate of Siris Capital Group will hold a 60% interest, and Agfa will hold a 40% interest in the jointly held company, EFI reports.
Ample Entertainment hires ex-Thinkfactory exec Brian Dale to oversee originals
LA-based factual prodco Ample Entertainment has hired Brian Dale, former exec at ITV America’s Thinkfactory Media, as senior VP of digital content.
AI Data Centers Emerge as a Hot Topic for Political Ads in 2026
A new analysis from the Absecon Group found that more than 700 candidates this year have run digital ads about data centers.
Review: Silent Hill: Townfall Largely Delivers on PS5 and Pro, Falls Short on PC
This unique setting deserves better.
Valley National to acquire Bluevine for $340M
Valley National Bancorp announced its plan to acquire Bluevine, a digital banking platform for small businesses, for $340 million. The acquisition aims to strengthen Valley's funding base, expand its small-business offerings, and accelerate its artificial intelligence capabilities to enhance its position in the digital banking sector.
AP Top 25: After Week 4
A couple teams had double digit place changes in this week’s poll.
The Americas are making progress in health but must accelerate action on emerging challenges, says PAHO Director
At the opening of the 63rd Directing Council, Dr. Jarbas Barbosa highlighted the Region’s public health gains, called for stronger regional cooperation, and underscored priorities including primary health care, vaccination, digital health and emergency preparedness.
Commentary: Civic preparedness has never been more critical
Comprehensive civic education is necessary to navigate our digital democracy and excel in postsecondary pursuits.
Dakota State University awarded $1M to strengthen rural healthcare cybersecurity
DSU’s new CyberRx SD will help South Dakota healthcare providers modernize technology, protect patient data and build long-term digital resilience.
Famitsu sales (9/14/26 - 9/20/26) - first week sales revealed for Fire Emblem: Fortune's Weave
The latest Japanese hardware sales from Famitsu are as follows: Switch 2 – 34,341 PS5 Digital Edition – 7,441 Switch OLED – 2,634 Switch Lite – 2,248 Switch – 823 PS5 Pro – 219 PS5 – 187 Xbox Series X – 136 Xbox Series X Digital Edition – 116 Xbox Series S – 19 For comparison’s sake, here are the...
Citizens Bank of Edmond Partners with Parlay to Power Small Business Lending at ROGER, Its Digital Bank for the Military Community
EDMOND, Okla. & ALEXANDRIA, Va., September 28, 2026--Citizens Bank of Edmond partners with Parlay to power small business lending at ROGER, opening a faster path to capital for the military community.
Sony details God of War Laufey’s Digital Deluxe Edition contents and pre-order bonus
Pre-orders for the next God of War game start on Tuesday…
God of War Laufey pre-orders open September 29, editions detailed
Physical and digital pre-orders for God of War Laufey will begin on September 29 at 10:00 a.m. local time, publisher Sony Interactive Entertainment and developer Santa Monica Studio announced.
Valley National Bancorp to Acquire Bluevine Inc., Accelerating Its Digital Small Business Growth Strategy and Meaningfully Enhancing Its Core Funding Capabilities
NEW YORK, N.Y. and JERSEY CITY, N.J., Sept. 28, 2026 (GLOBE NEWSWIRE) -- Valley National Bancorp (“Valley”) (NASDAQ: VLY) and Bluevine Inc. (“Bluevine”) announced today that they have entered into a definitive agreement whereby Valley will acquire Bluevine, a leading nationwide digital banking platform for small businesses. The acquisition directly aligns with Valley’s stated strategic priorities of enhancing its funding base, expanding its small business franchise, and accelerating its digital
WELL Health Subsidiary WELLSTAR Announces Conditional Approval for TSXV Listing and Files Filing Statement
WELLSTAR has received conditional approval from the TSX Venture Exchange as a Tier 1 issuer, subject to satisfaction of the TSXV's customary listing conditions, and is expected to commence trading on or around October 1, 2026, under the ticker symbol "WSTR".Vancouver, British Columbia--(Newsfile Corp. - September 28, 2026) - WELL Health Technologies Corp. (TSX: WELL) (OTCQX: WHTCF) ("WELL"), a digital health company focused on positively impacting health outcomes by leveraging technology to...
Salesforce and Innovation City Launch AI-Powered Business Registration Platform
The new implementation combines AI platform capabilities powered by Salesforce with Innovation City's digital ecosystem, enabling businesses to access services and complete registration processes faster through more responsive interactions, while operating within Innovation City’s established governance and regulatory framework.
Walmart says it's not using personal information to set prices as it expands digital shelf labels
Walmart is aiming to assuage customers' fears about its new pricing technology as it rolls out digital price labels at its stores.
Oasis Sells Out All 42 Shows On 2027 Tour
Oasis is once again proving that apparently everybody wants to live forever -- or at least see the Gallagher brothers play “Wonderwall” again.
State officials approve 14.6% rate increase for individual premiums on ACA marketplace
Marylanders who purchase individual health care plans on the state’s insurance marketplace will see a second year of double-digit increases to their monthly healthcare costs.
Business People: Evereve hires Target exec Alanna Baker to lead digital
RETAIL Evereve, an Edina-based national women’s fashion chain, announced the appointment of Alanna Baker as its first chief digital officer. Baker joins Evereve from Target Corp., where she most recently served as vice president of…
Review: Control Resonant: An Impressive PC Version With Superb Scalability
Plus: optimised settings, RT recommendations and much more.
5 Affordable Digital Gadgets That Can Fit On Your Keychain
As the name suggests, keychains naturally carry keys, but they can also fit a host of digital gadgets, including power banks, retro gaming consoles, and more.
Could AI Commerce Reshape Meta (META)’s Business Model?
Meta Platforms, Inc. (NASDAQ:META) is expanding the commercial capabilities of its Muse AI assistant through a strategic partnership with Shopify, giving investors another potential avenue for AI monetization beyond digital advertising. On September 21,Shopify CEO Tobias Lütke announced a partnership with Meta to bring Shop Pay agentic checkout to Muse, allowing users to shop from […]
2026 Beijing International Week for Science Literacy Launched in Beijing
PR Newswire | BEIJING, Sept. 27, 2026 /PRNewswire/ -- The 2026 Beiji
‘SNL’ pokes fun at Trump and Mamdani’s relationship
New York Knicks star guard Jalen Brunson hosted the Season 52 premiere of “SNL.” He talked about proving his “biggest doubters” wrong by leading his team to win the NBA championship. The episode also poked fun at President Donald Trump and New York City Mayor Zohran Mamdani’s political relationship.
UCLA receives $75 million in NSF grants for quantum technology
Two UCLA quantum computing institutes received grants from the National Science Foundation worth a combined $75 million Aug. 25. The institutes – Fault-Tolerant Quantum Systems, Architectures and Applications and Challenge Institute for Quantum Computation – aim to advance quantum technologies, which function faster than classical computers or standard digital devices.
Maryland officials approve 14.6% rate increase for individual premiums on ACA marketplace
Marylanders who purchase individual health care plans on the state’s insurance marketplace will see a second year of double-digit increases to their monthly healthcare costs.
Microsoft Excel can now put multiple values in a single cell
Microsoft is changing one of Excel’s most familiar rules: a cell no longer has to contain just one value. The company has introduced lists, arrays in cells and nested arrays, giving users new ways to keep multiple pieces of information together without turning them into a single block of text. The features are currently rolling […]
I created an interactive digital avatar of myself — and you can talk to it
After obtaining an interactive avatar and training it to discuss venture fraud, I have mixed feelings about making AI clones of ourselves.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Today we have a fascinating piece by long-time Forced Entertainment fan Ben Kulvichit, speaking to Tim Etchells about their latest show Cold Sweat, how they are integrating lip-sync and AI voices into their work, the question of ‘authenticity’ on stage, and how lip-sync has even opened the door for them to make “something a little bit like drama”. This piece is a paid partnership with the Southbank Centre, where you can see Cold Sweat next month – we’re very grateful to the Southbank Centre for their ongoing support for Exeunt. Holly Williams ‘It was immediately interesting and uncanny’ **By Ben Kulvichit** “Is the microphone on?” So goes one of the opening lines of Signal to Noise, delivered by a human performer lip-syncing to an AI-generated voice. The voice is American, cheery but sluggish, slowed down into a gelatinous drawl. It repeats ad infinitum in a farce of stuckness; an answer never materialises. I find myself asking the same question as I hop on a Google Meet call with Tim Etchells, the artistic director of Forced Entertainment. We spend five or ten minutes frowning at each other, muting and unmuting, me gesticulating in semaphore into my webcam, checking if I am coming through now, restarting the laptop. To Etchells, I appear exaggeratedly mouthing words, my voice missing. In this gloopy purgatory of broken communication, life imitates art imitates life imitates art. We try a Zoom instead. Forced Entertainment, the pioneering British theatre company who have been at the avant-garde of performance since the 1980s, turned an interesting artistic corner with Signal to Noise, created on the occasion of their 40th anniversary. The whole performance employed this lip-sync technique to AI voices; on the face of it a left-field move from a company whose identity has long been grounded in the earthy, immediate presences of its performers and its unassuming, low-tech approach to theatricality. The technique, however, turned out to provide the company with a “rich new seam” of artistic enquiry, and has now spawned a trilogy of works. The second instalment, Cold Sweat, plays at Sheffield Theatres, Southbank Centre, and Lancaster Arts in October, while the third part, Everything Must Go, has been touring in Europe and is slated to come to the UK in 2027. As is often the case with Forced Entertainment shows, the main conceit for this work didn’t arrive until quite late. They were “four or five weeks into rehearsals for Signal to Noise,” Etchells recalls, and getting nowhere. Away from rehearsals, he had been playing around with feeding “weird texts” to AI voices to see how they would cope with them – “basically for my own amusement” – and was compelled by the uniformly “serviceable, benign, good-natured” tone they would read in, no matter how poetic, fractured or experimental the writing. On a hunch, he brought some examples into rehearsals and the performers gave lip-syncing a go. “It was immediately interesting and uncanny,” he recalls, with the performers having to deal in the moment with the problem of mapping themselves onto another artificial ‘performer,’ which itself was dealing with the problem of a very human text. “Almost all the writing for these projects would be useless to us unless it was done in this way,” says Etchells. “We wouldn’t know what to do with it. It’s too poetic. It’s too fictional. It’s too tangled.” But exploring lip-syncing along to the text has opened “an enormous reservoir of ways of thinking about writing and performing.” Subscribe to Exeunt, and get two in-depth pieces on theatre a week, direct to your inbox Subscribe Forced Entertainment have long been sifting through the detritus of popular culture, from daytime TV to end-of-the-pier vaudeville, magic acts and clown shows, to find frameworks for their own unusual entertainments. Lip-syncing, then, makes sense for them to experiment with. As a mode of performance, it’s wired into popular consciousness through pop stars trying to convince stadium audiences of their liveness, or those same voices as channeled through the made-up lips of contestants on RuPaul’s Drag Race, or movie dialogue spreading virally through the host bodies of TikTok users. For Etchells, lip-syncing is often about “approaching real voices and trying to take on their aura,” subsuming that original human presence into yours. “There’s a very basic, elemental sort of theatre magic to it, produced in this very easy way.” This broad approach resonates with instances of lip-syncing within contemporary performance, too. In works like Re-Member Me and Showmanism, performance artist Dickie Beau acts as a kind of spirit medium for archival recordings (this process of re-membering – as in, giving corporeal form to voices – relies on his masterfully precise actor’s technique), while Frankie Thompson is similarly possessed by a host of characters ranging from a nine-year-old Jacob Rees-Mogg to Cliff Richards, all of whom she finds compellingly nauseating, in the exorcism ritual that is her latest show, Horrible Things. What’s different about Forced Entertainment’s use of lip-syncing is that here, there is no original presence to be channeled. The performers are instead taking on what Etchells describes as “the voices of nobody,” or rather the “phantasmic, aggregated echoes” of the many many voices on whose data the AI has been trained, and which are now conjuring into existence words they never actually said. There is a sort of mournful, empty quality to these voices, having “washed up” far away from the people they originally belonged to, to find themselves in stranger’s mouths listing objects, wondering if anyone can hear them and glitching in interminable loops. There is a cold, sad anonymity to it all. Etchells remarks that occasionally the software company he used has notified him that particular people are withdrawing their voices from the platform, instructing him to cease use of those voices. Using these technologies in performance certainly brings up ethical questions around digital rights, consent, identity and ownership, although in the grand scheme of things, Etchells is fairly blasé about it: of all the purposes someone’s voice might be put to without their knowledge, “an avant-garde performance is probably the least of their worries.” [ ](https://exeuntmagazine.substack.com/p/frankie-thompson-horrible-things-essay-mental-health-compulsive-behaviours-pleasance-courtyard-soho-theatre) [ Frankie Thompson: How I manage my own ‘horrible things’ at the Edinburgh Fringe ](https://exeuntmagazine.substack.com/p/frankie-thompson-horrible-things-essay-mental-health-compulsive-behaviours-pleasance-courtyard-soho-theatre) Exeunt · Aug 25 [ Read full story ](https://exeuntmagazine.substack.com/p/frankie-thompson-horrible-things-essay-mental-health-compulsive-behaviours-pleasance-courtyard-soho-theatre) For the performers, though, lip-syncing to these strange, artificial voices is an odd task, requiring them to bend their live, human presence into the shapes produced by machines. Politically, it mirrors processes that are already at play in the continued computational automation of human life. Etchells brings up James Bridle’s writings on new technologies as a reference point: one example Bridle gives is of “chaotic storage”, a logistics technique employed by Amazon fulfilment centres whereby items are stored not according to traditional methods of categorisation or alphabetisation, but in a way that an algorithm determines to produce the most efficient routes for ‘picking’ based on customer purchase patterns. This appears completely random and incomprehensible to humans, with paddling pools sitting next to USB sticks sitting next to blowtorches, and so for the warehouse workers, the process of picking items becomes completely reliant on technology which tells them where to go. Our world is increasingly being designed not with humans in mind, but rather machines. As Etchells puts it, “technology malforms the space, and then you end up having to live in it.” Initially, Forced Entertainment tried their best to live in the world of machines: “I was in the it’s-got-to-be-perfect school of lip-sync,” says Etchells. But with their aesthetic being so tied to the failing act, the slipping mask, the shoddy costume, “it’s no surprise really that that didn’t last.” Instead, the performers got to enjoy being late for a line, or playing games with each other, “stealing” each other’s voices. Etchells compares it to the principles of ventriloquism, in which a free-floating voice unattached to a body is fundamentally discomforting and “sort of traumatic”. That discomfort is equally as alluring to Forced Entertainment as the satisfaction of precision, the pretence of authenticity only interesting if shown to be a pretence. Lip-sync has also opened up new avenues for the company. Having been allergic all their lives to Plays-with-a-capital-P, with Cold Sweat Forced Entertainment find themselves approaching something a little bit like drama. Rather than the presentational arena of Signal to Noise’s open white stage, Cold Sweat places us more decisively in a “fictional locale”: what appears to be “the aftermath of some disastrous party or backyard drinking binge” where three figures – family members, or neighbours, perhaps – are the last ones standing. “It’s all quite acrimonious and accusatory, everyone’s talking over each other.” For Etchells, this more fictional mode is “a door that we’ve never been able to open. We’ve just never really gone there.” Perhaps it is the technique of lip-syncing, an extra buffer of mediation, that allows them to venture away from the here-and-now without feeling that they have to commit to the “psychological claptrap” that comes along with acting; to be able to “play the game of theatre, without getting one’s hands too dirty.” As I wonder how else the impulses behind Forced Entertainment’s work have changed over time, it occurs to me that over the last ten years of new creations, with the exception of If All Else Fails, the company’s performers haven’t ever spoken on stage: there were two shows without any language at all, Out of Order and Under Bright Light, and then this trilogy of lip-sync works. Etchells agrees it’s a shift away from earlier productions, that were so often about “the actual voices of the performers and their actual presences. We had a lot of money, in some ways, on an authentic approach to what it might mean to speak on the stage.” But this sense of authentic presence itself had a fakeness to it; these days, Etchells can’t stand that mode of being onstage where performers “are here to be cheeky and witty versions of themselves. I don’t want to be charmed.” Pulling back into a more anonymous space has resulted in works that feel slightly sharper-edged, more brutal in a way. “All of these shows are post-Brexit, post-Trump, post-truth, post-everything,” Etchells notes. Speech, charisma, authenticity – these things feel politically loaded, and perhaps warmth and openness just don’t feel like the right tools to reflect the world we’re living in. “It feels like the space is closing down, and we’re trying to deal with the fact that the system, the structure that you’re in, is more oppressive and more powerful. It probably always was, but I think we’re just more tuned to it now.” Yet even without their voices, the performers’ distinctive presences – ones that many audiences have followed around for years, if not decades – still, inevitably, shine through as they physically navigate whatever unending task the system of the piece has set for them. They’re still trying to keep up with the onslaught of text, still running about, changing costumes, moving stuff around. The human is always stuck in the teeth of the machine, jamming the smooth, frictionless cheeriness of the not-real, gesticulating silently, trying desperately to communicate. Cold Sweat is at Sheffield Theatres, 2 to 3 October; Southbank Centre, London, 9 to 10 October; Lancaster Arts, 14 October [ ](https://exeuntmagazine.substack.com/p/exeunt-recommends-the-best-autumn-theatre-2026-lives-of-others-standard-of-living-our-friends-in-the-north-lanny-) [ Exeunt recommends... the best autumn theatre ](https://exeuntmagazine.substack.com/p/exeunt-recommends-the-best-autumn-theatre-2026-lives-of-others-standard-of-living-our-friends-in-the-north-lanny-) Exeunt · Sep 16 [ Read full story ](https://exeuntmagazine.substack.com/p/exeunt-recommends-the-best-autumn-theatre-2026-lives-of-others-standard-of-living-our-friends-in-the-north-lanny-) This piece was paid for by the Southbank Centre. Such support helps Exeunt to keep publishing the most interesting writing, about the most exciting theatre. Interested in partnering with Exeunt? Visit our Advertise with Exeunt page, where you can get more information, download an advertising pack, and find our contact details.
Jiang Feng: The Unravelling of German & European Politics
A state election in eastern Germany has become a revealing test of the changing political landscapes of Germany and Europe, writes Jiang Feng, Professor and Chairman of the Council of the Shanghai Academy of Global Governance and Area Studies (SAGGAS) at Shanghai International Studies University. His analysis follows the decisive victory of the Alternative for Germany (AfD) (which has been classified as right-wing extremist by German authorities)in the state of Saxony-Anhalt on 6 September, in which it finished far ahead of its mainstream rivals. Jiang previously served as Minister-Counsellor at the Chinese Embassy in Berlin. The following article was published on 8 September 2026 on huanqiu.com, the online platform of the Global Times. On 6 September, the results of the state election in Saxony-Anhalt, Germany, were announced. The Alternative for Germany (AfD), classified as far-right by German authorities, made history by becoming the largest party in the state parliament, winning 43.8 per cent of the vote — twice its share in the previous election. The Christian Democratic Union (CDU), which had governed the state continuously for 24 years, won just 17.2 per cent, its worst result ever in Saxony-Anhalt. On the night the results were announced, the atmosphere at the CDU gathering was unusually calm. There was neither shock nor argument, as if the defeat had long been expected. Several veteran party members who had spent years working in the state government said: “Defeat is not a bad thing. It is time to make changes.” This state election has not only upended Saxony-Anhalt’s political landscape, but also laid bare the deep tensions between Germany’s traditional party structure and model of governance, on the one hand, and an increasingly polarised society on the other. Its repercussions are already being felt at the federal level, making Saxony-Anhalt a useful case study of the broader trend towards political polarisation and realignment in Europe. Governing Difficulties after Electoral Victory The most immediate consequence of the election is a historic setback for the mainstream party order that took shape in post-war Germany. In Saxony-Anhalt, the AfD has leapt from a peripheral party to the largest political force in the state. Its electoral base has expanded beyond the traditional category of “marginal protest voters” to take on the characteristics of a cross-class coalition. The party has not only consolidated its support in rural areas, but also attracted many middle-class voters and even members of the social elite with stable jobs, their own homes, and substantial incomes. It has thus evolved from a “protest party” into one with the potential to govern. Despite its commanding lead in the vote, however, the AfD faces an institutional obstacle to governing the state: the mainstream parties’ long-standing “firewall” against it. Neither of the two potential routes to forming a government appears likely to break the current political deadlock. The first would be a coalition of establishment parties, led by the CDU and bringing together the Social Democratic Party (SPD), the Greens, the Left Party (Die Linke) and the Sahra Wagenknecht Alliance (BSW) in a cross-camp government. In terms of parliamentary arithmetic, such a coalition could prevent the AfD from forming a government and preserve the outward stability of the traditional political order. Yet these parties are fundamentally divided over key issues including immigration, the energy transition, economic management, and cultural and education policy. Coalition negotiations would therefore be extremely difficult, and even if a government could be formed, it would most likely prove short-lived. More importantly, an alliance of establishment parties aimed at keeping the largest party out of government would play directly into the AfD’s narrative that “political elites are suppressing public opinion”. It could deepen perceptions of political unfairness, further strengthening the AfD’s political capital, and creating a dynamic in which “the more it is suppressed, the more people vote for it”. Ulrich Siegmund, the AfD’s candidate for state premier, has said that if efforts to form a government fail because other parties refuse to cooperate, the AfD will push for a fresh election, which he believes could deliver the party an absolute majority of seats. This points to more intense political battles ahead. The second option would be a coalition between the AfD and the BSW. Together, the two parties would command a simple majority in parliament, making this, on paper, the quickest route to forming a government. The BSW is the only elected party that has not ruled out cooperation with the AfD, and the two parties share some common ground, including on policy towards Russia. There is therefore a degree of political basis for cooperation. Were such a coalition to materialise, Germany would see its first state government jointly formed by a party defined as far-right and one with a far-left background, creating what might be called a “bipolar anti-establishment alliance”. Such an outcome would fundamentally break with the ideological boundaries of post-war German party politics. It is worth noting that even if the AfD ultimately fails to enter the state government, its roughly 47 per cent share of parliamentary seats would give it a powerful blocking minority. Without its consent, major decisions requiring a two-thirds majority — including constitutional amendments, significant budgetary adjustments, and state-level institutional reforms — would be extremely difficult to pass. Therefore, whoever ultimately forms the government, the AfD will be an unavoidable force in Saxony-Anhalt politics, with a direct influence on the state’s legislative process. Systemic Failures in Germany’s Governance Model The Saxony-Anhalt election result reflects a systemic failure of Germany’s post-war mainstream-party model of governance to adapt to rapidly changing socioeconomic conditions. It stems from multiple, mutually reinforcing structural tensions and highlights the existing political system’s difficulty in adapting to “an increasingly polarised society First, collective anxiety has replaced individual material hardship as a central driver of political mobilisation. The rise of the AfD can no longer be explained simply by poverty or social marginalisation. Its increasingly cross-class electoral base suggests that what is driving voters towards the party is, above all, concern about the broader direction of society. This anxiety about the future of the political community goes beyond individual gains and losses. In political discourse, economic anxiety has become closely intertwined with immigration, while immigration and refugee issues are, in essence, questions of social fairness. This perception turns conflicts over the distribution of social resources into negative assessments of governing parties, providing a broad social basis for far-right political narratives. Second, regional disparities and East German identity have undermined the strategy of addressing eastern Germany’s structural challenges at the regional level. More than three decades after German reunification, eastern states such as Saxony-Anhalt have experienced periods of economic growth, but their underlying economic structures remain weak, and household incomes and wealth remain significantly below those in western Germany. At the same time, they continue to face population outflow, an ageing population, labour shortages, and other structural challenges. At a deeper level, historical experiences — including the collapse of the former East German economic system, mass unemployment during the transition, and the westward shift of decision-making power over major issues — have left some residents with a sense of being “second-class citizens” and of being excluded. For years, the German government treated the “syndrome” of reunification as a regional problem to be gradually addressed at the local level. That approach is becoming increasingly unsustainable, as regional development disparities emerge as a core structural factor shaping national politics. Third, the erosion of institutional trust is perhaps the most decisive factor. AfD supporters tend to distrust establishment institutions, including parliament, government, and the mainstream media. Their concerns about economic security, pensions, and social fairness are significantly greater than the social average. Increasingly, their support for the AfD reflects not an expectation that the existing system can be improved, but a search for an alternative to the current political order. Such a systemic deficit of trust will be extremely difficult for the traditional parties to repair in the short term. Fourth, a generational shift in political mobilisation has amplified political polarisation. Unlike traditional parties, which rely heavily on offline rallies and mainstream media coverage, the AfD has developed a social-media mobilisation strategy built around “raising an issue — identifying who is responsible — offering a simplified solution — building a shared identity”. It turns complex social tensions into concise political narratives, rapidly channelling public sentiment into political support. The contrast on the eve of the election was particularly telling. The establishment parties, together with trade unions and churches, organised an offline march attended by more than 10,000 people, but its reach was largely confined to those present and to traditional media coverage. The AfD held a much smaller indoor event, yet livestreaming on TikTok, YouTube, and other platforms, combined with the involvement of online influencers, gave it a reach and mobilising capacity far beyond that of the march. The contrast illustrates how the traditional parties’ methods of political mobilisation are increasingly struggling to keep pace with a political environment transformed by changes in media technology. A Microcosm of Structural Political Change in Europe The shockwaves from the Saxony-Anhalt election quickly travelled beyond the state to the federal level. Calls for political accountability followed immediately after the results were announced. The governing CDU and SPD are now under enormous pressure, while Chancellor Friedrich Merz and Vice Chancellor Lars Klingbeil face an unprecedented test. Political polarisation in Germany is no longer simply a regional phenomenon. The post-war model of multiparty government by establishment parties is breaking down and being reshaped. Viewed in a broader European context, the Saxony-Anhalt election is part of a continent-wide wave of party polarisation, mainstream-party decline, and rising right-wing forces. Far from an isolated phenomenon, it is a microcosm of the structural political changes unfolding across Europe. Weak economic growth, cultural tensions over immigration, and declining trust in institutions are fuelling the rise of right-wing forces in several countries, challenging the liberal internationalist order established in post-war Europe. As a core member state of the European Union, Germany’s ability to adapt its political system and the direction of its politics will have profound implications for both European integration and the evolution of the international order. Subscribe [ Pekingnology China’s Germany watchers take stock of Berlin’s uneasy turn On 7 December 2025, nearly 50 Chinese scholars and policy researchers gathered in Beijing for the 2025年德国形势年终研讨会 “2025 Year-End Seminar on the Situation in Germany… Read more 9 months ago · 31 likes · 1 comment · YIRUI LI and Yuxuan JIA ](https://www.pekingnology.com/p/chinas-germany-watchers-take-stock?utm_source=substack&utm_campaign=post_embed&utm_medium=web&embedding_publication_id=1151841) [ Jiang Feng on Germany's 2025 and beyond: no easy exit ](https://www.eastisread.com/p/jiang-feng-on-germanys-2025-and-beyond) Yirui LI and Yuxuan JIA · Jan 24 The following is an op-ed by Jiang Feng, published on 29 December 2025 at Shanghai Observer 上观新闻, the digital platform of Jiefang Daily, the official newspaper of the Shanghai Municipal Committee of the Communist Party of China (CPC). [ Read full story ](https://www.eastisread.com/p/jiang-feng-on-germanys-2025-and-beyond)
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