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Former Panthers QB joining Cowboys coaching staff
A former Panthers QB has found himself a new lane within the NFL.
Executive Turntable: Sphere & Fender Name New Chief Communications Officers
This week's Executive Turntable column includes Chris Palmer's elevation at Triple Tiger Records, Timo Hoffman joining Frontiers Label Group and more music industry promotions and hires.
Wisconsin joins lawsuit over new conditions for federal disaster funding
MADISON, Wis. (WXOW) — Wisconsin is joining 25 other states in suing the Trump administration over new federal funding conditions that would force states to change election laws and help
LeBron James to the Sixers: Philly sports world reacts
The Philadelphia sports world is reacting to the news that LeBron James is joining the Sixers.
Sports media reacts to LeBron James signing with Philadelphia 76ers
LeBron James finally made his free agency decision on Friday, and it was not what anyone expected. The NBA’s top newsbreaker, ESPN’s Shams Charania, shared the news with the world after being told directly by agent Rich Paul. James is not reuniting with one of his former teams, the Cleveland Cavaliers, nor is he joining…
Ohio State women's hockey adds Jack Johnson to coaching staff
The 2022 Stanley Cup winner is joining the women’s ice hockey coaching staff as associate head coach.
Jimmy John’s to relocate, add Baskin-Robbins
National ice cream shop Baskin-Robbins is coming to Sioux Falls, joining Jimmy John's in a new location.
Why Republicans are joining the fight against money in politics
Long assumed to be an issue exclusively of the left, it is a top issue of concern among Republican voters.
Xbox VP Leaves Just 3 Months After Joining Asha Sharma's Team
Jared Palmer had joined Xbox from Microsoft's CoreAI division
Samsung Debuts AI-Powered Health Assistant, Joining Packed Market
Samsung Electronics Co. is rolling out a new AI-powered assistant that acts as a virtual health companion, joining a growing number of tech companies using chatbots to deliver personalized wellness insights to its users.Samsung Health Assistant pulls in data from the user’s Galaxy smartphone, smartwatch or smart ring, the company said Tuesday. The firm also announced a series of other features coming to its health platform, particularly around heart metrics.
Draymond Green already knows his role if LeBron James decides to join the Warriors
Draymond Green has no trouble accepting his role if LeBron James does end up joining the Warriors.
Three companies to join Howard County business community
Through a joint venture between Greenebaum Enterprises Inc. and St. John Properties Inc., three tenants will be joining Montpelier Research Park in Laurel.
Veteran bilingual journalist joins North Bay Business Journal staff
Veteran bilingual journalist Raquel Issenberg is joining the staff of the North Bay Business Journal, where she will cover entrepreneurship, employment, job training and health care.
Handover of Health Commodities
Joint Handover of Health Commodities Speech of Chargé d’Affaires Steve Bremner (…) Thank you for joining us. I am here today to demonstrate how U.S. foreign assistance under President Trump’s America First Global Health Strategy and our bilateral health MOU makes America safer and stronger while helping Madagascar build a more self-reliant health system. Through our bilateral Global Health Memorandum of Understanding (MOU) signed in December 2025 with the Ministry of Public Health, our two governments outlined shared priorities and responsibilities, including a strong focus on infectious disease threats and Madagascar’s increasing ownership and co-investment in its own health system. The MOU outlines the structure and terms of U.S. support to Madagascar’s health sector from 2026 through 2030, with a total commitment of $134,305,000 from the U.S. government and $41,216,252 from the Government of Madagascar to work jointly to address malaria, maternal and child health, polio and global health security issues. Stronger health systems help prevent instability and reduce the risk that infectious diseases reach the United States, making both our countries safer. America First foreign assistance is clear and disciplined: It is a tool of strategic engagement, not global charity. Every U.S. taxpayer dollar must show measurable results, reduce long-term dependence on U.S. taxpayer resources, and support greater self-reliance in recipient countries. Support must be efficient and targeted, with zero tolerance for fraud, waste, or abuse. This year, through the U.S.-funded Global Health Supply Chain Program – Procurement and Supply Management project, we are distributing: 989,250 long-lasting insecticide-treated nets, worth $2,000,000 to 63 districts and 1,661 Community Health Centers across Madagascar, with the third and final delivery of these nets having arrived in late June. Through the U.S.-funded Momentum Country and Global Leadership (MCGL) project, we are funding: The full cost of Starlink internet connectivity equipment procurement, installation, and one-year subscription for 31 priority District and Regional Health Offices. Through the U.S.-funded Strengthening Infectious Disease Detection Systems project, we are supplying: 908,523 pieces of critical medical equipment and a modernized digital surveillance system to the Ministry of Public Health. These materials will strengthen health systems, improve response capabilities, and help those most in need of protection from mosquito-borne diseases — particularly malaria, which continues to claim the lives of children and women at an unacceptable rate. Deployed effectively, they will contribute to reducing maternal and newborn mortality in rural and hard-to-reach communities where the need is greatest. In these same underserved areas, Starlink connectivity will play a critical role in enabling the rapid transmission of health data and information to central levels, ensuring that decision-makers receive timely, actionable intelligence and can mount swift, coordinated responses to protect populations. For Americans, this support delivers concrete benefits. Stronger health systems in Madagascar help detect and contain infectious diseases before they spread across borders, protecting American and Malagasy families. More stable, healthier countries can expand trade and economic cooperation with the United States. Our goal is not permanent support; it is temporary, targeted assistance that helps Madagascar save lives while achieving greater self-reliance and independence from foreign assistance. To the health workers and community health agents here that will use the products we’re delivering today: your dedication and skills save lives. Your work exemplifies the kind of local ownership that will enable Madagascar to reduce dependence on foreign assistance and manage the country’s health challenges. This targeted support delivers results today while helping Madagascar build toward a future where it can sustain and expand those health gains independently, ensuring that today’s U.S. support leads to Madagascar’s self-sufficiency. Thank you, Misaotra.
LeBron James Social Media Post Leaves 76ers Fans Intrigued
LeBron James’ NBA free agency run has included hints that he’s interested in potentially joining the Philadelphia 76ers. Nearly two weeks down, James still hasn’t joined his next team after a run with the Los Angeles Lakers. Every move is being watched closely, and James’ latest location has Sixers fans talking. The superstar forward posted […] The post LeBron James Social Media Post Leaves 76ers Fans Intrigued appeared first on HEAVY.
Bentonville’s Dequane Prevo stayed the course with Arkansas football
Prevo is one of three current Razorback receivers to come from Bentonville High School, joining freshman Blair Irvin and junior CJ Brown.
New restaurants and businesses are in the works or expanding in popular downtown area in CT town
The city center is full of activity with multiple businesses at different stages joining the already impressive retail stores and restaurants.
Fidji Simo: The health advice from Zuckerberg she wishes she'd listened to
Fidji Simo, who worked at Facebook before later joining OpenAI, said she regretted not taking up Mark Zuckerberg offer's of a year of medical leave as she struggled with or POTS.
Meet the 14 houseguests joining Big Brother Season 28
CBS revealed the 14 houseguests for Big Brother Season 28, featuring a rocket scientist, MMA fighter, and more.
Justin Bieber and More Join World Cup Final Halftime Show Featuring Madonna, Shakira and BTS
NEW YORK (AP) — Justin Bieber will bring his swag to the World Cup's star-studded, Super Bowl-style halftime show, joining fellow headliners Madonna, Shakira and BTS, FIFA announced Wednesday. Afrobeats star Burna Boy, Venezuelan conductor Gustavo Dudamel and the PS22 Chorus — a choir of elementary ...
Yahoo Sports signs Josh Norris, Hayden Winks after shutdown of Underdog content network
Popular fantasy football commentators Josh Norris and Hayden Winks are joining Yahoo Sports. The duo, which hosted Underdog’s Fantasy Football podcast until this week, when Underdog shuttered its original content network, will bring their show to Yahoo’s digital platforms and FAST airwaves. Yahoo announced the move on Wednesday morning. The show will relaunch later in July. “When…
Hungary moves to overhaul university models banned from Horizon Europe
Hungary’s new government is aiming to overhaul the governance model of the institutions and universities that lost access to Horizon Europe and Erasmus+ funds “in a short timeframe,” according to Péter Horváth, the new state secretary for science policy and innovation. “As of today, the two non-university foundation-controlled institutions under my remit have been transformed,” he told Science|Business. “We hope the universities will follow and that this will be enough to satisfy the EU’s demands.”Under the previous government, led by Viktor Orbán and his Fidesz party, many academic and scientific institutions were restructured and made into special public trust foundations, with members strongly linked to the government given lifelong mandates and significant decision-making powers with little oversight. The European Commission deemed that this undermined academic freedom and transparency in the country, leading to a ban on 34 institutions in 2022, including 21 universities, which saw academics in Hungary lose access to Horizon Europe grants. The new Hungarian government, elected in May and led by Péter Magyar and his Tisza Party, has promised to dismantle this governance model and restore the institutions to EU programmes. As a result, the European Commission has promised to return access to the Erasmus+ education mobility programme, but so far no concrete agreement has been made on the Horizon Europe programme for research and innovation. Hungary has already made legislative changes in June to allow the institutions to be reformed and set a timeline for the implementation.The non-university foundations, which are mainly cultural centres such as the Foundation for Hungarian Culture or the Makovecz Campus Foundation, will all be dissolved by August 31 this year, a date tied to EU-set milestones that Hungary must meet to unlock frozen funds, with control transferred to relevant ministries. Meanwhile, the universities will have until 31 August 2027. For each university foundation, the government will set the dissolution date and the body to take over operations. There is no final decision on a permanent new model for the universities, according to Hungarian MEP Eszter Lakos, who is shadow rapporteur for the Horizon Europe specific programme, a separate piece of legislation detailing implementation rules for the EU’s next research programme, due to start in 2028. “The aim of the transition year is to settle this with [the universities], not to impose a model, and not to put them under state control,” she told Science|Business. “The goal is to give academic independence back to universities.”There are three models that are most likely to be implemented. One would be a return to a traditional, state-run model. Another could be a newer, more self-standing public institution. A third option would be a reformed version of the foundation models that meet EU standards. According to Lakos, the dismantling of the system put in place by the Orbán government is well underway and if all goes according to plan, Hungary could regain access to EU research money by the start of the next academic year in 2027. “I believe that the Hungarian government is doing the necessary changes so the universities could return as beneficiaries to Horizon from the next school year,” she said. In the meantime, “the universities, institutes and cultural assets carry on under proper public stewardship rather than a handful of unaccountable trustees,” said Lakos. The laws passed in June impose new safeguards: board terms are capped at four years and renewable only once, appointments are made through open competitions and sitting politicians cannot join joining these boards.It remains unclear whether a domestic science funding programme set up as a back-up scheme by the former government following the EU funding ban, called HU-rizon, could be continued. “This programme should never have had to have been established in the first place, but it has proven to be quite popular,” he said. “I am considering continuing this programme with a refined focus on helping international collaborations.”Re-organising the research network One of the first priorities for Horváth and his cabinet is to resolve questions over the future of the Hungarian Research Network, Hun-Ren. The network of academic institutes was taken away from the Hungarian Academy of Sciences in 2019 and turned into a quasi-private organisation, with similarities in its governance to the public trust foundations.Horváth and his team have consulted over 5,000 representatives from the network and the conclusion is broad unhappiness with the directors of all the institutes involved. “We have presented the results to the president and the chief executive of the network and this is currently being discussed,” Horváth said. The plan is to re-integrate the network back into the Academy of Sciences but in an improved way, “learning from mistakes of the past,” he added. The government also wants to reintegrate four humanities and social science research centres into the network that the previous government had transferred to Eötvös Loránd University. The transfer brought sharp criticism from the academic community, with a group of Hungarian research heads, including European Research Council grant recipients, sending an open letter to Orbán warning that the transfer would “cause historically significant harm to the entirety of Hungarian scientific life.” The transfer was “one of the biggest shames in Hungarian research in the past 20 years,” Horváth said. “We want to immediately re-integrate them back into the research network and to regain the trust of these institutions, because the way they were treated was really unfair.”Another pressing issue is the Élvonal Excellence Research and Talent Development Foundation, led by Nobel laureate Ferenc Krausz. The foundation signed a financing agreement with the former government earlier this year for a budget of over €730 million over the next five years. The goal is to create a world-class centre to attract top talent from abroad and to develop local researchers. But there was little transparency about this foundation, and news of its huge budget, which is nearly as much as Hungary’s entire research budget, caused a stir in the media following the recent elections. Another issue is that, as with the foundation boards of the institutes banned from Horizon Europe, there was little-to-no oversight of decisions led by Krausz. “It was an excellent idea but an unacceptable execution,” Horváth said of the foundation. “The fact that this is out of the Hungarian funding scheme, mostly concentrating on one person who decides on the budget is unacceptable for us.”The government plans to merge the centre with the National Research, Development and Innovation Office, the country’s R&D funding agency, with a reduced budget. Horváth is hopeful that Krausz will still be involved. The new government’s R&D goalsA phrase that crops up regularly during the discussion with Horváth is “democratic process.” The new state secretary is determined to involve Hungary’s research community in shaping future policies. This marks a departure from the previous government’s approach, and several people in Hungary’s research community have commented on the openness of the new government. In terms of concrete goals, Horváth and his team already have plans. He wants to create a new science fund in Hungary, based on the best practices of other European countries. The fund would not be tied to annual government budgets and would provide long-term, stable financing. “If we were to succeed in creating this fund, then I think it would be one of the biggest achievements for me in this period of government,” Horváth said. On the innovation side, he is looking into how best to bring in the private sector. “We want to make sure that we are working with the private sector to support innovation,” Horváth said. One of his big aims is to introduce entrepreneurship teaching into high schools. Hungary already has a reputable national academy offering research and innovation training in the field of natural sciences, and Horváth wants to expand this to all disciplines and across the whole country. “One of the main ways to elevate our innovative businesses is to teach our children to be innovative,” he said. “This will probably need ten years to pay off, but this is what we should do. Our aim is to make Hungary strong in our region, and this is what is needed.” Related articlesHungary’s Horizon Europe performance in numbersCommission unlocks Erasmus+ cash for Hungary, Horizon could be next‘Academic Huxit.’ Hungarian researchers speak out on impact of EU ban A more difficult task will be funding. The new government is aiming to increase research spending to 2% of the GDP by 2030, and then increase it to 3% in line with EU objectives. Currently, spending sits around 1.3%. But according to Horváth, the current budget, inherited from the previous government, is “heavily in the negative,” so any plans to increase research spending will have to start next year. Achieving 2% by 2030 already needs a big push, almost doubling the research budget. “This is something we’d definitely like to reach, and something I can see us achieving,” he said. “From the 2030s, I’d like to see an innovative generation growing up that can help us reach the 3% target.” Positivity in the new governmentDespite the many challenges facing Horváth and his team, the mood is positive. “It feels a bit like a start-up right now. Everyone is working 24/7, day and night, trying to do as much as they can. There is a lot of energy,” he said. It is a big change for the state secretary who, like many in his cabinet, is coming from a background in research or business, and not in politics. “Six weeks ago, I was sitting with my microscope and my research PhDs, so it’s been a big change for me,” said the computer scientist, who was previously the director of the Institute of Biochemistry at the Hun-Ren Biological Research Centre in Hungary and worked at the Institute for AI for Health at Helmholtz Munich. But he is relishing the task to transform the country’s R&D landscape. “We feel enormous support from the Hungarian people, but also from Europe,” he said. “We’ve received a lot of letters of support from around Europe. There is big trust there, and huge responsibility on our side. We want to get everything back on track, and there’s a lot to do.”
Dodgers' Shohei Ohtani Reaches Another Impressive Milestone Against Rockies
Shohei Ohtani continues to add to his laundry list of accomplishments by joining one of MLB's most prestigious clubs.
Khris Middleton reportedly rejoining Wizards from Mavericks in 6-team sign-and-trade deal
Khris Middleton reportedly rejoining Wizards from Mavericks via 6-team sign-and-trade deal
Duke Health’s Jonathan Posner named System Psychiatrist-in-Chief and Chair of the Department of Psychiatry and Behavioral Sciences
"I have been struck by the quality of the faculty, the strength of the institution, and the genuine warmth of the Vanderbilt community. I am thrilled to be joining Vanderbilt Health and look forward to the work ahead."
Rui Hachimura is joining the Clippers
The Lakers are losing yet another one of their key players in free agency.
Patrick Ewing reportedly joining Wizards' staff as assistant, with Steve Clifford coming aboard as coaching adviser
Patrick Ewing reportedly joining Wizards' staff as assistant, with Steve Clifford coming aboard as coaching advisor
Former CIA official left Google to start AI business: Career advice
Candice Bryant spent nearly 16 years at the CIA before joining Google. She shares why she left Big Tech and the philosophy that's guided her career.
U. of C. scientists call for halt to Quantum Shore construction, citing contamination and energy concerns
A group of graduate students, research staff and scientists, many affiliated with the University of Chicago, is joining the opposition to the Illinois Quantum and Microelectronics Park, arguing that their
Malik Willis Has 6 Career Starts and CBS Sports Just Ranked Him Among the NFL's Most Intriguing QBs
The NFL is a pass-heavy league, and teams rely on aerial attacks and high-scoring offenses not just to win games, but to contend for a Super Bowl championship. "After rejuvenating his career in Green Bay, Willis will get his first legitimate chance to be an NFL starting quarterback," DeArdo wrote. "It'll be a challenge, though, as Willis is joining a Dolphins team that is starting anew."
Cavs announce 2026 NBA Summer League roster
Nae’Qwan Tomlin will be joining the group heading to Vegas.
Freestone Grove's energy head Michael Pope leaves the firm
Michael Pope closed his firm, Wellfield Capital, before joining Freestone Grove to focus on energy trades. The fund will now focus on other sectors.
Report: Penguins sign Andrei Kuzmenko to one-year contract
The Pittsburgh Penguins keep adding, the latest is the report that winger Andrei Kuzmenko is joining the team for one year and $5.0 million. Kuzmenko has been among the NHL’s slowest skaters, but has the hands and scoring ability to cover up that deficiency. Curiously, his salary is right in the price range of Rickard […]
New details emerge on Xbox 'Positron', Microsoft's disc-to-digital program — as it seems likely Xbox Helix will drop discs too
Xbox Helix is likely to be joining PlayStation 5 in dropping discs. A new report describes how Microsoft plans to mitigate the issue.
Haleon teams up with Microsoft in 5-year AI pact to upgrade consumer health operations
Consumer health giant Haleon has tapped Microsoft to incorporate AI across its operations, joining a growing wave of healthcare and life sciences heavyweights turning to Big Tech to execute enterpr | Consumer health giant Haleon has tapped Microsoft to incorporate AI across its operations, joining a growing wave of healthcare and life sciences heavyweights turning to Big Tech to execute enterprise-wide digital overhauls.
Lightfoot claims Bally’s work doesn’t violate revolving door rules
Joining Bally’s could help Lightfoot preserve one of her top achievements as mayor, but is hard to square with her reformer credentials, a top watchdog told Crain’s.
How Would LeBron James Fit on the Philadelphia 76ers?
Imagine King James joining Joel Embiid and Tyrese Maxey. While his elite playmaking could spark a title run, complex salary cap hurdles and roster age remains significant risks.
Anthropic launches AI drug discovery program, joining tech giants in betting on healthcare
Anthropic will start an internal drug discovery program, part of a new push to sell artificial intelligence tools to drugmakers.
Anthropic launches AI drug discovery program, joining tech giants in betting on healthcare
Anthropic will start an internal drug discovery program, part of a new push to sell artificial intelligence tools to drugmakers.
Contract extension marks 'fresh start' for Taylor
Midfielder Fraser Taylor is relishing a "fresh start" under new St Mirren boss Craig McLeish after signing a two-year contract extension. The 23-year-old academy graduate, whose deal now runs to summer 2028, made his first-team debut in 2022 and featured 13 times for the Buddies last season before joining Partick Thistle on loan in January. "I'm really pleased, since the new manager has come in, he spoke to me on the off-season, and his ideas really suit the way I like to play," said Taylor.
2 New Order Members Step Away From Touring Due to Health Reasons
New Order announced Monday that Stephen Morris and Gillian Gilbert will not be joining their show at Primavera in Chile in November.
Jimmie Johnson joins TNT Sports as NASCAR analyst in 2026
Jimmie Johnson is joining TNT Sports as a NASCAR analyst in select races during the 2026 Cup Series season.
Cameron Carr discusses joining the Lakers
NBA mock drafts projected Cameron Carr getting selected between 15 and 20 in the first round. Ending up with the Lakers was more than he could have asked for.
St. Norbert, FVTC partner to make business degree transfer 'seamless'
St. Norbert and Fox Valley Technical College are joining forces to make getting a bachelor's in business at SNC easier.
Rochester Business Hall of Fame announces Class of 2026
Junior Achievement of Central Upstate New York and the Rochester Business Journal announced that three business leaders will be inducted into the Rochester Business Hall of Fame in 2026, joining 155 others who previously have been honored for their contributions to Rochester.
Department of Education investigates Maryland schools over boys access to girls sports and facilities
The U.S. Department of Education has launched an investigation into Maryland's Department of Education and three public School districts, claiming that boys are joining girls athletic teams and accessing girls facilities.
Crooked Letter Sports: With the College World Series and U.S. Open behind us, World Cup soccer takes center stage
Today’s show features wrap-ups of the CWS and U.S. Open, with veteran Mississippi soccer coach Dean Joseph joining the pod to discuss how the tournament is shaping up and the wizardry of Lionel Messi.
ANALYSIS: Fear not Britain, the EU doesn't agree on you rejoining either
Brussels heavyweights are clashing over whether Brexit can be reversed and on what terms
Corewell Health and Champions of the Heart Foundation bring cardiac emergency response training to residents
Corewell Health and the Champions of the Heart Foundation are joining forces to expand emergency preparedness and lifesaving training across Michigan.
Navy SEAL Shawn Ryan Joins Mental Health Tech Company to Help Veterans
“This is personal for me," Ryan told Military.com about joining the board of directors for INVI MindHealth.
Pols & Politics: Boston Mayor Wu joins Scottish statue traffic cone prank: ‘A sense of joy everywhere’
Boston Mayor Michelle Wu admitted to joining in on a traditional Tartan Army prank by placing a traffic cone on a statue outside City Hall. Plus: US Attorney Leah Foley’s special necklace.
Blue Jays’ Yimi García Not Yet Ready to Return
Yimi García's velocity was down during Thursday's rehab appearance, which was initially supposed to be his last tuneup before rejoining the Blue Jays.
Vance’s threat is the latest sign US could be breaking with Israel
The United States joining with Israel to launch a war in the Middle East was always a fraught situation for the longstanding US-Israeli alliance.
The European Council’s new political arithmetic
Four freshly installed prime ministers are joining the EU leaders’ table.
Jimmie Johnson joining TNT Sports as analyst
As it enters the second season of its media rights deal, TNT Sports is bolstering its NASCAR coverage by adding Jimmie Johnson.
Sanford Health CEO to speak at Healthcare of Tomorrow event
Sanford Health President & CEO Bill Gassen is joining the nation’s top health system executives at a conference by US News & World Report.
Stefon Diggs makes his case for joining Commanders in 2026
Stefon Diggs wants to play. And it sure sounds like he's looking for a homecoming with the Commanders.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
NC State football up to 15 commitments for 2027
NC State’s 2027 recruiting cycle is going well by Dave Doeren standards—call it Gunnermentum. Gunnercitement! Gunner … hell, I don’t know. NC State has 15 verbal commitments with the addition of offensive lineman Jacob Burns, a high-three-star prospect from Georgia. Burns is the fourth player to commit to NC State since Sunday, joining safety Alex […]
From YouTube to Disney+: Preschool hit 'Gracie's Corner' lands streaming and development deal
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From YouTube to Disney+: Preschool hit 'Gracie's Corner' lands streaming and development deal
The educational series “Gracie’s Corner” is joining Disney+.
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Federal health care cuts threaten Michigan hospitals. It’s time for Medicare for All.
Community hospitals are there for us at our most vulnerable moments. They’re where our children are born. We rush our loved ones to the local ER, post-stroke, when every second counts. Unfortunately, the federal government has left communities across Michigan at risk of losing that lifesaving care. That’s why working people are joining forces to call for change, and to build a society that puts patients before profits, with Medicare for All.
Is There a Business Case for Closing Fitting Rooms?
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open 42-bed medical rehabilitation hospital in South Point, Ohio
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Manav Suthar's dream debut: First Indian in 25 years to ...
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Did Gates just swing open for Sonics' return?
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World Ocean Day Celebration at Seacoast Science Center
For Seacoast Science Center, this year marks a remarkable 35 years of providing outstanding coastal and ocean education at Odiorne Point State Park along the New Hampshire seacoast! World Ocean Day, a global celebration that honors our one shared ocean, presents the perfect opportunity for us to invite our community to come together and celebrate the ocean that connects us all.On June 20th, the Center will host its flagship World Ocean Day celebration from 10 AM to 2 PM. Enjoy hands-on games, educational activities, naturalist-led tide pooling sessions, music, and much more! You’ll also have the opportunity to meet local scientists, divers, artists, and conservationists who are dedicated to safeguarding our one world ocean. See the schedule and the organizations joining us on our event web page: https://www.seacoastsciencecenter.org/world-ocean-dayWe can’t wait to see you by the coast for learning, discovery, and plenty of fun, all aimed at inspiring the conservation of our Blue Planet!
Will Colts and Bears both call Indiana home?
Will the Chicago Bears be joining the Indianapolis Colts in the state of Indiana?
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Jordan: 2026 World Cup Squad, Fixtures and Schedule
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After 14 NFL seasons, Russell Wilson enters a sports TV role
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LEGO Batman: Legacy Of The Dark Knight Finally Punches Up Switch 2 Release Date
Joining a particularly stacked month
Mancini not interested in joining Inter
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Martin Scorsese is betting on AI to transform storyboarding process
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Milan Momcilovic commits to Kentucky Basketball over Louisville Cardinals
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New York Democrats push redistricting amendment, joining national battle
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Former Packers WR lands with former Packers coach in Philadelphia
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Patriots players offer honest take on A.J. Brown rumors
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Society of Interventional Radiology announces support for bill that would cut $700M in Medicare costs
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Sabalenka, Osaka clash in blockbuster French Open tie
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Castleton moving sports to MASCAC
CASTLETON, Vt. (WCAX) - After nine years in the Little East, Castleton is moving the majority of its athletic programs to the Massachusetts State Collegiate Athletic Conference. 20 of the 26 Spartans sports programs will move ahead of the 2027-28 school year. Castleton previously played one football season in the MASCAC before joining the New Jersey Athletic Conference ahead of the 2025 season. The MASCAC currently includes seven state universities from Massachusetts. Castleton replaces the one private member, Anna Maria College, as it shut down permanently at the end of this school year. There are a few hurdles Castleton will have to figure out: while four of the six sports not joining the MASCAC don’t participate in a traditional collegiate conference, the tennis programs will likely need to find affiliate memberships to build schedules. And Castleton will have to schedule rival Norwich as part of its nonconference hockey slate...but athletic director Tim Barrett says it’s the right move for the Spartans, especially when it comes to football. “We’ve had ongoing conversations for the last couple of years regarding the possibilities within the MASCAC,” Barrett said. “Obviously, we had the one year relationship for football in the MASCAC, we enjoyed our time there, we felt at that point we were a natural fit for that conference. So we’re looking forward to it, we’re also looking forward to the next seasons within the Little East Conference, but I do think this was the right move at the right time.”
Magic reportedly hire Spurs associate coach Sean Sweeney as team's new head coach
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Milton Williams' blunt take on A.J. Brown possibly joining Patriots
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Google Health Premium joins AI Pro as weekly email redesigned
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Sports reporter Gabrielle Lucivero joining ESPN as part of WNBA coverage
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Dozens of Philly nightlife spots want to party until 4am during World Cup
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Pope Leo XIV isn't joining Anthropic, but the memes are funny
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One of horror's most iconic characters is finally coming to Dead by Daylight just in time for its tenth anniversary
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What do Spurs and West Ham need on final day?
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Riot Claims Valorant Anti-Cheat Software Isn't Bricking PCs
'They can absolutely get f*cked. I'll be joining whatever class action comes from this,' one player wrote