SCROLL NEWS / DISCOVERY
Search headlines
Find the stories shaping the conversation.
Results for " flu " 2,884 found 🔀 AI-powered Shuffle
MORNING BUSINESS REPORT: Colleges offering social media influencing degree, monthly jobs report
Jane King has these stories and more from the New York Stock Exchange for your Friday Morning Business Report.
Kentucky flu cases trending up as health departments stock up on vaccines
Statewide flu numbers are trending up slightly, while COVID-19 cases are flattening out after an earlier increase.
Columbia Health expands annual flu fair outreach to additional locations and day
Columbia Health expanded its annual flu fair this year, adding a second vaccination location and an extra day. Eligible affiliates have one day left of the four-day fair to stop by and get vaccinated.
Seasonal vaccinations available at Waushara County Health Department
The Waushara County Health Department has announced that seasonal vaccinations, including Influenza and COVID-19 vaccines, are available for local residents. Vaccination appointments are scheduled …
$7.5B plan for California science agency free from Trump’s influence will go to voters
Championed by UC scientists, the bond measure scheduled for the March 2028 ballot would help offset federal research cuts by the Trump admin.
Nearly $55 million awarded to boost healthcare access across rural Alabama
Gov. Kay Ivey announced that 34 grants totaling nearly $55 million are being awarded to healthcare providers and institutions throughout Alabama as part of the second round of the Alabama Rural Health Transformation Program (ARHTP) funding for 2026.
50 children in our area hit by cars every year; toxic pond water in Centennial Park; ‘gas station heroin’; plus other stories with Vanderbilt Health sources
In a news report following a Murfreesboro child who was killed by an automobile, reporter Amber Jayanth from WSMV Channel 4 News cited statistics gathered at Monroe Carell Jr. Children’s Hospital at Vanderbilt about pediatric pedestrian injuries. Trauma registry data from Monroe Carell indicates that about 50 children per year on average are treated after being hit by a car. William Schaffner, MD, Professor of Preventive Medicine, was quoted by several news outlets about public health issues, including: CNN (mRNA flu vaccine); ABC News and the American Journal of Managed Care (Pennsylvania measles outbreak); News Channel 5 (blue-green algae in the pond at Centennial Park, which can release toxins that make people and pets sick). WSMV Channel 4 News interviewed Saumya Aujla, MD, Assistant Professor of Clinical Physical Medicine and Rehabilitation, about the health risks of kratom, sometimes called “gas station heroin,” and why Tennessee banned the drug. WTVF News Channel 5 interviewed Brianna Smith, MD, Assistant Professor of Pediatrics, Hematology/Oncology at Monroe Carell Jr. Children’s Hospital at Vanderbilt for a piece on Childhood Cancer Awareness Month. Prevention interviewed Mitchell Gigandet, MD, Assistant Professor in the Neuro-Sleep Division, for a story about MDPI research on caffeine that used EEG imaging to see how the drug impacts sleep. It was found that caffeine may make sleep less restorative even when you fall asleep normally and stay in bed for eight hours. The Wall Street Journal reporter Laura Landro interviewed Joseph Schlesinger, MD, Professor of Anesthesiology Critical Care Medicine, for a story about ICU alarms keeping patients from getting sleep and creating alarm fatigue for nurses. Billboard reporter Melinda Newman interviewed country star Dasha about her upcoming vocal surgery at Vanderbilt Health. The story was picked up by numerous print and radio outlets including People.
Former Target Legal Chief Cashes-in Chips at Gambling Giant Flutter Entertainment
Flutter Entertainment was indefatigable CLO Don Liu's "second attempt" at retirement.
Sporting justice dismissed Rocchi and referee influence investigation
As expected, the sporting justice system has also shelved the investigation into Gianluca Rocchi and referees, confirming no direct contact with clubs including Inter.The scandal had at first seemed t...
How sex chromosomes influence lifelong health beyond determining biological sex
A new review published in Science brings together growing evidence that the X and Y chromosomes do more than determine biological sex. They also shape how cells function, age and respond to disease.
Could Congress Reshape the Next Round of Conference Realignment?
The Protect College Sports Act could limit the growth of the wealthiest conferences while making successful Mountain West programs more attractive for future expansion. By Roger A. Holien | Mountain West Connection College football realignment has largely been driven by television contracts, conference revenue, and schools seeking greater national exposure. Now, Congress could influence what […]
Ph.D. Recipient Dr. Sun Young Park Publishes on Gut Health Advertisement on TikTok
While earning her Ph.D. in Communication Theory and Research from Florida State University’s (FSU) School of Communication, Dr. Sun Young Park collaborated with Drs. Jaejin Lee and Braidyn Lazenby in her publication, “Gut health goes viral: analyzing influencer advertising for dietary supplements on TikTok”. This research examined how TikTok creators discuss gut health and promote…
Trump's $500 Obamacare 'rebate' checks land in prime political battlegrounds
President Donald Trump's administration is sending $500 payments to nearly 1 million Americans this week, in a move that strategists say could potentially influence races that may determine whether his Republicans maintain control of Congress in the November midterm elections.
Trump's $500 Obamacare 'rebate' checks land in prime political battlegrounds
President Donald Trump's administration is sending $500 payments to nearly 1 million Americans this week, in a move that strategists say could potentially influence races that may determine whether his Republicans maintain control of Congress in the November midterm elections.
‘Gobsmacked’: Florida parents, teachers decry changes to science education
The state’s education commissioner, responding to criticism, said Thursday he was “not advocating religious influence in the standards.”
Pflugerville to gain 2 restaurants, plus other business news
Several restaurants are coming soon to Pflugerville, including Ramen Ramen Tatsu-ya and Snooze. The community also welcomed two indoor golf simulator businesses over the summer.
How Washington Funded the Politicization of Science
Over the last half-decade, the National Science Foundation (NSF) has spent hundreds of millions of dollars on projects designed to influence academic policies, both in the sciences and other disciplines. The aim was to foster a progressive conception of social justice in these fields. In pursuit of this end, the foundation earmarked nearly a million dollars for a project titled “Creating Inclusive Scientific Societies through Policies and Practices,” over a million for a project on “Faculty Online Learning Communities for Gender Equity,” and over $2 million to foster “racial equity focused departmental change.” Through a public records request, I’ve obtained the proposals and progress reports for dozens of NSF grants designed to promote social justice. Although funding for these grants was eventually halted by the Trump administration, the projects illustrate an important facet of recent higher-education policy. Many of the university policies that promised “social transformation” didn’t arise in a vacuum. They were actively encouraged by outside funders—often by the federal government itself. Subscribe Accreditation—the peer-review process which enables universities to receive federal grants and student loans—has recently become a policy battleground, with accreditors wielding significant power over both universities and academic disciplines. In 2020, when Oregon Health and Science University’s medical school issued an extensive diversity action plan—which promised “consequences” for employees who failed to support “DEI, anti-racism and social justice”—it specifically pointed to the Liaison Committee on Medical Education (LCME), the medical-school accrediting body, to justify the overhaul. The NSF actively promoted DEI-focused accreditation policies. The proposal for a $1.2 million program on promoting “community engagement” in STEM, which I obtained through a records request, notes that the Accreditation Board for Engineering and Technology was exploring changes to its criteria “that would incorporate JEDI [justice, equity, diversity, and inclusion].” The proposal promised to “support broader JEDI efforts in the general criteria for engineering.” Another grant funded a conference designed to “identify and share best practices and strategies to integrate IDEA principles in accreditation criteria”—referring to an acronym that stands for “inclusion, diversity, equity, and accessibility.” Scholarly societies have become another flashpoint in debates over higher education. Critics argue that many of these societies, which have the power to shape entire disciplines, have become increasingly politicized. Again, through its giving, the NSF played a role in promoting this politicization. In one million-dollar grant that received funding in 2024, a group of psychologists proposed a series of social-justice reforms to the Society for the Psychological Study of Social Issues. The proposal, which I obtained via a records request, asserts that “[r]edistributing resources (such as moving different people into leadership roles) is not enough” and that the society’s “governance structures do not yet reflect its stated values of diversity, equity, and inclusion.” Its solution: review and rework the society’s criteria for leadership development, academic awards, conferences, and publications. Adjusting review criteria informed by “intersectionality” designed to fight “epistemic exclusion” is an easy way to introduce de facto ideological litmus tests into the peer-review process. For many of the grants I obtained, such litmus tests seem to be the point. “Academic departments are racialized social systems that produce and sustain the byproducts of systemic racism,” a proposal for a $2.7 million project funded in 2024 asserts, promising to develop “departmentally-focused change efforts that cultivate values, assumptions, and behaviors that advance racial equity.” The University of Illinois Urbana Champaign’s million-dollar “I-ADVANCE” project, which effectively created a small DEI bureaucracy on campus, promised to Embed 28 ADVANCE faculty fellows in STEM departments” to amplify its equity goals. Another $1.2 million project promised to create “faculty online learning communities,” made up of scientists at universities around the country, that would eventually build department-level diversity action plans. “Ultimately,” the proposal asserts, perhaps more perceptively than its authors realized, “both organizational change and intersectionality frameworks deal with power.” Indeed, such grants confer a great deal of power to administrators and scholar-activists, who can even use the mere availability of funding as a tool to advance their causes. That history is worth remembering amid today’s debate over federal involvement in higher education: Washington has been shaping university priorities for years, including by financing efforts to instill progressive ideas about race, gender, and equity into academic institutions—and many of the policies those grants encouraged remain embedded within universities long after the federal money has stopped flowing. John D. Sailer is the director of higher education policy and a senior fellow at Manhattan Institute. Share
Tanner Thomason dives into entertainment hot topics
Should you pay for your bestie to fly first class with you? Tom Cruise is still dancing, and Pete Davidson had something to say about influencers.
Saquon Barkley: fantasy bust or turnaround candidate?
Here's why Saquon Barkley's slow start isn't a fluke, and why he's headed toward his least-productive per-game season.
Amazon Refreshes Kindle, Kindle Paperwhite, and Kindle Colorsoft E-Readers With Flush Screens
There are also fun new colors and two page-turning accessories—a wireless remote and a cover case—that keep the e-reader fresh.
Science or strategy? Researchers call for transparency over the Anthropocene rejection
Since its introduction in 2000, the concept of the Anthropocene—the idea that human activities are the major driver of Earth systems—has become highly influential throughout society, including in culture, ...
BTIG Research Cuts Flutter Entertainment (NYSE:FLUT) Price Target to $110.00
BTIG Research cut their price objective on Flutter Entertainment from $113.00 to $110.00 and set a "buy" rating for the company in a research report on Thursday.
This new qubit could be 100 times less error-prone in superfluid quantum computer breakthrough
A proposed qubit made with superfluid helium could cut quantum computing error rates by around 100 times by shielding quantum information from common forms of electromagnetic noise. If experiments confirm the predictions, the technology could eventually work alongside today’s superconducting qubits or serve as a new kind of quantum memory.
One Small Step: Town Council candidate and art advisor talk religion, identity and how both shape their politics
Gabe Koerber and Shari Brownfield on how Catholicism and Judaism influence their political, community passions.
Democratic Michigan Senate hopeful Abdul El-Sayed explains how science influences his politics
Scientific American spoke to the Michigan Senate candidate about how his background in medicine has shaped his outlook
Inside Larry Ellison's Wide Web of Power, Money and Politics, As Oracle's Data Centers Claim Force Majeure
The $200 billion software titan has suctioned himself to many hubs of influence—from data centers to TikTok to Hollywood studios to the Oval Office itself. Tom Dotan dives deep into Ellison’s kingdom, starting on the island enclave of Lanai.
Democratic Michigan Senate hopeful Abdul El-Sayed explains how science influences his politics
Scientific American spoke to the Michigan Senate candidate about how his background in medicine has shaped his outlook
A high-stakes fight for state political power heats up, with Trump's agenda on the line
Political power in state legislatures and governors’ offices is at stake in the November elections in more than one-third of the states.
Bass lawyers help influencers file complaint against Raman campaign
Two influencers have accused Nithya Raman's mayoral campaign of paying social media influencers who improperly disclosed the payments. The legal fees for their complaint are being covered by Mayor Karen Bass' mayoral campaign.
Entertainment RX: Cancer treatment, concern for a gender-fluid grandchild
Entertainment RX, a new column from former Globe TV critic Matthew Gilbert, is an entertainment-guided advice column offering things to read, listen to, or watch that somehow address — or, in some cases, distract from — the issues readers write in about.
Anthem Draws on Behavioural Science for New “Healthy Influence”
The new approach draws on research into social and behavioural science that focuses on attention, emotion and trust.
Viewpoint: Kennedy’s ‘bad science’: MAGA embrace bolsters HHS secretary’s influence and popularity
Pennsylvania has recorded four measles deaths this year — the state’s first in 35 years — yet the federal government’s official measles death count still
Alix Earle boldly proclaims she’s ‘never read a book’
Influencer Alix Earle was asked about the last book she read, to which she replied she’s ‘never read a book.’
Pflugerville seeks input from small businesses to improve downtown
In an effort to improve its downtown, the City of Pflugerville is seeking input from small business owners interested in opening, relocating or expanding their businesses in the area.
Oregon health officials warn of early flu season, rising measles cases
State health officials say flu season has arrived early in Oregon, and COVID-19 is still in its summer surge.
What Does Your Office Say About Your Business? by Jennifer Kraner
What does your space say about you and your business? More importantly, does it give you the best possible first impression? The minute a client, customer or patient walks through your door, they’re forming an opinion about your business – sometimes consciously, sometimes without even realizing it. Your space is communicating something about you, whether you intend it to or not. At Big Sky Design, we work with all kinds of commercial businesses, including many medical practices, law firms and other corporate offices, and I’ve seen first hand how much thoughtful design can influence that first impression. For businesses in medical, legal, and financial fields, three things are particularly important: trust, privacy and professionalism. Your space should communicate all three while also reflecting who you are as a business. That can be challenging, especially in a new construction project. Often, so much of the budget goes toward the actual construction that things like lighting, comfortable seating, artwork and finishing touches get pushed to the side. But those are often the elements that make a space feel complete – and memorable. Think about your waiting room. Is it comfortable? Is the lighting welcoming? Does the layout make sense? When someone walks through the door, do they immediately know where to go and whom to speak with? In a medical office, there’s another important consideration: privacy. Reception areas can become surprisingly noisy places, with phone calls, conversations between staff and patients, and people discussing personal information. Hard surfaces throughout a space allow sound to bounce around, making it difficult to maintain privacy. We recently worked with an eye doctor's office that had exactly this problem. The reception desk had a large opening, and staff were making and taking phone calls right next to patients who were waiting. We designed an acoustic treatment that acted as a divider between the staff and waiting areas. It absorbed sound, but it also became a branded design element. It was a visual reminder to everyone in the space to be mindful of their voices and what others might be able to hear. Those kinds of thoughtful details can make a tremendous difference. And good commercial design doesn't have to mean making your space flashy. Sometimes it’s as simple as a calming color palette, beautiful artwork, plants, carefully selected lighting or comfortable upholstered furniture. In a medical setting, those touches can help soften what might otherwise feel clinical and reduce anxiety for patients who are already nervous about an appointment. I’ve been in waiting rooms where everyone feels packed together, and you can hear every conversation – even what’s happening in the restroom next door. That’s not the experience you want to create. Your office should also feel like your business. Are you telling people that you’re clean and modern? Sophisticated and unique? Warm and welcoming? Or, unintentionally, are you telling them that your business is outdated? You don’t necessarily need a complete renovation to change that message. Fresh paint, updated lighting, new artwork, better seating or a few branded design elements can make a space feel current and intentional. At Big Sky Design, we’ve worked with radiology, dermatology, and dental practices, among many others. Every practice is different, but the goal is always the same: creating a space that reflects the business behind it and gives every person who walks through the door a positive first impression. Because your office is part of your brand. Make sure it’s telling the story you want people to hear. Read more at bigskydesignonline.com.
Jackson County Health Department hosts walk-in clinics for flu season
The Jackson County Health Department will host walk-in clinics across Murphysboro and Carbondale to help make flu and COVID-19 vaccines more accessible.
Healthy Kids Healthy Futures: Misleading online health claims
In this edition of "Healthy Kids Healthy Futures," we're revisiting the topic of online health claims, diving deeper into posts made by influencers or created by AI.
How Data Center Backlash is Reshaping Politics
We’ll talk about the backlash and how that could influence who gets elected in November.
9th Circuit rejects arguments Prop. 211 law disclosing political donations is unconstitutional
There's nothing unconstitutional about a 2022 Arizona law requiring people be informed of exactly who is spending money on campaign ads designed to influence their votes, a federal appeals court ruled Wednesday.
Oregon health officials urge vaccinations ahead of respiratory virus season
The Oregon Health Authority anticipates a potentially severe season for illnesses, including influenza, RSV and COVID-19.
Resident Evil 5 and 6 Remakes Seemingly Confirmed by Capcom Exec
It seems as though the future of Resident Evil remakes is in flux, with it initially being reported that Resident Evil 5 and 6 would not be getting remakes following the expected Code Veronica and Resident Evil 1 remakes. However, comments by Jun Takeuchi, a franchise veteran who has served as...
MTV VMAs producer clarifies remark about ‘external’ influence leading to Taylor Swift’s new award
MTV VMAs producer clarified a colleague’s remark about ‘external’ influence leading to Taylor Swift’s new award, which she accepted Sunday, before the debut of her ‘Patient Zero’ music video.
Leave your politics behind: Greenland is a historic US victory
The United States, Denmark, and Greenland signed a permanent agreement granting the U.S. broad military access to Greenland to bolster North Atlantic security and counter influence from Russia and …
How Jordan Bardella's political youth was shaped by antisemitic ideology
Accused of writing antisemitic messages when he was a young activist, an allegation he denies, the president of the Rassemblement National came of age politically in a milieu strongly influenced by Alain Soral. An antisemitic polemicist who briefly belonged to the party, Soral remained a popular figure on the French far right throughout the 2010s and, for some, an ideological compass.
Beyond the ballot: UNK lecture highlights Nebraska women’s early political influence
KEARNEY - University of Nebraska - Kearney lecture will highlight Nebraska women's early political influence a...
New Quantum Algorithm Targets Bottleneck in Fluid-Flow Modeling
Oak Ridge National Laboratory researchers developed LuGo, a quantum algorithm that reduced quantum gate requirements by more than 95%.
3 takeaways from the MAHA Summit
Trump administration officials mingled with insurers, corporate executives and wellness influencers at the second Make America Healthy Again Summit. They discussed issues ranging from affordability…
Jefferson County health district ramps up awareness ahead of cold and flu season
As cooler weather approaches, health officials in Jefferson County are urging residents to prepare for cold and flu season by getting vaccinated and practicing
Health officials lower barriers with Parkersburg drive-thru flu shot clinic
Area residents rolled down their car windows and rolled up their sleeves on Tuesday morning as the Mid-Ohio Valley Health Department hosted a drive-thru flu shot clinic at the Wood County Center on Market.
New Jersey Health Department Issues Executive Directives to Ensure Access to Influenza, COVID-19, RSV, and Routine Childhood Vaccines
New Jersey Health Department Issues Executive Directives to Ensure Access to Influenza, COVID-19, RSV, and Routine Childhood Vaccines
Flutter Entertainment reacts to online betting and gaming ban in Brazil
Flutter (FLUT) halts Brazil online betting after a provisional ban; SEC filing outlines possible $70M revenue hit.
Poll: Voting to repeal WA 'millionaires tax' hinges on ballot details
A new poll suggests an initiative to repeal Washington's new high-earners tax is trailing badly, influenced by ballot language that discloses its budget impact.
Green Science Alliance Invented a New Colored Powder and Coloring Material Combined With Glass Components (Silica) That Can Be Easily Removed From Hands
Green Science Alliance has successfully developed a new material combining and compositing colorants (organic pigments, dyes, and fluorescent dyes) with silica...
Stifel reiterates Buy on Flutter Entertainment stock at $133
Stifel reiterates Buy on Flutter Entertainment stock at $133
“The Swan” contestant recalls fluid filling lungs after plastic surgery for divisive show: ‘I almost died’ for reality TV
Hulu’s nightmare-fuel documentary “The Swan: Behind the Mirror” takes viewers inside one of the most twisted reality series of all time.
How execs from Anduril to Zendesk are using personal agents
Top execs at companies like Anduril, Adobe, and KPMG are using personal AI agents for tasks like booking dog walkers and flu shots.
MPP Signs Multiple Regional Agreements To Expand Access To Flu Antiviral Medicine
The Medicines Patent Pool (MPP) has signed sublicense agreements with 11 manufacturers across multiple regions to expand access to generic baloxavir marboxil,
New campaign disclosures reveal how much American political campaigns spend on AI tools
Though politicians are quiet about how they use AI, the book Rewiring Democracy examines how AI is starting to influence American politics
Erika Kirk Doesn't Really Want to Talk Politics. So How's She Going to Lead Turning Point USA?
One year after Charlie Kirk’s murder, the MAGA movement is fracturing and the future of Turning Point USA—the influential and lucrative conservative youth organization he founded at 18—is uncertain. His widow now finds herself both its leader and a victim of the conspiracy mentality Kirk fomented. With unprecedented access to her world, Clara Molot set out to answer the question: Who is Erika Kirk?
Jefferies reiterates Flutter Entertainment stock rating citing US growth
Jefferies reiterates Flutter Entertainment stock rating citing US growth
How elite universities got tangled up in politics and petroleum
Half a century of corporate influence set the stage for Trump's attacks, a new study argues.
How elite universities got tangled up in politics and petroleum
Half a century of corporate influence set the stage for Trump's attacks on higher education, a new study argues.
Bichotte Hermelyn opens a new chapter: Choosing service over survival politics
Assemblymember Rodneyse Bichotte Hermelyn, one of Brooklyn’s most influential Democratic figures, announced she will not seek re‑election.
Study across 40 countries: Political activism linked to representation
Not happy with the election result? Don't worry. Election Day is not the only opportunity to influence politics.
Trump’s mail voting crackdown tests Postal Service leader who says he’s ‘not political’
David Steiner once criticized Donald Trump’s leadership style after seeing him on “The Apprentice.” Nearly two decades later, he finds himself navigating Trump’s influence on the Postal Service.
Flu vaccines offered at health department
Macon County Health Department is offering vaccines as flu season starts.
Are politicians using influencers to bolster their campaigns?
FOX 5 NY's Lisa Evers dives into the story to find the answers.
Old Forge library to host flu clinic
Herkimer County Public Health will offer flu vaccinations for adults at the Old Forge Library. No appointment or county residency is required.
FanDuel’s Parent Flutter Entertainment Loses Brazil After India
Brazil's about-face around online betting delivers the second blow to Flutter in a major market in two years.
Madonna Sparks Health Concerns After VMAs as Sources Claim She Was ‘Wobbling Back and Forth’—‘Everything Seemed to Unravel’
The singer also reportedly "looked flushed and fuzzy."
Executive Brain Health Is Business Infrastructure
The way leaders think, feel, and function influences every decision they make—and every team they lead.
Executive Brain Health Is Business Infrastructure
The way leaders think, feel, and function influences every decision they make—and every team they lead.
Flutter Entertainment PLC Stock (FLUT) Moved Down by 7.20% on Sep 28: Facts Behind the Movement
Flutter halted Brazilian betting operations after a government provisional measure banned online gaming.An extended shutdown will reduce revenue, adjusted EBITDA, and impact non-cash accounting assets.Technical indicators show sell signals, while the company reported annual revenue of $16.38B.
Flutter Entertainment (NYSE:FLUT) Shares Down 6.4%
Flutter Entertainment (NYSE:FLUT) Stock Price Down 6.4% - What's Next?
TCL’s new ‘Designer’ Google TVs are just like Samsung’s The Frame, starting at $899
TCL has launched a new “Designer Series” of TV sets running Google TV with a flush mount design and matte...
Health department, NorthLakes Community Clinic offering local flu shot clinics
Appointments are encouraged, but walk-ins are welcome at all locations, according to the health department.
Essentia Health hosting vaccine clinics ahead of respiratory virus season
As we move into fall, Oct. 1 marks the unofficial start of the respiratory illness season. This is typically when the Centers for Disease Control and Prevention (CDC) starts to see an uptick in reported cases of influenza, RSV and COVID-19.
Get flu and COVID shots before the end of October, public health officials say
Respiratory virus season is on its way, and health officials say it’s time to schedule seasonal vaccines for flu and COVID-19.
Dominique Lewis, Spotlighted By Influential Women, Connects Life Science Expertise With Holistic Wellness
A Career Rooted in Scientific Knowledge, Personal Growth, and Meaningful Transformation Washington, DC – Dominique Lewis has developed a distinctive
COA opens $25M health sciences center Oct. 1
Free flu shots, health screenings and a look inside a state-of-the-art hospital simulation center are all on the schedule when College of The Albemarle opens its new $25 million Regional
Flutter Entertainment - Ceases Sports Betting And Igaming Operations In Brazil As Of Sept 25, 2026
Flutter Entertainment PLC NYSE:FLUT:
Citizens reiterates Flutter Entertainment stock rating on NFL pricing data
Citizens reiterates Flutter Entertainment stock rating on NFL pricing data
Post football's big guys proud to be offensive linemen
If there's one thing about Post football, the Antelopes will have a successful running game. It starts with the big guys up front.
Flu shots now available for the UK campus community
UK students, employees and community members can now schedule their seasonal flu shots at convenient campus locations.
High airfares could stick around even if jet fuel prices fall
Travelers could be stuck paying high airfares even if oil and jet fuel prices fall. Major U.S. airlines and analysts say fluctuating fuel costs make it hard to plan ahead.
Mercy Health upcoming free flu shot event
Click here to view this video from wpsdlocal6.com.
Donald Trump rips into Maria Elvira Salazar in flurry of Truth Social posts Saturday
Trump made several posts critical of Salazar who broke from the President on immigration policy.
AI Is Telling Your Future Clients Who You Are. What Is It Saying?
The sources shaping what AI says about your business can influence how future clients and partners see you before they ever make contact.
Hauser Mental Health in Aviation Act Passes the Senate
The Senate passed the Hauser Mental Health in Aviation Act and a medication transparency bill for pilots and controllers. What they change and what comes next.
Hauser Mental Health in Aviation Act Passes the Senate
The Senate passed the Hauser Mental Health in Aviation Act and a medication transparency bill for pilots and controllers. What they change and what comes next.
Hauser Mental Health in Aviation Act Passes the Senate
The Senate passed the Hauser Mental Health in Aviation Act and a medication transparency bill for pilots and controllers. What they change and what comes next.
CDC vaccine policy recommendations grind to a halt under Health Secretary Kennedy - WSVN 7News | Miami News, Weather, Sports
NEW YORK (AP) — The Food and Drug Administration recently approved a new flu vaccine that tested well in older adults. But the federal agencyRead More
Flutter Entertainment (FLUT) Could Be 40% Undervalued On Revenue Beat And EPS Miss
Flutter Entertainment (FLUT) just delivered a mixed earnings update that drew a sharp response from the market, with revenue ahead of analyst expectations but earnings per share falling well short of forecasts. That miss on profitability lands on top of a weak stretch for Flutter Entertainment, with the share price down 18.23% over the past 30 days and falling 61.87% year to date. The 1-year total shareholder return has declined 70.29%, suggesting momentum has been fading as investors...
SSM Health offers seasonal flu vaccinations
SSM Health Fond du Lac Regional Clinic will offer flu vaccination clinics Oct. 15, 16, 19 and 22 in Ripon. Clinics will be held from 8:30 a.m. to 2 p.m. Flu vaccines are subject to availability, and COVID-19 vaccines will be offered if available.
VMAs producer confirms idea for award Taylor Swift will first receive ‘came from external’ influence
Taylor Swift is receiving the inaugural Artist Director Honors at this year’s ceremony.
VMAs producer confirms idea for new award ‘came from external’ influence
The MTV Video Music Awards is handing out its first-ever VMA Artist Director Honors to Taylor Swift on Sept. 27.
Business founders to share entrepreneurial advice at Utah Tech University’s Boost conference
In partnership with Southern Utah’s most influential business founders and leaders, Utah Tech University’s Atwood Innovation Plaza and the Nucleus Institute are hosting the entrepreneurship-focused conference Boost.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. [1] Intel, “Intel Tech Tour 2025 Panther Lake recap,” Doc. 866361, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/866361/ITT_2025_Panther_Lake_Recap1.pdf [2] Intel, “Core Ultra processors Series 3 datasheet, volume 1,” Doc. 872188-001, Jan. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/872188/872188-001.pdf [3] N. Horiguchi and E. Beyne, “Backside power delivery: How to power chips from the backside,” imec Reading Room, Nov. 25, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/how-power-chips-backside [4] W. Hafez et al., “Intel PowerVia technology: Backside power delivery for high density and high-performance computing,” in Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2, doi: 10.23919/vlsitechnologyandcir57934.2023.10185208. [5] K. Fischer et al., “Intel 18A platform technology featuring RibbonFET (GAA) and PowerVia for advanced high-performance computing,” in Proc. Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2025, pp. 1–3, doi: 10.23919/vlsitechnologyandcir65189.2025.11075006. [6] K.-F. Cheng, C.-L. Teng, H.-Y. Huang, and H.-C. Chen, “Metal oxide composite as etch stop layer,” U.S. Patent 12 176 247 B2, Dec. 24, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12176247B2/en [7] S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS J. Solid State Sci. Technol., vol. 4, no. 1, pp. N3029–N3047, 2015, doi: 10.1149/2.0051501jss. [8] A. V. Mule’, D. J. Towner, D. Seghete, C. R. Ryder, and A. A. Gonzalez, “Multi-layer etch stop layers for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20220102343 A1, Mar. 31, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20220102343A1/en [9] C.-C. Wang and J. H. Wang, “Interconnect structure with dielectric cap layer and etch stop layer stack,” U.S. Patent Appl. 20230253247 A1, Aug. 10, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20230253247A1/en [10] Y. J. Wu, K.-F. Cheng, C.-C. Lee, H.-K. Chang, and H.-Y. Huang, “Etch stop layer for interconnect structures,” U.S. Patent Appl. 20240332070 A1, Oct. 3, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240332070A1/en [11] M. G. Rainville, N. Shankar, K. S. Reddy, and D. M. Hausmann, “Deposition of aluminum oxide etch stop layers,” U.S. Patent Appl. 20180197770 A1, Jul. 12, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20180197770 [12] J. S. Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240112951A1/en [16] Applied Materials, “Applied Materials unveils chip wiring innovations for more energy-efficient computing,” Applied Materials Investor Relations, Jul. 8, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy [17] Samsung, “Samsung showcases AI-era vision and latest foundry technologies at SFF 2024,” Samsung Semiconductor, Jun. 13, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/ [18] C. W. Yeung et al., “Channel geometry impact and narrow sheet effect of stacked nanosheet,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2018, pp. 28.6.1–28.6.4, doi: 10.1109/iedm.2018.8614608. [19] S. Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
Cattaraugus County Health Department to begin offering influenza, covid vaccination clinics
By RICK MILLER Olean Star The Cattaraugus County Health Department will offer 11 influenza and covid vaccine clinics around the county over the next month. Be sure to bring photo identification and…