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High-level Lithuanian delegation visits Miami to strengthen links in tech and business
In the European Union, Lithuania stands out as the country that issues the most licenses for fintech companies and as a growing hub for diverse tech ventures.
Growing AI energy demands, the search for subatomic particles and the hottest amoeba
From the smallest building blocks of life to prehistoric vomit and a newly discovered amoeba that can really take the heat.
High Tide Named to Report on Business Ranking of Canada's Top Growing Companies for Sixth Consecutive Year
High Tide Inc. ("High Tide" or the "Company") (Nasdaq: HITI) (TSXV: HITI) (FSE: 2LYA), the high-impact, retail-forward enterprise built to deliver real-world value across every component of cannabis, announced today that it placed No. 315 out of 375 companies listed on the 2026 Report on Business ranking of Canada's Top Growing Companies, with a verified three-year revenue growth rate of 66% over the 2022 to 2025 measurement period. Highlighting the Company's increasing profitability profile, Ad
Uptown Somerset growing new business opportunities in familiar places
SOMERSET ― Five historic properties are presenting a promising future for a new generation of small business development in the borough's Uptown business district.
From pickups to idle plants: automakers seek lifeline from defence boom
Western automakers are chasing a defence spending boom as a way to sell more vehicles and make use of underemployed factories, though executives say military work will not make up for slowing car sales and growing Chinese competition.
Adexo Advertising Surpasses 500 Active Businesses and $20 Million in Managed Ad Spend
MINNEAPOLIS, MN / ACCESS Newswire / September 28, 2026 / , a Minneapolis-based AI advertising platform that builds and optimizes Facebook and Google Ads for local and service-based businesses, today announced that it now serves more than 500 active businesses and has managed more than $20 million in advertising spend since launching in 2022.The milestone reflects growing demand among small and mid-sized businesses for advertising measured by qualified leads and booked jobs rather than clicks.
Navigating the American Dream: How Integrated Financial Tools, Credit and Rewards Can Help Small Businesses Succeed
(Feature Impact) Owning a small business has been a cornerstone of the “American Dream” for generations. It represents the chance to transform a passion into a livelihood and legacy. However, turning dreams into reality is rarely a smooth or easy process and requires more than ambition alone. Today’s business owners need support and access to tools that enable them to overcome challenges and keep growing.#placement_678081_0_i{width:100%;margin:0 auto;}var rnd = window.rnd || Math.floor(Math.random()*10e6);var pid678081 = window.pid678081 || rnd;var plc678081 = window.plc678081 || 0;var abkw = window.abkw || '';var absrc = 'https://ads.empowerlocal.co/adserve/;ID=181918;size=0x0;setID=678081;type=js;sw='+screen.width+';sh='+screen.height+';spr='+window.devicePixelRatio+';kw='+abkw+';pid='+pid678081+';place='+(plc678081++)+';rnd='+rnd+';click=CLICK_MACRO_PLACEHOLDER';var _absrc = absrc.split("type=js"); absrc = _absrc[0] + 'type=js;referrer=' + encodeURIComponent(document.location.href) + _absrc[1];document.write('');Recent research conducted by the Capital One Insights Center shows 75% of more than 1,000 surveyed small business owners with more than one employee and annual revenues of up to $20 million are confident about the future, and 69% believe their business is actively primed for growth.While this optimism is promising, 47% of business owners still said their operations either stayed the same or became less efficient over the past year, citing issues like back-office friction and fragmented financial systems that make it difficult to get a clear picture of the health of their businesses.If you’re a small business owner eager to grow but not sure how to get there, start with this advice from real small business owners and experts at Capital One.Identify Sources of FrictionBefore you can pour effort into growth, you must understand what barriers are holding you back. Take time to look under the hood of your business to identify where time and energy is being lost.For example, you may be among the 78% of small business owners who feel stressed and uncertain about expense management – think hours spent hunting for receipts, manually entering numbers into software and reconciling accounts. Operational challenges aren’t just a hassle; they also pull attention away from important priorities like serving your customers and planning for growth. “We were focused on making as many candles as possible, especially during the busy season,” said Katie Roering, co-owner of Fontana Candle Co. “A lot of the back-office tasks like procurement, raw material purchasing, forecasting – all the really important things – were done at 3 a.m., 8 p.m. or on Saturday and Sunday, and there really just was not enough time in the day to get everything done that we needed to. We just knew as we continued to grow, we needed to streamline our processes, build out our team and keep moving forward.”Use Integrated Tools to Manage FinancesInstead of balancing 10 different tracking and analysis tools, you can turn to one-stop solutions to improve efficiency. Time gets lost when you’re forced to manually gather and interpret relevant data before you’re able to act. You need a platform that handles the busywork for you.Integrated, or “all-in-one,” financial tools – like accounting and bookkeeping platforms with automation capabilities or business credit cards featuring built-in analytical tools – allow you to easily stay on top of cash flow and day-to-day operations. For small businesses where every hour and dollar makes a difference, consolidating and automating systems can have an immediate impact. In fact, 51% of survey respondents said integrated tools have already fueled their growth.Leverage Credit Access and Rewards WiselyGrowth requires capital, so access to credit is a game-changer for many business owners, with 77% describing it as a key factor in achieving business resilience. Having funds accessible when you need them makes your business more capable of weathering storms such as equipment failures and seasonal slowdowns. It also puts the power in your hands to act when an exciting opportunity presents itself, like an inventory flash sale or the chance to advertise in a new market.Access to credit comes with another advantage: rewards. By using credit cards for your daily business expenses, you can earn cash back, points or travel rewards. Whether you redeem these to cover everyday expenses, book business trips or reinvest in the business, they can act as a bonus source of income. Learn to maximize rewards like the 84% of small business cardholders surveyed so you aren’t leaving money on the table.To learn more about how small business owners can identify obstacles, employ integrated financial tools and use credit as a tool for growth, read the full report at capitalone.com/about/insights-center.Photos courtesy of Shutterstock
Travis Etienne Injury Update is Key News for Saints
Travis Etienne hasn’t gotten his New Orleans Saints career off to a great start. It might be getting worse in Week 3. He appears to have sustained an injury. While the Saints were in the midst of throwing four touchdowns to tight ends (two to Juwan Johnson, two to Noah Fant), Etienne left the field […] The post Travis Etienne Injury Update is Key News for Saints appeared first on HEAVY.
Just One in Four People Trust Business Leaders as AI Adds to Global Trust Gap
Just 24% globally trust business leaders and only 23% trust AI chatbots, according to Ipsos, highlighting a growing leadership and AI trust challenge. Just 24% globally trust business leaders and only 23% trust AI chatbots, according to Ipsos, highlighting a growing leadership and AI trust challenge.
Fewer Than One in Four People Trust Business Leaders as AI Adds to Global Trust Gap
Just 24% globally trust business leaders and only 23% trust AI chatbots, according to Ipsos, highlighting a growing leadership and AI trust challenge. Just 24% globally trust business leaders and only 23% trust AI chatbots, according to Ipsos, highlighting a growing leadership and AI trust challenge.
Art that serves others: How a Harnett County muralist is making a lasting mark in her community
Van Goat Studios, which has been operating since 2019, has allowed Johnson to express herself and reflect the spirit of local communities through murals. Photo provided by Elyse Johnson.Elyse Johnson of Van Goat Studios in Dunn wants to spread her artistry and make a lasting mark in her community. Van Goat, which has been operating since 2019, has allowed Johnson to express herself through murals and decorating electrical boxes in the urban landscapes of North Carolina. On top of traditional mural painting, Johnson offers what she calls “portable murals,” an option tailor-made for structure owners who do not want to commit to a design for their wall.“A contractor builds a framed piece of wood, and then they can frame the ‘mural’ onto the wood, whether it’s into their building, whether it’s interior or exterior,” Johnson said. The beginnings of Johnson’s journey into establishing Van Goat Studios reflect the teachings she wants artists to take away today: everything is a learning opportunity. When she started Van Goat, she shared it was a joint venture with a business partner. “I mainly did that because I didn’t feel like I was ready to go and do this on my own,” Johnson said. Her business partner eventually dropped out of the project, deciding she wanted to pursue other forms of art. That is when Johnson was thrust into growing her business on her own during and in the aftermath of the COVID-19 pandemic. “I had built up my confidence enough to go out and reach new heights,” she said. “And I was probably one of the few that benefited from COVID.”The moment presented a silver lining for Johnson. One of her first projects was a Farmers Day mural for the town of Coats. “When COVID-19 hit, Coats was not able to hold their annual festival, so they had a little bit of savings. They decided they wanted to do something for their community without getting anyone sick,” Johnson said.From there, word of mouth spread. Now, Johnson has an organic way of approaching projects. “Like a lot of muralists, if I feel inspired by a building, I will just go up and talk to that building owner and tell them a mural is something they should consider,” Johnson said. But above all, Johnson says she wants art to be accessible to everyone. Johnson said she is trying to stick to projects that benefit “the little guys.” “I’m not trying to go for a project in downtown Raleigh to get the eight-foot-tall building,” Johnson said. “I’m not trying to go to those major cities and get those huge buildings for two reasons: one, I don’t want to go that high; two, my passion really lies with the small guys.” But due to financial constraints and the material reality of art commerce, that requires open communication, she added. “I don’t want to just snowball you with this huge price, and then you just shut me down because it wasn’t what you were thinking,” Johnson said. “At the same time, I am an advocate for the arts, so I’m not going to give you a $10,000 mural when you’re only going to pay $5,000.” There is a healthy balance in explaining the artistic process and working with clients and the surrounding community, Johnson said.“Your municipality invested this, and this is why they invested this, and this is how it’s going to help and improve your community,” she noted. “Same thing when I’m talking to a small business. You asked for me to come at you with this that is outside your budget. How do we make this still your same exact goal, but within your budget lines?” Johnson also provides lessons to aspiring artists. She does so with a mission: how do you master the balance between being a great artist and a competent business owner? “We still do art lessons, but I’m also going to give you business scenarios,” she noted.One of the scenarios she has come up with for her students is a T-shirt competition. “The kids have to think about ‘okay, I can’t just draw whatever I want on a T-shirt. I need to think about what colors Miss Elyse likes. What does Miss Elyse’s logo look like? What would Miss Elyse like?’” Johnson said. “So the design needs to be around that kind of concept.” As Johnson looks toward the future of Van Goat Studios, she is thinking of time, longevity and succession. Johnson is a new mom, which she said has shaped how she sees the future of the studio.“I still want my name and my business out there continuing, so that when my daughter is of age and she can be more independent, then I can be out there doing more and more,” Johnson said. “I would love to get a student to pass this on to, or an intern. I would love for this business to be passed on to the next generation and let them go.”
Newborn Planet Sets Record as Youngest Known World
Elias 2-24 b, a Jupiter-mass planet under a million years old, is the youngest world ever confirmed and is still growing in the disk around its star
Vučić resigns as Serbia prepares for both parliamentary and presidential elections
Vučić has faced growing pressure from student-led protests
Burnham’s plan for a radical reset collides with economic reality
Surging energy bills, higher borrowing costs and rising inflation have left the PM and his chancellor in a fiscal bind
Growing Research Reveals Potential Link Between Eye Health & Dementia Risk
Your eyes may offer more insight into brain health than once realized.
Where Republicans are playing offense ahead of the midterms
The outcome of the 2026 election will be determined primarily by how well Republicans play defense across the growing list of GOP-held House and Senate seats Democrats are targeting. But the GOP is also hoping to play offense by flipping some House and Senate seats Democrats now control.
OpenAI Pauses Training amid Growing Concerns over AI Agent Behavior
TEHRAN (Tasnim) – OpenAI has paused training of its latest AI models amid growing concerns about agents acting outside their instructions, following several incidents involving searches and interactions with US government websites.
Saudi entertainment center registrations jump 62% in 2 years
Saudi Arabia's active commercial registrations for entertainment centers surged 62% from 5,216 in 2024 to 8,462 by mid-2026, driven by a growing demand for family-oriented venues. Riyadh leads with 3,580 registrations, reflecting a trend where shopping malls increasingly incorporate entertainment options, enhancing their appeal to families and children.
Missouri State Football’s Growing Connection to the Lone Star State
Missouri State head coach Casey Woods and several players with Texas roots prepare to lead the Bears into a matchup against SMU in Dallas, marking the team's third consecutive trip to the state.
Slime Molds and the Growing Science Controversy Around “Intelligence”
Instead of claiming, like the eliminationist, that neither humans nor slime molds are really intelligent, the panpsychist will claim that they both are — and then minimize the difference between them.
Todd Meadows' death chronicled in harrowing 'Deadliest Catch' episode
"Deadliest Catch" is revealing the events that led to the death of one of its stars, Todd Meadows.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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A special thank you to Dr. Tamara Colvin for creating this opportunity through the Entrepreneurial Impact Awards, and to my mentor, Mr. Julius Cook, whose guidance during the Boots to Business program truly paid off. This recognition reflects the hard work of my staff and the trust our customers place in us every day — I’m grateful to serve this community and excited for what’s ahead.”MULTI-GENERATIONAL EXCELLENCE BJL Construction, Cleopatrice Robinson, president“This award is especially meaningful because we are more than a business — we are the continuation of a family legacy built through faith, hard work, craftsmanship, integrity and service. I gratefully acknowledge my grandfather, Deacon Benjamin “BJ” Lacy, Jr., whose example helped establish the foundation upon which our family’s entrepreneurial legacy was built. I also honor my father, the late Dr. Wilson Lacy, former president of BJL Construction. Working alongside him was both an opportunity and an education. He taught me that a business’s reputation had to be earned on every project through honesty, excellence, quality and service. As the current president, I recognize that I did not arrive at this moment alone. I stand on the shoulders of those who came before me, and I am sustained by those who continue to walk beside me.”MICRO BUSINESS Maybridge Development, LLC, Latisha Perkins, owner “I accept this award with so much pride and a whole lot of gratitude. First and foremost, I want to thank my higher power for continuing to guide me and give me the strength to keep going.When I first started this business and moved here to Fayetteville, I had no clue what I was getting myself into. This business has turned me every which way but loose, and I definitely had some moments where I was ready to just pack it up and head back to Georgia. I want to thank my Maybridge team, my village, The Hub, the FCEDC team and all the people and organizations here in Fayetteville who have believed in me and Maybridge and helped us get here.”COMMUNITY IMPACT Greater Life of Fayetteville, Georgeanna Pinckney, CEO & executive director “We are deeply honored to be recognized by FSU and the FSU HUB with the Community Impact Award presented to Greater Life of Fayetteville. I am especially grateful for this recognition because it tells us that you see what we do – and, more importantly, why we do what we do. Our commitment is to serve, empower and create meaningful opportunities for youth and families in our community. Most importantly, we give God first and foremost all the glory. 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More local nursing graduates are staying in the region, according to officials offering an update on the progress of the New Hanover Healthcare Career Partnership at a public forum last night. According to Jack Watson, dean of UNCW’s College of Health & Human Services, the number of UNCW nursing graduates choosing to remain in the area after graduation has climbed from 27% to the mid-40% range. The New Hanover Healthcare Career Partnership aims to address the region’s healthcare worker shortage, with a key focus on nursing through strategic partnerships between UNCW, Cape Fear Community College (CFCC), New Hanover County Schools and the Wilmington Chamber of Commerce Foundation. "Each of the partners had pathway programs,” said Watson, “but they were almost at times done in a silo." One of the New Hanover Community Endowment's largest commitments to date, the collaborative received a $22.3 million grant in 2023, to be disbursed over three years, beginning in 2024. At the public forum, leadership addressed the nursing bottleneck created by the pandemic, and Laurie Whalin, president of the Novant Health Coastal Region, acknowledged that Novant Health had relied heavily on travel nurses during that period, with travel nurses making up about 47% of staff and nursing turnover at 35% at the height of the pandemic. "I can say we are in a tremendously different place today,” Whalin said at the forum. The number of travel nurses employed by the Novant Health Coastal Region has dropped to around 100 today, which Whalin says accounts for less than 4% of the workforce. Roughly two years into the grant term, major stakeholders in the collaboration pointed to various accomplishments tied to the initiative. According to Stephen Hill, vice president of talent development with the Greater Wilmington Chamber of Commerce, 250 more nurses live in New Hanover County in 2026 than in 2023. Whalin added that between 2021 and 2025, the Novant Health Coastal Region has hired close to 1,200 registered nurses. Additionally, according to Whalin, over the past two years, hiring and retention of nursing graduates from UNCW increased by 103%, while hiring and retention of nursing graduates from CFCC increased by 70%. Mandy Mills, director of career & technical education at New Hanover County Schools, pointed to the launch of its first Health Sciences Academy program, established across the county's four traditional high schools (Hoggard High School, Laney High School, Ashley High School and New Hanover High School), which started with 38 students last year. Mills also pointed to growth in the district’s Nursing Fundamentals course, which grew from 10 seats in 2023 to 50 in 2025-2026 and is now offered at all four traditional high schools. Watson emphasized the growing nursing class sizes and offered an update on the school’s accelerated nursing degree, which launched last year. Eleven students graduated in the first class, and all passed their boards on the first try, Watson said. This year’s class has 24 students. When the endowment announced its $22.3 million grant for the collaborative in 2023, UNCW and CFCC were each slated to receive the bulk of the funds, at about $10 million each. UNCW’s plans for the grant money included expanding its simulation lab, Watson said. He added that construction is expected to begin on the simulation lab this year and will likely extend through next year. According to Mary Ellen Naylor, dean of Health & Human Services at CFCC, the college has experienced growth in its associate degree nursing retention, rising from 59% in 2023 to 76% for the May 2026 class. CFCC used part of its endowment funding to support wraparound services, including a housing stipend, tuition assistance, exam assistance, emergency assistance, drop-in daycare and clinical and educational supplies. "We have very strong … students, but once they get into the program, there are competing priorities,” Naylor said. “They are working multiple jobs. They have children. They're single parents." According to Naylor, in 2026, 94% of students who used support services are still enrolled or have graduated. Addressing a question from an audience member about an approaching “enrollment cliff,” driven largely by dropping birth rates, Watson and Naylor said demand remains strong at both schools. “Right now … we do have more applicants than we have spots in our nursing program, and it is still a competitive process to get into,” Watson said. “I do not foresee that changing.” "(We've) doubled enrollment in our nursing programs over the last few years, but just as Dean Watson said, we still have very robust applicant pools, so it is still very competitive to get in,” Naylor said. "We have the applicant pool to support that, but again, it's not as easy as just saying, 'Okay … we're going to take another 90 students.' It's making sure all the resources and infrastructure that we need to educate the students outside the classroom is there as well." In response to a question about applying the collaborative model to other healthcare positions besides nursing, Sophie Dagenais, CEO and president of the endowment, said she sees the potential for the model to expand to other healthcare jobs and even other industries, but that the endowment hopes to learn from this model first. “This is a grant that is in year two of three years, and first we wanted to learn what is this going to demonstrate, what will we learn and then how may we scale it possibly,” she said. According to endowment spokesperson Amber Rogerson, funds for the program are set to expire after June 2027. “It's too early to discuss what happens after that,” wrote Rogerson in an email, “though we know the partners are considering the future, and some of the work supported by the grants is now built into their regular operations.”
Health Care Partnership outlines workforce progress
More local nursing graduates are staying in the region, according to officials offering an update on the progress of the New Hanover Healthcare Career Partnership at a public forum last night. According to Jack Watson, dean of UNCW’s College of Health & Human Services, the number of UNCW nursing graduates choosing to remain in the area after graduation has climbed from 27% to the mid-40% range. The New Hanover Healthcare Career Partnership aims to address the region’s healthcare worker shortage, with a key focus on nursing through strategic partnerships between UNCW, Cape Fear Community College (CFCC), New Hanover County Schools and the Wilmington Chamber of Commerce Foundation. "Each of the partners had pathway programs,” said Watson, “but they were almost at times done in a silo." One of the New Hanover Community Endowment's largest commitments to date, the collaborative received a $22.3 million grant in 2023, to be disbursed over three years, beginning in 2024. At the public forum, leadership addressed the nursing bottleneck created by the pandemic, and Laurie Whalin, president of the Novant Health Coastal Region, acknowledged that Novant Health had relied heavily on travel nurses during that period, with travel nurses making up about 47% of staff and nursing turnover at 35% at the height of the pandemic. "I can say we are in a tremendously different place today,” Whalin said at the forum. The number of travel nurses employed by the Novant Health Coastal Region has dropped to around 100 today, which Whalin says accounts for less than 4% of the workforce. Roughly two years into the grant term, major stakeholders in the collaboration pointed to various accomplishments tied to the initiative. According to Stephen Hill, vice president of talent development with the Greater Wilmington Chamber of Commerce, 250 more nurses live in New Hanover County in 2026 than in 2023. Whalin added that between 2021 and 2025, the Novant Health Coastal Region has hired close to 1,200 registered nurses. Additionally, according to Whalin, over the past two years, hiring and retention of nursing graduates from UNCW increased by 103%, while hiring and retention of nursing graduates from CFCC increased by 70%. Mandy Mills, director of career & technical education at New Hanover County Schools, pointed to the launch of its first Health Sciences Academy program, established across the county's four traditional high schools (Hoggard High School, Laney High School, Ashley High School and New Hanover High School), which started with 38 students last year. Mills also pointed to growth in the district’s Nursing Fundamentals course, which grew from 10 seats in 2023 to 50 in 2025-2026 and is now offered at all four traditional high schools. Watson emphasized the growing nursing class sizes and offered an update on the school’s accelerated nursing degree, which launched last year. Eleven students graduated in the first class, and all passed their boards on the first try, Watson said. This year’s class has 24 students. When the endowment announced its $22.3 million grant for the collaborative in 2023, UNCW and CFCC were each slated to receive the bulk of the funds, at about $10 million each. UNCW’s plans for the grant money included expanding its simulation lab, Watson said. He added that construction is expected to begin on the simulation lab this year and will likely extend through next year. According to Mary Ellen Naylor, dean of Health & Human Services at CFCC, the college has experienced growth in its associate degree nursing retention, rising from 59% in 2023 to 76% for the May 2026 class. CFCC used part of its endowment funding to support wraparound services, including a housing stipend, tuition assistance, exam assistance, emergency assistance, drop-in daycare and clinical and educational supplies. "We have very strong … students, but once they get into the program, there are competing priorities,” Naylor said. “They are working multiple jobs. They have children. They're single parents." According to Naylor, in 2026, 94% of students who used support services are still enrolled or have graduated. Addressing a question from an audience member about an approaching “enrollment cliff,” driven largely by dropping birth rates, Watson and Naylor said demand remains strong at both schools. “Right now … we do have more applicants than we have spots in our nursing program, and it is still a competitive process to get into,” Watson said. “I do not foresee that changing.” "(We've) doubled enrollment in our nursing programs over the last few years, but just as Dean Watson said, we still have very robust applicant pools, so it is still very competitive to get in,” Naylor said. "We have the applicant pool to support that, but again, it's not as easy as just saying, 'Okay … we're going to take another 90 students.' It's making sure all the resources and infrastructure that we need to educate the students outside the classroom is there as well." In response to a question about applying the collaborative model to other healthcare positions besides nursing, Sophie Dagenais, CEO and president of the endowment, said she sees the potential for the model to expand to other healthcare jobs and even other industries, but that the endowment hopes to learn from this model first. “This is a grant that is in year two of three years, and first we wanted to learn what is this going to demonstrate, what will we learn and then how may we scale it possibly,” she said. According to endowment spokesperson Amber Rogerson, funds for the program are set to expire after June 2027. “It's too early to discuss what happens after that,” wrote Rogerson in an email, “though we know the partners are considering the future, and some of the work supported by the grants is now built into their regular operations.”
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Reform and the UAE – a threat to British politics
By Alex Carlen The United Arab Emirates likes to present itself as part of the solution to the climate crisis. The oil-rich Gulf state has committed to Net Zero by 2050, hosted COP 28, and even declared “championing climate action” as one of three strategic objectives for this week’s session of the United Nations General Assembly. But behind the scenes the UAE has quietly built one of its closest political relationships in Europe with the party most hostile to climate action in Britain: Nigel Farage’s Reform UK. There is no evidence that the UAE is funding Reform. But a new FairSquare report, Petro-populism: the UAE–Reform threat, published today, documents a growing political relationship that should concern anyone interested in the integrity of British democracy. Reform’s leaders have embraced the UAE’s political model and promoted positions that align closely with the Emirati government’s priorities, while the UAE has given Farage and his party unusually warm access and public backing. What is emerging is not simply a relationship between British politicians and a wealthy Gulf state, but a channel through which an authoritarian government can cultivate political influence here, and abroad. Democracy for Sale relies on its readers. If you already support us, thanks so much. If you don’t, sign up to support fearless independent investigative journalism. Subscribe Back in January, Nigel Farage appeared at a GB News event in Dubai. On the 50th floor of a tower overlooking the luxury resorts and upscale residences of Palm Jumeirah, the Reform leader declared: “I want Clacton to look like this.” At the event – which Farage never declared on his official register of interests – senior Emirati officials mixed with British expats. Farage was keen to flatter. “We recognise you are our friends”, he said, assuring them that “a Brexit London, a Reform London, will remember you.” Controversy surrounding Reform’s finances and its susceptibility to foreign influence have centred around high-profile donations from billionaire crypto donors, and the jailing of Nathan Gill, Reform’s former leader in Wales, for accepting bribes to give pro-Russia speeches. Far less attention has been paid to Reform’s blossoming new alliance with the UAE, an oil-rich authoritarian state with a track record of ruinous anti-democratic interventions. Farage wasn’t always so fond of the UAE. Back in 2023 he called it an “absolute monarchy with an abysmal human rights record.” Now Reform’s hierarchy calls the UAE home. Deputy leader Richard Tice splits his time between his constituency and Dubai and has called on the UK to learn from the UAE. The party’s treasurer Nick Candy runs a firm which has been in partnership with a UAE-state linked firm since 2024. Nadhim Zahawi sits on the board of an Abu Dhabi think tank alongside an array of the most senior UAE officials and is reportedly close to three brothers of the country’s despotic ruler Mohammed Bin Zayed. Reform’s leading lights have effusively praised the UAE’s governance model, defended it from criticism, and advanced its political agenda in the UK. GB News, whose two major shareholders – the Legatum Foundation and Paul Marshall – have strong links to the UAE, has been more than happy to broadcast UAE propaganda and was forced to pay damages in 2025 after airing a false claim about a UK charity by the UAE “disinfluencer” Amjad Taha. The UAE has responded in kind. When the UAE Minister for Foreign Affairs conducted an official visit to the UK in May, Farage was the only non-government figure granted an audience. UAE state media publicised the meeting, and said that they discussed “the strategic relations between the two countries and ways to enhance them in a manner that serves mutual interests.” For the UAE these ‘mutual interests’ largely concern its paranoia over political Islam, and in this regard the UAE-Reform alliance is part of a broad and troubling pattern. Following a crackdown on dissent at home in the aftermath of the Arab Spring, the UAE has offered material and political support to a range of violent and authoritarian actors willing to oppose the Muslim Brotherhood with no regard for the consequences. Its meddling in Egypt, Tunisia, Yemen, and most notably Sudan, have been devastating. The UAE’s strategy of seeking out partners on the political fringes who it believes will advance its interests is not unique to Britain – it extends beyond the Middle East to Europe and the US. In France, it has offered clandestine support to Marine Le Pen through secret meetings, as well allegedly funding trips to the region after which Le Pen returned with a renewed focus on the UAE’s perceived enemies – Qatar and the Muslim Brotherhood. Left-wing opposition leader Jean-Luc Mélenchon has accused the UAE of smearing him and of “encouraging discrimination, hatred or violence”. In the US, the UAE actively supported the rise of Donald Trump, establishing itself as a key ally during both his first and second terms. Around these relationships sits a wider ecosystem of figures willing to amplify UAE narratives, that even extends to Andrew Tate and Tommy Robinson. Subscribe In Britain, the UAE has used a combination of aggressive diplomacy and illicit, disruptive tactics to achieve its policy goal of eliminating any perceived threat from political Islam. In 2012, for instance, it threatened to block billion-pound arms deals with the UK and stop inward investment if David Cameron did not act against the Muslim Brotherhood and rein in the BBC’s coverage of the group – going so far as to suggest, with no supporting evidence, that the group had infiltrated the BBC. It has financed smear campaigns against a high-profile UK charity and funded a mercenary to secretly surveil, and possibly assassinate, a British national on British soil. In Reform UK, the UAE has finally found an ally willing to not only ban the Muslim Brotherhood, but to publicly vilify the group and repeat the UAE’s claims that dangerous Muslims are a fifth column in British society, a narrative that aligns with the Islamophobia and anti-immigration sentiments that underpin Reform’s populist politics. The Rycroft review into foreign interference concluded that “hostile states and non-state actors have a clear incentive to attempt to undermine UK democracy.” The UAE’s network and alliance with Reform must be understood within that framework. It is a powerful, disruptive and deeply authoritarian actor with the resources and networks to intervene in our politics, and a track-record of doing so in a multitude of other countries. The evidence of the threat the UAE poses is overwhelming. The question is whether parliamentarians are willing to call the UAE out and demand action using the tools that the government has to respond. Placing the UAE on the “Enhanced Tier” of the Foreign Registration scheme alongside Russia and Iran would send a powerful signal to the UAE that its meddling will no longer be tolerated, and would place Farage’s next trips to the UAE under the scrutiny they deserve. Alex Carlen is research and advocacy manager at London based human rights organisation FairSquare and author of its new report Petro-populism: the UAE–Reform threat. Subscribe
KFF/AP Survey Probes Rural Voters’ Increasing Anxieties About the Rising Cost of Living, Including Health Costs, Heading into the Midterm Elections
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