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The rise of AI suspicion
As images, videos and text generated by artificial intelligence become more common online, people are increasingly being asked to make difficult judgments: Is this real? Was it made by a person? Can it be trusted? Those questions are no longer limited to computer scientists or technology companies. They now shape how people encounter news, social media, art and books.
Koning Health Announces Agreement with HealthTrust Performance Group, Expanding Access to Advanced Breast CT Technology
/PRNewswire/ -- Koning Health, global leader in breast computed tomography (CT) technology, today announced a new agreement with HealthTrust Performance...
Taft ISD hosts Math, Science STEM family night
Taft ISD students recently received the chance to show off their Science, Technology, Engineering, and Math (STEM) skills during a family night and book fair at the district’s Woodroe Petty
Entertainment Stocks To Add to Your Watchlist
Warner Bros. Discovery, Walt Disney, Verizon Communications, Take-Two Interactive Software, and Spotify Technology are the five Entertainment stocks to watch today, according to MarketBeat's stock screener tool. Entertainment stocks are shares of publicly traded companies involved in producing, dis
Atlas Entertainment, Culture Genesis Set Creator Development Pact
Charles Roven's Atlas Entertainment and creator representation firm Culture Genesis have struck a film, TV and short-form content development pact.
FDA puts aging on its regulatory science agenda
At ARDD 2026, senior FDA officials sketch how a therapy targeting aging might one day reach approval, revealing that longevity is a priority.
Florida State University doctoral student transforms ‘forever chemicals' research into commercial possibilities through NSF's I-Corps program
A Florida State University doctoral student has developed a new approach to destroying “forever chemicals” and is now taking the technology beyond the
Trimble still evaluating possible transport tech business sale
Trimble continues to weigh a possible sale of its transportation technology business after potential buyers approached the company with acquisition interest.
Thomson Reuters and KKR complete joint venture for Global Print Business
/PRNewswire/ -- Thomson Reuters Corporation (TSX/Nasdaq: TRI), a global content and technology company, today announced that it has closed on its previously...
How Washington Funded the Politicization of Science
Over the last half-decade, the National Science Foundation (NSF) has spent hundreds of millions of dollars on projects designed to influence academic policies, both in the sciences and other disciplines. The aim was to foster a progressive conception of social justice in these fields. In pursuit of this end, the foundation earmarked nearly a million dollars for a project titled “Creating Inclusive Scientific Societies through Policies and Practices,” over a million for a project on “Faculty Online Learning Communities for Gender Equity,” and over $2 million to foster “racial equity focused departmental change.” Through a public records request, I’ve obtained the proposals and progress reports for dozens of NSF grants designed to promote social justice. Although funding for these grants was eventually halted by the Trump administration, the projects illustrate an important facet of recent higher-education policy. Many of the university policies that promised “social transformation” didn’t arise in a vacuum. They were actively encouraged by outside funders—often by the federal government itself. Subscribe Accreditation—the peer-review process which enables universities to receive federal grants and student loans—has recently become a policy battleground, with accreditors wielding significant power over both universities and academic disciplines. In 2020, when Oregon Health and Science University’s medical school issued an extensive diversity action plan—which promised “consequences” for employees who failed to support “DEI, anti-racism and social justice”—it specifically pointed to the Liaison Committee on Medical Education (LCME), the medical-school accrediting body, to justify the overhaul. The NSF actively promoted DEI-focused accreditation policies. The proposal for a $1.2 million program on promoting “community engagement” in STEM, which I obtained through a records request, notes that the Accreditation Board for Engineering and Technology was exploring changes to its criteria “that would incorporate JEDI [justice, equity, diversity, and inclusion].” The proposal promised to “support broader JEDI efforts in the general criteria for engineering.” Another grant funded a conference designed to “identify and share best practices and strategies to integrate IDEA principles in accreditation criteria”—referring to an acronym that stands for “inclusion, diversity, equity, and accessibility.” Scholarly societies have become another flashpoint in debates over higher education. Critics argue that many of these societies, which have the power to shape entire disciplines, have become increasingly politicized. Again, through its giving, the NSF played a role in promoting this politicization. In one million-dollar grant that received funding in 2024, a group of psychologists proposed a series of social-justice reforms to the Society for the Psychological Study of Social Issues. The proposal, which I obtained via a records request, asserts that “[r]edistributing resources (such as moving different people into leadership roles) is not enough” and that the society’s “governance structures do not yet reflect its stated values of diversity, equity, and inclusion.” Its solution: review and rework the society’s criteria for leadership development, academic awards, conferences, and publications. Adjusting review criteria informed by “intersectionality” designed to fight “epistemic exclusion” is an easy way to introduce de facto ideological litmus tests into the peer-review process. For many of the grants I obtained, such litmus tests seem to be the point. “Academic departments are racialized social systems that produce and sustain the byproducts of systemic racism,” a proposal for a $2.7 million project funded in 2024 asserts, promising to develop “departmentally-focused change efforts that cultivate values, assumptions, and behaviors that advance racial equity.” The University of Illinois Urbana Champaign’s million-dollar “I-ADVANCE” project, which effectively created a small DEI bureaucracy on campus, promised to Embed 28 ADVANCE faculty fellows in STEM departments” to amplify its equity goals. Another $1.2 million project promised to create “faculty online learning communities,” made up of scientists at universities around the country, that would eventually build department-level diversity action plans. “Ultimately,” the proposal asserts, perhaps more perceptively than its authors realized, “both organizational change and intersectionality frameworks deal with power.” Indeed, such grants confer a great deal of power to administrators and scholar-activists, who can even use the mere availability of funding as a tool to advance their causes. That history is worth remembering amid today’s debate over federal involvement in higher education: Washington has been shaping university priorities for years, including by financing efforts to instill progressive ideas about race, gender, and equity into academic institutions—and many of the policies those grants encouraged remain embedded within universities long after the federal money has stopped flowing. John D. Sailer is the director of higher education policy and a senior fellow at Manhattan Institute. Share
Missouri S&T researcher receives joint appointment with Savannah River National Laboratory
Dr. Michael S. Moats, a professor of materials science and engineering at Missouri University of Science and Technology, has been granted a joint appointment with Savannah River National Laboratory (SRNL). “Savannah River National Laboratory has assembled an exceptional team of researchers advancing critical minerals and materials technologies that are vital to our nation’s energy security...Continue Reading Missouri S&T researcher receives joint appointment with Savannah River National Laboratory
Agassi Sports Entertainment Forms Let's Play, LLC, With Goal of Building a Unified Global Club Network
Jonathan Fornaci Named President of Let's Play, LLCLAS VEGAS, NV / ACCESS Newswire / October 1, 2026 / (OTCID:AASP) ("ASE" or the "Company"), a sports, media, and technology platform focused on the global racket sports ecosystem and built around the iconic brands of Andre Agassi and Stefanie Graf, today announced the formation of Let's Play, LLC, a wholly-owned subsidiary, as well as the appointment of Jonathan Fornaci as President of Let's Play, LLC. As the newly formed facilities division of A
Infosys and Columbia University Launch Strategic Collaboration Across Deep Research to Drive Innovation and Unlock Business Value
/PRNewswire/ -- Infosys (NSE: INFY) (BSE: INFY) (NYSE: INFY), a global leader in AI-first business consulting and technology services, today announced a...
This new qubit could be 100 times less error-prone in superfluid quantum computer breakthrough
A proposed qubit made with superfluid helium could cut quantum computing error rates by around 100 times by shielding quantum information from common forms of electromagnetic noise. If experiments confirm the predictions, the technology could eventually work alongside today’s superconducting qubits or serve as a new kind of quantum memory.
ISU leader: Regions need an AI plan
It’s a good idea for regions to develop an AI plan, as the disruptive technology is changing the local economy and how businesses operate, said Mike Howard, director of the Iowa State University Murray G. Bacon Center for AI Ethics in Business. “It’s really hitting pretty much every industry that you can imagine,” Howard said.…
Global Health & WASH: October 2026 Funding Opportunities (26 new opportunities)
41 opportunities on the Global Health & WASH page this cycle, 26 of them new. The health money on this page is mostly research money, and much of it is aimed at people early in their careers. Funder after funder, from the TANGO2 Research Foundation’s Research Pathways grants to the South African Medical Research Council’s Early Investigators Programme to the National Ataxia Foundation and Alex’s Lemonade Stand Foundation, is funding early-career investigators and the institutions that host them, with a clear tilt toward researchers based in or from the Global South, from AMBSO in Uganda to Kenya’s CONNECT-VAX network to Ersilia’s AI Incubator for African drug discovery. The money is organized by disease as much as by need: narrow foundations, the Parkinson’s Foundation, NTAP for neurofibromatosis, the RUNX1 Research Program for an inherited blood disorder, each run their own grant, so the question for an applicant is less which health problem you work on than which foundation owns your disease. The largest European cheques go to consortia only, with the European Innovation Council putting up to EUR €4 million behind a single healthy-ageing project and UNITE up to EUR €1 million behind each cross-border digital health team. Water sits apart, almost entirely in applied utility research: the Water Research Foundation’s cluster of USD $250,000 to $500,000 projects, each built around a utility problem from sewer laterals to reuse treatment. And the biggest single pot is public: HRSA is renewing community health center service areas with awards of up to USD $10 million each. This post is for paid subscribers. This helps support the time and effort it takes to curate and organize these opportunities. Subscribe To keep this accessible to everyone who needs it, we’re happy to offer pay what you can rates. You can find more details here. Open Opportunities 2027 Building the Field of Health Advocacy Grant, Georgia Health Initiative. *New!* *Closing soon!* Georgia Health Initiative, a nonprofit private foundation focused on health equity, is opening its 2027 Building the Field of Health Advocacy Grant to strengthen the organizations that push for healthier systems across the state. The Initiative treats advocacy as infrastructure, backing one-year projects that range from urgent responses to shifting federal policy to longer arc campaigns on housing, behavioral health, care access, and food security. It wants coalitions that elevate community voice, apply an equity lens, and arrive ready to deploy concrete strategies, and it deliberately seeks variety in issues, communities, and organizational size. The optional webinar and required lobbying training signal a funder investing in a durable field, not one grant cycle. The strongest fits are Georgia nonprofits and public agencies ready to turn advocacy readiness into systems change. Geographies: United States. Who can apply: Tax-exempt 501(c)(3) public charities, state or local government agencies, or coalitions/collaboratives using a 501(c)(3) fiscal sponsor, that work in Georgia on behalf of Georgians and align with the mission, vision, and values of Georgia Health Initiative. Only one application per organization, though an organization may be listed as a partner or subcontractor on multiple applications. Funding amount: Organizations can apply for up to USD $80,000 per project; the Initiative anticipates investing a total of USD $1.36 million. Targeted Sectors / SDGs: Governance, Policy & Advocacy · SDG3; SDG10. Deadline: October 2, 2026. Learn more and apply here. TDD Research Pathways Grant, TANGO2 Research Foundation. *New!* *Closing soon!* The TANGO2 Research Foundation, working with a founding gift from Tango2UK, is opening its TDD Research Pathways Grant to fund early-career investigators anywhere in the world who study TANGO2 Deficiency Disorder. The foundation is using this money to seed pilot work and to build a research community around a rare disorder that few labs currently study. It wants to back emerging scientists, clinicians, and trainees who will stay with this field, not one-off projects, which is why it requires a committed mentor and real institutional support and asks each applicant for a plan for future contributions. The design rewards promise and persistence over track record. The strongest fits are students, residents, postdoctoral fellows, and new investigators ready to commit to TANGO2 research. Geographies: Global. Who can apply: Early-career investigators worldwide, including undergraduate, graduate, and medical trainees, postdoctoral fellows, residents, and clinical or research fellows. Early-career investigators must hold a PhD, MD, or equivalent doctoral degree and be within 10 years of that degree or within 5 years of initiating rare disease research, engaged in postdoctoral research at an academic institution, teaching hospital, or nonprofit research institute. Currently enrolled trainees and transitional PhD candidates beginning a postdoctoral appointment at a nonprofit institution by July 1, 2026 are also eligible. All applicants must identify a qualified mentor with relevant TDD or rare disease research experience and demonstrate institutional support. Funding amount: Up to USD $15,000. Targeted Sectors / SDGs: Innovation, Science & Technology. Deadline: October 2, 2026. Learn more and apply here. Call for Expression of Interest (EOI): AMBSO Impact Research Initiative, Africa Medical and Behavioral Sciences Organization (AMBSO). *Closing soon!* The Africa Medical and Behavioral Sciences Organization is inviting expressions of interest for its Impact Research Initiative, which funds early-stage pilot studies and proof of concept work on priority health challenges. AMBSO is a Ugandan research organization backing bold ideas that can grow into larger studies, and its tracks span antimicrobial resistance, epidemic preparedness, artificial intelligence for diagnostics, HIV prevention, climate and health, cancer, maternal and child health, and non-communicable diseases. The small award size and direct-cost-only rule point to a funder that wants evidence rather than overhead, and that favors projects able to attract follow-on money or use AMBSO’s own research infrastructure. Eligibility runs worldwide, welcoming researchers and institutions inside and outside Africa. The strongest fits are researchers with a feasible pilot that generates policy-ready evidence. Geographies: Global. Who can apply: Open worldwide to researchers, academic institutions, and research organizations whose work aligns with generating high-impact health evidence. Independent researchers are eligible if affiliated with an academic or research institution. Doctoral students are encouraged to apply as part of a research team led by a faculty Principal Investigator. Community-based organizations and other eligible entities may apply. Projects may be implemented inside or outside Uganda. Funding amount: Up to USD $10,000 per project, with no minimum funding threshold. Targeted Sectors / SDGs: SDG3. Deadline: October 2, 2026. Learn more and apply here. Entrepreneurs for Resilience 2027 (E4R27), Swiss Re Foundation. *Closing soon!* Swiss Re Foundation is opening the tenth edition of Entrepreneurs for Resilience, which backs healthcare social enterprises expanding affordable, quality primary care for low-income communities across low- and middle-income countries. The Foundation is using catalytic, blended funding plus multi-year advisory to take risk out of scaling, helping proven models reach more people sustainably rather than stay stuck at pilot size. It looks to back brick-and-click enterprises that pair physical care with digital tools and build affordability through savings, payments, or microinsurance, ideally integrated with public health systems. Requiring earned revenue, real customer scale, and gender-inclusive teams signals that this is growth capital for commercially serious ventures, not seed money. The strongest fits are established, revenue-generating healthcare enterprises ready to scale access for underserved populations. Geographies: Global. Who can apply: For-profit and hybrid healthcare social enterprises serving low-income and underserved populations in low- and middle-income countries, using combined physical and digital (brick-and-click) healthcare delivery models. Applicants must demonstrate measurable social impact, generate at least 50% of income through earned revenue, have been established no later than December 2023, already serve at least 50,000 people with potential to scale, and have at least 30% low-income customers. Preference for gender-inclusive enterprises with at least one female founder or at least 30% women in management. Funding amount: Pilot funding of up to USD $45,000 for the 6-8 shortlisted social enterprises; up to USD $1 million in blended funding (up to USD $600,000 unconditional plus up to USD $400,000 conditional) shared among 3-4 finalists over a two-year implementation period; total programme funding approximately USD $1.3 million. Targeted Sectors / SDGs: Innovation, Science & Technology · SDG3; SDG5. Deadline: October 4, 2026. Learn more and apply here. Horizon HealthTech 2026, IIITD Innovation & Incubation Center. *Closing soon!* IIITD Innovation and Incubation Center is opening Horizon HealthTech 2026, a nine-month MedTech incubation cohort run under the aegis of BIRAC EDGE for founders building medical devices, diagnostics, surgical and interventional tools, or remote monitoring. The center is backing teams that already hold a validated proof of concept and want to reach a tested prototype, pairing each founder with a named expert and clinical validation through a hospital partner. What they seek to back is Indian health technology that can survive real clinical scrutiny and regulatory review, not slideware. The structure, with lab access, CDSCO guidance, IP support, and investor connects, signals a program built to make startups ready for follow-on capital. The strongest fits are early-stage MedTech teams with defensible IP and a working path from bench to bedside. Geographies: India. Who can apply: Early-stage teams/startups with a validated idea/proof of concept (TRL 3 onwards) working on medical devices, diagnostics, surgical/interventional technologies, or remote monitoring, holding IP or with potential to generate IP. Funding amount: No cash award amount is stated on the official program page. Benefits are in-kind: prototyping lab and equipment access, clinical/hospital validation (Max Healthcare), expert mentorship, CDSCO regulatory guidance, IP filing support, workspace, cloud credits and tools, and investor connects. Run under the aegis of BIRAC EDGE and builds a path to follow-on Government/VC/Angel funding. Targeted Sectors / SDGs: Innovation, Science & Technology · SDG3; SDG9. Deadline: October 5, 2026. Learn more and apply here. OpenAI AI and Teen Development Research Grant Program, OpenAI. *New!* *Closing soon!* OpenAI is opening its AI and Teen Development Research Grant Program to fund independent studies of how generative AI shapes the lives of young people ages 13 to 17. OpenAI wants a stronger evidence base on how teens actually use these tools and what that use does to their social and emotional development, so that product teams, policymakers, and regulators can act on findings rather than assumptions. It seeks work on emotion regulation, relationships, belonging, and the safeguards that keep teens safer, welcoming interdisciplinary teams and any methodology. That it will fund research whose conclusions may not favor AI providers, and prioritizes studies touching ChatGPT, signals a genuine appetite for credible outside scrutiny. The strongest fits are research groups grounded in adolescent development, well-being, and AI safety. Geographies: Global. Who can apply: Researchers aged 18 or older who are affiliated with a research institution or organization, and/or have significant experience relevant to child or adolescent development, well-being, human-computer interaction, AI impacts, or a closely related field. Multiple institutions may collaborate. OpenAI is seeking to fund research rather than for-profit initiatives and will not prioritize for-profit organizations. Funding amount: Individual research grants up to USD $1 million, totaling up to USD $5 million; maximum 10% of each grant for overhead or indirect costs. Targeted Sectors / SDGs: Social Inclusion & Community Wellbeing; Innovation, Science & Technology. Deadline: October 6, 2026. Learn more and apply here.
Zacks Industry Outlook Highlights Disney, Madison Square Garden Entertainment, People and Reservoir Media
DIS, MSGE, PPLI and RSVR pursue content and technology strategies as media faces cord-cutting and weaker broadcast TV demand.
Center on Science and Technology being evaluated due to budget constraints
Princeton is reviewing the Center on Science and Technology as part of broader budget reductions, though its courses and StudioLab operations will continue through the current academic year.
Buzz and business impact: Where AI is delivering value
Artificial intelligence has become a popular tool for a significant number of senior living and care providers, with many leveraging this technology to create value for residents, patients and staff members alike. But sometimes AI can be used like a hammer in search of a nail, offering oversimplified solutions for complex challenges, experts warn.
Kyndryl Report: As AI Broadens Modernization Agenda, Leaders Prioritize Business Outcomes Over Replacing Legacy Systems
Global survey reveals how 2,000 business and technology leaders are addressing AI-driven demand across IT elements Nearly half of organizations are behind...
Business Technology Isn’t One Category: 7 Areas Leaders Should Know Before Modernizing
Effective modernization starts with strategic clarity. Leaders should understand these seven core technology areas before investing in AI, systems and digital infrastructure.
AI safety measures widely backed by most Americans, poll finds
WASHINGTON — A vast majority of Americans favor requiring artificial intelligence companies to meet independent safety benchmarks for their models, even if those standards mean slowing development of the technology,
Zacks Industry Outlook Highlights Disney, Madison Square Garden Entertainment, People and Reservoir Media
DIS, MSGE, PPLI and RSVR pursue content and technology strategies as media faces cord-cutting and weaker broadcast TV demand.
DHS Science and Technology Directorate Reorganizes Research Capabilities
The Homeland Security Department revamps research, development, test and evaluation to improve alignment with mission needs.
Micron Technology Tops Lofty Fiscal Q4 Goals, Guides Above Views
Micron Technology beat Wall Street's sky-high targets for its fiscal fourth quarter and with its outlook. Micron stock rose.
Beyond Horizon: Science and competitiveness brief
As Brussels debates how to extract more economic value out of its investments in science and technology, this news tracker brings together the latest developments in EU and national R&I policies, as well as updates on how the worlds of research and industry are working together for a more prosperous Europe.If you have any tips, please email them at news@sciencebusiness.net.You can read the full archive of this blog here.
Best Entertainment Stocks To Add to Your Watchlist
Warner Bros. Discovery, Walt Disney, Roblox, Verizon Communications, and Spotify Technology are the five Entertainment stocks to watch today, according to MarketBeat's stock screener tool. Entertainment stocks are shares of publicly traded companies involved in producing, distributing, or deliverin
Journalists to discuss AI, technology at Drake’s Bucksbaum Business Lecture
Drake University will host journalists Karen Hao and Nicholas Thompson for its fourth annual Bucksbaum Lectureship in Business at 7 p.m. Oct. 21 at the Knapp Center. The lecture, titled “Decoding America’s Tech Moment,” will explore the evolving technology industry and the implications of artificial intelligence. Hao is a bestselling author and award-winning AI reporter…
Iowa's opportunities to expand digital infrastructure
The Technology Association of Iowa brought developers, energy companies, and business leaders together to discuss digital infrastructure in Iowa, highlighting an opportunity for the state to lead in the industry. Brian Waller, president of TAI, delivered the keynote speech during the Iowa Digital Infrastructure Summit on Sept. 29. He argued that data centers support a…
Sportico’s Invest London Unveils Agenda With Global Sports Leaders
Sportico is bringing the sports business industry’s premier event series to London next week. Taking place Oct. 6 at Fulham Pier, Invest London will convene leaders across sports, finance, media and technology to explore where the industry’s next wave of growth will come from. Today, Sportico unveils an agenda spanning global football ownership, basketball’s European …
Sportico Unveils Invest London Speaker Agenda
Invest London will convene leaders across sports, finance, media and technology to explore where the industry’s next wave of growth will come from.
Oklahoma officials highlight rural health program’s first-year progress
Oklahoma is expanding rural healthcare access through new funding for workforce development, technology and medical services.
AT&T Proof of Concept Labs™ Has Spent 30 Years Validating Technology for Customers
The AT&T Proof of Concept Labs is one of the industry's first customer-led labs, helping test and validate networking technologies.
Funding forensic science is essential to keeping New Mexico’s justice system working - NM Department of Public Safety
At the New Mexico Department of Public Safety’s Forensic Laboratory, continuing to produce reliable, accredited results is not necessarily about chasing the newest technology. Often, it is about replacing equipment that has simply reached the end of its useful life. That distinction is important as the state considers how much to invest in the laboratory […]
What Does Anthropic’s Wet Lab Mean for Pharma?
Anthropic has established a wet lab in the San Francisco East Bay. In this article, experts explore what this means for scientific oversight, data ownership, and AI’s potential to transform drug discovery and rare disease research.
DarkIris Inc. Provides Business Update on Cine3.AI Global Expansion and Entertainment Technology Ecosystem
HONG KONG, Sept. 30, 2026 (GLOBE NEWSWIRE) -- DarkIris Inc. (Nasdaq: DKI) (the “Company” or “DarkIris”), an innovative technology provider in the digital media and entertainment sector, today provided a business update highlighting recent progress in the development and global deployment of its flagship AI video production platform, Cine3.AI, as well as the Company’s North American expansion and interactive entertainment initiatives. Advancing Cine3.AI for the “Cinema 3.0” Era Following continue
Debt service and the Pentagon. Private equity and the politics of the US housing market. The return of black lung disease & the Franco-Prussian War in color.
Thank you for opening your Chartbook email. RALPH BALSON. 1890—1964. Oil and enamel, signed. Source: Gavekal This going to hurt - the two 7s in the US: diesel and mortgage rates Source: Gavekal In the US housing market, costs are soaring and the role of corporate, private equity-backed buyers is high on the mid-term election agenda. HEY READERS, THANK YOU for opening the Chartbook email. I hope it brightens your day. I enjoy putting out the newsletter, but tbh, what keeps this flow going is the generosity of those readers who clicked the subscription button. If you are persuaded to click, please consider the annual subscription of $60. It is both better value for you and a much better deal for me, as it involves only one credit card charge. Why feed the payments companies if we don’t have to. Subscribe It is striking how, since 2020, big banks have dropped out of the political spotlight in the US. For contributing subscribers only. Subscribe Rates of the lung disease pneumoconiosis among working US coal miners have risen to levels not seen in nearly 40 years Source: Bloomberg Chinese Clean Technology Exports For contributing subscribers only. Subscribe Ralph Balson (1939) Portrait of Grace Crowley Cole, G. O. & Haseman, S. M., (2023) “‘The Substance of Paint’: Class and Materiality in the Work of Ralph Balson”, Open Library of Humanities 9(2). Ralph Balson (1890–1964) was an English plumber and house painter who emigrated to Australia in 1913 and subsequently became a key member of Sydney’s artistic avant-garde. He is credited with having the first solo exhibition of purely abstract painting in Australia in 1941. Despite his role in developing Australian non-objective painting, Balson remained principally a house painter, working on his art practice at weekends. In 1955 he retired on a state pension and became a full-time artist. Balson’s artistic education and methods were critically shaped by his working-class background. He did not travel abroad until 1960 and was an avid auto-didact. His materials, palette, techniques and compositional strategies were likewise informed by his trade. Balson’s profession as a painter-decorator made him conspicuous within the predominantly middle-class Sydney art scene, though his painting partner Grace Crowley considered it an advantage in their pursuit of constructive painting. This paper explores the impact of Balson’s trade on his trajectory towards pure abstraction. While his art was at odds with the predominantly figurative mode of class-conscious art in Australian Modernism, we argue that it is embedded in the experience of class through its creative adaptation of labour into aesthetics. Source: OLH Svetlana Alexievich, The Art of Oral History No. 1 Paris Review Issue 257, Fall 2026 Interviewed by Elena Kostyuchenko INTERVIEWER How were you able to go to Chernobyl? Did you need special papers? ALEXIEVICH It was a time of chaos. They let me right into the zone. … More than anything, there was confusion. Adamovich [Ales Adamovich, the Soviet Belarusian writer], I remember, persuaded Gorbachev to send in the scientists, who showed up without even bringing their shaving kits. They were told that there had been an explosion at a nuclear power plant, but for some reason they thought that they’d be there for only a day or two. The first time I went was several months later, and people kept telling me about things they didn’t understand—how the fishermen couldn’t find worms, because they’d burrowed deep into the earth, how the milk wouldn’t curdle at the cheese factories. The honeybees wouldn’t come out of their hives. The evacuations started, I think, in the first month. The old women hid, they wouldn’t leave. I mentioned radiation to one of them and she said, “I’ve seen that radiation, all right! It’s yellow with green in it. I saw puddles of it in my garden, and I told the other women, and we ran and looked, and she had it in her garden, and the other one, too!” God, it was wild, the way the mind made sense of it. There was a story going around about Gorbachev telling the scientists to show him the radiation. “We can’t, it’s invisible.” “But I want to see it!” I also ran into the soldiers who’d been flown in on helicopters from Afghanistan. I asked them, “What are you doing here with your machine guns?” They said, “We’re collecting the radiation, that’s what.” So you had some of them running around with their guns, others out in the village washing off firewood or burying soil in the soil. These were the kinds of things that exploded our worldview. They made you realize that culture was just a chest filled with old manuscripts. There were no books in there that could help me. Our philosophers turned out to be useless when faced with the unprecedented. Derrida, Baudrillard—philosophy fell silent. What was happening? How would we live with it? That’s when I decided it simply needed to be witnessed. Which is what I did. INTERVIEWER I wanted to ask about how you talk to people. … ALEXIEVICH Yes, we sit and we talk—about what interests me and about life in general. About love, about everything in the world. That way, what comes out is three-dimensional. If you cut straight to the part you need, which is what journalists do, it won’t be interesting, and it won’t be the truth, either. Not the whole truth. INTERVIEWER Do people always open up when you ask questions, or can questions get in the way? ALEXIEVICH You have to ask questions, of course. Your job is to scour away the banality and return people to their true selves, to make them face what they rarely tap into. With every new person, you have to find a new way to do it. When you ask an interesting question or you share what happened to you, you help people really think about what they’re saying and not just repeat whatever they’ve picked up from the newspaper. But not everybody is capable of it, not everyone wants to put themselves through that. Either the chemistry starts to kick in or it doesn’t. A person might be wonderful, but you can tell that the conversation just isn’t going to happen. You can try to push it, but it will be a product of your own intellect, rather than of that mysterious connection. Life doesn’t come from the mind. Some people I can call two years after our last conversation, and they’ll say, “Oh, Svetochka! I think of you all the time,” and we’ll start talking again. With others, that won’t happen. That doesn’t mean they’re not extraordinary people, just that you can’t connect with them. They might have some insight, but you don’t have the right antenna to pick up their signal. Source: The Paris Review Colorized Franco-Prussian war … the ruins of Strasbourg with a French photographer and his mobile dark room. Ralph Balson (1961) Matter Painting If you’ve scrolled this far, you know you want to click: Subscribe
OBIO marks $1bn funding milestone for Canadian health tech ventures
Life sciences and technology companies supported by the OBIO's CAAP have collectively raised more than $1bn in capital.
How to Listen to Your Favorite Music, Online or Off the Grid
Streaming services can introduce you to a wonderland of nearly unlimited audio, but downloading your digital collection has advantages.
Virginia CEO pay continues to shatter records
Virginia CEO compensation rose to record levels in 2025, led by Capital One's Richard D. Fairbank and DXC Technology's Raul J. Fernandez, reflecting strong equity awards.
South Dakota awards over $13M in behavioral health grants to expand rural care
South Dakota is awarding over $13M in behavioral health grants to help 12 rural clinics expand mental health care, modernize technology, and improve crisis care.
How the 'Money Out of Politics' ballot initiative would work if passed
The senate and gubernatorial races are getting most of the attention, but there's a ballot initiative voters will decide on in November. Eric Lupher with the Citizens Research Council of Michigan discusses how the initiative aiming to get money out of politics would work if passed. Plus, AI Expert John Patterson discusses the technology's role in the 2026 vote.
Whistleblowers allege top NC health officials used false information to secure Medicaid funds
In a newly unsealed federal lawsuit, former state workers allege North Carolina health officials used false information to secure federal funding for a Medicaid technology overhaul, and that federal regulators approved money despite red flags. The lawsuit was dismissed but might be revived.
WATCH: Trump announces accord signed by top AI companies to 'self-police' development
Many of the executives gathered in Washington have called for a slowdown in the development of the technology after several hgh-profile incidents where AI agents have gone rogue.
From Windmills To Ballrooms: Trump’s ‘National Security’ Playbook
Banning journalists from the White House, justifying a triumphal arch, rejecting restrictions on artificial intelligence technology – the positions may be far afield of each other, but they have some commonalities. In addition to being publicly unpopular and legally uncertain, President Donald ...
USA SPORTS DELIVERS VIEWERSHIP RECORDS AND MILESTONES IN INAUGURAL SEASON OF WNBA COVERAGE AHEAD OF WNBA FINALS ON USA NETWORK THIS OCTOBER
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Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
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Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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