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Tuesday ‘Dawg Bites Knows Effort Counts Twice
Welcome to Tuesday, Bulldog Fans! Your Bulldogs are 4-0, and undefeated in conference play. 40+ points in each win, each by 4 touchdowns, ranked #2 in the land, and yet (we know, we know). These are the first world problems UGA fans face in this golden era of Georgia football. A wise man once told […]
Gen. George Marshall's Leesburg home designated National Park Service affiliated area
The General George C. Marshall House in Leesburg, known as Dodona Manor, has been designated an affiliated area of the National Park Service.
‘An opportunity to compete’: DC-area small businesses connect with big institutions
Small minority-owned construction businesses in the D.C. area connected with large contractors at an event at Georgetown University’s Capitol Campus Monday.
Senate Health Panel Delays Bill as Nominees Await Vote
Senate Health Committee recesses HHS markup as measles cases rise. Surgeon General nominee delayed. See why this matters for public health policy.
Scientists solve 1840s space weather mystery
19th century Nature account of 1841 train delayed by geomagnetic storm got year wrong—thanks to a typo.
Fetal surgeon Payam Saadai, MD, to join Rady Children’s Health Orange County
Fetal surgeon Payam Saadai, MD, to join Rady Children’s Health Orange County. Recruitment will advance specialized fetal care for families across Southern California.
Dawg Sports on the Radio
There’s a lot to talk about regarding Georgia’s 41-13 win over Oklahoma. It should be a pretty fun conversation. That’s why I’ll be listening to the glockenspiel player from MaconDawg’s favorite U2 cover band (UAndYourMama2) on WFOY in St. Augustine(102.1 FM/1240 AM) this evening around 6:45 pm Eastern to talk Georgia Bulldog football on SportsNow with […]
GU Politics Welcomes Fall Fellows, Expands Programming to Capitol Campus
The Georgetown Institute of Politics and Public Service (GU Politics) introduced its Fall 2026 class of fellows on Wednesday, Sept. 9, bringing former government officials, political strategists…
Dr. Georges C. Benjamin: Health For All Is True National Security
Dr. Georges Benjamin of the APHA advised NPF fellows about political division that hamper healthcare quality and access and says the U.S. needs a healthcare system that includes everyone.
Gorgeous Lost Bird Species The Ghana Cuckooshrike Rediscovered In Forests Of The Cote d'Ivoire
The bird had not been seen in over 13 years.
Georgia governor's race: Where Bottoms and Jackson stand on health care
Where do Bottoms and Jackson stand on Medicaid expansion and health care access? Credits: Video by Miasarah Lai, Sources: AJC | CSPAN | Riley Bunch / AJC
One geology step closer to the Moon
As we prepare to return to the Moon, Europe’s leading geology training for astronauts PANGAEA celebrates its 10th anniversary turning extraordinary places on Earth into classrooms for space exploration.
Bridge DePaul is making room for political disagreement on campus
The group is entering its second year with plans to focus on dialogue, voter information and student engagement with different political ideas.
How voting rights restorations could impact the midterms
Geography, voting patterns and time all may mitigate the political parties’ ability to capitalize on a new well of potential voters to draw from.
Dungeon Crawler Carl’s Hero Is a Coast Guard Veteran. Here's Why That Matters
A reluctant hero in boxer shorts and ill-fitting pink Crocs stumbles through a galaxy wide dungeon clutching a show cat and wit.
EFI and Agfa’s DPS Business to Combine and Form a Global, Full-Service Industrial Inkjet Company
September 28, 2026 – 7.45 AM CET Regulated information – Contains inside information EFI and Agfa’s DPS Business to Combine and Form a Global, Full-Service Industrial Inkjet Company Combination to Create a Broader, More Diversified Business with a Comprehensive Product Portfolio, Expanded Geographic Reach and Enhanced Capabilities to Serve Customers Across Key End Markets Mortsel, Belgium and Londonderry, N.H. – September 28, 2026 – 7.45 a.m. CET Electronics for Imaging, Inc. (“EFI”), a leading
What to Stream: Quavo album, 'East of Eden' series and 'Minecraft Dungeons II'
A limited series adaptation of “East of Eden” and a new album from Quavo are among streaming releases coming in October. “Teenage Sex and Death at Camp Miasma” premieres Friday
The Winning Smart Victory Post #121
Mateer has led Georgia to a 28-0 halftime lead over the Sooners. Oops. My bad…..forgot where I was for a moment. Yesterday was a perfect day for football. You may remember that DS (Dear Son) applied to UGA back in the day, and was accepted. Because UGA’s Engineering program was new back then, he opted […]
The Wackiest And Wildest Looks From The VMAs Red Carpet
From Lady Gaga’s legendary meat dress to live animals, the VMAs red carpet is home to some of the most outrageous pop culture moments.
5 TV Shows To Watch If You Like The Dungeon Crawler Carl Books
Need something to watch while Dungeon Crawler Carl makes its way to Peacock? From death games to monster meals, these five shows have plenty to offer.
Orbitals Game Review
Despite the gorgeous veneer, the characterization and writing in Orbitals don't have anywhere near the same amount of gas that everything else in it does.
Anna Kendrick Is “Over the Moon” About Directing ‘The Seven Husbands of Evelyn Hugo’
The 'Babies' actress covered George Clooney, 'Twilight' ("what the f*** am I doing here?") and 'Pitch Perfect's "revisionist history" in a career-spanning conversation at the Zurich Film Festival.
Vanderbilt football vs Georgia game time, TV channel announced
See Vanderbilt football's game time and TV info against Georgia in a Week 5 SEC road game.
Minecraft is getting its first new dimension in 14 years, and it's called The Sift
Mojang has announced The Sift, Minecraft's first new dimension in more than 14 years.
Tennessee Titans scouted Oklahoma vs. Georgia
The Tennessee Titans scouting presence remains mysterious as the team evaluates talent for the 2027 NFL Draft.
Commentary: Arkansas football takes care of business to bushwhack upstart Tulsa
The positives coach Ryan Silverfield said Arkansas would build on following last week's home loss to Georgia are magnified as the Razorbacks out-gained their visitors by 200 yards in the rout.
See top photos from Nashville SC's match against Toronto FC
See photos from Nashville SC's Eastern Conference matchup against Toronto FC at Geodis Park on Sept. 26.
MVDs: Oklahoma Edition
You don’t unceremoniously sink the Sooner Schooner without a total team effort. But even then some Bulldogs are bound to stand out above the crowd for their efforts. Those dandy ‘‘Dawgs are your MVDs, the Most Valuable Dawgs from Georgia’s 41-13 victory over Oklahoma. Offense: Talyn Taylor. Taylor’s 4 catches for 110 yards represented a […]
Misery in Georgia: How John Mateer's play continues to be 'a problem' for OU
ATHENS, Georgia — John Mateer still is not cutting it in an OU uniform.
Oklahoma Sooners Suffer Humiliating Loss to the Georgia Bulldgos
Four first-half turnovers and a stagnant offense betrayed Oklahoma’s elite defense in Athens, allowing the Bulldogs to cruise toward a dominant victory before the fourth quarter began
Sooners implode in Athens, lose 41-13
OU lost 41-13 to No. 2 Georgia (4-0) in embarrassing fashion at Sanford Stadium in Athens Saturday.
Evening College Football Live Thread
if your primary objective for this Saturday was to watch the Georgia Bulldogs put up a dominant win in Sanford Stadium then you can mark that one mission accomplished. If you’re now looking for something to do, there are plenty of other intriguing matchups on the slate for this evening. South Carolina travels to Alabama […]
Minecraft Is Getting A New Dimension Called The Sift In 2027
The Sift will first be released with Minecraft Dungeons 2 later this month before arriving in the base game.
Business founders to share entrepreneurial advice at Utah Tech University’s Boost conference
In partnership with Southern Utah’s most influential business founders and leaders, Utah Tech University’s Atwood Innovation Plaza and the Nucleus Institute are hosting the entrepreneurship-focused conference Boost.
Minecraft Dungeons II’s New Dimension Coming to Minecraft Java & Bedrock Edition
At Minecraft LIVE, Mojang announced that the first new dimension in 14 years - The Sift - will be coming to both Minecraft Dungeons II and Minecraft Java & Bedrock Edition. Learn more inside.
OU-Georgia: Live updates, TV details
Availability: The final Southeastern Conference gameday availability report dropped ahead of kickoff with junior defensive lineman David Stone listed as a gametime decision and senior linebacker Kip Lewis set to
Georgia still tops for business following nationwide survey
Georgia’s political leaders are celebrating the state’s ranking as the top location for corporate expansions for the 13th year in a row.
The Camilla Foundation to host 3rd annual "Cultivating Hope: An Evening for Children's Health" on October 6
The Camilla Foundation will host its third annual "Cultivating Hope: An Evening for Children's Health" on Tuesday, October 6, 2026, at The Botanic Garden at Georgia Southern University in Statesboro. The public event will raise funds and awareness for children's mental health services in Bulloch County.
Behold the horrors of DLSS 5, NVidia's real-time AI graphics improver
DLSS 5 is Nvidia's AI-powered tech for dynamically repainting video game scenes in real-time, with more realistic lighting, textures and geometry. Controversial enough on recent games, where it succeeds (more…
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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All-SEC Oklahoma star out for Georgia football game
The Oklahoma Sooners will be without an All-SEC OL against Georgia. QB John Mateer is 1-4 when he has taken three sacks since joining OU
5 Georgia players to know ahead of Saturday's matchup
Five Georgia players to watch against Oklahoma: Gunner Stockton, Craig Dandridge Jr., Nate Frazier, Raylen Wilson and KJ Bolden.
Everton's International's: Tyrique George Shines as Braiden Graham Snubbed
Everton's international contingent continue to shine, with Tyrique George a standout.
Charles brothers 'brilliant' in NI's landmark win
The Charles brothers led the way for Northern Ireland at both ends of the field during the side's Nations League win over Georgia in Tbilisi.
From Sense and Sensibility to Kill Jackie: your complete entertainment guide to the week ahead
Daisy Edgar-Jones dons the bonnet in Georgia Oakley’s take on the Jane Austen classic, and Catherine Zeta-Jones battles assassins in a madcap action caper
Bay Area sports calendar, Sept. 26-27
Stanford quarterback Davis Warren and the Cardinal host Georgia Tech on Saturday at 7:30 p.m. (ESPN)
Georgia Secretary of State warns election officials off political betting
Georgia Secretary of State Brad Raffensperger is warning election officials and poll workers across the state not to place bets on political races as prediction market apps surge in popularity.
Georgia governor candidate Rick Jackson talks veteran health care
Republican candidate for Georgia governor Rick Jackson made a campaign stop in Savannah on Friday afternoon, meeting with local veterans to address health care challenges facing military families and residents across the state.
Georgia governor candidate Rick Jackson talks veteran health care in Savannah
Republican candidate for Georgia governor Rick Jackson made a campaign stop in Savannah on Friday afternoon, meeting with local veterans to address health care challenges facing military families and residents across the state.
Airport sewer spill affecting Flint River health, tests show
After a sewage spill from the world’s busiest airport, tests in a river that supplies drinking water to more than 400,000 Georgians found E. Coli levels so high they were off the charts
Trump’s disruption to TV coverage during Xi visit frustrates Chinese officials
President Donald Trump spent months plotting ways to impress Xi Jinping.
Jenna Bush Hager recalls discovering dad George W. Bush’s previous engagement: ‘Started crying and made it about myself’
The former president was previously engaged to Cathryn Lee Wolfman in 1967.
O'Neill left 'baffled' by refereeing in late win
Michael O'Neill has said he was "baffled" by some of the refereeing decisions in Friday's 1-0 win in Georgia in the Nations League.
Georgia x Northern Ireland - Highlights, Summary and Match Report
Georgia controlled much of the contest at the Boris Paichadze Dinamo Arena, finishing with 62.2% possession, 11 shots and nine corners, while Northern Ireland were more direct with 12 attempts of thei...
Why the 2026 election could be the worst midterm for the GOP this century
The Republican Party’s two worst midterm elections in the 21st Century were in 2006 and 2018. In the former, an unpopular Middle Eastern war cost George W. Bush dearly. In 2018, voters balked at the upending of historic norms and chaotic style of a new president named Donald Trump.
Five things national media and former OU players are saying ahead of Georgia
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Next Week on XBOX: New Games for September 28 to October 2
Minecraft Dungeons II, Gears of War: E- Day Premium Edition, Ace Combat 8: Wings of Theve, The Witcher 3: Wild Hunt — Remastered, and more coming soon to XBOX.
Throwback Dawg Day: Was It The Best Win Ever?
Let’s be honest. Memory lane has been fun this week. When thinking about Oklahoma paying a visit to Athens on Saturday, the instant flashback is to Jan. 1 2018 in that instant classic in the Rose Bowl. Georgia has had so many wins of of jubilation over the years, and to Bulldogs fans, there is […]
Russ Becker Will Lead the MN Business Partnership as Its New Chair
The CEO of APi Group, an engineer and Minnesota native, succeeds Medtronic CEO Geoff Martha.
Yankees’ Anthony Volpe decision got tougher after one huge swing
For six innings Thursday, the Yankees trailed Tampa Bay 4-0. By the end of the eighth, George Lombard Jr. had […]
Iron helped scientists trace Earth’s oxygen. Now it’s telling a bigger story
New research shows the same geological record also bears the fingerprints of mountain building and the rise of land plants
Roma and Hull City locked in race for Kvernadze
Frosinone’s Giorgi Kvernadze is one of the most sought-after players at the moment. The Georgian winger, who has made an excellent start to the season, has reportedly attracted the attention of seve...
Critzer named head of UGA Department of Food Science and Technology
ATHENS, Ga. -- University of Georgia food science expert Faith Critzer has been named head of the Department of Food Science and Technology effective Aug. 1. Critzer, who...
Oklahoma’s Turnover Woes Could Doom Their SEC Run
Oklahoma's -4 turnover margin and weak rushing game are major red flags against Georgia. Here is why the Sooners are in serious trouble this weekend.
Georgia v Northern Ireland
Let us know how you rate the performances of the players on both sides and we'll bring you the results at the end of the game.
Chinese Scientists Say Compact Quantum Magnetometer Tracks Hidden Targets in Field Tests
A quantum magnetometer that detected underground train activity, located a buried magnet and monitored a geomagnetic storm in field tests.
America’s newest soccer star, plus a bad night for Green Bay
The Pulse Newsletter 📣 | This is The Athletic’s daily sports newsletter. Sign up here to receive The Pulse directly in your inbox. Good morning! Don’t get fined today. Coming up: 😮 A Falcons blowout win? ✅ The latest MLB playoff clinches 👋 Say hello to Cavan Sullivan Geoff Stellfox / Getty Images It’s a busy day, so this will be short. Important stuff from last night: The Falcons routed the Packers on the road, 35-14, in one of the more surprising results of the early NFL season. A lesson learned: Having a competent quarterback to go with Atlanta’s...
'If you do want to be a criminal, there is no better place to do it': Author Rose George dives into the dark depths of the fishing industry
Live Science spoke with Rose George, journalist and author of "Every Last Fish," about her book, which delves into the murky world of the fishing industry, the intelligence of the animals harvested, and the hurdles preventing sustainability in the oceans.
Georgia Institute of Technology professor Munmun De Choudhury discusses AI, mental health and humanity
On Wednesday evening, students, faculty and community members gathered in Mills Hall to hear Munmun De Choudhury, a computer scientist, social scientist and professor of interactive computing at the Georgia Institute of Technology, speak as part of the Hastings Initiative lecture series. De Choudhury’s research focuses on digital mental health and the effects of emerging […]
Olympiacos Eyeing OFI Goalkeeper as Panathinaikos Complicates Move
Olympiacos face a strategic battle for OFI Crete's Nikolaos Christogeorgos, as a complex resale clause grants fierce rivals Panathinaikos the power to hijack the deal.
Northern Ireland XI vs Georgia – Predicted lineup and team news
Northern Ireland are ready to kick off their UEFA Nations League Group B journey with an away fixture against Georgia on Friday at the Boris Paichadze Dinamo Arena.Michael O’Neill’s side arrive in...
George Kittle weighs in on 49ers’ surprising early success
San Francisco 49ers tight end George Kittle weighs in on the team's early success.It’s only been about three weeks into the NFL season, and no team might be hotter than...
Lakers Rob Pelinka, JJ Redick confident in offseason roster changeover
Las Vegas Realtors elect new officers, board of directors for 2027
Outgoing president George Kypreos will be replaced by incoming president Shane Nguyen.
Jonathan Fortney, Dan Costa honored by American Geophysical Union
Astronomy and astrophysics professor Jonathan Fortney receives 2026 Whipple Award and ecology and evolutionary biology professor Dan Costa named 2026 AGU Union Fellow
Local business celebrates 30 years of bringing Mexican Western wear to north Georgia
Boots may be her business, but selling her culture is her passion.
Conflict mapping research group founded by OSU researcher wins national award for open science
The American Geophysical Union has awarded the 2026 Open Science Recognition Prize to the Decentralized Damage Mapping Group, an international research team co-founded by Oregon State University Professor Jamon Van Den Hoek and postdoctoral scholar Corey Scher.The prestigious award is in recognition of DDMG’s contributions of satellite mapping data of regions beset by war, conflict or natural disasters to the public sphere, particularly to aid in humanitarian response and provide journalists with up-to-date information.
Concerns about misuse of flock cameras cross Alabama’s political aisle
U.S. Sen. Katie Britt, R-Alabama, joined colleague Sen. Raphael Warnock, D-Georgia, in asking the Department of Justice to give guidance on flock cameras.
First in entrepreneurial excellence: FSU celebrates local businesses at inaugural Impact Awards Gala
The Entrepreneurial Impact Awards Gala provided a formal night out for Fayetteville’s business community. The event took place at the Rudolph Jones Student Center on Thursday, Sept. 10. Photo by GFBJ. Fayetteville State University (FSU) and the Fayetteville-Cumberland Regional Entrepreneur and Business HUB (FSU HUB) came together to celebrate Fayetteville’s business community. The two organizations rolled out the blue carpet at the Rudolph Jones Student Center for their inaugural Entrepreneurial Impact Awards Gala held on Thursday, Sept. 10.The gala honored outstanding entrepreneurs and business leaders who demonstrate excellence, foster growth and inspire the next generation of innovators within the FSU and broader business community.FSU HUB Director Dr. Tamara Colvin was able to highlight that this new milestone was a great way to show local success stories, not just tell.“That one-stop shop that’s across the street, we never promised that everyone would be successful, but what we did promise was access. Four years ago, we opened up an entire ecosystem: counseling, capital, contracts, connections, certifications,” shared Colvin. “I want to thank the judges who took up hard work for choosing tonight’s honorees. That’s never an easy task when the whole region is full of people worth recognizing at the HUB. We practice what we preach: Res Non Verba: Deeds, not words.” A few of the inaugural recipients of the awards shared their statements with the Greater Fayetteville Business Journal.STUDENT ENTREPRENEUR Boolean Wiring LLC, Esean Rose, owner “I am truly honored and grateful to receive the Student Entrepreneur of the Year Award. I want to thank Fayetteville State University, the judges and everyone who has supported me throughout this journey. This award represents more than recognition for where Boolean Wiring is today. To me, it represents the potential of where we are going. I am excited about growing the company, creating jobs, serving our community and building something that can have an impact far beyond Fayetteville.”VETERAN-OWNED BUSINESS SpeediPrint Inc., Dazrell Fleming, owner “I’m honored to accept the Veteran-Owned Business Award on behalf of the entire SpeediPrint team. A special thank you to Dr. Tamara Colvin for creating this opportunity through the Entrepreneurial Impact Awards, and to my mentor, Mr. Julius Cook, whose guidance during the Boots to Business program truly paid off. This recognition reflects the hard work of my staff and the trust our customers place in us every day — I’m grateful to serve this community and excited for what’s ahead.”MULTI-GENERATIONAL EXCELLENCE BJL Construction, Cleopatrice Robinson, president“This award is especially meaningful because we are more than a business — we are the continuation of a family legacy built through faith, hard work, craftsmanship, integrity and service. I gratefully acknowledge my grandfather, Deacon Benjamin “BJ” Lacy, Jr., whose example helped establish the foundation upon which our family’s entrepreneurial legacy was built. I also honor my father, the late Dr. Wilson Lacy, former president of BJL Construction. Working alongside him was both an opportunity and an education. He taught me that a business’s reputation had to be earned on every project through honesty, excellence, quality and service. As the current president, I recognize that I did not arrive at this moment alone. I stand on the shoulders of those who came before me, and I am sustained by those who continue to walk beside me.”MICRO BUSINESS Maybridge Development, LLC, Latisha Perkins, owner “I accept this award with so much pride and a whole lot of gratitude. First and foremost, I want to thank my higher power for continuing to guide me and give me the strength to keep going.When I first started this business and moved here to Fayetteville, I had no clue what I was getting myself into. This business has turned me every which way but loose, and I definitely had some moments where I was ready to just pack it up and head back to Georgia. I want to thank my Maybridge team, my village, The Hub, the FCEDC team and all the people and organizations here in Fayetteville who have believed in me and Maybridge and helped us get here.”COMMUNITY IMPACT Greater Life of Fayetteville, Georgeanna Pinckney, CEO & executive director “We are deeply honored to be recognized by FSU and the FSU HUB with the Community Impact Award presented to Greater Life of Fayetteville. I am especially grateful for this recognition because it tells us that you see what we do – and, more importantly, why we do what we do. Our commitment is to serve, empower and create meaningful opportunities for youth and families in our community. Most importantly, we give God first and foremost all the glory. We thank Him for giving us the wisdom, strength, vision and unity to continue doing this great work in our community.” SMALL BUSINESS OF THE YEAR Crowder Trucking LLC, Carlos & Valerie Morrison Crowder, owners “I want to thank God for always keeping his hands on Crowder Trucking. I’m truly honored and grateful to receive the Small Business Award from the FSU HUB. Running a small business is not always easy. There are long days, difficult decisions, unexpected challenges and plenty of moments when you have to remind yourself why you started. But there are also incredible moments like this one that remind you that the hard work is worth it,” shared Valerie Morrison Crowder.OTHER WINNERS INCLUDE: Alumni Entrepreneur - The Two-Six Project, Grant Bennett, founder and president Fayetteville State University Faculty Award - Dr. Christy Swinson Emerging Business Award - Genuine Luxury Beauty Salon Legacy Award - Gillis Farms Inc. Industry Titan of the Year - Eaton Corporation Entrepreneur of the Year- Let Me Cater to You, Chef Judith Cage, owner
Empty stadium 'not something we've focused on'
Northern Ireland manager Michael O'Neill believes the near-empty stadium in Friday's Nations League game will impact hosts Georgia more than his own side.
Engineers connect health wearables and implants using the body as the network
Using the human body to transmit signals, Georgia Tech engineers have created a wireless networking system that allows tiny implantable sensors and actuators to communicate with each other and with wearable ...
Thomas Sorber Is Thunder's Forgotten First-Round Wild Card
Hidden behind injuries and draft-day hype, the physical Georgetown product offers a bruising interior presence and elite wingspan that could redefine the Thunder’s versatile frontcourt rotation.
Georgia's Kvaratskhelia 'proud' of Best comparison
Paris St-Germain's Khvicha Kvaratskhelia says he already feels like he has achieved "something special" to be nominated for the Ballon d'Or.
Energy Department will spend nearly $2 billion to squeeze more electricity from the nation's aging power grid
The money will go toward 31 projects across 26 states that are expected to produce more than 23 gigawatts of additional electricity capacity — enough to power 16 million homes.
Fire damages more than 160 golf carts at Brandywine business
More than 160 golf carts were damaged in a fire Thursday morning at a commercial golf cart repair business in Brandywine, according to the Prince George’s County Fire/EMS Department.
New entertainment spot ‘Funder Alley’ opens in Fort Oglethorpe, GA
Discover Funder Alley, a fresh entertainment spot in Fort Oglethorpe, Georgia, offering duckpin bowling, axe throwing, and darts alongside a varied food menu and full bar. Located on Battlefield Parkway, it boasts both indoor and outdoor seating options, perfect for casual fun and group events.
Fire damages more than 160 golf carts at Brandywine business
More than 160 golf carts were damaged in a fire Thursday morning at a commercial golf cart repair business in Brandywine, Maryland, according to the Prince Geor
Fire damages more than 160 golf carts at Brandywine business
More than 160 golf carts were damaged in a fire Thursday morning at a commercial golf cart repair business in Brandywine, Maryland, according to the Prince Geor
EU science policy wonks debate prospect of stronger ties with Canada
Europe’s research and innovation sector has started asking questions on how European Commission President Ursula von der Leyen’s offer to make Canada “the first associate member of the EU” would actually work in practice, and who will get to shape priorities in a transatlantic relationship that is getting stronger. The Commission says it wants “a new model of association” under which the EU and Canada will aim to develop “a shared space” to face ongoing challenges. “Working in close coordination with our member states and the European Parliament, we will aim to create a new form of partnership that has not existed until now, building the closest imaginable form of association with a partner outside Europe,” a spokesperson told Science|Business.Locked in an escalating trade war with US President Donald Trump, who has repeatedly talked of annexing Canada, Prime Minister Mark Carney has been looking east, but full EU membership was never in play. Taking the floor a day after von der Leyen’s proposal, he agreed to strengthen ties under “an alliance of the future” but reined in enthusiasm on the new label. He also suggested expanding Canada’s involvement in the Erasmus+ student mobility scheme, to which it currently has limited access, and the next iteration of Horizon Europe. Canada joined the present Horizon Europe in 2024, but only contributes to collaborative projects.Neither side has detailed the next practical steps in developing this new relationship. “I think nobody at the moment truly knows how this will work,” said Michael Browne, chief executive and founder of Crowdhelix, a global collaborative network that connects players in research and innovation. “It’s more of a statement of intent for closer collaboration, which requires legislative frameworks and approval processes, which have not started.”Kurt Deketelaere, secretary general of the League of European Research Universities, said von der Leyen’s pitch to Canada is “politically significant, but the legal content still has to be negotiated and constructed.”Mattias Björnmalm, secretary general of the Cesaer university group, agreed that she had only opened “a political door” to Canada, as “associate membership does not come with a predefined set of rights in the EU institutions.”Not only does this status not currently exist as a legal category in the two treaties that set up how the EU functions, but the Commission president cannot unilaterally create a new category of EU membership.According to Deketelaere, Article 217 of the Treaty on the Functioning of the EU, which allows the bloc to make association deals with non-EU countries involving reciprocal rights and duties, is “the most obvious existing legal basis for building a much deeper EU-Canada relationship.”Getting universities involvedNo matter how this new cooperation takes shape, Liviu Matei, who heads the School of Education, Communication and Society at King’s College London, hopes to see universities involved in discussions from an early stage.“Its primary motivations, entirely justifiably, are political and geopolitical,” he said. “In the area of higher education, however, restricting the initiative to political and geopolitical considerations would limit the scope of cooperation and lead to distorted frameworks and counterproductive implementation.”It is all the more important since academic interests on the two sides of the Atlantic are “neither identical nor fully aligned,” Matei added. “This is not insurmountable; it simply requires work to articulate the details of this privileged cooperation, including its governance and funding frameworks, as well as its substantive content in education and research.”Related articlesCanada looks to deepen research and education links with the EUZaharieva hopes for a Horizon Europe deal in 2026Canada might participate in European Research Council schemes, for example, which was not on offer in the present Horizon Europe association agreement. But “there would have to be something in it for the EU,” Browne said. “They don’t want to be funding projects outside of the EU where intellectual property is going to sit outside of the EU. There has to be some kind of transfer of knowledge.”But access to funding will not by itself resolve all the practical difficulties of working together, said Björnmalm. “For researchers and students, these include visas and residence arrangements, recognition of qualifications and study periods, and the conditions for pursuing a research career across borders,” he said. “For universities, there is scope for more predictable access to shared laboratories, computing and research data, and stronger support for joint doctoral training and long-term institutional partnerships.”Linda Doyle, provost and president of Trinity College Dublin, said Europe should strive for the “closest possible expression” of this new political alliance. “If Europe is serious about recovering its voice and its place in the world, it needs to be strongly allied with countries who share its values and its vision for a stable, rules-based, peaceful world.”
Efi Foufoula-Georgiou elected to the Royal Academy of Engineering
Expert on water and climate science recognized as an international fellow
George Karlaftis warns younger teammates before matchup with Dolphins
During Wednesday's press conference, Kansas City Chiefs DL George Karlaftis warned teammates before Week 3 vs. the Miami Dolphins | @EdEastonJr
University System of Georgia makes business decision with chancellor pick
The University System of Georgia Board of Regents has named Thomas A. Fanning as sole finalist for chancellor, with a final vote scheduled for Oct. 1.
Ed Sheeran doesn’t want to be political, but music always has been
Celebrities using their fame to champion causes they care about is not new, says George Luke. Christians shouldn't hurl hate at those whose views they don't agree with - you can just choose not to listen
In rural Pa., doctors confront the hidden health impacts of environmental disasters
This article originally appeared on Inside Climate News, a nonprofit, non-partisan news organization that covers climate, energy and the environment. In February 2023, George Garrow jumped in his car and hurried to help people impacted by a freight train that had derailed in East Palestine, Ohio. The crash happened about a quarter-mile west of the […]
74-84: Chart
Astros 5, Mariners 6 Mariners Win: Julio Rodríguez, +0.46 WPARewrite: George Kirby, -0.18 WPA Game Thread Comment of the Day
Oklahoma's Michael Fasusi ruled out against Georgia in initial report
Oklahoma Sooners football received mixed news from Wednesday's initial availability report ahead of Georgai.
Former South Jersey transit official enters plea deal in political revenge case
Bryan Bush pleaded guilty to obstruction in relation to a case where payment was denied to a contractor who had allegedly fallen out of favor with George E. Norcross III.
NVIDIA Unleashes The Next Chapter of Neural Rendering & Path Tracing With RTX Kit SDK While RTX Mega Geometry 2.0 SDK Gives Devs the Ability To Stream Insane Levels of Detail
NVIDIA unleashes RTX Kit and RTX Mega Geometry 2.0 SDKs, giving devs a taste of next-gen Neural Rendering, Path Tracing & game technologies.
American Geophysical Union’s 2026 Eugene Shoemaker Lecture
Award: The American Geophysical Union’s Eugene Shoemaker Lecture is presented annually and recognizes excellence in planetary exploration.