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Mayor O'Connell touts Nashville's business longevity record in recent speeches
He wants to shed light on the positive side of Nashville's economy at a time when high-profile hospitality businesses have closed.
5 weekend events not to miss in Greenville, Spartanburg and Anderson
Looking for weekend plans? From Oktoberfest and the Spartanburg International Festival to Anthony Hamilton and more, the Upstate is packed with events.
Boston 25 News
In Somerville, a unique partnership between city leaders and a local business is creating just that type of space, while also helping young people explore new interests, develop skills, and prepare...
Car crashes into wall of Hopkinsville business
Hopkinsville Fire Department crews were on the scene after a car crashed into a building.Fire crews and EMS personnel responded around 9:31 p.m. Tuesday night t
Arts & Entertainment Calendar
Freeboot Fridays: Downtown Greenville Partnership and the City of Greenville hosts Freeboot Friday, the ECU Pirates pregame party, at Five Points Plaza at Fifth and Evans streets from 5:30-8:30 p.m.
Virginia Democrats warn more healthcare strains loom after November election
Christina Rivera kept her health insurance this year because she needed major back surgery. But maintaining coverage meant absorbing a monthly premium that rose from $235 in 2025 to $1,336 in 2026 — with a higher deductible. “That’s just not reasonable for anybody who is relying on the ACA for healthcare,” said Riviera, a Charlottesville-area resident and founder of the nonprofit Called to Justice. “I don’t have that sitting around. It’s not in the cushions of the couch.” Small nonprofits often depend on the Affordable Care Act marketplace because reasonably priced group coverage is out of reach, Rivera said. After enhanced federal premium tax credits expired last December, her insurance bill became another financial burden alongside groceries, gasoline and utilities.
Governor’s School for Science and Mathematics ranked top school in SC, 3rd in US by research company
HARTSVILLE — The South Carolina Governor’s School for Science and Mathematics has been recognized by Niche. com as the best public school in South Carolina and the third best public school in the nati...
'Illegal activity' prompts liquor denial, tobacco hearing for Peoria business
PEORIA - A convenience store situated along Knoxville Avenue will not be allowed to sell alcohol, despite narrowly receiving site approval following weeks of debate at City Council.
Ryan O’Reilly’s Future With Nashville Predators Uncertain
While there has been a lot of change with the Nashville Predators this summer, there could be more this season.Veteran forward Ryan O’Reilly is entering the final year of a $18 million deal and may not be part of the leadership corps sometime this season.He has been an assistant captain for the franchise since his […] The post Ryan O’Reilly’s Future With Nashville Predators Uncertain appeared first on HEAVY.
Mike Johnson, Bernie Sanders to campaign in Central Valley for 22nd District race
The dueling visits come as Rep. David Valadao and challenger Randy Villegas face off in one of the country’s most competitive congressional races.
CPS cited mother’s mental health as 'safety factor' before Mechanicville killings
WRGB CBS 6 provides local news, weather forecasts, traffic updates, notices of events and items of interest in the community, sports and entertainment programming for Albany, New York and nearby towns and communities in the Capital City area, including Cohoes, Watervliet, Colonie, Bethlehem, Guilderland, New Scotland, Coeymans, Green Island, Knox, Berne, Westerlo, Rensselaerville, Colonie, Menands, Green Island, Ravena, Altamont, Voorheesville.
Upstate bridge death ruled suicide, prompts mental health discussions
A man’s death at a Greenville County bridge has been ruled a suicide, sparking conversations about mental health challenges and available resources.
Gambit's Best of New Orleans 2026: Entertainment
Design by Dora Sison / Gambit Best Bounce Artist googletag.cmd.push(function() { googletag.display('ad-1492300'); }); 1. Big Freedia (Instagram: @bigfreedia)2. Ha Sizzle (Instagram: @hasizzlethevoice)3. Subtweet Shawn (Instagram: @subtweetshawn1) Trixie Minx Photo by Sophia Germer / The Times-Picayune Best Burlesque Performer1. Trixie Minx (Instagram: @trixienola)2. Bella Blue (Instagram: @bellablueforever)3. Miss Angie Z (Instagram: @missangiez) Best Casino1. Caesars New Orleans (8 Canal St., 800-427-7247; caesars.com/caesars-new-orleans)2. Treasure Chest Casino (4550 Williams Blvd., Kenner, 504-443-8000; treasurechest.com)3. Boomtown Casino (4132 Peters Road., Harvey, 504-366-7711; boomtownneworleans.com) Best Drag Performer1. Debbie with a D (Instagram: @debbiewithad)2. Katrina Waters (Instagram: @katrinawaters504)3. Laveau Contraire (Instagram: @laveaucontraire) Best Festival (that's still around)1. New Orleans Jazz & Heritage Festival (nojazzfest.com)2. French Quarter Festival (frenchquarterfest.org)3. Hogs For The Cause (hogsfest.org) Best Food Festival1. New Orleans Fried Chicken Festival (friedchickenfestival.com)2. Oak Street Po-Boy Festival (poboyfest.com)3. New Orleans Jazz & Heritage Festival (nojazzfest.com) Tipitina's Photo by Sophia Germer / The Times-Picayune Best Live Music Venue1. Tipitina’s (501 Napoleon Ave., 504-895-8477; tipitinas.com)2. The Broadside (600 N Broad St., 504-766-0871; broadsidenola.com)3. The Fillmore (6 Canal St., 504-881-1555; thefillmorenola.com) Best Live Music Club1. Maple Leaf Bar (8316 Oak St., 504-866-9359; mapleleafbar.com)2. Snug Harbor Jazz Bistro (626 Frenchmen St., 504-949-0696; snugjazz.com)3. Chickie Wah Wah (2828 Canal St., 504-541-2050; chickiewahwah.com)3. Blue Nile (532 Frenchmen St., 504-766-6193; bluenilelive.com) Best Local Blues Artist/Band1. Little Freddie King (littlefreddieking.com)2. Samantha Fish (samanthafish.com)3. Tab Benoit (tabbenoit.com) Best Local Brass Band1. Rebirth Brass Band (rebirthbrassband.com)2. Hot 8 Brass Band (hot8brassband.com)3. The Soul Rebels (thesoulrebels.com) Best Local DJ1. Paul Lakeway (Instagram: @paul_lakeway)2. DJ Soul Sister (Instagram: @djsoulsister)3. ANTWIGADEE! (Instagram: @antwigadee) Best Local Funk Band1. Dumpstaphunk (dumpstaphunk.com)2. Galactic (galacticfunk.com)3. Big Sam's Funky Nation (bigsamsfunkynation.com) Kaye the Beast Provided Photo by Catherine Debuys Best Local Hip-Hop Group/Artist1. Kaye the Beast (Instagram: @kayethebeast)2. La Reezy (Instagram: @lareezymusic)3. Pell (Instagram: @pellyeah) Best Local Movie Theater1. The Broad Theater (636 N. Broad St., 504-218-1008; thebroadtheater.com)2. The Prytania (5339 Prytania St., 504-891-2787; theprytania.com) googletag.cmd.push(function() { googletag.display('ad-1492297'); }); 3. The Prytania Theatre at Canal Place (333 Canal St., 3rd floor, 504-290-2658; theprytania.com) Best Local Music Artist/Band1. Robin Barnes & The Fiya Birds (robinbarnesmusic.com)2. Trombone Shorty (tromboneshorty.com)3. Sweet Crude (sweetcrudeband.com) Best Local Rock Band1. The Revivalists (therevivalists.com)2. Better Than Ezra (betterthanezra.com)3. Cowboy Mouth (cowboymouth.com) Best Wedding Band/ DJ1. The Mixed Nuts (themixednuts.com)2. Bucktown All-Stars (bucktownallstars.com)3. Warm Advice (warmadvice.com) Doreen Ketchens Provided photo Best Local Street Performer1. Doreen Ketchens (doreensjazz.org)2. Jourdan Blue (Instagram: @jourblue)3. Sariyah Idan (ariyahidan.com) Best Local Theater Company1. The Tennessee Williams Theatre Company of New Orleans (504-264-2580; twtheatrenola.com)2. Le Petit Theatre (616 St. Peter St., 504-522-2081; lepetittheatre.com)3. The NOLA Project (504-302-9117; nolaproject.com) Best Local Traditional Jazz Group/Artist1. Preservation Hall Jazz Band (preservationhalljazzband.com)2. Kermit Ruffins (@ruffinsbbq)3. Trombone Shorty (tromboneshorty.com) Best Marching Band1. St. Augustine High School Marching 100 (Instagram: @staugmarching100)2. Edna Karr High School Marching Band (Instagram: @theofficialkarrband)3. The Roots of Music Marching Crusaders (therootsofmusic.org) Best Mardi Gras Parade1. Muses (kreweofmuses.org)2. Iris (kreweofiris.org)3. Endymion (endymion.org) 610 Stompers Photo by Chris Granger / The Times-Picayune Best Mardi Gras Dance Krewe1. 610 Stompers (610stompers.com)2. Amelia EarHawts (aecabinkrewe.com)3. The Jamettes (Instagram: @thejametteskrewe) Best Place to See Burlesque/Drag1. The AllWays Lounge & Cabaret (2240 St. Claude Ave., 504-218-5778; theallwayslounge.net)2. The Original Nite Cap (1300 St. Bernard Ave., 2nd floor, 504-224-2854; Instagram: @originalnitecap)3. The Country Club (634 Louisa St., 504-945-0742; thecountryclubneworleans.com) Best Place to See Comedy1. Sports Drink (1042 Toledano St.; sportsdrink.org)2. The Howlin' Wolf (907 S. Peters St., 504-529-5844; thehowlinwolf.com)3. Big Couch New Orleans (1045 Desire St.; bigcouchnola.com) Best Local Comedian1. Ryan Rogers (ryanrogerscomedy.com)2. Mark Normand (marknormandcomedy.com)3. Cyrus Cooper (Instagram: @cyrusjcooper) Best Strip Club1. The Penthouse Club (727 Iberville St., 504-524-4354; penthouseclubneworleans.com)2. Rick’s Cabaret (315 Bourbon St., 504-524-4222; rickscabaretneworleans.com)3. Larry Flynt's Hustler Club (225 Bourbon St., 504-524-0010; neworleanshustlerclub.com) Best Performing Arts Center1. Jefferson Performing Arts Center (6400 Airline Dr., 504-731-4700; jeffersonpac.com)2. Saenger Theatre (1111 Canal St., 504-525-1052; saengertheatreneworleans.com)3. Mahalia Jackson Theater for the Performing Arts (1419 Basin St., 504-525-1052; mahaliajacksontheater.com) .donate-gambit-article-module-container { text-align: center; padding: 10px; /* background-color: #24da6d; */ background-color: rgb(153, 0, 0); margin-bottom: 20px; } .donate-gambit-article-module-title { font-weight: bold; color: #fff; } .donate-gambit-article-module-copy { color: #fff !important; font-size: 16px; } .donate-gambit-article-module-button { background-color: black; width: 50%; border-color: black; font-size: 16px; } .donate-gambit-article-module-button:hover { background-color: black; } @media only screen and (max-width: 600px) { .donate-gambit-article-module-button { font-size: 14px; width: 100%; } .donate-gambit-article-module-copy { font-size: 14px; } } BECOME A GAMBIT MEMBER AND JOIN OUR KREWE TODAY For more than 40 years, Gambit has covered New Orleans, for New Orleans. We’ve stood up to city hall with you, cheered the Saints with you, danced in the streets with you and cried over our collective loss with you. And we’re plannin’ on being here for 40 more. To do that, we need your help. Become a Gambit member today and help us continue our mission SUPPORT GAMBIT
Vanderbilt Clarksville Hospital getting multimillion-dollar health record system upgrade
Vanderbilt Clarksville Hospital is transitioning to Epic, a new electronic health record system designed to enhance the coordination of care and improve efficiency.
The Family Business Advantage: Third Quarterly Power Breakfast of 2026 explores how family businesses balance legacy and innovation
Photo by GFBJAnother successful Power Breakfast is in the books. The Greater Fayetteville Business Journal hosted its third quarterly Power Breakfast of 2026 on Tuesday, Sept. 29. Local leaders and decision-makers gathered to network and learn from the panel about how established principles drive long-term stability while allowing for operational evolution. The panel featured Managing Partner of Luigi’s Italian Chophouse & Bar, Nate Ernst; Inside Sales at Hubbard Supplyhouse, Mary Grace Hurley; Chief Operations Officer for Copiers Plus, Drew Smith; and CEO of Holmes Security Systems, Stephen Wheeler. The panel was moderated by Lauren Willets, director of the Family Enterprise Center at UNC’s Kenan-Flagler Business School. Throughout the discussion, the panelists returned to a common idea: family businesses thrive when they preserve the relationships and values at their core while remaining open to change.Each panelist shared personal stories that carried practical lessons. Stephen Wheeler emphasized the role of relationships with customers and employees, saying, “What makes a family business successful today is relationships.” Mary Grace Hurley echoed Wheeler’s sentiment, describing relationships as a lasting inheritance, including a customer connection that began when she was young and continued into her working life. “If something’s given to you, that’s going to cost you too,” added Nate Ernst. He explained this philosophy by sharing that, in his view, earning responsibility builds credibility and confidence.Another hot topic was the idea of tradition versus change. For these businesses that have been around for a century or even more, it can be difficult to escape the “we’ve always done it this way” caveat, but these speakers emphasized how change has been an integral part of their growth and longevity. A family business can honor its history without being bound by it.“Innovation and tradition–they don’t have to be competing with one another,” shared Hurley. She pointed to changes in how businesses operate, including the adoption of computers and new management practices. Ernst stressed that adaptation is essential, while Wheeler described how his family’s electrical contracting business had evolved into a security-focused company. The details of the work may change, but identifying and upholding core values is key to embracing change while maintaining the character of a business. “I think it’s just important to remember why you started in the first place. What was your mission? What are your core values? And to reevaluate those,” shared Drew Smith.In addition to the first-hand accounts and wisdom shared by panelists, Moderator Lauren Willets recommended two novels during the panel for those seeking additional educational resources. Those two novels are “Hug of War: How to Lead a Family Business with both Love and Logic”by Cathy Carroll and “In the Company of Family: How to Thrive When Business Is Personal” by Melissa Mitchell-Blitch. Preparing the next generation requires more than handing over a title or company. Wheeler argued that future leaders need genuine passion and a vested interest in the business. The panelists were in agreement that succession is a process, and there is not one clear answer for how to perfectly prepare for it. Leaders must cultivate readiness, keep communication open and make room for the next generation to earn responsibility while being sure not to neglect the business in the here and now. “Today’s Power Breakfast was one of our best events yet! Between the passion and in-depth knowledge of the panelists, the great audience questions and the guidance and expertise of Mrs. Willets, the conversation was both engaging and informative,” shared GFBJ Publisher Faith Hatton. “A lot of small businesses in Fayetteville are family-owned and grown, and it’s great to be able to spotlight some of the businesses that have stood the test of time by strengthening the next generation of leadership and preparing them for ownership. I hope everyone received some inspiration and ideas that they can bring back to their own businesses and organizations!”We thank everyone who attended this Power Breakfast and hope you’ll all join us for the next Power Breakfast on Dec. 8. Details about the event will be shared on our social media and in future email updates. To learn about becoming a Power Breakfast sponsor, contact the Greater Fayetteville Business Journal at 910.240.9697 or marketing@bizfayetteville.com.
University Auto And Tire opens location in Elkins
Fayetteville-based University Auto and Tire recently opened its second location after acquiring a 6,500-square-foot vehicle maintenance shop on 3.2 acres in Elkins. Will and Bernadette Helton own University Auto and...
University Auto And Tire opens location in Elkins
Fayetteville-based University Auto and Tire recently opened its second location after acquiring a 6,500-square-foot vehicle maintenance shop on 3.2 acres in Elkins. Will and Bernadette Helton own University Auto and...
Lady A's Charles Kelley diagnosed with rare blood cancer after painful health scare
Lady A's Charles Kelley shared a video revealing that unexplained rib fractures led doctors to discover multiple myeloma, a rare blood cancer.
Jaguars name Zane Collins senior vice president for live entertainment
With experience in Jacksonville, the executive will manage events at the “Stadium of the Future” and Daily’s Place.
Women in Business: Kenzie Biggins, founder of Worxbee
An idea that began to percolate in grad school has grown into a thriving business which matches virtual executive assistants with business leaders.
Governor candidate Jerri Green talks minimum wage, health care in Clarksville speech
Speakers addressed the crowd from a podium under the pavilion at the Blue South BBQ in Clarksville on Sept. 26, 2026.
Heartland Whole Health Launches 'Blueprint for Rural Healthcare Transformation'
Bentonville's Heartland Whole Health Institute has launched Heartland Whole Health Connect, which it calls a pioneering initiative designed
5 things to do this week in Greenville
See our curated list of upcoming and ongoing arts, culture and entertainment events in the Greenville area. Send us your events at greenville@postandcourier.com.
Pickleball social club in Greenville combines fitness and community
As pickleball continues its surge in popularity across the country, health experts say picking up a paddle offers significant benefits for both the body and mind.
Construction continues on upcoming Crispy Cones at Covenant Health Park
See inside as construction continues on upcoming Crispy Cones at Covenant Health Park in downtown Knoxville on Sept. 28, 2026.
Palm Beach residents appointed to Cox Science Center board of trustees
Palm Beach residents Deborah Norville, Bill Roberts and Thomas Rosin are among seven new board members of the Cox Science Center & Aquarium.
Glenville State cuts ribbon on new College of Business
Glenville State University marked the creation of its College of Business with a ribbon cutting Wednesday. In recent years the university has added an MBA and moved two business degrees online.
WBIR Channel 10
WBIR Channel 10 in Knoxville, Tennessee produces award-winning, community-centered content "Straight From The Heart" of East Tennessee. We strive to be good citizens, to do what is right, and to be fair and honest. We care.
Beshear creates new state office to amplify Kentucky’s musical legacy, entertainment economy
Gov. Andy Beshear announced the creation of the Governor’s Office of Music Friday during an appearance at Bourbon & Beyond in Louisville, one of the state’s marquee music festivals.
ReadyKids says need for youth mental health services outpaces capacity
ReadyKids says the need for youth mental health services in the Charlottesville area is greater than its current capacity.
Riley Green brings That's Just Me Tour to Greenville in May
Country star Riley Green will bring his That's Just Me Tour to Greenville on May 1 at Bon Secours Wellness Arena.
Hayden Panettiere's ex alleges missing items, raises alarm over her estate
Hayden Panettiere's ex-fiancé, Wladimir Klitschko, is taking his "urgent" concerns over the "Nashville" actress' estate to court.
Cirque Italia’s Metropolis show coming to Coralville
Cirque Italia in October will bring to Coralville its tale of a country boy swept away from his farm and into the heart of urban chaos.
New polls show Graham holding slim lead over Andrews in SC Senate race
The Trafalgar Group and InsiderAdvantage have released polling in the U.S. Senate race showing one percentage point separates Graham and Andrews.
Councilman Kevin Carrico will not seek reelection, announces new Jacksonville business venture
Greenville’s Pelham Hills shopping center acquired by CenterSquare Investment Management
CenterSquare Investment Management has acquired the Pelham Hills shopping center off Pelham Road in Greenville.
Oct. 1 Vallejo/Vacaville Arts-Entertainment Source: Faces and Places
The Vacaville Indivisible rally, “Save Our Democracy — Register to Vote,” was held on Sept. 19 in front of Vacaville City Hall.
October 1 Vallejo/Vacaville Arts-Entertainment Source: Activities
Vallejo Hike Club’s Morning Hike is set for Friday at 7 a.m., at Mare Island Shoreline Heritage Preserve, 167 O’Hara Court, Vallejo.
Vanderbilt Clarksville Hospital's electronic health record system to undergo multimillion-dollar upgrade
On Oct. 3, Vanderbilt Clarksville Hospital will transition to a new electronic health record system that will enhance care coordination.
Penguins finalize roster ahead of this week’s season opener
The Pittsburgh Penguins have finalized the team’s opening night roster before this week’s season-opener against the Philadelphia Flyers. The Penguins’ roster for the opening game against Philadelphia will consist of 13 forwards, 7 defensemen and 2 goalies. The opening night roster consists of Egor Chinakhov, Sidney Crosby, Connor Dewar, David Gustafsson, Filip Hallander, Ville Koivunen, […]
Fun Spot America has many items up for auction. Here's what you could buy
Fun Spot America Atlanta is auctioning bumper cars, arcade games and other rides after the Fayetteville park permanently closed in July.
Greenville Country Music Fest back at CCNB Amphitheatre
The Greenville Country Music Fest is set to return to CCNB Amphitheatre at Heritage Park in Simpsonville on April 30 and May 1, 2027.
Maternal health fair, community baby shower to be held Oct. 24
The event is designed to improve access to maternal health information, wellness resources and parenting support.
5 Things Auburn Fans Learned About the SEC This Weekend
Auburn football improved to 3-1 with its first SEC win under Alex Golesh, but Week 4 revealed much more about the conference. Florida is surging, Mississippi State has found a star in Kamario Taylor, and Tennessee showed major offensive concerns ahead of Auburn's trip to Knoxville.
Tennessee Tech Offers In-state Tuition For Huntsville-area Students
For students who want to go to college out-of-state, Tennessee Tech is looking for you.
South Carolina high school football schedule for Week 7
It's Week 7 of the South Carolina high school football season. Check out the schedule of games across the state for Oct. 2.
Drake Maye's slump goes from bad
Drake Maye's performance in Jacksonville felt worse than his fourth-quarter debacle in the season opener at Seattle
No. 1 Texas outlasts No. 14 Tennessee 20-17 in Knoxville with Trump watching
Texas dominated defensively with 10 sacks, led by Colin Simmons.
Diaper maker grows jobs, investment in Rockingham County
Belgium-based Drylock Technologies has exceeded its investment and job creation promises in Reidsville in Rockingham County. The hygiene products manufacturer promised in February 2024 to invest $26.9 million to create 113 jobs at its first U.S. factory for baby care products. Since then, Drylock has invested more than $31 million and has 212 workers who […]
98-year-old business says 'we don't qualify' for Nashville legacy incentive proposals
Delgado Guitars has been helping Music City strum since 1928 but says none of the Nashville Mayor's proposed small business grants would help them, writing they
NC State a 6.5-point underdog to Louisville
NC State dips back into conference play with the toughest opponent on its schedule this season, the Louisville Cardinals. It would have been a good idea to come into this one with a record better than 2-2, but Louisville is probably thinking the same thing. The Cardinals are coming off a surprising three-point home loss […]
Iberville Parish hosts Mental Health Awareness Week
Iberville Parish hosts six days of mental health events in October featuring workshops, screenings and a walk.
Iberville Parish hosts Mental Health Awareness Week
Iberville Parish Government is hosting six days of events in October in observance of Mental Health Awareness Week.
Civil Rights photographer sees echoes of past in South Carolina debates
Civil Rights photographer Cecil Williams says South Carolina has made progress, but new debates over race and representation remain.
Driftwood Oven serves pizza and dance club vibes with After Dark
Driftwood Oven in Lawrenceville becomes an unlikely (and tasty) nightclub destination during its monthly After Dark DJ dance/pizza party.
Nuclear reactors, data center campuses, gas-powered plants proposed in Iberville, Ascension
If completed, the project would add an extra 20% to Louisiana's electricity generation capacity.
Thorpe joins Ballad Health Medical Associates Pediatrics
Katie Thorpe has joined Ballad Health Medical Associates Pediatrics — Greene Mountain, a department of Greeneville Community Hospital, where she will specialize in pediatrics.
Parker Health Insurance joins GCP
Click here to view this article from greenevillesun.com.
Parker Health Insurance joins GCP
Click here to view this article from greenevillesun.com.
5K memorial walk raises funds for first responder mental health support
Community members gathered Saturday at Asheville-Buncombe Technical Community College for the inaugural 5K walk event benefiting first responder mental health.
One Knox SC vs Westchester SC at Covenant Health Park, See photos
One Knoxville SC takes on Westchester SC at Covenant Health Park in the Old City in downtown Knoxville on Sept. 27, 2026.
Mack Hollins leads Patriots in Week 3 with six grabs
Mack Hollins finishes with six catches for 87 yards in Week 3 against Jacksonville.
Another three-catch day for Romeo Doubs in Week 3
Romeo Doubs musters 49 yards on three catches in Week 3 against Jacksonville.
TreVeyon Henderson shut down in Week 3
TreVeyon Henderson totals 29 yards in Week 3 versus Jacksonville.
Drake Maye posts three turnovers in loss to Jaguars
Drake Maye continues his turnover-prone ways as New England gets routed by Jacksonville in Week 3.
See the brilliance: Dunn artist creates and sells glass artwork that shines brightly
Cindy Akers-Gilford creates stained glass, fused glass, mosaics, handmade glass jewelry, pendants, suncatchers and other original glass artwork in her studio in Dunn, N.C. Photos provided by Cimply Broken.Self-made Artist and Founder of Cimply Broken, Cindy Akers-Gilford is helping people “see the brilliance” in all things with her glass artwork. Akers-Gilford started her business right after she retired from 20+ years as a civilian contractor at Fort Bragg. The official opening date for Cimply Broken was Nov. 8, 2021.“It’s been quite the adventure ever since. Not only did I have to learn how to manage a small business, but I’ve never taken a class in stained glass or anything I currently do,” shared Akers-Gilford. Her work includes stained glass, fused glass, mosaics, handmade glass jewelry, pendants, suncatchers and other original glass artwork.“I chose glass art just by happenstance. I saw a video on YouTube with a gentleman using plates and resin to make beautiful windows. I used that idea and created a simple picture frame-sized piece for myself. It was beautiful. I put it up in my window and pretty much forgot about it for a few days. Well, one beautiful sunny morning I went up to my studio, and the sun was rising and the light was shining beautifully through that piece. It was absolutely stunning. I thought that it was the perfect reflection of how God’s light shines through each of us. It was broken glass, so it changed ever so slightly as the sun continued to rise in the sky. I thought it poignant – like each of us – we all shine bright and differently in God’s glorious light, and we are all simply broken as well. We are all made beautiful in his light,” explained Akers-Gilford.The name of the business was inspired by the artist’s name and her faith-driven mission. “Simply became ‘Cimply’ as a play on my name and ‘simply’… and ‘Broken’ because we are all Cimply Broken – but each of us is beautiful,” added Akers-Gilford.Akers-Gilford sells her glass art at the Dunn Farmers Market when the weather is bearable, but mostly from her website at www.cimplybroken.com. “I enjoy getting lost in the creative process. I work out of my home, and I often compare my studio to Walmart returns after Christmas time. It’s hectic, busy and there are always at least 10 things being created simultaneously- it is fun!” shared Akers-Gilford. Her goal for the business is to continue to watch customers as they spot a piece of work from a distance and walk up to it in awe. “That is my biggest joy! I don’t speak to them until they speak – that is their moment to ‘See The Brilliance,’ which is my moniker,” shared Akers-Gilford. She also shared she would love to someday become part of an artist collective in Dunn.
Art that serves others: How a Harnett County muralist is making a lasting mark in her community
Van Goat Studios, which has been operating since 2019, has allowed Johnson to express herself and reflect the spirit of local communities through murals. Photo provided by Elyse Johnson.Elyse Johnson of Van Goat Studios in Dunn wants to spread her artistry and make a lasting mark in her community. Van Goat, which has been operating since 2019, has allowed Johnson to express herself through murals and decorating electrical boxes in the urban landscapes of North Carolina. On top of traditional mural painting, Johnson offers what she calls “portable murals,” an option tailor-made for structure owners who do not want to commit to a design for their wall.“A contractor builds a framed piece of wood, and then they can frame the ‘mural’ onto the wood, whether it’s into their building, whether it’s interior or exterior,” Johnson said. The beginnings of Johnson’s journey into establishing Van Goat Studios reflect the teachings she wants artists to take away today: everything is a learning opportunity. When she started Van Goat, she shared it was a joint venture with a business partner. “I mainly did that because I didn’t feel like I was ready to go and do this on my own,” Johnson said. Her business partner eventually dropped out of the project, deciding she wanted to pursue other forms of art. That is when Johnson was thrust into growing her business on her own during and in the aftermath of the COVID-19 pandemic. “I had built up my confidence enough to go out and reach new heights,” she said. “And I was probably one of the few that benefited from COVID.”The moment presented a silver lining for Johnson. One of her first projects was a Farmers Day mural for the town of Coats. “When COVID-19 hit, Coats was not able to hold their annual festival, so they had a little bit of savings. They decided they wanted to do something for their community without getting anyone sick,” Johnson said.From there, word of mouth spread. Now, Johnson has an organic way of approaching projects. “Like a lot of muralists, if I feel inspired by a building, I will just go up and talk to that building owner and tell them a mural is something they should consider,” Johnson said. But above all, Johnson says she wants art to be accessible to everyone. Johnson said she is trying to stick to projects that benefit “the little guys.” “I’m not trying to go for a project in downtown Raleigh to get the eight-foot-tall building,” Johnson said. “I’m not trying to go to those major cities and get those huge buildings for two reasons: one, I don’t want to go that high; two, my passion really lies with the small guys.” But due to financial constraints and the material reality of art commerce, that requires open communication, she added. “I don’t want to just snowball you with this huge price, and then you just shut me down because it wasn’t what you were thinking,” Johnson said. “At the same time, I am an advocate for the arts, so I’m not going to give you a $10,000 mural when you’re only going to pay $5,000.” There is a healthy balance in explaining the artistic process and working with clients and the surrounding community, Johnson said.“Your municipality invested this, and this is why they invested this, and this is how it’s going to help and improve your community,” she noted. “Same thing when I’m talking to a small business. You asked for me to come at you with this that is outside your budget. How do we make this still your same exact goal, but within your budget lines?” Johnson also provides lessons to aspiring artists. She does so with a mission: how do you master the balance between being a great artist and a competent business owner? “We still do art lessons, but I’m also going to give you business scenarios,” she noted.One of the scenarios she has come up with for her students is a T-shirt competition. “The kids have to think about ‘okay, I can’t just draw whatever I want on a T-shirt. I need to think about what colors Miss Elyse likes. What does Miss Elyse’s logo look like? What would Miss Elyse like?’” Johnson said. “So the design needs to be around that kind of concept.” As Johnson looks toward the future of Van Goat Studios, she is thinking of time, longevity and succession. Johnson is a new mom, which she said has shaped how she sees the future of the studio.“I still want my name and my business out there continuing, so that when my daughter is of age and she can be more independent, then I can be out there doing more and more,” Johnson said. “I would love to get a student to pass this on to, or an intern. I would love for this business to be passed on to the next generation and let them go.”
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Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Lord’s Acre Festival serves up food, entertainment, mingling - The Daily Reporter
Volunteers help fill containers with chicken and noodles Sept. 19 during the Lord’s Acre Festival at McCordsville United Methodist Church in McCordsville. The perennially popular dish is sold for festival dining or carry-out until it sells out. The 74th annual festival took place Sept. 18-19.
Arts and entertainment calendar
Events coming up in the Greenville area offer music, arts, theater and family fun. Here is a sampling. “Today” refers to events scheduled for Saturday, Sept. 26.