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Cost-Free Entertainment Platforms Propel Growth in the Ad-Supported Streaming TV Sector
The FAST market is driven by increasing consumer adoption of cost-free streaming, expanding ad-supported content, and enhanced personal advertising technologies. This growth is further accelerated by smart TV integration, diverse content offerings, and rising digital video libraries, notably in Asia-Pacific. Free Advertisement (Ad)-Supported Streaming Television (TV) (FAST) Market Free Advertisement (Ad)-Supported Streaming Television (TV) (FAST) Market Dublin, July 02, 2026 (GLOBE NEWSWIRE) --
Scientists devise new method for tracing environmental PFAS contamination better
Perfluoroalkyl and polyfluoroalkyl substances (PFAS) are a class of synthetic chemicals widely used in industrial processes and consumer products because of their resistance to heat, water and oil. However, ...
Sony to end physical PlayStation game discs for new releases starting in 2028
Sony says all new PlayStation games released after January 2028 will be sold digitally, reflecting changing consumer demand and the gaming industry's broader move away from physical media.
Sony says goodbye to discs for new PlayStation games in 2028
Sony said it will stop production of physical discs for PlayStation games in response to industry and consumer shifts.
Haleon teams up with Microsoft in 5-year AI pact to upgrade consumer health operations
Consumer health giant Haleon has tapped Microsoft to incorporate AI across its operations, joining a growing wave of healthcare and life sciences heavyweights turning to Big Tech to execute enterpr | Consumer health giant Haleon has tapped Microsoft to incorporate AI across its operations, joining a growing wave of healthcare and life sciences heavyweights turning to Big Tech to execute enterprise-wide digital overhauls.
Is Accel Entertainment (ACEL) Outperforming Other Consumer Discretionary Stocks This Year?
Here is how Accel Entertainment (ACEL) and American Outdoor Brands, Inc. (AOUT) have performed compared to their sector so far this year.
Sony will cease production of discs for new PlayStation games in 2028
New games sold for PlayStation consoles will only be available digitally and won’t be sold on discs effective January 2028, Sony has announced. The move applies to all PlayStation games released from that point on, including those made by Sony and those released by third parties. The PlayStation group calls the change “a natural direction for Sony Interactive Entertainment to adapt to consumer trends as the general preference for digital media significantly outpaces physical discs,” according to a PlayStation blog post reviewed by Game File in advance of its publication. As movies, TV and music have shifted from physical media to an age of downloads and streaming, Sony’s move could speed the demise of physical media in a gaming. The industry has offered consumers games via cartridges, cassettes, floppy discs, CDs, DVDs and Blu-Rays across a 50-year stretch. Sony has been reporting to investors in recent years that PlayStation games have been increasingly purchased as downloads, not as discs. The most recent figures show nearly four in five purchases of full games for PlayStation 4 and PlayStation 5 were purchased digitally in the past year. Stats like that may cause today’s news to carry an air of the inevitable. But Sony’s declaration for 2028 is still likely to produce a shock, as the biggest gaming platform on the planet that uses game discs leaves them behind. Discs going away, but the fate of game boxes is unknown Sony is committing to still selling games in physical retailers even after they drop discs in 2028. Just how those games will be sold—in boxes with codes inside, as cards marked with digital redemption codes—is unclear. Digital games will also continue to be sold in the online PlayStation Store. New games released for PlayStation consoles prior to January 2028 will be unaffected by the policy change, Sony says. That means the PS5 games of 2027, be they a new Madden, a new God of War, a new Call of Duty, a new Sly Cooper (one can dream?), would still potentially be offered on disc. PlayStation 6 implications Sony’s timeline for a transition to a no-disc era will also spin up more speculation about the timing and configuration of Sony’s next-generation console, the probable PlayStation 6. “This pretty much guarantees that PS6 won’t arrive until 2028 at the earliest,” Piers Harding-Rolls, senior games research analyst at Ampere Analysis tells Game File. Harding-Rolls also concludes from today’s news that “the base version of a PS6 will not include a physical media drive,” as Sony looks to keep costs down on the device. Sony itself is saying nothing about the PS6 today: not its timing, nor how it might or might not support internal or external disc drives in order to run disc-based PS4 and PS5 games, should the console be backwards compatible. The many signs this was coming Industry support for games being released on physical media has been waning. As has consumer interest in them. PC games effectively went all-digital years ago, thanks to the popularity of playing games through Steam and other digital storefronts. The Covid-19 pandemic and the lockdowns that kept much of the global population home helped shift shopping patterns toward downloads. Sony’s own data shows PlayStation game downloads being an uncommon consumer choice a decade ago and now becoming the norm. On consoles, physical media has been in such decline that Sony and Microsoft both launched their current gen Xbox Series and PS5 consoles in 2020 with cheaper versions that lacked disc drives. In early 2024, Phil Spencer, then head of Xbox, told me that ““[w]e ship games physically and digitally, and we’re really just following what the customers are doing.” He added that the game industry had become an outlier in still supporting disc-based entertainment, even as movies and TV have bailed on discs in favor of downloads and steaming: “Gaming consoles themselves have kind of become the last consumer electronic device that has a drive. And this is a real issue, just in terms of the number of manufacturers that are actually building drives and the cost associated with those. And when you think about cogs that we’re going to go put in a console—and as you have fewer suppliers and fewer buyers—the cost of the drive does have an impact.” Last year, the Nintendo’s Switch 2, which uses cartridges rather than discs, introduced the concept of game-key cards, which are physical media that contain no game, just a prompt for a download. Even disc-based games aren’t what they once were, now frequently containing just stubs of games rather than the whole thing. The website Does It Play has tested over 3000 games and found that, for example, that the disc version of this year’s hit 007: First Light, only contained the game’s first mission, with the rest needing to be downloaded. Beyond all that, last week brought the news that Grand Theft Auto VI, likely the biggest game launch this decade, will debut for PS5 and Xbox Series without a disc-based version. Today’s big news comes to you for free. Game File is a reader-supported publication. To receive new posts and ensure more of my work is possible, please consider becoming a free or paid subscriber. Subscribe Discs helped define PlayStation However the trends in entertainment may be going, it is still remarkable to see PlayStation ditch discs given their importance in PlayStation history: In the late 1990s, the first PlayStation’s support for games on relatively cheap CD-ROMs instead of traditional game cartridges allowed the upstart console to outmaneuver cartridge-based systems from Nintendo and Sega, as it drove down game prices down in the process. (The cheaper disc format even prompted Final Fantasy VII maker Square to taunt Nintendo in a magazine ad, saying that if the game was “available on cartridge, it’d retail for around $1200.”) PlayStation devices often doubled as machines for watching movies and TV on the latest disc-based formats. In the late 2000s, for example, Sony’s pricy PS3 gained traction as a go-to device for playing then-novel Blu-Ray discs. In 2013, Sony effectively roasted the digital game-sharing restrictions proposed by rival Microsoft for its upcoming Xbox One console by showing how games could be shared for the then-upcoming PS4. In a 21-second clip that has over 20 million views on YouTube, one PlayStation executive simply handed a game box—presumably with disc inside—to another, who said “thanks.” Sony’s possible motivations The PlayStation announcement today cites “consumer preferences” and a shift away from discs among “the broader entertainment industry,” but does not delve into the decision-making process that brought Sony to this point. Sony is not discussing the economics of this move (I asked!), but there are a number of potential factors: Abandoning discs will spare Sony the cost of manufacturing and shipping them, which analysts and industry veterans I spoke to said could account for $1 or so of a game’s retail price. For first-party games, that’s direct savings for Sony, though the amount is limited by the winnowing percentage of people who were even buying the disc-based versions. For third-party games, Sony could pass the savings on to partners or just retain the better profit margin for themselves. As the 2024 comments from Phil Spencer alluded to, leaving discs behind could mean leaving disc-drives behind, allowing Sony to produce consoles more cheaply. Switching to digital-only for games could diminish the risks of copies of new games leaking. It would also seemingly make second-hand sales of used games impossible, pushing more people to buy their own copies of games. These economic benefits for Sony could be boons for the games industry overall, Ampere analyst Piers Harding-Rolls tells Game File. Among other things, it could free publishers and retailers from having to worry about securing an inventory of game discs when trying to sell games, he noted. “If there is a way to streamline the business of games retail, I generally think it’s a good thing for the industry as it removes unnecessary costs,” Harding-Rolls said. “This will help offset pressure on margins from other directions – development and staffing costs for example.” Should the industry shift from game boxes that contain discs to smaller, cheaper game cards, Harding-Rolls said, that reduces pressure on publishers and retailers. “The advantage of everything going digital for the industry is that sales can be tracked much more easily and there is less commercial risk for publishers wanting to continue selling via retail,” he said. The shift to no discs will also likely impact game development timelines, as developers will no longer face the same urgency to have a build ready to submit to PlayStation for the production of a disc, as industry experts noted around GTA VI’s no-disc news last week. Instead, projects may gain weeks of development time, in the event delivery deadlines for platform approval move closer to release date. Preservationists’ likely worries While millions of gamers have shifted to digital, there are still people who associate game discs—and only game discs—with actual ownership of PlayStation games. That portion of the gaming community spoke up last week about wanting to buy a version of GTA VI that they could hold in their hands, could lend to a friend and could potentially pop into a well-preserved PS5 console three decades from now and still see it run. Such gamers didn’t want to worry that they’d merely purchased a digital copy that could lose access to the game if, say, the company behind the game someday turns of the servers that transmit downloadable copies. Digital copies of games are inherently less long-lasting, because consumers aren’t actually buying a game (on a disc), just buying access to the game. The fine print in online gaming shops notes this, as does a recent law that went on the books in California in 2025. That lasw requires game publishers doing business in the state to refrain from words like “sell” when offering digital copies of games, unless they explicitly tell consumers that what’s being sold isn’t the game itself but a potentially revocable license to access it. A Sony spokesperson noted to Game File that “[w]ith all digital content, including games, movies, and music, players are purchasing a personal license for non-commercial use.” Regarding the fears of PlayStation games being lost to time in an all-digital era, the rep also noted that Sony remains “committed to delivering experiences from past generations to the new platforms our players are using.” They noted that PlayStation has used emulation and remasters to keep offering its classic games to modern gamers. It’s true that many consumers have become accustomed to not having physical copies of new music albums or movies, but the relative precariousness of digital copies of games is in fact being highlighted today by…. Sony’s other big announcement: the upcoming closure of the PS3 and PS Vita online stores Sony said today that it will be closing the online marketplaces for its PlayStation 3 console and PS Vita handheld in most countries in July 2027 (sooner elsewhere: August 2026 for the PS3 store Mexico, Honduras and Nicaragua; late 2026 for PS3 in other Latin American countries and the Middle East). “We know this news may be disappointing to PS3 and PS Vita players who hold a special place in their hearts for this generation of gaming,” Sony said in its announcement, saying the move “was not an easy decision for us to make.” Sony said that PS3 and Vita marketplaces “are no longer able” to support modern commerce systems, prompting a “need” to close the shops and focus on more modern PlayStation platform stores. The news may spark some deja vu. Sony announced back in March 2021 that it planned to take the PS3, Vita and PlayStation Portable marketplaces offline that summer. The move would have caused some 2,000 digital-only games to become unavailable for new purchasers, according to a VGC analysis at the time. Fans complained loudly. By April 2021, Sony walked back the PS3 and Vita shop closures, with then PlayStation boss Jim Ryan saying “it’s clear that we made the wrong decision here.” This time around, Sony is giving a longer notice period in most regions. The closure of those stores is still likely to cut off access to new purchases of digital-only PS3 and Vita games. The current PlayStation 5 marketplace sells PS5 and PS4 games, as well as a selection of PS1 and PS2 games. It does not sell PS3 games, because games for that platform can’t run on the system (some are offered via a PlayStation Plus streaming option). Vita games also aren’t sold via PS5. Sony says digitally purchased PS3 and Vita games will be downloadable after the stores’ shutdowns “for the foreseeable future.” Sony’s move contrasts with Microsoft’s Xbox platform, which continues to sell and support games from all four Xbox console generations. But it puts it in line with Nintendo, which disabled purchases in the marketplace for its Wii console (a contemporary of the PS3) in 2019. Nintendo discontinued purchases in the online shop for its 3DS portable (a contemporary of the Vita) in 2023. The big questions about Sony’s 2028 post-disc era Will Microsoft follow suit, ending support for new disc-based games on Xbox platforms and therefore all game consoles, too? Whether Microsoft does or not, will third-parties that can no longer release games on discs for PlayStation, simply ditch the disc options across the board? Given the GTA VI no-disc experiment launching this November, will more game publishers decide to forgo disc-based offerings even in 2027? How will no-disc PS5/6 games be packaged and sold in brick-and-mortar retail stores? What becomes of game sharing in an all-digital era? Will Sony modify its current set-up, which currently allows some sharing of digital games across a pair of consoles, to allow more casual lending? (See for example, Nintendo’s year-old system of letting players lend a digital game to another player in a “family group” for up to 14 days.) Will there be a version of a PS6 with a disc drive? Or will a drive be offered as an add-on? And how will gamers who want to retain access to PS4/PS5 disc-based games react to whichever configurations Sony chooses to offer? What will the final disc-based PlayStation game be?
Physical disc production ending in January 2028 for new games releasing on PlayStation consoles
In response to shifting trends in consumer preference, new games will be released on PlayStation Store and at retailers in digital formats only.
Republic Business Credit Provides $2MM E-Commerce ABL Facility to Emerging Retailer
Republic Business Credit funded a $2 million e-commerce asset-based lending facility for an Amazon third-party seller of consumer goods. The facility includes
Peptides are the latest US health craze. But what exactly are they?
While peptides are taking the health and wellness category by storm for various use cases, what exactly are they? Leerink Partners senior research analyst Michael Cherny helps break down what a peptides are, how people are choosing them for personal health and recovery reasons, and who the biggest winners in consumer pharmaceuticals could be if their popularity continues to grow.
New data shows consumers dropped health coverage after Republicans let subsidies expire
Republican officials don’t deny the accuracy of the data, though they’ve repeatedly tried to argue that the reduction is a positive development. It’s not.
A $1000 PlayStation 6 No Longer Sounds Crazy, As Sony Doesn’t Intend To Sell Hardware At Significant Losses
The PlayStation 6 is set to launch at one of the most challenging times for consumer tech, if not the most challenging. With the rising prices of components, RAM and SSDs above all, manufacturers are having an extremely hard time keeping costs down, and with a bill of materials that is now close to $1000, there's a very high chance the system will cost way more than most anticipated. Adding fuel to the fires of speculation is Sony itself, as the company heavily suggested in a recent investor Q&A session that it won't heavily subsidize the system. "We regard hardware as the base […]
States seek to lower drug prices by targeting the companies that manage them for health plans
TOPEKA, Kan. — As consumers worry about medication costs, states are trying to lower drug prices by reining in big companies that oversee prescription coverage for health insurers. Some of those companies, called pharmacy benefit managers, also own pharmacies, and one of them, CVS, has spent millions of dollars fighting
Consumer-Directed Health Care: Promise or Pitfall
This panel will examine the evidence and policy outlook for consumer-directed health care as a federal solution to expanded coverage, with a focus on affordability, access, and health outcomes.
Q1 Earnings Highlights: Sphere Entertainment (NYSE:SPHR) Vs The Rest Of The Consumer Discretionary - Leisure Facilities Stocks
Earnings results often indicate what direction a company will take in the months ahead. With Q1 behind us, let’s have a look at Sphere Entertainment (NYSE:SP...
It's Xbox's turn (again), as console prices keep going up
Microsoft announced a price hike for the Xbox Series consoles today, the third in little over a year. Effective August 1, the Xbox Series S, which launched in 2020 for $300, will cost $500 in the U.S. The Xbox Series X, which launched in 2020 at $500, will go for $800. This follows a round of PlayStation 5 price increases from Sony this spring, and a slow-motion increase for Nintendo’s Switch 2, which will kick in in the U.S. in September. (Mind you, there were also eight video game industry price hikes in six months of 2025). The chart up top shows the sudden ascent of console prices over the past year, a sudden surge in an already unusual hardware generation. Prices had been flat for years, now “up” is the new “flat.” Game console prices used to go down across the length of a console generation, but not this time around. Microsoft’s explanation for the new price hike today: We hoped another price increase would not be necessary, and we have spent the last several months working with suppliers on options. Unfortunately, console storage and memory prices have increased by more than 2.5x and we expect another doubling by the fall of 2027. The entire consumer electronics industry is struggling with the current components crisis, but the effects are particularly hard on consoles. Unlike phones, computers, speakers, and other consumer devices, consoles are typically not sold at a profit, but instead for less than they cost to make. This is an issue well beyond game consoles. Apple announced price hikes on its computers and tablets today as well. Game File is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe Item 2: Brutal Bungie cuts Bungie laid off “most” of its Destiny development team and some developers who worked on Marathon, the newest game from the struggling Sony-owned studio. A WARN notice issued by Sony to Washington State, where Bungie is based, tallied cuts impacting 292 workers, effective next month. That’s strictly for Bungie/Sony jobs in Washington and wouldn’t account for any elsewhere. The video I clipped below shows the redacted list of Bungie cuts filed to Washington State officials. As you’ll see, I had to scroll for a while… In a note emailed to PlayStation workers and published online, PlayStation game studios chief Hermen Hulst offered the following explanation for these latest cuts at Bungie: This is painful news, especially for talented colleagues whose roles have been eliminated. This decision was made only after extensive discussion and careful consideration, and I want to provide some context on how we arrived here. Over the past several months, together with Bungie leadership, we reviewed the studio’s long-term direction, development priorities, resource needs, and role within our broader portfolio strategy. We explored multiple alternatives before concluding that a reduction was necessary to align the studio’s resources with its current priorities and long-term goals. In 2022, Sony bought Bungie for $3.7 billion. The studio’s marquee game, the multiplayer live service shooter Destiny 2 was losing popularity at the time. Its next game Marathon, released earlier this year, has been well-reviewed but had a slow start. Bungie is renowned for making great shooter games, and Destiny fans have mourned the wind-down of Destiny 2. They’ve also expressed bewilderment over reports that Destiny 3 is not, per Bloomberg, immediately in the cards.
Consumer Discretionary Stocks Drawing Institutional Rotation Into Live Entertainment Leaders
With the Federal Reserve hinting at a pause in rate hikes, stubborn inflation still in the background, and several large companies surprising on earnings, consumer discretionary stocks are back in focus for investors weighing risk and opportunity. This article looks at how that mix of easier policy signals, solid corporate reports, and ongoing geopolitical and supply chain issues could affect larger U.S. consumer-focused companies. It will walk through 3 stocks from a curated screener that...
US economy grew at 2.1% in first quarter
First-quarter GDP grew at 2.1%, above the expected 1.6%, as equipment investment in AI and computers along with consumer spending led growth.
In 3-game healthcare series, underdog large-language models sweep specialized AI powerhouses
Pitting three multipurpose LLMs against two healthcare-specific AI tools, researchers have discovered the consumer-level AI can beat its purpose-built counterparts in healthcare scenarios—and soundly, at that.
Trump spoke with Live Nation CEO shortly before surprise Justice Department settlement, court filing reveals
Live Nation’s chief executive spoke with President Donald Trump less than a month before the ticketing and events giant reached a surprise antitrust settlement with the Justice Department that consumer advocate groups have largely panned.
Bose Launches Bose Studios, Sets Steven Soderbergh Project (EXCLUSIVE)
Bose, the consumer audio company, has announced the launch of branded entertainment company Bose Studios, unveiling details on its slate.
Google’s New $100 Speaker Makes a Weak Case for Gemini in the Home
The Google Home Speaker is the first new device of its kind to come from Alphabet Inc. in six years. In that time, Google has reshaped itself as an industry leader in artificial intelligence, with its Gemini platform now ubiquitous across consumer hardware like smartphones and web services like Search, Workspace and YouTube.
Record profits, terrible service: something’s got to give for US consumers
Experts say consolidation and market power have left consumers paying more for less
Women's health startup Xella Health exits stealth
The women's health startup is starting with direct-to-consumer memberships.
The Fitbit Air takes a smarter approach to the AI health dumpster fire
To be fair, the bar for AI consumer health is in hell.
The Fitbit Air takes a smarter approach to the AI health dumpster fire
To be fair, the bar for AI consumer health is in hell.
Stada Weighs €6 Billion Takeover of CVC-Backed Cooper Consumer Health
Stada is exploring a potential purchase of Cooper Consumer Health from its private equity owners, people familiar with the matter said, as it hunts for acquisitions on the back of record profits.
Regions Bank Announces New Leaders in Key Markets to Drive Business Growth and Customer Experience
Lisa Phillips to lead Consumer Banking in Georgia and the Carolinas; Mia Hubbard to serve as Retail Service Delivery Manager for the entire Regions branch network. Regions Bank on Tuesday announced two key leadership appointments that will drive continued business growth in vibrant Southeastern markets while also supporting consistent service enhancements at branches throughout the company’s 15-state retail banking footprint. Longtime Regions banker Mia Hubbard (top left) will serve as Retail Service Delivery Manager, and Lisa Phillips (lower, right) will succeed Hubbard as Consumer Banking Executive for Regions in Georgia and the Carolinas. Lisa Phillips will serve as Consumer Banking Executive for Georgia and the Carolinas, overseeing branch performance and growth in vital and fast-growing markets such as Atlanta, Charlotte, and additional cities across the three states. Phillips succeeds Mia Hubbard , who is taking on the role of leading Service Delivery across Regions’ entire
French Business Activity Extends Drop With Economy ‘Frail’
French business activity shrank for a sixth month after higher energy costs sparked by the Iran war hurt confidence and consumer spending.
Following user outcry, AMD reinstates memory encryption in consumer CPUs
Critics saw the move as an underhanded way to steer them toward more costly chips.
China’s rare earth dominance highlights global supply chain vulnerabilities
China’s dominance in rare earth processing and magnet manufacturing has given it significant influence over global supply chains for products ranging from electric vehicles and wind turbines to consumer electronics and advanced defense systems, The New York Times reports. Although rare earth minerals are mined in several countries, China controls much of the refining and […]
Chipotle and Cava are thriving as consumers prioritize value
Chipotle and Cava are thriving as consumers shift spending to perceived restaurant winners, focusing on quality over cost amid a "K-shaped" economy.
DCCA expands pathway for mental health professionals ahead of July 1 launch
The Department of Commerce and Consumer Affairs is preparing for the July 1 implementation of Act 93, which creates new provisional licenses for associate psychologists, associate marriage and family therapists, and associate mental health counselors.
Campbell County health and food inspections (6/12/26–6/18/26)
GILLETTE, Wyo. — The Consumer Health Services Division of the Wyoming Department of Agriculture conducts inspections of retail food establishments throughout Wyoming (where there is not a local health department that does inspections) to help ensure safety of Wyoming residents. Campbell County establishments are inspected at least once a year by the WDA. All of […]
Growing Interest in Liver Wellness Leads Consumers to Explore PureHealth Research Liver Health Supplements
What does it actually mean to feel "off" after a heavy meal, a few too many late nights, or a season of indulgence? More often than not, the answer points back to the liver – and PureHealth Research is spotlighting growing consumer interest in liver wellness, highlighting how targeted nutritional support could play a role in maintaining healthy liver function and overall well-being.
Not TP-Link, Not Netgear: This Wi-Fi Router Gets Consumer Reports Top Rating
According to Consumer Reports, the Asus ROG Strix GS-BE12000's reliable throughput and high power makes it the best single-unit Wi-Fi router on the market.
Autopsy Of A Freshly Cooked 10Gbit SFP+ Network Adapter
With the advent of affordable 2.5 Gbit, 5 Gbit, and 10 Gbit consumer networking gear, more and more people are taking advantage of these higher networking speeds, with [This Does Not Compute] havin…
Does Advertising Business Growth Assert AppLovin Corporation (APP) as a High-Growth Large-Cap Stock to Buy?
AppLovin Corporation (NASDAQ:APP) is one of the high-growth large-cap stocks to invest in now. On June 10, Benchmark reiterated a Buy rating on AppLovin Corporation (NASDAQ:APP)and a $775 price target. The research firm remains bullish on the stock, impressed by the company’s prospects in its consumer advertising business. A recent investor presentation affirmed management’s confidence […]
Gigabyte confirms Ryzen 9 PRO 9965X3D support on consumer X870 motherboard
Gigabyte has added AMD’s new Ryzen PRO 9000 desktop processors to the CPU support list for its X870 AORUS TACHYON ICE motherboard.
Egg Prices Are Way Down, but That’s Hurting Farmers
An oversupply of hens has lowered wholesale egg prices. But consumers may not reap the full benefits because of producer contracts and higher costs.
Cottage Cheese Shortages Are Driven by TikTok and ‘Protein-Maxxing’
TikTok and “protein-maxxing” are driving a cottage cheese squeeze that’s left some consumers desperate.
California is getting ready to increase a health insurance tax. Will it affect your premium?
Private plans say they'll pass the cost to consumers — meaning families could pay $400 more a year to help keep Medi-Cal afloat.
Premium credit cards promise rewards, but change how consumers spend
Premium rewards cards offer points, lounge access, and luxury perks — but those rewards are also changing how consumers think about spending.
Air Conditioning Is Becoming More Vital to Oregon’s Public Health and Safety
Air conditioning, especially in the Willamette Valley, has become a public health necessity rather than a consumer preference, says Vivek Shandas.
Snap finally debuts its long awaited AR glasses, Specs, and, oof, they aren't cheap
After many years, Snap is finally launching its next consumer-focused smart glasses line.
Snap’s first consumer AR glasses are coming this fall for $2,195
Snap is finally launching augmented glasses for the public
Spotting Winners: PENN Entertainment (NASDAQ:PENN) And Consumer Discretionary - Casino Operator Stocks In Q1
Looking back on consumer discretionary - casino operator stocks’ Q1 earnings, we examine this quarter’s best and worst performers, including PENN Entertainment (NASDAQ:PENN) and its peers.
EU rules out mandate to keep video games playable, seeks voluntary code
The European Commission said on Tuesday it cannot require video games to remain playable after they are withdrawn from sale, but will work with industry and consumer groups on a voluntary code of c...
GLP-1 and weight-loss drugs: How fast-track health solutions are reshaping FMCG
GLP-1 weight-loss drugs are reshaping FMCG as health, body control, and self-optimization trends redefine consumer behaviour across Europe.
Dave & Buster's Entertainment Q1 Earnings Call Highlights
Dave & Buster's Entertainment (NASDAQ:PLAY) reported weaker-than-expected first-quarter results for fiscal 2026, with management pointing to macroeconomic pressure in April, a softer consumer backdrop and promotional missteps as contributors to a 5.4% decline in comparable store sales. Chief Ex
Not LG, Not Sennheiser: This Soundbar Gets Consumer Reports' Best Audio Rating
The HW-Q900F soundbar stands out for Dolby Atmos performance, dialogue clarity, and multi-speaker design in independent audio testing.
Users cry foul after AMD stripped memory crypto from its consumer CPUs
AMD's stripping of TSME from consumer CPUs appears to be a deliberate, covert move.
Has Accel Entertainment (ACEL) Outpaced Other Consumer Discretionary Stocks This Year?
Here is how Accel Entertainment (ACEL) and Hugo Boss (BOSSY) have performed compared to their sector so far this year.
The $4 Billion Coffee Pod Business Faces Its Biggest Threat Yet
Billions of coffee pods are sold every year. Coffee giant Lavazza is betting that consumers are finally ready for a different approach.
Paranovus Entertainment Technology Limited Signs Non-Binding Letter of Intent to Acquire Jabanero Inc.
NEW YORK, NY / ACCESS Newswire / June 15, 2026 / Paranovus Entertainment Technology Ltd. (NASDAQ:PAVS) ("PAVS" or the "Company"), a consumer products and digital commerce solutions company, today announced that it has entered into a non-binding Letter ...
What This Iran Deal Might Mean for American Consumers | WSJ Politics Newsletter for June 15
Plus, Kevin Warsh wants the Fed to say less, and AI deepfakes muddle the midterms
How morals influence food, health decisions
Olin’s Sydney Scott researches why consumers act the way they do in the grocery aisle – and the doctor’s office.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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