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Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL

Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Sep 25 • 3:21 AM EDT • Health • finance.yahoo.com

AMA grant boosts patient-driven approach to cervical cancer screening

One of the AMA Community Health Impact Lab micro grants will back an innovative effort at Jefferson Health to boost screening.

Sep 25 • 3:00 AM EDT • Health • ama-assn.org

Uefa fears Premier League impact on transfer market

Uefa believes "a clear two-speed system" is emerging in the transfer market due to huge spending by Premier League clubs this summer.

Sep 24 • 6:18 PM EDT • Sports • sports.yahoo.com

Downtown Round Rock business rebrands as Alcove, opens expansion

The bar and restaurant formerly known as Sociedad rebranded to its original name of Alcove, owner Michelle Ly confirmed in September.

Sep 24 • 6:08 PM EDT • Business • communityimpact.com

Lake Austin drawdown canceled after concerns from business owners

The City of Austin has canceled a drawdown of Lake Austin after business owners expressed concerns about the economic impact.

Sep 24 • 5:50 PM EDT • Business • fox7austin.com

Politics Friday: How would having a woman as governor changes Capitol issue set?

Friday at noon, Minnesota is on the verge of joining the solid majority of states to have a woman as governor. We discuss what impact that could have on issue debates. Also, a look at the polling.

Sep 24 • 4:16 PM EDT • Politics • mprnews.org

Nick Robinson talks new film ‘Charlie Harper,’ favorite romantic movies

Seattle actor Nick Robinson shares how his new film, "Charlie Harper" (out Thursday) was impacted by the Netflix Western series "The Abandons."

Sep 24 • 4:00 PM EDT • Entertainment • yakimaherald.com

Trib wins LION Publishers Business of the Year

The Florida Trib was awarded LION Publishers medium/large tier Business of the Year for its operational resilience, financial health, and journalistic impact amid its statewide expansion this year.

Sep 24 • 3:36 PM EDT • Business • floridatrib.org

HHS Seeks Public Input on Wireless Technology Safety, Scientists Urge Caution

A call for the public to share their experiences on the health impacts of wireless technologies has raised eyebrows among scientists.

Sep 24 • 3:34 PM EDT • Science • aip.org

Empty stadium 'not something we've focused on'

Northern Ireland manager Michael O'Neill believes the near-empty stadium in Friday's Nations League game will impact hosts Georgia more than his own side.

Sep 24 • 2:57 PM EDT • Sports • sports.yahoo.com

Measuring the toll of extreme heat on workers’ health | Harvard T.H. Chan School of Public Health

Researchers are working to quantify the impact of working in extreme heat and humidity in order to help identify interventions that make a difference.

Sep 24 • 12:53 PM EDT • Health • hsph.harvard.edu

Lancaster County small businesses, private nonprofits impacted by drought eligible for low-interest loans

Low-interest federal disaster loans are available for small Lancaster County businesses and private nonprofits impacted by drought earlier this year.

Sep 24 • 12:40 PM EDT • Business • lancasteronline.com

DC Health Link Not Impacted by Federal Health Insurance Cancellations

Earlier this week, the Trump Administration announced plans to remove more than 750,000 Americans from health insurance plans purchased through healthcare.gov, a marketplace established by the Affordable Care Act (ACA). The administration alleges that the removed individuals were fraudulently enrolled in the program. In the District of Columbia, the DC Health Benefit Exchange Authority (DCHBX) […]

Sep 24 • 12:33 PM EDT • Health • hillrag.com

Two Long Island businesses score $20K grants

Two small businesses on Long Island received $20,000 grants through the L.O.C.A.L. Small Business Grant Program, supported by Optimum Business and the LIA Foundation, to help expand operations and enhance community impact. The program also provides advertising support and has awarded nearly $750,000 to LOCAL businesses since 2024.

Sep 24 • 11:12 AM EDT • Business • libn.com

AI is impacting local kids’ mental health: How can we keep them safe?

Editor’s note: This story contains mentions of suicide and self-harm. If you or someone you know needs help, call, text, or chat the 988 Lifeline.

Sep 24 • 10:14 AM EDT • Health • springfieldnewssun.com

Myrtle Beach officials approve revised plans for Carolina RockFest

The event is now tentatively scheduled for April 30-May 2 at Burroughs & Chapin Pavilion Place. "We did some preliminary analysis several years ago and that weekend would be generate, year one, around $20-25 million," Visit Myrtle Beach President Stuart Butler said. "This will grow through the years. CCMF generates about $52 million economic impact on our community. CCMF brought new first-time visitors to Myrtle Beach and turned them into repeat visitors.

Sep 24 • 9:39 AM EDT • Entertainment • myhorrynews.com

STC Trustees Take Leadership Roles on Core Committees

The duties of a South Texas College Board of Trustee expand past once-a-month meetings and event appearances, with committee involvement where most large decisions are made and crucial conversations that impact the college, students, faculty and staff are held.

Sep 24 • 9:31 AM EDT • Business • texasborderbusiness.com

Honda Internships Take UToledo Business Finance Student From Helper to Project Lead

Ella Boerger was one of four students who shared the value and impact of their experiential learning journeys with the UToledo Board of Trustees this week.

Sep 24 • 3:45 AM EDT • Business • news.utoledo.edu

In rural Pa., doctors confront the hidden health impacts of environmental disasters

This article originally appeared on Inside Climate News, a nonprofit, non-partisan news organization that covers climate, energy and the environment. In February 2023, George Garrow jumped in his car and hurried to help people impacted by a freight train that had derailed in East Palestine, Ohio. The crash happened about a quarter-mile west of the […]

Sep 24 • 3:15 AM EDT • Health • penncapital-star.com

Turning investment into impact to advance women’s health

Governments and businesses are increasingly putting women's health higher on the agenda, and public-private collaboration will be key to making progress.

Sep 24 • 3:00 AM EDT • Health • weforum.org

Catching up with: Ginger Ewing, executive director of Terrain

Terrain, the nonprofit arts organization that began as a one-off event nearly two decades ago, is entering a new era of growth as it expands its staff, programs, and economic impact on Spokane’s creative community.

Sep 24 • 3:00 AM EDT • Business • spokanejournal.com

Fintech After the Midterms: 3 Thoughts on How Politics Might Impact Policy

If the polls—and the prediction markets—are any indication, then the Democratic Party stands a better than even chance of taking control of the US House of Representatives after the mid-term elections in November.

Sep 24 • 1:32 AM EDT • Politics • finovate.com

Local business feels the impact of diesel prices

Sierra Feed received 100% of its inventory through diesel powered transportation, they say the price of diesel has doubled and they have to get tough and creative to continue business.

Sep 23 • 8:46 PM EDT • Business • kolotv.com

GOAL Medals Ceremony Celebrates Sports & Entertainment Venues’ Sustainability Impact

GOAL took part in Climate Week NYC by hosting two days of programming that included a behind-the-scenes tour of UBS Arena, a fireside chat featuring National

Sep 23 • 8:00 PM EDT • Entertainment • news.pollstar.com

New Yorkers could pay $26,000 out of pocket for climate change

“Energy. Impact. Action.” Is the official theme for Climate Week NYC 2026.

Sep 23 • 7:09 PM EDT • Politics • spectrumlocalnews.com

UNC Charlotte launches NC Economic Impact Center

UNC Charlotte has launched a N.C. Economic Impact Center that university officials envision as a place businesses and others will come when they need reliable information fast. “We are going to be a center and a repository for local data, constantly updating data, so that business leaders and civic leaders can come to us for […]

Sep 23 • 6:35 PM EDT • Business • businessnc.com

SCHEDULE: 2026 Brazos Valley Fair & Rodeo features youth livestock shows, live entertainment

The 2026 Brazos Valley Fair and Rodeo will feature youth livestock shows, a children's business fair, carnival rides and concerts from Oct. 23-25.

Sep 23 • 2:20 PM EDT • Entertainment • communityimpact.com

Scientists Uncover Gravity’s Impact on the Human Genome

Researchers build microgravity simulator to illuminate how external forces affect our cells

Sep 23 • 2:17 PM EDT • Science • nyu.edu

Wildfire Smoke Is an Escalating Public Health Crisis

Wildfires produce immense smoke and chemicals that can impact the health of individuals across cities. Discover global wildfire trends and how to prepar...

Sep 23 • 12:09 PM EDT • Health • iqair.com

Populous’ Jonathan Mallie Named a 2026 VenuesNow All-Star

Jonathan Mallie, Global Director and Managing Director of the Americas at Populous, has been named a VenuesNow 2026 All-Star, an annual list that honors those in the live events and venue management industry, celebrating their leadership, innovation, and impact on the global live entertainment environment.

Sep 23 • 11:07 AM EDT • Entertainment • populous.com

YouTube announces Custom Feeds, GIF comments, and ’Your podcast lineup’

At Made on YouTube 2026 today, YouTube announced a slew of new features. We’ve highlighted the capabilities that will impact...

Sep 23 • 10:30 AM EDT • Technology • 9to5google.com

Playoff Countdown: New England Revolution, St. Louis CITY mean business

Most teams have eight games left. The end is nigh. Until then… Each week, we’ll look at four teams rising or falling in the standings, three players making an impact, and three storylines to watch. An Audi 2026 MLS Cup Playoffs race 4-3-3, if you will. Four teams we're monitoring

Sep 23 • 9:51 AM EDT • Business • mlssoccer.com

Astrana Health Data Breach Reported; Impact Under Investigation

Do you believe your information may have been exposed in the Astrana Health data breach? Read more about the incident.

Sep 23 • 9:41 AM EDT • Health • classaction.org

AI CEO on China's space threat, AI development

Vanter CEO Dan Smoot joins the show to discuss China's impact on space satellites and technology. He analyzes President Donald Trump's comments on artificial intelligence and the importance of maintaining the U.S. tech lead.

Sep 23 • 8:24 AM EDT • Business • foxbusiness.com

OneSpartanburg Inc. holds annual celebration, honors 2026 award winners

“Our Annual Celebration aims to be more than a traditional chamber update, we want to take time to recognize the impact our organization and our partners – both public and private – have on Spartanburg County,” said OneSpartanburg President and CEO Allen Smith.

Sep 23 • 7:00 AM EDT • Business • upstatebusinessjournal.com

In Rural Pennsylvania, Doctors Confront the Hidden Health Impacts of Environmental Disasters

Researchers are learning more about the long-term public health effects of living through extreme weather, especially in more isolated communities.

Sep 23 • 5:00 AM EDT • Health • insideclimatenews.org

How extreme heat can affect your mental health

Extreme heat does more than cause physical harm. Experts explain how rising temperatures impact mental health.

Sep 23 • 4:01 AM EDT • Health • augustachronicle.com

Chargers' Oronde Gadsden has chance to make major impact

Chargers tight end Oronde Gadsden could see a major uptick in production after the team lost two tight ends to IR.

Sep 23 • 1:43 AM EDT • Sports • sports.yahoo.com

FedExCup Fall Schedule 2026

The 2026 FedExCup Fall is here. For many players, the next eight events could have a major impact on their 2027 PGA Tour season.While the FedExCup Fall doesn’t carry the same spotlight as the playoffs, it can be an important stretch for players looking to improve their position in the standings, secure playing opportunities and, […] The post FedExCup Fall Schedule 2026 appeared first on HEAVY.

Sep 23 • 12:56 AM EDT • Sports • sports.yahoo.com

Maine Health receives $4.5M NIH grant to study PFAS impact on bone health

Sep 22 • 10:33 PM EDT • Health • newscentermaine.com

Small Business Administration announces approval of disaster loans for those impacted by Empire Towers

Governor Wes Moore announced Tuesday that the Small Business Administration has approved his request for a Small Business Administrative Declaration to provide Economic Injury Disaster Loans.

Sep 22 • 9:10 PM EDT • Business • wmar2news.com

The potential local impact of Spanberger's data center 'framework'

Gov. Abigail Spanberger released her blueprint for regulating data center development last week, billing it as “a new way forward for how this industry does business in the Commonwealth.”

Sep 22 • 7:45 PM EDT • Business • loudountimes.com

Frisco sustainable business relaunches, Breckenridge hotel debuts renovations and more

Minimal Impact reopens under new ownership in Frisco Scents of soaps, lotions and household cleaners fill Minimal Impact’s tiny Frisco storefront, where shelves newly packed with sustainable goods fill the shop following its reopening this...

Sep 22 • 6:45 PM EDT • Business • summitdaily.com

Packers make decision impacting Micah Parsons' injury return date

Micah Parsons injury update: The Green Bay Packers have made a decision that hints at where they're at with Parsons.

Sep 22 • 5:55 PM EDT • Sports • sports.yahoo.com

How Index Switches Will Impact Tencent Music Stock Investors

Tencent Music Entertainment Group was removed from the FTSE All-World Index on its NYSE listing and added on its SEHK listing in September 2026, while fresh research updates highlighted mixed views on its core music operations and broader platform trajectory. The index switch concentrates liquidity closer to Tencent Music Entertainment Group’s onshore business footprint. This may sharpen investor focus on how its streaming, social entertainment, and offline initiatives line up with...

Sep 22 • 5:24 PM EDT • Entertainment • simplywall.st

A's Have Looming Roster Decisions to Make

With 10 players on the 60-day IL, the A's will have to add them back to the 40-man roster this offseason. Those decisions will have an impact on the team's offseason approach.

Sep 22 • 4:03 PM EDT • Sports • sports.yahoo.com

Scientists discover largest new impact crater in the solar system ever—on our moon

The crater, named after geologist and lunar surface expert Tom McGetchin, spans more than two football fields wide

Sep 22 • 4:00 PM EDT • Science • scientificamerican.com

Democrats pounce on report tying Collins to defense contractor

It all started when ProPublica investigated the impacts of President Donald Trump’s decision to clean house at the FBI and the Department of Justice in 2024.

Sep 22 • 2:11 PM EDT • Politics • spectrumlocalnews.com

ChatGPT writes weaker emails for women, new research shows

Johns Hopkins study reveals AI chatbots respond differently based on gender-coded language prompts, impacting workplace communication.

Sep 22 • 12:16 PM EDT • Technology • businessinsider.com

Voters, scientists say candidates should dig into environmental issues

Extreme weather events cost taxpayers and impact recreation and health, experts say.

Sep 22 • 11:39 AM EDT • Science • civicmedia.us

2026 Women of Influence Alum of the Year: Kristi Knous

The Business Record has named Community Foundation of Greater Des Moines President Kristi Knous the 2026 Women of Influence Alum of the Year. The annual award was launched in 2024 to celebrate a past Woman of Influence who has continued making an impact since being honored by the Business Record. Knous was honored as a…

Sep 22 • 11:31 AM EDT • Business • businessrecord.com

What CDC's new teen health survey shows, and what it skips

Teen suicide risk hit a 10-year low in 2025. Guns, sexual violence, and self-harm. Where are the 2025 data on transgender teens? Missing data changes public health policy. Teen suicide risk hit a 10-year low in 2025. CDC asked more than 10,000 high school students over 100 questions in spring 2025. Yesterday, it published a report covering a fraction of them. The report focsed on five areas: diet, physical activity, sleep, digital behaviors, and mental health, reflecting the priorities of the Make America Healthy Again movement. There was good news. Fewer teens seriously considered suicide in 2025 than in any survey year since 2015: 14%, down from 20% in 2023. Sadness fell. Underlying Conditions is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe Sports participation, which dipped to 49% in 2021, is back to its 2015 level of 58%. Daily PE fell from 27% to 20% in two years, while fewer students eat breakfast daily than a decade ago. Guns, sexual violence, and self-harm. The questionnaire is public, and it goes well beyond those five areas. Students answered questions about sexual violence, self-harm, and whether they got help when they felt sad or anxious. They said how quickly they could get a loaded gun. They reported whether food ran out at home and whether they felt close to people at school. There were questions about sexual identity, including whether they were transgender. The report did not publish any of the answers students gave to those questions. CDC posts the raw survey data online, so anyone can see what the report left out. The report doesn’t cover the health of sexual minority students. Among students who identified as gay, lesbian, bisexual, questioning, or another non-straight identity, persistent sadness fell from 66% to 57% between 2023 and 2025. Serious thoughts of suicide fell from 41% to 30%. Those drops were bigger than the ones among straight students, although the gap remains wide: 28% of straight students reported persistent sadness, about half the rate of LGBQ+ students. About 1 in 7 girls reported sexual violence in the past year. One in 6 students hurt themselves on purpose. Among students who needed help for sadness or anxiety, half rarely or never got it. And among students who had seriously considered suicide, 43% said they could get a loaded gun without an adult’s permission. One protective factor rose sharply. In 2023, 55% of students said they felt close to people at their school; in 2025, 63% did. CDC’s earlier research ties that kind of connection to better mental health. Where are the 2025 data on transgender teens? In 2023, CDC's national survey asked high school students, for the first time, whether they were transgender. Their answers are the only nationally representative data on transgender teens, and their mental health is by far the worst of any demographic. That year, 71% of transgender students reported persistent sadness, 54% seriously considered suicide, and 26% attempted it, compared with 38%, 18%, and 8% of cisgender students. But we don’t have 2025 data. The timing matters because students took the survey in spring 2025, as federal policy toward transgender youth shifted. On January 28th, an executive order directed agencies to end federal support for gender-affirming care for people under 19, and several hospitals paused that care within days. In February, the CDC said it would no longer process transgender identity data. Later in 2025, the Supreme Court upheld Tennessee’s ban on gender-affirming care for minors, and HHS ended the 988 Lifeline’s dedicated line for LGBTQ+ youth. Researchers disagree about how much state policy shapes trans teens’ mental health. A 2024 Trevor Project study estimated that anti-trans laws increased suicide attempts among trans and nonbinary youth. Critics dispute its methods and its estimates. The 2025 survey could have added national evidence to that fight. CDC collected the data but hasn’t publicly released it. Missing data changes public health policy. Surveillance works as a feedback loop. It can show officials whether their policies help or hurt. The CDC didn’t provide data on the students most exposed to transgender policy shifts. The report kept measures that frame health as personal choice, like fruit, breakfast, and sports. It left out measures that track policy, like gun access, mental healthcare, food at home, and school climate, all of which respond to what legislators and agencies decide. HHS did not respond to questions that I sent on September 21st.

Sep 22 • 10:31 AM EDT • Health • celinegounder.com

SeaSTORE Scientists Measure Trawling's Impact On Irish Sea Carbon Storage

The SeaSTORE project is conducting real-world research cruises in the Irish Sea to measure how seabed trawling disturbs stored carbon and whether that carbon ultimately reaches the atmosphere. Findings will be shared with UK policymakers to inform net zero, biodiversity, and food security decisions.

Sep 22 • 10:30 AM EDT • Science • oceannews.com

Tom Brady, Kirk Cousins, Fernando Mendoza and the Las Vegas Raiders' surprise start to the NFL season

Sky Sports NFL presenter Neil Reynolds explores the early impact of Kirk Cousins in leading the Las Vegas Raiders to a surprise unbeaten start through the first two weeks of the season; Cousins starred in Sundays win over the Los Angeles Chargers as he plays mentor to Fernando Mendoza

Sep 22 • 10:28 AM EDT • Sports • skysports.com

The UIndy College of Health Sciences Recognizes Outstanding Alumni with 2026 Awards

The University of Indianapolis’s College of Health Sciences (CHS) proudly recognized outstanding alumni who have achieved exceptional success and leveraged their UIndy education to make a significant impact in their field, within their communities, and in the world. This year’s CHS Alumni Awards recipients were: Ralph Reiff '80 (Physical Education, Biology) A first-generation college student,

Sep 22 • 9:50 AM EDT • Science • news.uindy.edu

The UIndy College of Health Sciences Recognizes Outstanding Alumni with 2026 Awards

The University of Indianapolis’s College of Health Sciences (CHS) proudly recognized outstanding alumni who have achieved exceptional success and leveraged their UIndy education to make a significant impact in their field, within their communities, and in the world. This year’s CHS Alumni Awards recipients were: Ralph Reiff '80 (Physical Education, Biology) A first-generation college student,

Sep 22 • 9:50 AM EDT • Health • news.uindy.edu

OPINION: How the Political Divide is Changing Gen Z

Libby Ferguson discusses the impact that political polarization is having on Gen Z and our college campuses.

Sep 22 • 9:00 AM EDT • Politics • kansan.com

2026 CALS Distinguished and Outstanding Alumni Honored

The College of Agriculture and Life Sciences celebrated its alumni award winners on Sept. 18. From the field to the lab, find out how they're making an impact.

Sep 22 • 8:20 AM EDT • Science • cals.ncsu.edu

Micron 2 GB GDDR7 Memory Chips Reach End Of Life, Leaving RTX 50 Series Fully Dependent On Samsung And SK Hynix

Micron halts production of 2 GB GDDR7 memory chips, impacting RTX 50 GPU availability; 3 GB modules deemed largely ineffective.

Sep 22 • 7:49 AM EDT • Technology • wccftech.com

Is 50 the new 60?

Subscribe TL;DR: Younger generations are showing signs of worse health compared to earlier-born cohorts at the same age This backward “drift” is showing up both in mortality risk and chronic disease Worsening trends in obesity and diabetes are the most consistent signals Taking the long view, we’ve made astonishing gains in health and life expectancy in the last century. Global average life expectancy has more than doubled from 32 years in 1900 to 73 years in 2024. (But don’t forget, there were still old people when life expectancy was 32). As people lived longer, they also generally lived healthier along the way. It turns out that avoiding things that can kill you early, like malnutrition and lots of childhood infections, also keeps you healthier later in life. In a classic 2004 paper, Finch and Crimmins proposed that cohorts of children who benefited from fewer early life infections had less lifetime exposure to inflammation and cardiovascular disease later in life, accelerating mortality improvements at older ages. Poor nutrition in the womb has also been linked to a higher risk of later chronic disease. The upshot is that improvements in childhood health can pay dividends many decades later. The combination of better living conditions (nutrition, sanitation) and medical advances (antibiotics, vaccines, blood pressure meds, etc) meant that people’s healthy lifespan generally expanded, even as they lived longer. Aging researchers call this best-case scenario “compression of morbidity”—meaning we delay the onset of disease and disability even faster than the years of life we are adding. During my 20+ year research career, we could generally bank on the idea that younger generations would not only live longer but also keep getting healthier along the way. “60 is the new 50” as they say… Enter “Generational Health Drift” Sadly, this expectation of steady progress may be changing. You’ve probably heard that US life expectancy gains have slowed to a crawl in the past couple of decades. Mortality improvements are also slowing (though less dramatically) in many other high-income countries (you can read more about that in a review paper I wrote here). Mortality is a very blunt health measure, but it is often a good barometer for the broader population health trends happening underneath. And we are now seeing that younger generations may be in worse health at similar ages compared to earlier born cohorts. My collaborator Prof. George Ploubidis at University College London coined this worsening health in more recently born cohorts “generational health drift.” “Generational health drift” is bad news on multiple fronts. Most obviously, we don’t want our health progress to go backward. But the timing is also bad, since our populations are aging. In demographic terms, “population aging” means that the proportion of the population at older ages (i.e >65 years) is increasing. Fun demography fact: Current population aging is not due to the recent declines in the birth rates making the news, but declines in fertility decades ago, after the “baby boom.” As baby boomers reach older ages, the smaller cohorts behind them mean the percentage of older adults will increase. For example, the share of the population age 65 and older in the US increased from 12.4% in 2004 to 18.0% in 2024. This story of population aging was written long ago. Many worry that population aging will put pressure on health care and pension systems. But if people reach older ages in better health than in years past, those fiscal pressures would be less dire than projected. Healthy older people can also continue to contribute to society in many valuable ways, including paid work, caregiving, community service….even high political office 🤷. On the flip side, if younger generations reach retirement age in worse health and with more disabling conditions, this could magnify the societal challenge of population aging. Evidence for worsening generational health A recent paper that I LOVED in the Proceedings of the National Academy of Sciences by Dr. Leah Abrams and colleagues examined which birth cohorts (aka generations) were behind worsening US mortality. Behold the Lexis diagram (cue swooning demographers). Calendar time is on the x-axis, age on the y-axis. Birth cohorts can be followed over time as they age on the diagonal lines moving up and to the right. This figure plots the year-on-year % change in all-cause mortality at a given age. Green shading indicates mortality improvements over time, white is stagnation, and gray shading indicates worsening mortality. Following the diagonal line for those born in 1950, you can see a noticeable shift from green to gray that follows this cohort for most of their lives. This gray shading shows generally worsening mortality for the 1950 to 1959 birth cohorts compared to their predecessors across all ages. Concerningly for my GenX and elder millennial peeps, there was also a deterioration in mortality for birth cohorts born in the 1970s and 1980s, visible as dark gray areas at ages 30 to 45 during the 2010s. While some of these mortality changes reflect specific shocks such as the opioid epidemic, most deaths still occur from major causes of death such as cardiovascular disease and cancer. For cancer, the gray in the top left corner of the figure below reflects the legacies of smoking for older cohorts, followed by a period of green with improvements in cancer mortality as smoking rates declined. But the white/gray shading in the bottom right corner highlights a stagnation and reversal of the cancer trends, with cohorts born around 1970 to 1985 experiencing worsening cancer mortality. This deterioration was most noticeable for colon cancer mortality, possibly linked to obesity or dietary factors. Not just dying more, but less healthy along the way. A recent paper by Dr. Laura Gimeno of University College London (of which I am a co-author), found evidence that more recently born cohorts in Great Britain have stagnating or worsening health. A stylized picture of what“generational health drift” might look like: The review paper found: Rates of childhood overweight and obesity were highest among Gen Z. Rates of diabetes in the 40s almost doubled from 3.1% among the Baby Boomers to 5.9% in Generation X. Gen Z reported higher rates of poor mental health in adolescence compared to earlier-born groups. These UK results are consistent with studies showing worsening health across generations in the US as well. A 2021 US study found that more recently born cohorts had worse biological markers (like blood pressure and blood sugar) than earlier generations at the same age. A separate 2022 study of Americans aged 50 and over found that more recently born generations had a higher number of chronic diseases, with younger age of disease onset. A 2024 Lancet paper found that in the US, women born in 1945 had 33% obesity prevalence at age 50, rising to 48.2% for women born in 1970 turning 50. So what’s going on, and can we turn it around? We don’t have a definitive answer for what’s causing the deteriorating health of younger cohorts, but circumstantial evidence points to worsening trends in obesity and diabetes in both the US and UK. Remember that cohort trends reflect lagged effects of early environments, and younger generations have faced both earlier onset and more severe obesity across their lifetimes. Despite these very concerning trends, the future is not set in stone. We’ve reversed poor generational health trends before: drops in smoking are a major reason cancer and heart disease deaths fell so dramatically in recent decades. GLP-1 drugs may finally turn the tide against rising rates of obesity and diabetes, though it is still early days. But things could also get worse…for example from a return to higher levels of childhood infectious diseases that can have a lasting impact on health. See for example: [ ](https://jenndowd.substack.com/p/dont-you-forget-about-measles-the) [ Don’t You Forget About Me(asles): The Virus That Erases Immune Memory ](https://jenndowd.substack.com/p/dont-you-forget-about-measles-the) Jenn Dowd, PhD · March 24, 2025 [ Read full story ](https://jenndowd.substack.com/p/dont-you-forget-about-measles-the) Even as an optimist, emerging data on the “generational health drift” has my full attention. For most of my research career, we took it for granted that each generation would be healthier than the last. But if present trends continue, **50 could be the new 60….**and Gen Z celebrities will soon look older than Paul Rudd :). Stay well, Jenn Share the Health! If you found this post useful, please share it with a friend. Share

Sep 22 • 6:03 AM EDT • Health • jenndowd.substack.com

Is Roberto De Zerbi Misusing Mateus Fernandes For Tottenham?

Mateus Fernandes has struggled to make an impact for Tottenham Hotspur since joining from West Ham in the summer.

Sep 22 • 5:04 AM EDT • Sports • sports.yahoo.com

CSU experts say rising heat will negatively impact academics this fall

Fort Collins just logged its warmest summer on record. Nighttime lows aren’t dropping the way they used to. And through most of September, nearly every day has landed above the historical average for the month. For Colorado State University students, that’s more than a matter of sweating through class; researchers say it could be shaping...

Sep 22 • 2:00 AM EDT • Science • collegian.com

SBA offering low-interest loans for businesses impacted by drought

UMATILLA COUNTY — The U.S. Small Business Administration (SBA) is offering disaster assistance for businesses in Oregon, Washington and Idaho that were impacted by drought this year. The SBA announced […]

Sep 21 • 9:00 PM EDT • Business • eastoregonian.com

BKL Nightly: Greg Connors on the Bills, Business and Life Behind the Curtain

Connors & Ferris co-founder Greg Connors joins Thad on BKL Nightly to talk Buffalo Bills football, from the team’s early-season start to the players making an impact. Connors also takes viewers behind the curtain of his longtime relationship with the Bills as a business partner and shares more about the career and community work that have shaped his life.

Sep 21 • 8:12 PM EDT • Business • rochesterfirst.com

Connecticut, Arizona congresswomen celebrate Hispanic-owned businesses in Fair Haven

FAIR HAVEN, Conn. (WTNH) — Two congresswomen toured Grand Avenue in Fair Haven Monday, showcasing the contributions, hard work and impact of Hispanic-owned businesses in Connecticut. U.S. Rep. Rosa…

Sep 21 • 6:59 PM EDT • Business • wtnh.com