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October Prime Day is a week away, and new early deals just dropped: iRobot, Lego, Ninja and more are up to 80% off
Before Prime Big Deal Days officially starts (and popular products sell out), Amazon loyalty members can add household basics, gifts and much-needed upgrades to their carts.
Netflix on Building Products as Artifacts of Fandom
Netflix's Filippo Zuffada explains how the streamer is building year-round licensing momentum and why partners need to start with fandom, not format
Musician upholds 74 lashes for hijabless performance as Iran continues entertainment crackdown
The court found that a hijabless performance had violated “public decency through the production and publication of obscene and immoral content on cyberspace platforms.”
Kristaps Porzingis out indefinitely to start Warriors training camp due to health issue
Not a great way to start training camp for a Warriors team that needs health to go its way this season.
Financial Boost For Global Health On Sidelines Of UN General Assembly
Several significant pledges for global health – covering reproductive health, 'transition' and Ebola – were made on the fringes of last week’s United Nations
Meta launches enterprise AI business seeking to cash in on vast spending
Chief executive Mark Zuckerberg opens a new front in his push to turn huge investment in the technology into profits
COTTON IN BEAUTY: A Sustainable, Sensorial & Science Backed Solution
This eBook examines how brands can leverage cotton's hypoallergenic, biodegradable and sensorial properties to create differentiated products, from facial wipes and reusable rounds to period care and adult incontinence.
Russian drones hit Kyiv science academy and hospital
One person killed and six injured in attack on capital, as Volodymyr Zelenskyy urges countries to do more to protect Ukraine
Trump administration lowers fuel economy standards, critics say at a significant environmental cost
The change furthers President Donald Trump’s promise to revoke policies that encouraged or created incentives for the production of electric vehicles.
12 New Things to Expect From Apple This October
October will be an especially busy month for Apple this year, with the company set to release the iPhone Duo, both iOS 27.1 and iOS 27.2, and a new Mac Studio configuration with 512GB of RAM. In addition, up to six more Apple products may be unveiled next month, such as new iPad mini, HomePod mini, and Apple TV 4K models. Below, we have outlined 12 new things to expect from Apple this October. Confirmed iPhone Duo: The foldable iPhone Duo launches on Friday, October 23.
Cambridge redevelopment project creates sustainable opportunities
The Packing House – a historic landmark in Dorchester County – has transformed from a vacant factory into a bustling site for businesses, entrepreneurs, food production, and community programming. Originally constructed in 1920 as the Cambridge...
Peanuts Entertainment Launches With Mirabel Sisters Feature
Amílcar Franco has launched the London-based Peanuts Entertainment, a production company focused on developing Latin American stories
Peanuts Entertainment, London-Based Production Company Focusing on Latin American Stories, Launches With Mirabal Sisters Feature ‘Alive in Their Garden’ (EXCLUSIVE)
Peanuts Entertainment, a production company focused on developing what it describes as “culturally rooted Latin American stories for international audiences,” has launched in London. The new outfit ha...
Activist Jana pushes Fiserv to accelerate cost cuts and tap Palantir
Activist investor Jana Partners is urging Fiserv to more than double its planned cost cuts and use software firm Palantir's products to speed up its own technology transformation program, according to a letter sent to the payments company that was viewed by Reuters.
Diaper maker grows jobs, investment in Rockingham County
Belgium-based Drylock Technologies has exceeded its investment and job creation promises in Reidsville in Rockingham County. The hygiene products manufacturer promised in February 2024 to invest $26.9 million to create 113 jobs at its first U.S. factory for baby care products. Since then, Drylock has invested more than $31 million and has 212 workers who […]
BMW M2 Gets A Dramatic 3.0 CSL Makeover
Riverti Automobili reshapes the G87 BMW M2 with 3.0 CSL-inspired bodywork, while key specs like power and production remain under wraps.
Enagic rep tells moms to disinfect with 'magic water,' and the science falls apart
Effective disinfection depends on proven products, clear instructions, and a little skepticism, especially when a sales pitch starts sounding more like a chemistry magic trick.
Scientists Test an Unexpected Sleep Aid Made From Tree Roots
A pilot study suggests that oil from underused Hinoki roots could be used in scented products for relaxation. Falling asleep can be compared to easing down a dimmer switch, with brain activity gradually shifting as sleep deepens. Researchers studying Hinoki, or Japanese cypress, are exploring whether its scent could help smooth that transition for women
Fall Into Good Health
As temperatures drop and routines begin to change, fall is a great time to take stock of your horse’s health and wellness needs. From nutrition and recovery to grooming, hoof care and forage, these products can help keep horses feeling their best through the changing season and into winter.
AI assessors says current science hasn't caught up to the safety measures people want
Anthropic and OpenAI say they are working with third-party evaluators to make sure their products are safe. Some evaluators caution that current AI science lags behind what people are calling for.
EFI and Agfa’s DPS Business to Combine and Form a Global, Full-Service Industrial Inkjet Company
September 28, 2026 – 7.45 AM CET Regulated information – Contains inside information EFI and Agfa’s DPS Business to Combine and Form a Global, Full-Service Industrial Inkjet Company Combination to Create a Broader, More Diversified Business with a Comprehensive Product Portfolio, Expanded Geographic Reach and Enhanced Capabilities to Serve Customers Across Key End Markets Mortsel, Belgium and Londonderry, N.H. – September 28, 2026 – 7.45 a.m. CET Electronics for Imaging, Inc. (“EFI”), a leading
Oscar Health (OSCR) Shares Moved, What Is Catching Investors' Attention?
Why Oscar Health’s latest product push matters now Fresh commentary around Oscar Health (OSCR) centers on management’s push for higher earnings per share through tighter medical loss ratios, new offerings such as the Lucy Healthcare Marketplace, and wider use of AI tools. At a share price of $29.60, Oscar Health has pulled back over the past week with a 7 day share price return of down 5.4% and a 30 day share price return of down 2.9%. However, the 90 day share price return of 3.8% and year...
Kremlin pressures Russian businesses to pay for drone defences
Vladimir Putin backs army and spy agencies’ push to make businesses defend themselves from Ukrainian strikes
Photos show Baghdad Ballet Academy students taking the stage at Baghdad’s Al-Sinbad Theater
BAGHDAD (AP) — Students from Baghdad’s Ballet Academy performed a production titled “Mermaid” before an audience at Al-Sinbad Theater on Friday. Wearing colorful costumes, dancers of different ages presented solo and ensemble routines, moving through choreographed formations, leaps and turns...
Photos show Baghdad Ballet Academy students taking the stage at Baghdad's Al-Sinbad Theater
BAGHDAD (AP) — Students from Baghdad’s Ballet Academy performed a production titled “Mermaid” before an audience at Al-Sinbad Theater on Friday.
FYI BR: video production training at the arts council, Honey Gold at the planetarium and more
The Honey Gold Experience will perform live at LASM’s planetarium on Oct 3, blending original music and visuals in an immersive dome show with custom video collages and live sound design.
Sennheiser Momentum 5 review: Great sound, incredible battery life, and few compromises
I spent the last few weeks with the Sennheiser Momentum 5 to determine if this pair actually stands out, testing everything from sound quality and noise cancellation to comfort and battery life.
Newsom signs bills to expand reproductive healthcare in California
Gov. Newsom signs bills focusing on reproductive healthcare in California. Some of the bills focus on increasing access to abortion.
Cup & Kettle rebuilds Bloomington tea business after flooding, construction
Cup & Kettle shifted from a cafe to tea production after years of setbacks.
Jodi's Journal: When your town lacks Trader Joe's, entrepreneurialism emerges
Meet the one-woman personal shopper/shuttle for Sioux Falls-area customers desperate for their favorite products from Trader Joe's.
13 Cool New Gadgets to Keep on Your Radar
Catching you up on the past week’s most notable product releases.
Vikings Offensive Solution Identified for Matching Productive Defense
With the running game sidelined by injuries, quarterback Kyler Murray must lean on red zone threat Jauan Jennings to finally unlock a stagnant offense against Tampa Bay.
Nursing Homes Have Become Last-Resort Housing
Finding the right care for older adults facing homelessness could be part of a broader rethinking of long-term care, writes Michele Cohen Marill.
Maha split shows all is not well with Kennedy’s US health revolution
Republicans worry Make America Healthy Again is an electoral liability while activists claim it has abandoned its values
Watch: 404NotFound on Turning Every Step into Meaningful Health Insights
The official communications channel of Samsung Electronics, providing all the latest stories regarding the company's products, people and businesses.
Colorado recalls marijuana vape company's products sold at more than 400 stores
Colorado public health and marijuana regulation authorities issued on Friday a recall of marijuana vape devices believed to be contaminated with a volatile industrial solvent.
Canadian doctor cracks the ‘science of a healthy, happy retirement’ — and anyone can do it
While you might be focused on your financial portfolio, don’t forget to make contributions to your ‘life’ portfolio.
Assessment of Health Warning Label Compliance on Smokeless Tobacco Products in Bhubaneswar, India
Introduction: Use of smokeless tobacco (SLT) is a serious public health problem in India. Health warning labels (HWLs) play a vital role in imparting information regarding the adverse health eff...
What Is a ‘Pocket Rescission’? Inside Trump’s Move to Cancel $810 Million in Federal Funding
The Trump Administration is seeking to claw back spending that was approved for programs including those serving immigrants, refugees, minority groups, and children.
No, Xbox didn't pay $400 million for Hideo Kojima's 'PHYSINT'
A new rumor going around this weekend has put Xbox's investment in Kojima Productions way above the real figure. But it remains to be seen just how spendy the projects will end up being.
What's the Most Overrated Business Advice?
Let us know the most overrated business advice you've gotten in the comments.Subscribe to The Hustle:🔗 https://clickhubspot.com/vu3lGet the 5-minute newsletter keeping 2M+ innovators in the loop🔗 https://clickhubspot.com/3klnAbout HubSpot: HubSpot is a customer platform that provides education, software, and support to help businesses grow better. The platform includes marketing, sales, service, commerce, operations, and website management products that start free and scale to meet our customers’ needs at any stage of growth. Today, thousands of customers around the world use HubSpot’s powerful and easy-to-use tools and apps to attract, engage, and delight customers.#TheHustle #HubSpot
Robert Saleh Wants to Get One Titans Player More Involved
After a quiet debut, rookie Nicholas Singleton could see an expanded workload as injuries thin the backfield, providing the explosive Penn State product a chance to shine.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Top Stories: Apple Leaks, Siri AI Settlement, and More
The Apple rumor mill never stops, and this week MacRumors was able to break the news of details on several upcoming products.
Weight loss drugs could help treat women’s reproductive health issues, experts say
Experts say weight loss drugs could help women struggling with PMOS.
Lazio Stalwart Reaches Verbal Agreement With Balotelli’s UAE Club
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Tyson Bagent Injury Update: Bears QB Receives Unfortunate Update
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Funko warned it might not last 12 months. Its new CEO came from Netflix with a plan.
Funko, the company behind the big-headed Pop! figurines, warned last year it might not survive, squeezed by tariffs, canceled retail orders and its own overproduction. A new CEO based in Los Feliz is trying to turn it around.
Funko warned it might not last 12 months. Its new CEO came from Netflix with a plan.
Funko, the company behind the big-headed Pop! figurines, warned last year it might not survive, squeezed by tariffs, canceled retail orders and its own overproduction. A new CEO based in Los Feliz is trying to turn it around.
Ken San Jose set for Broadway debut in ‘Evita’ revival
Ken San Jose will star in the upcoming Broadway revival of "Evita" via Instagram/@ kensanjose Filipino American performer Ken San Jose will make his Broadway debut in the 2027 revival of Evita, joining the ensemble of director Jamie Lloyd’s production starring Rachel Zegler as Eva Perón. Previews begin Feb. 27 at the Winter Garden Theatre in New York,…
Long-Time PlayStation Publisher Says "The Discussion May Change" Around Physical Media
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Forum examines health questions surrounding chemicals in consumer products
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ProTributeBands.com Clarifies Direct Booking Model for Corporate Event Entertainment Planners
SAN RAMON, CA - September 25, 2026 - PRESSADVANTAGE -ProTributeBands.com, the curated booking and lead generation platform for high-end tribute bands, has outlined how its direct-booking structure works for event planners seeking corporate event entertainment. Under the model, bands featured on the platform negotiate terms and close each booking directly with the client, while ProTributeBands follows up to keep the transaction moving smoothly.The structure separates ProTributeBands.com from traditional booking agencies that insert themselves into every contract. Rather than acting as an intermediary that controls the final agreement, the platform connects event planners, performing arts centers, festivals, wedding clients, and private party hosts with pre-screened, national-act-caliber tribute acts, then steps back so the parties can settle details themselves. The platform maintains contact with both sides to ensure momentum is not lost during the process.Founded by David Victor, former guitarist and co-lead vocalist of the multiplatinum band BOSTON, ProTributeBands.com features tribute acts covering artists such as Queen, The Beatles, ABBA, Journey, The Eagles, and Pink Floyd. Selected bands receive optimized profile pages and booking leads generated through the platform."Event planners often assume a booking platform means another layer of negotiation and markup," said David Victor, Founder of ProTributeBands.com. "The approach here is different. The bands negotiate terms and close each booking directly, which keeps the conversation honest and the details accurate. The platform stays involved by following up so nothing stalls between the first inquiry and the signed agreement."The direct-booking method reflects how corporate and private event planning typically operates. Planners frequently need to confirm technical requirements, stage dimensions, scheduling, and performance specifics with the people who will actually be on stage. By allowing those conversations to happen between the client and the band, the model aims to reduce miscommunication that can occur when information passes through a third party.ProTributeBands.com applies a screening process before an act appears on the platform, focusing on production quality, musicianship, and readiness for larger venues. The company ranks tribute bands across categories including Queen, The Beatles, The Eagles, Journey, Pink Floyd, and BOSTON tributes, drawing on performance quality and audience response.The ProTributeBands guide to hiring a tribute band offers additional context for planners weighing these decisions, covering topics such as understanding the audience and event, assessing entertainment value, viewing an act in person before hiring, and reviewing rider and insurance requirements. The guide addresses the practical considerations planners face when selecting an act for a corporate function, festival, or private celebration."A tribute production for a corporate audience has to hold the room the same way a headline act would," Victor said. "The vetting exists so planners can trust that the act they see listed can deliver at that level, and the direct-booking structure lets them confirm every detail with the band before committing."ProTributeBands.com serves clients across the United States and abroad, working with tribute acts that perform at performing arts centers, summer concert series, product launches, corporate parties, private parties, and wedding receptions. The platform also accepts artist submissions from tribute bands seeking consideration for inclusion. The company operates online at protributebands.com.###For more information about ProTributeBands.com, contact the company here:ProTributeBands.comDavid Victor(925) 236-0217hello@protributebands.com11040 Bollinger Canyon Road Suite E-938, San Ramon, CA 94582
PlayStation's Newest Survey Sparks Community Pushback Against Sony's Plans to End Physical Game Discs
PlayStation has released a survey that any member of the public can fill out, as long as they’re an adult — and players are using the opportunity to push back on Sony’s plans to end the production of physical game discs.
Quixote shutters supplying business, lays off 60 employees
Hudson Pacific-owned Quixote sold its grip, lighting and production supplies businesses to Cinelease, cutting about 60 jobs as Hollywood's production slump drags on.
Quixote shutters supplying business, lays off 60 employees
Hudson Pacific-owned Quixote sold its grip, lighting and production supplies businesses to Cinelease, cutting about 60 jobs as Hollywood's production slump drags on.
Meta VR Glasses Plan Imax Entertainment Push
Mark Zuckerberg unveiled a major VR product this week, with the company turning to Disney, Imax, Dolby, James Cameron and others to help create a cadence of content.
Musco expands testing capabilities with new Oskaloosa facility
Oskaloosa-based Musco Lighting has opened a new 30,000-square-foot product testing facility at 601 First Ave. W, expanding its ability to design, test and support lighting solutions. The facility brings testing and certification in-house, providing additional resources to evaluate and improve product performance as lighting and electronics become more complex. The opening coincides with Musco’s 50th…
iPad Mini 8 Leaked: A20 Pro Chip, Landscape Camera, and More
Apple's next-generation iPad mini will feature the A20 Pro chip, a rearranged front-facing camera, and a new speaker system, leaked code reveals. The information originates from Apple's own code (spotted by MacRumors contributor Aaron Perris) and also shows clear product images of the new iPad mini. Although images of the device only show the front, leaving any design changes of the rear or side profile unknown, there are still visible changes.
Exclusive: First Look at HomePod Mini 2 in Three New Colors
Apple's new HomePod mini will share the same design as the original model and come in five colors, MacRumors has found. The information originates from Apple's own code (spotted by MacRumors contributor Aaron Perris) and shows clear product images of the new models in all of their colors. The above image contains Apple's own icons, which specifically refer to a "HomePod mini 2". The new HomePod mini will come in green, pink, blue, white, and black.
Health experts warn to avoid kratom products
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HBO’s Billionaire Divorce Drama War Doesn’t Know What It’s Trying to Say
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LIVE: Six years on from COVID-19, is the world ready for the next pandemic?
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NCL unveils entertainment for Norwegian Aura, including Whitney Houston tribute
The Norwegian Aura, which will debut in May 2027 out of Miami, features the headlining production “Whitney: A Celebration of Whitney Houston.”
NCL unveils entertainment for Norwegian Aura, including Whitney Houston tribute
The Norwegian Aura, which will debut in May 2027 out of Miami, features the headlining production “Whitney: A Celebration of Whitney Houston.”
New rock production brings its own legends lineup
“Ikons of Rock” has moved into The Strat Theater, where it is getting loud.
Sony reportedly surveying developers about PlayStation disc-ending decision - is it having second thoughts?
Sony's decision to end PlayStation disc production has been hugely controversial, seemingly even among developers. A rumoured survey suggests Sony has noticed.
Are girls more social from birth?
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'I would encourage patience with Wirtz'
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Wellness kiosk in the Memorial Union makes it convenient for OSU community to buy basic healthcare products, STI tests and more
A new vending machine in the basement of the Memorial Union on Oregon State University’s Corvallis campus is now stocked with a variety of over-the-counter healthcare products, from cortisone to contraceptives to COVID tests.
US lawmakers pitch tax credit bill for entertainment industry
The law seeks to reshore production work for movies and TV to the US
Letter: Ethics of science cannot be separated from who funds it
From Vincent Straub, Interdisciplinary researcher, University of Oxford Nuffield Department of Population Health, Oxford, UK
The Empire Forum to unite retina science, industry, and investment
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Democracies in glass houses
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Federal legislation introduced to boost Hollywood production with tax credit
The Motion Picture, Television and Entertainment Revitalization Act would establish a 20% tax credit on labor expenses for American workers on qualifying film and TV productions.
Paolo Banchero Plummets in Latest NBA Player Rankings
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Bills TE Kincaid is once again pulling his weight in production
The fourth-year player is leading the Bills (2-0) with 12 catches and is third in the NFL with 225 yards receiving.
The Latest Licensing Deals From Global Brands
New partnerships span collectibles, apparel and entertainment as brands expand product lines across gaming, fashion and lifestyle categories.
Iowa State researcher part of multistate team recognized for work to improve livestock reproduction
Karl Kerns, assistant professor of animal science at Iowa State University, is part of an interdisciplinary team recognized this week with agInnovation's national 2026 Excellence in Multistate Research Award for collaborative work to improve reproductive performance in cattle and sheep.
Apple has three products launching soon that we’ve waited a long time for
Apple has had a big month, and is set to keep going strong in October with several product unveilings soon that we’ve waited a long time for.
Griffin MSI’s new design must go back to the drawing board: ‘Carbuncle in the park’
The two-story, 458-foot long entry pavilion threatens to visually overpower the landmark museum's historic entrance and great lawn.
Lawmakers Introduce 20-30% Federal Film Incentive
Lawmakers have introduce da 20%-30% stackable film incentive in a bid to restore domestic production.
Thomas Sorber Is Thunder's Forgotten First-Round Wild Card
Hidden behind injuries and draft-day hype, the physical Georgetown product offers a bruising interior presence and elite wingspan that could redefine the Thunder’s versatile frontcourt rotation.
GNDC honors legislator and business with awards at policy summit
Baker Boy was recognized for its continued investment in its people, operations and community
Walker Kessler's ESPN Rise Sends Clear Message to Utah Jazz
A 25-spot rankings surge for the Lakers’ newest center exposes a harsh reality: elite production often stays hidden until paired with superstars and the national spotlight.
EU science policy wonks debate prospect of stronger ties with Canada
Europe’s research and innovation sector has started asking questions on how European Commission President Ursula von der Leyen’s offer to make Canada “the first associate member of the EU” would actually work in practice, and who will get to shape priorities in a transatlantic relationship that is getting stronger. The Commission says it wants “a new model of association” under which the EU and Canada will aim to develop “a shared space” to face ongoing challenges. “Working in close coordination with our member states and the European Parliament, we will aim to create a new form of partnership that has not existed until now, building the closest imaginable form of association with a partner outside Europe,” a spokesperson told Science|Business.Locked in an escalating trade war with US President Donald Trump, who has repeatedly talked of annexing Canada, Prime Minister Mark Carney has been looking east, but full EU membership was never in play. Taking the floor a day after von der Leyen’s proposal, he agreed to strengthen ties under “an alliance of the future” but reined in enthusiasm on the new label. He also suggested expanding Canada’s involvement in the Erasmus+ student mobility scheme, to which it currently has limited access, and the next iteration of Horizon Europe. Canada joined the present Horizon Europe in 2024, but only contributes to collaborative projects.Neither side has detailed the next practical steps in developing this new relationship. “I think nobody at the moment truly knows how this will work,” said Michael Browne, chief executive and founder of Crowdhelix, a global collaborative network that connects players in research and innovation. “It’s more of a statement of intent for closer collaboration, which requires legislative frameworks and approval processes, which have not started.”Kurt Deketelaere, secretary general of the League of European Research Universities, said von der Leyen’s pitch to Canada is “politically significant, but the legal content still has to be negotiated and constructed.”Mattias Björnmalm, secretary general of the Cesaer university group, agreed that she had only opened “a political door” to Canada, as “associate membership does not come with a predefined set of rights in the EU institutions.”Not only does this status not currently exist as a legal category in the two treaties that set up how the EU functions, but the Commission president cannot unilaterally create a new category of EU membership.According to Deketelaere, Article 217 of the Treaty on the Functioning of the EU, which allows the bloc to make association deals with non-EU countries involving reciprocal rights and duties, is “the most obvious existing legal basis for building a much deeper EU-Canada relationship.”Getting universities involvedNo matter how this new cooperation takes shape, Liviu Matei, who heads the School of Education, Communication and Society at King’s College London, hopes to see universities involved in discussions from an early stage.“Its primary motivations, entirely justifiably, are political and geopolitical,” he said. “In the area of higher education, however, restricting the initiative to political and geopolitical considerations would limit the scope of cooperation and lead to distorted frameworks and counterproductive implementation.”It is all the more important since academic interests on the two sides of the Atlantic are “neither identical nor fully aligned,” Matei added. “This is not insurmountable; it simply requires work to articulate the details of this privileged cooperation, including its governance and funding frameworks, as well as its substantive content in education and research.”Related articlesCanada looks to deepen research and education links with the EUZaharieva hopes for a Horizon Europe deal in 2026Canada might participate in European Research Council schemes, for example, which was not on offer in the present Horizon Europe association agreement. But “there would have to be something in it for the EU,” Browne said. “They don’t want to be funding projects outside of the EU where intellectual property is going to sit outside of the EU. There has to be some kind of transfer of knowledge.”But access to funding will not by itself resolve all the practical difficulties of working together, said Björnmalm. “For researchers and students, these include visas and residence arrangements, recognition of qualifications and study periods, and the conditions for pursuing a research career across borders,” he said. “For universities, there is scope for more predictable access to shared laboratories, computing and research data, and stronger support for joint doctoral training and long-term institutional partnerships.”Linda Doyle, provost and president of Trinity College Dublin, said Europe should strive for the “closest possible expression” of this new political alliance. “If Europe is serious about recovering its voice and its place in the world, it needs to be strongly allied with countries who share its values and its vision for a stable, rules-based, peaceful world.”
Diginex Consolidates Group-Wide Expertise and Launches Sustainability Science & Intelligence Initiative to Accelerate Product Innovation and Drive Measurable Client Outcomes
Group-wide activity integrates advisory, regulatory and methodological expertise across Diginex products and solutionsUnder the leadership of new interim CEO, Archana Kotecha, the intention is to turn insight into practical action and ultimately help clients achieve better, measurable outcomes.Johannes Weber named VP of Sustainability Science and Intelligence LONDON, Sept. 24, 2026 (GLOBE NEWSWIRE) -- Diginex Limited (NASDAQ: DGNX) (“Diginex” or the “Company”), a leading provider of Sustainabili
Formulated with authority: Separating science from marketing in vet-formulated products
Vet related claims must go beyond pet food product labels into R&D and formulation.
Rooted in science: Rooted Owl brings science-backed solutions to the pet supplement category
The company offers nine different targeted capsule supplements, along with five hemp-derived products.
KFF Women’s Health Survey Explores How Women Navigate Contraceptive Information
Many reproductive-age women seek health information through online sources, where they may encounter false or misleading information about contraception, according to the 2026 KFF Women’s Health Survey. And an Ohio health department’s new AI policy offers a rare example of a health-specific policy addressing accuracy and public trust.
GTA 6 Datamine Reveals 'The Goodtime State
A mysterious new GTA 6 product has been leaked to be coming to the Rockstar Store called the Vice City Collection.
Puka Nacua Injury Update: Rams WR’s Week 3 Status Revealed
Puka Nacua missed Week 2 due to injury, and it might be a while before we see him on the field. Originally selected in the fifth round of the 2023 NFL Draft, the BYU product quickly became one of the biggest draft steals in recent memory. Developing an immediate connection with quarterback Matthew Stafford, the …
Can Marcus Mariota Keep Washington Commanders' Offense on Track?
Jayden Daniels’ injury leaves Marcus Mariota with more than a starting job. He inherits an offense missing its biggest rushing threat, dealing with injuries along the offensive line and searching for more production from its WR1. Through it all, Mariota must keep Washington’s offense moving.
DERMATOLOGIST-FOUNDED SKINCARE BRAND PREQUEL LAUNCHES SKIN HEALTH ADVISORY BOARD
/PRNewswire/ -- Prequel, the dermatologist-founded skincare brand dedicated to advancing skin health through effective, accessible products and education,...
Science Debunks Cracked Solar Panel Fears
Scientific studies suggest cracked solar panels present little environmental danger, with protective designs limiting chemical exposure and testing showing contamination levels remain below established safety limits.
Australia Condemns ‘Unacceptable’ OpenAI Breach of Government Health Portal
The breach follows a string of incidents involving AI models going rogue.
HSBC plans India equity broking return after 13 years amid IPO boom, sources say
HSBC is re-entering India's equity broking business after an absence of more than a decade, seeking to capitalise on a robust pipeline of share sales and rising demand from wealthy clients for equity market products, two people with direct knowledge of the matter said.
The Beats 360 are essentially true wireless earbuds disguised as headphones.
As confirmed by Beats product manager Jeff Bruksch, the new Beats 360 headphones use a true wireless architecture with each earcup containing its own battery, antenna, and processing components. It allows Beats to “significantly reduce the cabling between the two sides,” according to Bruksch. > Because we don’t have the traditional system including a charging case, we have a cable for power supply and power management between the left and right sides so that you don’t have to charge both sides and the left and right sides power on/off together. Having a cable for power management only explains the lack of audio support through the USB-C.