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Maui’s Deer Crisis: Science, Strife, and Inertia (Part One)
By some estimates, there are nearly as many axis deer as there are people across the three islands of Maui County. Roving herds can wreck a farmerʻs…
Air taxis to connect Texas airports to business hubs
Archer Aviation says its taxis will turn 90 minute drives into 20 minute flights.
Marco Rubio’s Greek Panegyric / Celebration: Political Theory and Praxis
Prologue Translating the ideals of Greek history, politics, democracy, theater, athletics, the Delphi peace vision, philosophy, science, technology,
Los Angeles health authorities report 2nd second rabies-positive raccoon
In a follow-up on the report a rabies-positive raccoon found in Los Angeles County, the first in more than 5 decades, the LA County Department of Public Health is investigating a second rabies-positive raccoon found in the Westlake Village area of Los Angeles County. Public Health has confirmed that the first raccoon was positive for a variant of rabies typically found in bats. Strain testing for the second raccoon is currently pending. The second rabid raccoon was found in a backyard in the vicinity of where the first raccoon was reported and appeared sick and aggressive. No residents or pets were exposed to the raccoon. Two people at a worksite may have been exposed to the raccoon and are receiving recommended follow-up for rabies post-exposure prophylaxis. The World’s Deadliest Viruses Prior to these detections, the last confirmed rabid raccoon in Los Angeles County was detected in 1973, when the skunk variant (strain) of rabies was still present in the County. That strain has not been detected in Los Angeles County since 1979. In 2014, a skunk infected with the bat variant of rabies was detected in Long Beach. “The detection of rabies in another raccoon is an important reminder to never touch, handle, or feed any wild animals, even when they appear healthy,” said Muntu Davis, MD, MPH, Los Angeles County Health Officer. “Always keep a safe distance from wildlife and contact your local animal control if you encounter an animal that appears to be sick, injured, or behaving unusually. It is also critical to ensure your pets are up to date on rabies vaccination so they are protected before any potential exposure. Keeping your pets vaccinated is one of the most important steps you can take to protect your entire family.” Outbreak News Today is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
Health spending on Southampton taxis surges by 75%
It comes as the department looks to review spending for off-island hospital treatment.
ARK Invest Bets One Business Can Lift Tesla Stock to $4,400
ARK Invest’s open-source model values Tesla at about $4,400 per share in 2031, with robotaxis at 80% of enterprise value.
Eye Microbiome: How Bacteria May Influence Eye Health and Disease
The ocular surface hosts a low-abundance microbial community that may help regulate immune defenses, while changes in its composition have been associated with inflammatory and infectious eye diseases. Research into the gut-eye axis and microbiome-targeted therapies suggests possible diagnostic and treatment applications, but the underlying mechanisms, causal relationships, and clinical effectiveness remain uncertain.
Earth Shifted Quickly On Its Axis Four Times In Last 320 Million Years, Including When Dinosaurs Reigned
Frankly, it’s surprising the dinosaurs didn’t get dizzy.
Scientists find evidence for several Earth axis shifts during the age of dinosaurs
Sea-level changes offer an independent record of dramatic Jurassic and Cretaceous episodes when the solid Earth may have reoriented.
Is 50 the new 60?
Subscribe TL;DR: Younger generations are showing signs of worse health compared to earlier-born cohorts at the same age This backward “drift” is showing up both in mortality risk and chronic disease Worsening trends in obesity and diabetes are the most consistent signals Taking the long view, we’ve made astonishing gains in health and life expectancy in the last century. Global average life expectancy has more than doubled from 32 years in 1900 to 73 years in 2024. (But don’t forget, there were still old people when life expectancy was 32). As people lived longer, they also generally lived healthier along the way. It turns out that avoiding things that can kill you early, like malnutrition and lots of childhood infections, also keeps you healthier later in life. In a classic 2004 paper, Finch and Crimmins proposed that cohorts of children who benefited from fewer early life infections had less lifetime exposure to inflammation and cardiovascular disease later in life, accelerating mortality improvements at older ages. Poor nutrition in the womb has also been linked to a higher risk of later chronic disease. The upshot is that improvements in childhood health can pay dividends many decades later. The combination of better living conditions (nutrition, sanitation) and medical advances (antibiotics, vaccines, blood pressure meds, etc) meant that people’s healthy lifespan generally expanded, even as they lived longer. Aging researchers call this best-case scenario “compression of morbidity”—meaning we delay the onset of disease and disability even faster than the years of life we are adding. During my 20+ year research career, we could generally bank on the idea that younger generations would not only live longer but also keep getting healthier along the way. “60 is the new 50” as they say… Enter “Generational Health Drift” Sadly, this expectation of steady progress may be changing. You’ve probably heard that US life expectancy gains have slowed to a crawl in the past couple of decades. Mortality improvements are also slowing (though less dramatically) in many other high-income countries (you can read more about that in a review paper I wrote here). Mortality is a very blunt health measure, but it is often a good barometer for the broader population health trends happening underneath. And we are now seeing that younger generations may be in worse health at similar ages compared to earlier born cohorts. My collaborator Prof. George Ploubidis at University College London coined this worsening health in more recently born cohorts “generational health drift.” “Generational health drift” is bad news on multiple fronts. Most obviously, we don’t want our health progress to go backward. But the timing is also bad, since our populations are aging. In demographic terms, “population aging” means that the proportion of the population at older ages (i.e >65 years) is increasing. Fun demography fact: Current population aging is not due to the recent declines in the birth rates making the news, but declines in fertility decades ago, after the “baby boom.” As baby boomers reach older ages, the smaller cohorts behind them mean the percentage of older adults will increase. For example, the share of the population age 65 and older in the US increased from 12.4% in 2004 to 18.0% in 2024. This story of population aging was written long ago. Many worry that population aging will put pressure on health care and pension systems. But if people reach older ages in better health than in years past, those fiscal pressures would be less dire than projected. Healthy older people can also continue to contribute to society in many valuable ways, including paid work, caregiving, community service….even high political office 🤷. On the flip side, if younger generations reach retirement age in worse health and with more disabling conditions, this could magnify the societal challenge of population aging. Evidence for worsening generational health A recent paper that I LOVED in the Proceedings of the National Academy of Sciences by Dr. Leah Abrams and colleagues examined which birth cohorts (aka generations) were behind worsening US mortality. Behold the Lexis diagram (cue swooning demographers). Calendar time is on the x-axis, age on the y-axis. Birth cohorts can be followed over time as they age on the diagonal lines moving up and to the right. This figure plots the year-on-year % change in all-cause mortality at a given age. Green shading indicates mortality improvements over time, white is stagnation, and gray shading indicates worsening mortality. Following the diagonal line for those born in 1950, you can see a noticeable shift from green to gray that follows this cohort for most of their lives. This gray shading shows generally worsening mortality for the 1950 to 1959 birth cohorts compared to their predecessors across all ages. Concerningly for my GenX and elder millennial peeps, there was also a deterioration in mortality for birth cohorts born in the 1970s and 1980s, visible as dark gray areas at ages 30 to 45 during the 2010s. While some of these mortality changes reflect specific shocks such as the opioid epidemic, most deaths still occur from major causes of death such as cardiovascular disease and cancer. For cancer, the gray in the top left corner of the figure below reflects the legacies of smoking for older cohorts, followed by a period of green with improvements in cancer mortality as smoking rates declined. But the white/gray shading in the bottom right corner highlights a stagnation and reversal of the cancer trends, with cohorts born around 1970 to 1985 experiencing worsening cancer mortality. This deterioration was most noticeable for colon cancer mortality, possibly linked to obesity or dietary factors. Not just dying more, but less healthy along the way. A recent paper by Dr. Laura Gimeno of University College London (of which I am a co-author), found evidence that more recently born cohorts in Great Britain have stagnating or worsening health. A stylized picture of what“generational health drift” might look like: The review paper found: Rates of childhood overweight and obesity were highest among Gen Z. Rates of diabetes in the 40s almost doubled from 3.1% among the Baby Boomers to 5.9% in Generation X. Gen Z reported higher rates of poor mental health in adolescence compared to earlier-born groups. These UK results are consistent with studies showing worsening health across generations in the US as well. A 2021 US study found that more recently born cohorts had worse biological markers (like blood pressure and blood sugar) than earlier generations at the same age. A separate 2022 study of Americans aged 50 and over found that more recently born generations had a higher number of chronic diseases, with younger age of disease onset. A 2024 Lancet paper found that in the US, women born in 1945 had 33% obesity prevalence at age 50, rising to 48.2% for women born in 1970 turning 50. So what’s going on, and can we turn it around? We don’t have a definitive answer for what’s causing the deteriorating health of younger cohorts, but circumstantial evidence points to worsening trends in obesity and diabetes in both the US and UK. Remember that cohort trends reflect lagged effects of early environments, and younger generations have faced both earlier onset and more severe obesity across their lifetimes. Despite these very concerning trends, the future is not set in stone. We’ve reversed poor generational health trends before: drops in smoking are a major reason cancer and heart disease deaths fell so dramatically in recent decades. GLP-1 drugs may finally turn the tide against rising rates of obesity and diabetes, though it is still early days. But things could also get worse…for example from a return to higher levels of childhood infectious diseases that can have a lasting impact on health. See for example: [ ](https://jenndowd.substack.com/p/dont-you-forget-about-measles-the) [ Don’t You Forget About Me(asles): The Virus That Erases Immune Memory ](https://jenndowd.substack.com/p/dont-you-forget-about-measles-the) Jenn Dowd, PhD · March 24, 2025 [ Read full story ](https://jenndowd.substack.com/p/dont-you-forget-about-measles-the) Even as an optimist, emerging data on the “generational health drift” has my full attention. For most of my research career, we took it for granted that each generation would be healthier than the last. But if present trends continue, **50 could be the new 60….**and Gen Z celebrities will soon look older than Paul Rudd :). Stay well, Jenn Share the Health! If you found this post useful, please share it with a friend. Share
An Epic View of the Seasons
The tilt in Earth's axis of rotation makes the apparent position of continents shift with the seasons in imagery from a NASA camera in deep space.
Rabies confirmed in Brown County cow. MDH recommends shots for 9 people who were exposed
MDH recommended nine people obtain rabies post-exposure prophylaxis as they may have been exposed to saliva from the infected animal. The disease is extremely dangerous and life-threatening to both humans and animals.
City of Durango will move almost 30 employees to Axis Health building ahead of City Hall construction
Community Development and Engineering building faces demolition
Two years after its rocky launch, Civilization 7's first paid expansion Earthrise is on its way - but first comes the atomic age
As the legendary Civilization series celebrates its 35th anniversary, developer Firaxis has unveiled a host of new updates coming to Civilization 7.
Sid Meier's Civilization VII adds Arc of Tomorrow update and Earthrise expansion
At PAX West, in celebration of the franchise’s 35th anniversary, 2K and Firaxis Games announced new updates for Sid Meier's Civilization VII.
‘Unfinished business’: Travis Kalanick revisits robotaxis with new start-up
Atoms gears up for hiring spree and could link with Uber, the company he was ousted from almost a decade ago
Sid Meier’s Civilization VII major update ‘Arc of Tomorrow’ and paid expansion ‘Earthrise’ announced
Publisher 2K and developer Firaxis Games have announced the major update “Arc of Tomorrow,” paid expansion “Earthrise” and version 1.5.0 update for Sid Meier’s Civiliz…
Tesla's Cybercab launch draws US regulator probe
Tesla is facing a NHTSA audit inquiry into its self-certification for the Cybercab hours after deploying a small number of the robotaxis in Austin.
Self-flying air taxis and drones: Boeing sells key aviation technology businesses to Archer
Boeing is selling Wisk, SkyGrid and Insitu to Archer in a major deal combining autonomous aircraft, drones, airspace technology and AI.
Praxis Profit launches new executive advisory service to help Tahoe business owners strategically maximize profitability
SOUTH LAKE TAHOE, Calif. – Praxis Profit, a boutique strategic chief financial officer advisory firm, announced today its full-suite of financial decision-making consultancy service including cash flow visibility, margin protection and executive level financial decision-making...
2026 MLB trade deadline bold predictions: Tigers send Tarik Skubal to NL contender; Yankees, Cubs get busy
Mike Axisa uses his crystal ball to predict the biggest moves (and non-moves) before the Aug. 3 deadline
Stereotaxis completes major cardiology tech acquisition
The deal, first announced in April, includes an upfront payment of $20 million and up to an additional $25 million based on certain milestones.
Waymo robotaxis have easter eggs for the July 4 celebration
Waymo is tweaking the in-car experience to get into the festive spirit for the Fourth of July.
The Sims 4 Update: Official Patch Notes (June 30th, 2026)
Maxis and EA have just released a brand new The Sims 4 Update across all officially supported platforms. Including PC, Mac, Xbox and Playstation platforms.
Efzimfotase alfa demonstrated improvements in bone health in treatment-naïve pediatric patients with hypophosphatasia achieving median difference of 1.67 vs placebo in RGI-C Score at week 25 in MULBERRY Phase III trial
Positive results from the MULBERRY Phase III trial showed that efzimfotase alfa (ALXN1850), an investigational enzyme replacement therapy, demonstrated a statistically significant and clinically meaningful improvement in bone health in children (2 to
Waymo recalls 3,871 robotaxis over software issue
This is Waymo's second recall this year, following a May recall tied to one of its robotaxis entering a flooded roadway.
Waymo recalls nearly 4,000 robotaxis after cars enter freeway work zones
Waymo has paused freeway robotaxi operations and recalled nearly 4,000 vehicles after more than a dozen incidents involving autonomous cars entering closed construction zones.
Report: Redundancies at Microsoft owned Zenimax have begun
It is reported that redundancies have begun at Zenimax, the umbrella company that includes Bethesda, ID, Arkane and others.
As Civilization 7's lengthy revitalisation continues, much-requested hotseat multiplayer is one of several new features arriving next week
Almost 18 months after Civilization 7's bumpy launch, Firaxis' slow and steady course correction is set to continue with the launch of another major update.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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Health Alert: U.S. Embassy – June 2, 2026 – Thailand Enhanced Ebola Screening - U.S. Embassy & Consulate in Thailand
Health Alert: U.S. Embassy – June 2, 2026 – Thailand Enhanced Ebola Screening Ebola Screening Location: International Ports of Entry, Thailand Event: Thailand has implemented Ebola disease-related screening and quarantine measures for travelers who stayed in or transited through Ebola disease-affected countries, including the Democratic Republic of the Congo and Uganda. Effective May 27, 2026, travelers from the Democratic Republic of the Congo, Uganda, or other neighboring countries with cross-border transmission will be screened by communicable disease control officers at the international port of entry in Thailand and could be subject to mandatory quarantine or self-isolation for at least 21 days. Failure to comply with quarantine or isolation orders may result in fines, imprisonment, or both under Thai law. Thailand currently has no confirmed Ebola cases but has implemented these measures following the World Health Organization’s Public Health Emergency declaration. For more information, contact Thailand’s Department of Disease Control hotline at 1422. Actions to Take: Follow directions from Thai authorities. Review Consular Information for Americans Regarding the Ebola Outbreak Stay up to date with the latest CDC Travel Health Notices Review the CDC’s Ebola Disease: Current Situationand Ebola Disease Basics Prepare or update your personal emergency plan. Review the Traveler’s Checklist. If at risk for Ebola disease, alert your healthcare provider if you are experiencing symptoms consistent with Ebola disease to receive guidance prior to presenting for care. Continue to take malaria prophylaxis if recommended, as the symptoms of malaria can mimic symptoms of Ebola disease, leading to preventable health scares. Monitor your health for 21 days following travel if you traveled to an area experiencing an Ebola disease outbreak. If you are a U.S. citizen or national planning to travel to the United States, contact your airline to confirm your flight and route. Enroll and update your information in the Smart Traveler Enrollment Program (STEP). Follow the Department of State on Facebook and X . Visit state.gov and the U.S. Embassy in Thailand website. Assistance: U.S. Embassy Bangkok Phone: +66 02-205-4000 Email: ACSBKK@state.gov https://th.usembassy.gov/ State Department – Consular Affairs 888-407-4747 or 202-501-4444 Thailand Country Information Enroll in Smart Traveler Enrollment Program (STEP) to receive security updates
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Health Alert: U.S. Embassy in Rwanda (May 23, 2026) - U.S. Embassy in Rwanda
Health Alert: U.S. Embassy in Rwanda (May 23, 2026) Health Alert: U.S. Embassy in Rwanda (May 23, 2026) Location: Rwanda, countrywide Event: Entry and Exit Requirements Due to the Ebola outbreak, Rwanda has implemented new entry and exit requirements. On May 22, 2026, the Ministry of Health of Rwanda announced that all foreign nationals who have traveled to, or transited through, the Democratic Republic of the Congo (DRC) within 30 days of their travel to Rwanda will be denied entry. Rwandan nationals and foreign residents with valid proof of residency in Rwanda can enter and are subject to mandatory quarantine procedures. Travel to the U.S. Review the U.S. Centers for Disease Control and Prevention (CDC) information on what travelers need to know about returning to the United States from DRC, Uganda, and South Sudan. Actions to Take: Do not travel to the Democratic Republic of Congo (DRC). Monitor the Ministry of Health of Rwanda webpage for local updates. If you are planning to travel to the United States, contact your airline to confirm your flight and route. Review the CDC webpage on the Ebola Current Situation. Review Consular Information for Americans Regarding the Ebola Outbreak. Review the CBP webpage for information on entry restrictions Notify friends and family of your safety. Have a plan to depart in case of emergency. Have travel documents up to date and easily accessible. Review the CDC Travelers’ Health Page for Rwanda. Continue to take malaria prophylaxis as recommended, as the symptoms of malaria can mimic symptoms of Ebola, leading to preventable health scares. Monitor your health for 21 days following travel in an area with an Ebola outbreak. If at risk for Ebola, alert your healthcare provider if you are experiencing symptoms consistent with Ebola to receive guidance prior to presenting for care. Review the Department of State’s Rwanda Travel Advisory for general health information. Refer to the U.S. Embassy’s list of medical providers. Check with your travel insurance provider about medical evacuation options should you fall ill while overseas. Enroll in the Smart Traveler Enrollment Program (STEP) to receive safety and security updates. Assistance: U.S. Embassy Kigali, Rwanda 30 KG 7 Avenue (Kacyiru) +250-252-596-400 ACSKigali@state.gov https://rw.usembassy.gov State Department – Consular Affairs 888-407-4747 or 202-501-4444 Rwanda Country Information Enroll in Smart Traveler Enrollment Program (STEP) to receive security updates. Follow us on Facebook and X
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Your Thymus and Your Healthspan
Our thymus gland plays a central role in the development or our immune system, specifically for supporting T cell development (how these cells got their name, maturation and differentiation in the thymus) and discriminating between self and foreign, non-self antigen proteins with production of dendritic cells. As we age, our thymus gland shrinks—the process known as involution—with progressive change from spongy to fatty tissue, with loss of functionality. But this process, with respect to timeline and extent, markedly varies from one person to the next. And to make things even more complicated, our thymus gland anatomy and precise location in the chest also is highly variable. So the famous Frank Netter diagrams from the 1960s (such as at left below) don’t capture the remarkable heterogeneity that a random set of 12 chest CT scans (below at right). What I consider as 2 landmark papers in Nature this week (here and here) used AI to quantify health of the thymus in 2 large cohorts, and then correlate the metric to a broad array of health outcomes. In this edition of Ground Truths, I’m going to cover three questions: (1) How was thymus health determined by AI?; (2) How is thymus health linked to key clinical outcomes? and (3) Are there ways we can promote a healthy (aka rejuvenate) thymus gland in our later years? Subscribe 1. How was thymus health determined by AI? This was accomplished by extensive work developing and validating an AI pipeline for 2 stages, the first for localization and segmentation of the thymus bed, and the second to quantify a digital marker, termed the thymic health score. There’s a lot to this algorithmic development, so I won’t go into all the details, but just provide a rudimentary outline of what was done. The 1st stage used supervised learning with 2 radiologists reviewing 2,461 chest CT scans. That work trained a 3D U-Net model to automatically identify the thymic bed’s 3D cropped region using center of mass coordinates, which reached 99.8% accuracy. The 2nd stage used a foundation model that was pre-trained with SwAV (which stands for Swapping Assignment between multiple Views), a self-supervised model, that generated a high-dimensional thymus representation of 4,096 features. That compares to the radiology reductionist and subjective scoring of 0 to 3 where 0 means the thymus is fully degenerated and fatty, and 3 is considered dense, intact glandular soft tissue. Notably, the self-supervised learning (SSL) performance was superior to supervised (AUC ~0.75 vs 0.55, respectively) reflecting the shallowness of the 0-3 classifier vs SSL’s holistic, self-taught AI. The thymic health score ranged from 0 to 100, with the highest number indexed to fully preserved thymic health. The algorithmic work extended to explainability with both Shapely value distribution, meaning the model was holistic not relying on any “magic” pixel, and occlusion sensitivity, demonstrating the model’s performance was not affected by ribs, sternum, lung tissue, but rather focused on the thymic bed directly. Below are a few saliency maps from the occlusion sensitivity that indicate the thymic bed focus, not affected by neighboring structures, using the jet color scale. Now the AI was ready for processing ~25,000 CT scans, each over 30 MB files, from the 2 large participant cohorts to provide a thymic health score, it did so in less than 14 hours, which is less than 2 seconds per scan! Share 2. How is thymus health linked to key clinical outcomes? The two cohorts were the National Lung Screening Trial, NLST (N=25,031) and the Framingham Heart Study, FHS (N=2,581) each with baseline demographics and long term follow up of >12 years for health outcomes. From the NSLT, you can see below that increased age and body-mass index were correlated to reduced thymic health. And, overall, men had reduced thymic health scores compared with women. There are a lot of graphs in the paper for outcomes, for both the NLST and FHS cohorts. To simplify the major outcomes, below is a composite Figure with striking reduction of all-cause mortality and for the different causes of death. The results were consistent between the 2 cohorts. For example, the cardiovascular mortality hazard ratio average was 0.57 in NLST and 0.38 in FHS (weighted to be 0.53 for the aggregate). The reduction of mortality also extended to digestive diseases and pulmonary disease (data not shown below). Lung cancer incidence was reduced by 36% for high vs low thymic health (Figure below, with a panel -incidence and b panel-mortality, adjusted for age, sex, BMI, smoking status). Notably, there was a smoker’s paradox: lower incidence and improved survival for lung cancer in smokers who had a high thymus health score. Smoking was associated with lower thymic scores whereas alcohol was not. Higher thymic health was linked to higher HDL cholesterol, lower triglycerides, lower fasting blood glucose, and lower systolic and diastolic blood pressure. Inflammation biomarkers, such as C-reactive protein and interleukin-6, were elevated in the people with lower thymic health scores. In their second paper, the same team looked at the relationship between thymic score and outcomes for 3,476 patients receiving cancer immunotherapy. The non-small cell lung cancer progression-free survival was reduced in patients with low thymic health score. A parallel relationship for survival was seen for other types of cancer including melanoma, breast, and kidney with a 44% lower risk among high thymic scores (Figure). A similar pattern was seen with different immune checkpoint inhibitors. The thymus health score outperformed programmed death ligand-1 (PD-L1)and tumor mutation burden (TMB) assay of the tumor and was an independent prognostic marker of progression-free survival. In this dataset, a direct connect with thymus score and adaptive immune function was noted with a correlation before cancer treatment for both T-cell diversity and thymus T-cell production (a metric known as T cell receptor excision circles). Thymus Removal Study There is a highly relevant citation about thymus function before moving onto ways to rejuvenate it. In 2023, a very important study of thymus removal during cardiothoracic surgery was published, with 1146 patients undergoing thymus removal vs 1146 matched controls (mean age 55 years). The adverse outcomes for thymus removal were striking, with a 2.9 higher risk of all-cause mortality and doubling of cancer incidence, 1.5 fold increase in cancer mortality, and 1.5-fold increase in autoimmune diseases. The immune function showed marked compromise after thymus removal, as reflected by CD4+ and CD8+ T cells (Figure below) Share Ground Truths 3. Are there ways we can promote a healthy (aka rejuvenate) thymus gland in our later years? In recent months we’ve learned a lot about the process of thymus involution and the pathways by which this may be modulated. Thymus involution is primarily due to loss to thymus epithelial cells (TECs) and there are 2 subtypes with different functions: the cortical, responsible for positive selection of T cells, and the medullary, for negative selection. When adipose tissue infiltrates the thymus, thymic adipocytes are pro-inflammatory, knocking out T-cell output. Likewise, systemic inflammation, or “inflammaging,” from smoking, obesity, and chronic stress promote thymic adipocytes. Now, from preclinical studies, we know about key pathways that account for these processes. Historically, back in 2014, FOXN1 was recognized as a single master transcription factor essential for TEC function, with studies in mice with forced FOXN1 upregulation leading to thymus regeneration. That laid the foundation for potential regrowth of quiescent thymus cells. It took awhile to find pathways to accomplish this goal and to even refute its role as the master regulator. The Liver-Thymus Axis Feng Zhang and his team recently showed that injection of an mRNA vaccine to the liver encoding DLL1, IL-7 and FLT3-L in combination, factors known to support thymopoiesis (Figure), successfully enhanced immune function in aged mice. However, the effect was transient. The FGF21 Story Two reports in 2025 addressed the thymus gland’s production of FGF21, a growth factor (fibroblast growth factor 21) and its control of thymus involution. This growth factor is also produced by the liver, but it doesn’t have impact on the thymus in aged rodent models. In contrast, The liver’s hepatocyte growth factor (HGF) has been shown to reverse senescent TEC structural changes. Growth hormone stimulates production of insulin growth factor-1 (IGF-1) in the liver and the thymus. Two small studies in human participants (TRIIM, for Thymus Regeneration, Immunorestoration, and Insulin Mitigation) of 6 and 50 people, respectively, treated with combined human growth hormone, metformin and DHEA, suggested the potential of slowing epigenetic aging and improving thymus mass and function. But the combination of drugs, small sample, and lack of controls make conclusions murky. Increased thymus FGF21 led to increased CD8 T cells in old mice and extended healthspan and improved physical performance. Building on the previous FOXN1 data, ablation of β-klotho, the obligatory co-receptor for FOXN1, accelerated thymic aging. The benefit to FGF21 was confirmed in a companion paper using an FGF21 knock-in mouse model showing thymus enlargement and increased TECs throughout the lifespan. (schematic Figure below). The accompanying editorial for these 2 papers speculated: “The proposed link between age-associated thymus involution and organismal aging is intriguing, and suggests we might seek to achieve systemic rejuvenation by counteracting thymic involution.” Other Factors Lessons from the Axolotl (Mexican Salamander) In an elegant set of experiments of the axolotl (Figure), known for its complete thymus regeneration after total surgical removal, mediators were identified. Surprisingly FOXN1 was dispensable. But midkine, a growth factor, appeared to be the driver, the initiator of thymus cell growth, survival, and repair. Other components that contributed were Postn+ (periostin-expressing mesenchymal niches) and Ccl19, a chemokine protein from the bloodstream. RANK and RANKL RANK (receptor activator of nuclear factor κB its ligand (RANKL) have been considered key regulators of medullary TECs. In a study of both aged mice and human thymus cell cultures, their key role was confirmed, with multiple benefits of resorting TEC function, recruitment of progenitor cells, and T cell development. Subscribe Summing Up This body of work strongly supports the health of the thymus gland as a critical regulator of human healthspan, not just a correlate or link. The new landmark studies are reinforced by the regenerative biology experimental models that have shown, via an array of mediators, that healthspan of aged mice is at least in part dependent on thymus gland function and its critical role for maintaining adaptive immunity. It sure seems that we’d be better off having an immune reservoir of naive T cells instead of a profile in older adults of exhausted, low quality, memory T cells, with a senescent phenotype. It is striking that we ignored the importance of the thymus gland for many decades. A wake-up call was the results of the thymectomy matched control study reviewed here, with the opposite of high thymic health score improved health outcomes. The convergence of AI and healthspan here is notable. The exceptional and laborious work for developing and validating (no less explaining) the AI to quantify thymus health set the foundation for probing the connect the major health outcomes in two cohorts with extensive follow-up. We’ve never had a way to meaningfully quantify the thymus gland before, so this represents important leverage of supervised, self-supervised, and transformer models. The study wouldn’t have been possible without AI. And it begs the question as to whether there are ways we can maintain our thymus at a high health score. But it’s not so simple to rejuvenate our thymus. There are multiple risks including the induction of autoimmunity, increasing the risk of cancer, and inducing a pro-inflammatory state. For example, factors that increase TEC proliferation could compromise the medulllary negative selection process and leak out auto-reactive (self-attacking) T cells. Thymic cells could be induced to proliferate, but we know, for example, that growth hormone and IGF-1 are associated with an increase risk of cancer. If thymus rejuvenation doesn’t clear out the accumulated senescent cells in older adults, then inflammation within the gland could block the production of TECs. Keeping these risks in mind, we now have identified many ways to keep our thymus healthy as we age that undoubtedly will be tested in clinical trials going forward. Ultimately, the benefit-to-risk tradeoffs will be defined. In the meantime, we have desperately needed an immunome. As I’ve stressed in multiple prior Ground Truths, we have no test in the clinic to assess a patient’s immune status! It was very encouraging for me to get an email from Hugo Aerts, the senior author of the landmark papers in the days after they were published: “I also wanted to say that your Substack on “Why We Need an Immunome” was inspiring for this work. We found it a very compelling perspective and greatly enjoyed reading it.” Just having an assessment of a person’s immune status via a chest CT scan, with millions of these performed per year, might help in guiding the right immunotherapy for cancer (e.g. more intensive, combinations for those with low thymic health scores) and help define people who are increased risk for age-related diseases of cancer, cardiovascular, and neurodegenerative. The main theme of Super Agers is that we now have many layers of data (genetics, proteins, biomarkers, organ clocks that can be integrated via multimodal AI) for us to define a person’s specific risk decades before one of these age-related diseases leads to symptoms, enabling prevention. From the new studies this week, we can add thymus health score as yet another way to understand a person’s risk, a window into their adaptive immune system and healthspan. And perhaps someday we will be able to safely rejuvenate the thymus, or maintain its health through one’s life, and use the thymus health score to monitor. NB: I wrote this post (No A.I.) A Quick Poll Loading... ********************************************************************* Thanks to Ground Truths subscribers (now > 200,000) from every US state and 212 countries. Your subscription to these free essays and podcasts makes my work in putting them together worthwhile. Please join! If you found this interesting PLEASE share it! Share Ground Truths Paid subscriptions are voluntary and all proceeds from them go to support Scripps Research. They do allow for posting comments and questions, which I do my best to respond to. Please don’t hesitate to post comments and give me feedback. Let me know topics that you would like to see covered. Leave a comment Many thanks to those who have contributed—they have greatly helped fund our summer internship programs for the past two years. It enabled us to accept and support 47 summer interns in 2025! We aim to accept even more of the several thousand who will apply for summer 2026.
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