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Triad Business Bank renews criticism of M&F Bank deal
Greensboro’s Triad Business Bank launched more criticism of the plan by Durham-based M&F Bancorp, to merge into a larger African-American-owned peer, Optus Financial of Columbia, South Carolina. M&F has rebuffed offers since August from Triad, which hopes to derail M&F’s combination with Optus in a transaction valued at about $105 million. M&F plans a Nov. […]
Inside the Orlando Magic's Opening Night Loss
The Orlando Magic received a big performance from Paolo Banchero, but it was not enough to secure a win at home to open the 2026-27 NBA season.
This week in Santa Cruz County business: Cruz Foam ceases operations; West Coast Community Bank celebrates Nasdaq listing
Santa Cruz-based Cruz Foam, which developed a biodegradable packaging made from shrimp shells and other natural materials, has closed and sold off its intellectual property, Jessica M. Pasko reports in her weekly look at local business. Meanwhile, Santa Cruz-based West Coast Community Bancorp has moved its stock listing to the Nasdaq Stock Market, a milestone executives say is more than two decades in the making.
Venomous primate thought lost to science for nearly a century turns up in gardens and on roads across Indonesia
Local wildlife rescue center publishes data in a new paper revealing the critically endangered Bangka slow loris still survives across the Indonesian island of Bangka
Regional Banks Put AI Into Core Operations as Business Lending Grows
Third-quarter results from PNC, U.S. Bancorp, Truist, Fifth Third, Regions and KeyCorp show that regional banks are putting artificial intelligence into
A Deep-Sea Mining Trial Rapidly Threw The Seafloor Ecosystem Off Kilter
Even short-term disturbance has significant impacts.
Quarterly income up almost 5% for Centennial Bank parent company
Conway-based Home BancShares on Wednesday (Oct. 14) reported third-quarter net income of $129.451 million, up 4.7% compared with the same period in 2025. The per share earnings of 65 cents...
Chinatown businesses say teen fights, robberies are hurting business as crime rises
D.C. police seek two suspects after a man was robbed of designer shoes and a phone in Chinatown. Nearby workers describe recurring disturbances.
Jase Richardson Reflects on Orlando Magic's 'Sloppy' Preseason Loss
Orlando’s sloppy turnover troubles and Paolo Banchero’s shooting slump fueled a double-digit loss, prompting Jase Richardson to demand more physicality and poise before the regular season begins.
Paolo Banchero Recaps 'Pretty Good' Offensive Performance
Orlando's young star breaks down the team's lethal pick-and-roll chemistry and a high-assist night that signals a shift toward a more dynamic, unselfish offensive identity this season.
Houston police responded to a man in a mental health crisis. ICE arrested him
Houston Public Media obtained records showing interactions between HPD and ICE during a mental health crisis, suicide attempt and domestic disturbances.
NYCC apologizes for ‘repeated disturbance’ during panel, actor slams fan for ‘disrespecting’ his castmates (exclusive)
“I will always step in to protect that space,” Rogers tells EW, while NYCC producer ReedPop says it’s “taking steps to ensure any future incidents are addressed in a swifter manner.”
Vivian Kobusingye Birchall: The People Behind the Global Health Catalyst Summit
Vivian Kobusingye Birchall: The People Behind the Global Health Catalyst Summit / Augustin Bancalari, cancer care, Cancer research, Gavriel Ngwa, Geminai LLC,
Suspect at large after man stabbed outside Northeast Side restaurant, police say
San Antonio police say a disturbance outside a business escalated into a stabbing Friday night. The victim was hospitalized as the suspect fled, briefly reentered the building, and remains at large.
Johnson & Johnson survey finds women not connecting menopause to eye health changes
Hot flashes, mood and sleep disturbances are common themes for menopause: But vision changes are not as well recognized on the list of common symptoms. | Hot flashes, mood and sleep disturbances are common themes for menopause: But vision changes are not one that makes the list of common symptoms. Now, J&J is looking to highlight this often-overlooked issue.
Paolo Banchero is Set to Lead With Vengeance
Fueled by a bitter playoff exit, Orlando’s cornerstone demands collective urgency and peak efficiency to transform the Magic from first-round mainstays into legitimate Eastern Conference powerhouses.
Why Paolo Banchero is Ready to 'Dominate Every Single Night'
Armed with elite conditioning and a refined interior presence, Orlando’s cornerstone enters his third season hunting consistency and a superstar leap to lead the Magic through the East.
Now an elder statesman, former Gov. Gray Davis surveys his career in a major Berkeley project
After 17 lengthy recording sessions and more than a decade of review and revision, Davis and the Oral History Center at Bancroft Library are releasing their monumental history of a career that help shape modern California.
Why Paolo Banchero Needs Massive Leap Into Superstardom
Orlando must shatter a cycle of first-round exits, demanding that their cornerstone hunter trades jump-shot settling for interior dominance and elite efficiency to join the league's elite.
Paolo Banchero at the table: Banchero said he was …
Paolo Banchero at the table: Banchero said he was …
Valley National to acquire Bluevine for $340M
Valley National Bancorp announced its plan to acquire Bluevine, a digital banking platform for small businesses, for $340 million. The acquisition aims to strengthen Valley's funding base, expand its small-business offerings, and accelerate its artificial intelligence capabilities to enhance its position in the digital banking sector.
Valley National Bancorp to Acquire Bluevine Inc., Accelerating Its Digital Small Business Growth Strategy and Meaningfully Enhancing Its Core Funding Capabilities
NEW YORK, N.Y. and JERSEY CITY, N.J., Sept. 28, 2026 (GLOBE NEWSWIRE) -- Valley National Bancorp (“Valley”) (NASDAQ: VLY) and Bluevine Inc. (“Bluevine”) announced today that they have entered into a definitive agreement whereby Valley will acquire Bluevine, a leading nationwide digital banking platform for small businesses. The acquisition directly aligns with Valley’s stated strategic priorities of enhancing its funding base, expanding its small business franchise, and accelerating its digital
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Parliamentarians representing 16 countries from across the Asia-Pacific region concluded the Ninth Meeting of the Asia-Pacific Parliamentarian Forum on Global Health (APPFGH) today, reaffirming their key role in advancing universal health coverage (UHC) amid the risks and opportunities posed by AI and climate change. In adopting the Phnom Penh Communiqué, parliamentarians urged fellow legislators regionwide to strengthen sustainable financing for UHC to widen access to health for all, including the most vulnerable populations; promote responsible governance of AI amid ethical concerns over this fast-evolving technology; and build climate-resilient health systems to anticipate and respond to mounting pressures ranging from rising sea levels in coastal areas to air pollution and other environmental degradation.The National Assembly of Cambodia, with support from Cambodia’s Ministry of Health and the World Health Organization (WHO), hosted the Forum in Phnom Penh from 11 to 13 August 2026 – the first time the Forum has convened in a Mekong country.Parliamentarians urge action to close gaps in accessIn the Communiqué, parliamentarians recognized that at-risk and marginalized groups are the ones most severely affected by gaps in access to health services. These groups include people living in poverty, women and children, persons with disabilities, older people, migrants, refugees, and those in rural, remote or island communities. The Communiqué urges fellow parliamentarians and policy-makers to advocate for laws and policies that support sustainable financing to protect people from financial hardship, with a focus on primary health care, prevention and equity. "The Communiqué is a call to action. It sets out ambitious, concrete measures that deliver meaningful impact on the ground. We are all accountable for advancing universal health coverage and translating our commitments into tangible results. Cambodia is fully committed to advancing UHC, including the promotion of ‘healthy people, prosperous country’ campaign,” said Samdech Maha Rathsapheathika Thipadei Khuon Sudary, President of the National Assembly of the Kingdom of Cambodia.His Excellency Professor Chheang Ra, Minister of Health of the Kingdom of Cambodia, highlighted the need for collaboration beyond the health sector. “Universal health coverage cannot be achieved by the Ministry of Health alone. It requires support, particularly from parliamentarians, across political, legislative, financial, social protection, education, infrastructure, and environmental domains. While each country follows its own path, one factor is universally critical for success: strong governance and leadership. We all believe in this principle, and in our respective political roles, we remain committed to strengthening these key success factors to ensure that no one is left behind.”Promoting responsible AI adoption Parliamentarians acknowledged that, while AI has already demonstrated its ability to improve access to health services and support delivery, careful and ethical governance is necessary to safeguard quality, safety, privacy and public trust. This underscores the importance of parliamentarians in promoting legal and regulatory frameworks addressing liability, records ownership and data governance, while embracing innovation that protects ethical practice.“Without strong governance, safeguards for privacy and data security, sustainable financing, and attention to those most at risk of exclusion, new technologies may widen existing gaps instead of closing them. This is why parliamentarians matter. We pass laws. We approve budgets. We scrutinize government action. We represent communities. We can ask whether health services are reaching rural, remote, ageing, poor, and marginalized populations. We can ask whether innovation is being guided by equity, evidence, and ethics,” said Hon. Man Hee Lee, President of the Asia-Pacific Parliamentarian Forum on Global Health.Building climate-resilient health systemsParliamentarians also reiterated that the climate crisis is a direct threat to people’s health and to achieving UHC more broadly, deepening the same gaps in access already faced by at-risk and marginalized communities. They recognized the need for WHO Member States to ensure sufficient national appropriations and oversight, and for parliamentarians to raise awareness in their constituencies and mobilize local action in building climate-resilient and sustainable health systems.“Universal health coverage, climate change and AI cannot be addressed in isolation. The same communities struggling to access health services today are often the ones most exposed to climate shocks, and most in need of the opportunities AI can offer if this technology is governed responsibly,” said Dr Saia Ma’u Piukala, WHO Regional Director for the Western Pacific. “Having served previously in this Forum myself as a parliamentarian from Tonga, I recognize how the Phnom Penh Communiqué reflects the shared resolve of legislators across the Asia-Pacific region: the laws parliamentarians pass and the budgets they approve help ensure this progress reaches the people who need it most.”As the Forum drew to a close, delegates reflected on what they would carry back to their own parliaments and constituencies.“I wish to share three points here worth carrying home from Phnom Penh: we need to invest in primary health care as the foundation of coverage; we need to remove the barriers that keep people from care, whether financial, geographic or social; and we need to build systems that are inclusive by design, protecting those most at risk of being left behind,” added Hon. Ouch Borith, First Vice-President of the Senate of the Kingdom of Cambodia.###Notes for editors:The Asia-Pacific Parliamentarian Forum on Global Health (APPFGH) is a platform for parliamentarians to exchange ideas, build political will, strengthen capacity and foster collaboration towards sustainable health action. This was the ninth meeting of the APPFGH, with the theme “Universal Health Coverage in the era of Climate Change and Artificial Intelligence”. Target 3.8 of the Sustainable Development Goals calls on countries to achieve universal health coverage, including financial risk protection, access to quality essential health services, and access to safe, effective, quality and affordable essential medicines and vaccines for all. In the Western Pacific, UHC service coverage index (SDG 3.8.1) rose from 63 in 2000 to 81 in 2023 (figures include Indonesia), and roughly one in four people in the Western Pacific have experienced financial hardship (SDG 3.8.2). Progress towards UHC in the Asia-Pacific region remains uneven, with hundreds of millions of people still lacking access to essential health services or facing financial hardship due to health-related expenses. Strengthening the role of parliaments – through legislation, financing and oversight – is central to closing this gap and accelerating progress towards UHC across the region.Parliamentarians participating in APPFGH in Cambodia this week include: Hon. Pehin Dato Adanan YUSOF, Brunei Darussalam; Hon. Rosmawatty ABDUL MUMIN, Brunei Darussalam; Hon. LORK Kheng, Kingdom of Cambodia; Hon. YOS Phanita, Kingdom of Cambodia; Hon. KHOUN Khundy, Kingdom of Cambodia; Hon. HENG Halim, Kingdom of Cambodia; Hon. KHOENG Noupheap, Kingdom of Cambodia; Hon. SENG Nhak, Kingdom of Cambodia; Hon. LY Sukry, Kingdom of Cambodia; Hon. NHOEURN Raden, Kingdom of Cambodia; Hon. Dr Ratu Atonio LALABALAVU, Republic of Fiji; Hon. Vijay NATH, Republic of Fiji; Hon. Man Hee LEE, Republic of Korea; Hon. Dr Jiho CHA, Republic of Korea; Hon. Jonghun BAEK, Republic of Korea; Hon. Youngsuk SEO, Republic of Korea; Hon. Dr Phayvanh KEOPASEUTH, Lao People’s Democratic Republic; Hon. Suhaizan Bin KAIAT, Malaysia; Hon. Dr Perpetua KONMAN, Federated States of Micronesia; Hon. Ganmaa DAVAASAMBUU, Mongolia; Hon. Charmaine SCOTTY, Republic of Naoero; Hon. Vincent Ambance KUMURA, Papua New Guinea; Hon. Dr Edwin CRUZADO, Republic of the Philippines; Hon. AUUAPAAU Mulipola Aloitafua Mulipola, Samoa; Hon. ASIATA TAVUI Tafu Salevao, Samoa; Hon. Dr Alani Petelo TANGITAU, Tonga; Hon. Paul PAOLO, Republic of Vanuatu; Hon. Franklyn Ezra WILLIAM, Republic of Vanuatu.For more information, contact: WHO Regional Office for the Western Pacific: wprocom@who.int National Assembly of the Kingdom of Cambodia (International Relations Department): ir.nacambodia@gmail.com
Business Restructuring Review Vol. 25 No. 4 July-August 2026
In This Issue New York Bankruptcy Court: Premature Allegations of Creditor Mistreatment Insufficient to Deny Chapter 15 Recognition of Foreign Restructuring Proceeding In In re ARD Finance, S.A., No. 25-12794 (MG), 2026 WL 817458 (Bankr. S.D.N.Y. Mar. 25, 2026), the U.S. Bankruptcy Court for the Southern District of New York was presented with a petition seeking chapter 15 recognition of Luxembourg's recently enacted bankruptcy law governing judicial reorganization proceedings. The court granted the petition, turning aside challenges to recognition voiced by a creditor group arguing that recognition should be denied based upon allegations of unfairness to creditors in the Luxembourg proceeding that would make recognition manifestly contrary to U.S. public policy. According to the bankruptcy court, recognition was warranted because: (i) the rules and procedures governing the proceeding under Luxembourg law were fundamentally fair; (ii) the petition otherwise satisfied chapter 15's recognition requirements; and (iii) the creditor group's allegations were premature, given the fact that the Luxembourg court presiding over the debtor's restructuring proceeding had not confirmed a restructuring plan, and all creditors had the right to participate fully and voice their objections in the proceeding (including the right to appeal an order approving a plan). [read more …] Florida Bankruptcy Court Examines Scope of Discovery in Chapter 15 Cases In In re Banco Master, S.A., No. 25-24568-SMG, 2026 WL 931729 (Bankr. S.D. Fla. Apr. 6, 2026), the U.S. Bankruptcy Court for the Southern District of Florida granted in part and denied in part post-recognition motions filed by an insider of a foreign debtor seeking to bar or limit discovery sought by the debtor's foreign representative concerning allegedly voidable transfers involving the debtors' U.S. real property. According to the court: (i) although chapter 15 includes its own discovery provisions among the relief that may be granted to a foreign representative, the expansive discovery available in cases under other chapters of the Bankruptcy Code is also available in chapter 15 cases; (ii) the discovery sought by the foreign representative was permissible; (iii) discovery regarding matters that were the subject of a pending adversary proceeding had to be undertaken under the more restrictive rules applicable to such proceedings; and (iv) a discovery request would be barred to the extent that it sought production of documents or testimony from a subpoenaed entity that exceeded the geographic limitations specified in such rules. [read more …] Delaware District Court Affirms Chapter 15 Recognition Order Enforcing Nonconsensual Third-Party Releases In U.S. Int'l Dev. Fin. Corp. v. Credito Real S.A.B. de C.V. SOFOM, E.N.R. (In re Credito Real S.A.B. de C.V. SOFOM, E.N.R.), 677 B.R. 192 (D. Del. 2026), appeal filed, No. 26-2356 (3d Cir. June 5, 2026), the U.S. District Court for the District of Delaware affirmed a bankruptcy court order granting chapter 15 recognition to a Mexican "concurso mercantile" proceeding and enforcing nonconsensual third-party releases approved by the Mexican court. Agreeing with the bankruptcy court that the releases were not manifestly contrary to U.S. public policy, the district court concluded: "It is well settled that U.S. bankruptcy courts can give effect to foreign orders in recognized foreign proceedings pursuant to the authority granted in Chapter 15, even when those orders contain relief unavailable under U.S. law. [The appellant's] arguments misconstrue the Supreme Court's narrow holding in Purdue, applicable in Chapter 11 cases, as well as the statutory framework of Chapter 15 and its core policy objectives. Accordingly, I will affirm the Enforcement Order." The ruling has been appealed to the U.S. Court of Appeals for the Third Circuit. [read more …] Fifth Circuit: Bankruptcy Court, Not State Court, Had Jurisdiction to Allow or Disallow Administrative Expense Claim In Storey Minerals Ltd. v. EP Energy E&P Co., LP (Matter of EP Energy E&P Co., LP), 169 F.4th 609 (5th Cir. 2026), the U.S. Court of Appeals for the Fifth Circuit affirmed lower courts' rulings disallowing a creditor's administrative expense claim. It also rejected the creditor's argument that, because the claims were predicated on state law, a state court should adjudicate the merits of the state law causes of action before the bankruptcy court could allow or disallow the claim as an administrative expense. According to the Fifth Circuit, even though the causes of action were based on state law, the bankruptcy court had jurisdiction to determine whether the creditor's claims should be conferred with administrative expense priority in the debtors' chapter 11 case. [read more …] New York Bankruptcy Court: Dismissal of Involuntary Chapter 11 Case Filed Prior to Commencement of Foreign Restructuring Proceeding Unwarranted In In re Xinyuan Real Estate Co. Ltd., No. 25-10745 (PB), 2026 WL 592250 (Bankr. S.D.N.Y. Mar. 3. 2026), the U.S. Bankruptcy Court for the Southern District of New York considered the bona fides of an involuntary chapter 11 petition filed by certain holders of U.S. dollar-denominated notes against a holding company for a group of Chinese property development companies that filed a restructuring proceeding in the Cayman Islands after the noteholders filed the involuntary chapter 11 petition. The court denied the debtor's motion to dismiss the chapter 11 case. Given the timing of the filing of the Cayman Islands restructuring proceeding, the absence of any progress in the proceeding for seven months, the debtor's need to restructure notes governed by U.S. law, and the debtor's lack of any meaningful contacts to the Cayman Islands, dismissal of the chapter 11 case was unwarranted under the applicable provision of the Bankruptcy Code, international comity, or the doctrine of forum non conveniens. [read more …] Bankruptcy Court Evaluates Trustee's Authority to Sell Avoidance Actions and Right of Target Defendants to Object In In re Law Enf't Officers Sec. Union, No. 24-70277-JAD, 2026 WL 560452 (Bankr. W.D. Pa. Feb. 27, 2026), a chapter 7 trustee sought court approval to sell certain avoidance actions to a creditor of the debtor's estate. Potential targets of the subject avoidance actions objected, arguing that such claims were nontransferable powers of the trustee rather than saleable estate property and urging the court to approve their competing settlement with the trustee. The U.S. Bankruptcy Court for the Western District of Pennsylvania disagreed with the potential defendants, holding that they lacked standing to object to the proposed sale, that avoidance actions are indeed estate property, and that the sale—rather than the settlement—best served the estate's interests. [read more …] U.S. Supreme Court Bankruptcy Roundup in Brief In Keathley v. Buddy Ayers Construction Inc., No. 25-6, 2026 WL 1686028 (U.S. June 11, 2026), the U.S. Supreme Court overturned a Fifth Circuit decision judicially estopping a chapter 13 debtor from asserting a personal injury claim against a construction company because the debtor failed to disclose the claim during his bankruptcy case. In so ruling, the Court held that "[t]he Fifth Circuit erred by artificially narrowing its inquiry to whether the debtor had knowledge of the underlying facts or a potential motive to conceal the claim." It represents the first time that the Court has applied judicial estoppel in the bankruptcy context, although it has suggested in other contexts that it may be inappropriate where an inconsistent legal position resulted from "inadvertence or mistake." Also in June, the Court denied petitions for certiorari in a few notable bankruptcy cases. [read more …] Newsworthy Heather Lennox (Cleveland/New York) (Star Individual), Bruce Bennett (Los Angeles) (Senior Statesperson), Kevyn D. Orr (Washington) (Eminent Practitioner), Gregory M. Gordon (Dallas) (Band 1), Carl E. Black (Cleveland), Corinne Ball (New York) (Senior Statesperson), Brad B. Erens (Chicago), Jeffrey B. Ellman (Atlanta), T. Daniel Reynolds (Cleveland), and Dan T. Moss (Washington/New York) were recognized as leading lawyers in the practice area Bankruptcy/Restructuring in the 2026 edition of Chambers USA: The World's Leading Lawyers for Business. The 2026 edition of Lawdragon 500 Leading Bankruptcy and Restructuring Lawyers ranked the following lawyers: Corinne Ball (New York) (Hall of Fame), Bruce Bennett (Los Angeles), Carl E. Black (Cleveland), Jeffrey B. Ellman (Atlanta), Brad B. Erens (Chicago), Gregory M. Gordon (Dallas), Heather Lennox (Cleveland/New York), Joshua M. Mester (Los Angeles), and Kevyn D. Orr (Washington). Fabienne Beuzit (Paris) and Jasper Berkenbosch (Amsterdam) were among the "Leading Individuals" ranked in the 2026 edition of The Legal 500 EMEA guide in the field of Restructuring and Insolvency or Insolvency. Rodolphe Carrière (Paris) was named a "Next Generation Partner" in the practice area Insolvency. Sid Pepels (Amsterdam) was selected by Global Restructuring Review's 40 under 40 2026. He was identified as a Rising Star within the global cross-border restructuring community. Global Restructuring Review is a leading digital subscription service, news outlet, and information platform dedicated exclusively to cross-border insolvency and corporate restructuring law. Fabienne Beuzit (Paris), Rodolphe Carrière (Paris), and Isabelle Maury (Paris) were recognized in the 2027 edition of The Best Lawyers in France™ in the practice area Insolvency and Reorganization Law. An article written by Corinne Ball (New York) titled "Comity and Fairness are Critical to Granting Additional Assistance under Chapter 15: A Canadian Reverse Vesting Order and Related Releases in Proceedings Involving Canadian and U.S.-Affiliated Companies Are Approved" was published in the June 24, 2026, edition of the New York Law Journal. An article written by Caitlin K. Cahow (Detroit) titled "New York Bankruptcy Court Weighs In on Adequate Assurance of Future Performance under Assigned Leases and Chapter 11 Plan Exculpation Provisions" was published on June 8, 2026, in Lexis Practical Guidance. An article written by Trisha L. Mowbray (Real Estate; Chicago) and Ryan Sims (Washington) titled "Chapter 11 Plan that Abridged Non-Debtor Lessee's Rights to Remain in Possession After Rejection Unconfirmable as Having Been Proposed in Bad Faith" was published on June 16, 2026, in the Harvard Law School Bankruptcy Roundtable. An article written by Dan T. Moss (Washington/New York), Corinne Ball (New York), Isel M. Perez (Miami), and David S. Torborg (Washington) titled "Texas Bankruptcy Court Adopts Barnet Rule Requiring Foreign Debtor to Have U.S. Assets to Be Eligible for Chapter 15 Relief" was published on June 10, 2026, in Lexis Practical Guidance. An article written by Daniel J. Merrett (Atlanta) and Nathaniel Parr (Atlanta) titled "Southern District of Texas Clarifies Post-Purdue Course for Consensual Third-Party Releases and Gatekeeping Provisions" was published on June 11, 2026, in Lexis Practical Guidance. An article written by Corinne Ball (New York) titled "LMEs, Sophisticated Investors and Equitable Mootness: The Fifth and Third Circuits Warn Against Testing the Limits of Chapter 11" was published in the June 2026 issue of the American Bankruptcy Institute Journal. Nicholas J. Morin (New York) was quoted in an article titled "Serta Ruling Offers Damages Road Map in Lender-on-Lender Disputes," published by Bloomberg Law on July 7, 2026. The article discussed U.S. Bankruptcy Judge Christopher Lopez's July 7, 2026, ruling that participating lenders in Serta Simmons Bedding's 2020 non-pro rata uptier exchange breached the credit agreement's ratable-sharing provision, and awarding excluded lenders more than $261 million in damages. The opinion resolves six years of litigation related to Serta's 2020 transaction, where it raised $200 million in new financing and exchanged $1.2 billion of term loans for $875 million in superpriority debt. Judge Lopez found that the debt-for-debt exchange constituted a "payment" under the credit agreement, requiring proportional sharing among lenders, and dismissed various defenses raised by the participating lenders. The case is Serta Simmons Bedding LLC v. AG Centre Street Partnership (In re Serta Simmons Bedding LLC), 2026 WL 1968535 (Bankr. S.D. Tex. Jul. 7, 2026). The New York Law Journal has recognized Andrew M. Butler (New York) as a 2026 "Rising Star" in Restructuring/Bankruptcy as part of the New York Legal Awards. The Rising Star category recognizes New York's most promising lawyers age 40 and under who have distinguished themselves through exceptional legal work, leadership, and contributions to the profession. Lawyer Spotlight: Daniel J. Merrett Dan Merrett, a partner in the Atlanta Office, has spent nearly 20 years representing all manner of stakeholders in complex corporate restructurings and chapter 11 reorganizations. His practice extends to related transactions and disputes involving acquisitions; divestitures; credit facilities; securities; environmental obligations; and vendor, employee, and governance matters. Dan has substantial experience managing mass tort liabilities, including the restructurings and related chapter 11 cases of affiliates of Georgia Pacific and Johnson & Johnson, implemented to resolve asbestos and talc liabilities. He also represents key parties in energy and infrastructure matters, including facility owners, EPC contractors, and joint-venture parties. Dan was a key player in the restructuring teams in the historic bankruptcies of the City of Detroit and Chrysler. His other significant representations in chapter 11 cases include AFA Foods, Alpha Natural Resources, Dana Corporation, M&G Chemicals, McDermott International, Monster/CareerBuilder, Transtar Industries, and Westinghouse. He is licensed in both the United States and England & Wales and recognized in restructuring by Chambers USA and Best Lawyers.
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PARKERSBURG – The Artsbridge calendar for the week: TODAY * Geppetto Woodcarver’s Wood Quilt display, 9 a.m. to 4 p.m., WesBanco, Market Street, Parkersburg WEDNESDAY * Diane Wigal wildlife photography exhibit, 9 a.m. to 4 p.m., WesBanco, Market Street, Parkersburg * Story Hour, ages 3-6, 10-11 a.m., Marietta Public Library * Bookworms Storytime, ages 3 […]
Scientists Stunned: Colossal Eggs Discovered 3,500 Meters Beneath an Active Volcano
Beneath an active seafloor volcano off Vancouver Island, researchers have documented a congregation of giant eggs at roughly 3,500 meters, a discovery that reframes how life can flourish under extreme conditions. The eggs belong to the Pacific white skate, an elusive deep‑sea species adapted to cold, crushing pressure and perpetual darkness. What seemed an unlikely nursery is actually a geothermally warmed refuge, where subtle heat helps embryos survive a marathon incubation. The finding links volcanic energy to a quiet engine of biodiversity, turning a hostile landscape into an incubator. A living volcano, a hidden nursery The seamount long assumed dormant now exhales mineral‑rich, shimmering plumes, proof of hydrothermal life at depth. Expedition cameras swept across black basalt and pale bacterial mats, revealing vents that pulse with warmth. That warmth, though modest by human standards, alters the physics of development for cold‑adapted embryos. In a realm where metabolism creeps, even a few degrees can mean faster growth and higher survival. The volcano is not only active; it is ecologically formative, drafting a blueprint for a thriving oasis. Giant eggs and a skate built for the abyss The Pacific white skate, Bathyraja spinosissima, is built for the abyss: broad wings, armored spines, and a life history that trades speed for endurance. Females lay outsized, rectangular “mermaid’s purses,” often 46–50 centimeters long, packed with rich yolk to fuel years of growth. In the frigid deep, embryos can require around four years to hatch, a timeline that magnifies every energetic advantage. The scale is striking—large eggs, large adults, and a textbook case of deep‑sea gigantism. The volcano’s gentle heat may literally shave months or years from the wait. Why heat matters at the bottom of the sea Hydrothermal circulation delivers low‑level warmth without the turbulence that would scatter fragile egg‑cases. Slightly elevated temperatures accelerate enzyme kinetics, nudging development along while keeping embryos within a safe range. Mineral‑laden fluids likely shape local microbiomes, which, in turn, can influence biofilms on egg surfaces. The environment acts like a slow, steady incubator, countering the deep sea’s tyrannies of cold and scarcity. For a species with long maturation and few offspring, every incremental boost compounds across generations. An ecosystem sculpted by fire and water Seafloor volcanoes create steep environmental gradients, stitching together hot vents, cool eddies, and mineral gardens into mosaic habitats. Microbes harvest chemical energy, seeding food webs that support crustaceans, fishes, and skates. Cameras documented egg‑cases nestled among rocky ledges, near communities nourished by vent‑driven chemistry. These islands of productivity behave like deep‑sea oases, sustaining life far beyond the vent orifice’s flickering light. The nursery’s success underscores how geological forces engineer biological opportunity. “Finding a cradle of life tucked beneath a breathing volcano reminds us that the planet’s harshest places can be profoundly generous.” What the discovery could change The nursery reframes conservation priorities in regions where volcanism quietly underwrites reproduction. Protecting hydrothermal corridors could safeguard entire lifecycles, not just charismatic adults spotted during occasional surveys. It also sharpens questions about how climate‑driven shifts in ocean circulation might influence vent activity, temperature fields, and embryo survival. With methodical mapping, time‑series cameras, and environmental DNA, scientists can track whether nurseries remain stable or drift with geologic rhythms. Key implications include: Enhanced understanding of deep‑sea reproduction at hydrothermal sites. New conservation targets centered on geothermal nurseries. Comparative studies with other volcanic regions, from the Galápagos to rift zones. Biotechnological insights from organisms adapted to long, cold development. Better models of how seafloor heat shapes regional biodiversity. Methods behind the revelation Remotely operated vehicles threaded through chimney fields, gathering video, temperatures, and mineral signatures. High‑definition imagery captured the distinctive, horned egg cases, their edges dusted with fine volcanic silt. Geochemical profiles mapped how heat and chemicals disperse, outlining the “thermal lanes” where eggs most cluster. Combined, these datasets reveal a nursery organized by geothermal topography, with egg‑cases concentrated in pockets of gentle, sustained warmth. A fragile boon in a changing ocean Deep‑sea environments feel remote, yet they intersect with global pressures: mining proposals, cable routes, and shifting oxygen levels. The nursery’s resilience hinges on stable heat flow, intact substrates, and minimal disturbance from noise or sediment. Safeguarding such places is not just about protecting novelty; it preserves a slow, ancient strategy that lets large, long‑lived animals endure in the coldest reaches of the Pacific. Where geology and biology meet, the planet’s deep time still writes living stories. This volcano‑warmed nursery adds a vital chapter to that story, revealing how subtle thermal gifts can tip the scales toward life in the abyss. With each dive, researchers trace the contours of an unseen world, where fire feeds water, and water—against all odds—feeds the future.
Why your brain may be sabotaging your balance as you age
Balance problems in aging and Parkinson’s may come from the body working too hard, not too little. Scientists found that the brain and muscles become overactive during even minor disturbances, yet this actually weakens balance recovery. At the same time, muscles can stiffen against each other, making movement less stable. This unexpected pattern could help predict who is more likely to fall.
Entertainment and more in the Mid-Ohio Valley
PARKERSBURG – The Artsbridge calendar for this week: TODAY * Geppetto Woodcarver’s Wood Quilt display, 9 a.m. to 4 p.m., WesBanco, Market Street, Parkersburg * Art is Life/Life is Art, ages 55-plus,10:30 a.m. to 12:30 p.m., Parkersburg Art Center * Butterfly Photo Holder, ages 13-plus,11 a.m. to noon, Marietta Public Library * Hygge Club, adults, […]
Zions Bancorporation to Acquire Fannie Mae and Freddie Mac Business Line from Basis Investment Group
/PRNewswire/ -- Zions Bancorporation, N.A. (NASDAQ: ZION) today announced that it has entered into a definitive agreement to acquire the agency lending...
Shia LaBeouf causes disturbance in hotel lobby while wearing only his underwear after New Orleans arrest
Shia LaBeouf was filmed causing a disturbance in a hotel lobby in Rome after he was arrested in New Orleans: 'Give me a f---ing match.'
Entertainment and more in the Mid-Ohio Valley
PARKERSBURG — Events and programs for the week from Artsbridge: TODAY * Geppetto Woodcarver’s Wood Quilt display, 9 a.m. to 4 p.m., WesBanco, Market Street, Parkersburg * Homeschoolers Music Class, grades K-2 and 3-5, 10 a.m. to 12:30 p.m., Parkersburg Public Library * Art is Life/Life is Art, ages 55+, 10:30 a.m. to 12:30 p.m., […]
'Teen Mom 2' star Jenelle Evans' son checked into mental health facility: report
Evans' son Jace allegedly threatened to kill himself and his grandmother last month and officers responded to a "troubled teen disturbance."
'Teen Mom 2' star Jenelle Evans' son checked into mental health facility: report
Evans' son Jace allegedly threatened to kill himself and his grandmother last month and officers responded to a "troubled teen disturbance."
Entertainment and more in the Mid-Ohio Valley
The Artsbridge Calendar of Events for the week: Today * Geppetto Woodcarver’s Wood Quilt on display, 9 a.m. to 4 p.m., WesBanco, Market Street * Art is Life/Life is Art, ages 55 and up, 10:30 a.m. to 12:30 p.m., Parkersburg Art Center * Hygge Club, adults, 11 a.m. to noon, South Parkersburg Public Library * […]
Providence sports bar temporarily closed after disturbance
A sports bar in Providence is temporarily closed after an incident happened Saturday evening, according to police.
Magic rout visiting Wizards behind Paolo Banchero’s 37 points
ORLANDO, Fla. — Entering Tuesday’s game against the Wizards, the Magic knew they’d already be without Franz Wagner, who is managing an extended rehab of a left high ankle sprain. Then, in the hours leading up to tipoff, Orlando learned it would also be without Anthony Black (right quad contusion) for the second game in a row and Wendell Carter Jr. (left ankle soreness) while hosting Washington ...
Entertainment and more in the Mid-Ohio Valley
PARKERSBURG — The Artsbridge calendar of events for this week: TODAY * Geppetto Woodcarver’s Wood Quilt on display, 9 a.m. to 4 p.m., WesBanco, Market Street, Parkersburg * Art is Life/ Life is Art, ages 55+ 10:30 a.m. to 12:30 p.m., Parkersburg Art Center * Lunch and Learn Lecture with the Belpre Tree Commission, noon […]
Detroit Pistons deep dive, polarizing Paolo Banchero + Unrivaled awards
Warrants: Man assaults ECU Health police officer, causes disturbance at hospital
WITN reports a Greenville man is behind bars after court documents show he assaulted a police officer at ECU Health Medical Center.