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TQL’s RICO response: rips carriers’ ‘poor business practices’
The first response in the RICO case initiated by a group of carriers against giant 3PLs C.H. Robinson and TQL has been filed by the latter, and it has two
SpaceX earnings put Elon Musk's Starlink cash cow to the test
Elon Musk is taking a big swing in his bet to turn Starlink into a mobile carrier just in time for earnings.
EE announces iPhone Handoff pricing details for UK customers
As part of its iPhone Duo preorder announcement, UK carrier EE has announced pricing details for iPhone Handoff – making...
Verizon Will Charge $10 a Month for iPhone Handoff
Verizon plans to charge customers $10 per month for the iPhone Handoff feature that Apple added in iOS 27. iPhone Handoff allows one phone number to be shared across two separate iPhones. Pricing was included in Verizon's iPhone Duo announcement today, with the carrier confirming iPhone Handoff will work with the iPhone Duo and the iPhone 18 Pro models.
Opinion: How politics and policy are rewriting the rules of parcel delivery
By Daniil DavydoffFollowing the U.S. parcel delivery market can feel like tracking a race. Tactical moves to increase network capacity, build facilities, and launch tools, as well as strategic changes in leadership and operating models, dominate assessments of which carriers are gaining or losing ground, but political and policy forces are shaping those decisions. Labor […] The post Opinion: How politics and policy are rewriting the rules of parcel delivery appeared first on FreightWaves.
DFW Business Datebook: AT&T, Texas Instruments and airlines report
Fort Worth-based American Airlines and Dallas-based Southwest Airlines will report third-quarter earnings this week in key moments for each carrier.
Daldrop Opens for Business in Southern Oswego County
$10 Million Facility in the L. Michael Treadwell Oswego County Industrial Park marks the largest expansion outside of Germany in the company’s 73-year history By Stefan Yablonski [caption id=attachment_11076 align=alignright width=450] Daldrop SBB CEO Jens Daldrop addresses attendees at the 2025 groundbreaking for the project. Daldrop also chairs the advisory board of Germany-based Daldrop Group.[/caption] A new era of cleanroom technology is underway in Central New York. The Daldrop Group’s advanced manufacturing facility and U.S. headquarters is physically built within the L. Michael Treadwell Oswego County Industrial Park. This industrial park is located in the town of Schroeppel. It marks the largest expansion outside of Germany in the company’s 73-year history. Daldrop SBB is based in Neckartailfingen, Germany. It is a global supplier of cleanroom technology, primarily to the pharmaceutical industry. It designs and builds advanced cleanroom environments for the pharmaceutical, biotechnology and medical technology industries. It nvested $10 million in the new project. “We broke ground in 2025; we were under construction all winter. We just opened this spring, early spring,” said Benjamin Morrow, operations manager and control. The company consolidated sites in Salina and DeWitt into the industrial park in Schroeppel, Morrow added. “The next move here is to maximize every square inch of this facility and then we are already looking at the expansion. So, it is more capital investment on equipment — definitely higher-end automation in additional equipment so we can produce more components and then to support the ever-growing base in North America,” Morrow continued. “We are the headquarters for service, maintenance and spare parts. So as Daldrop has more and more installations, they need more and more service, maintenance and spare parts. So that will come out of this facility as well — it already is.” “As a global leader in GMP (global manufacturing support) pharmaceutical cleanrooms for decades, I am very proud to bring manufacturing jobs to Upstate New York,” said Mike Sullivan, president of Daldrop US operations. Key to choosing Southern Oswego County [caption id=attachment_11077 align=alignright width=450] Daldrop SBB at the L. Michael Treadwell Oswego County Industrial Park when the company announced the start of construction.[/caption] Sullivan said that the selection of the Schroeppel industrial park was mainly due to the help of Operation Oswego County and two people in the organization. “Prior to being purchased by Daldrop International from the Stuttgart region of Germany, Vince Bongio was a founding partner in SBB Inc. as well as our head of engineering. We based out of Syracuse due to Vince’s skills in HVAC and the manufacturing capabilities found in Syracuse,” said Sullivan. Bongio moved to Syracuse from California in the 1970s to work in Carrier’s Industrial Division of Large-Scale Petrochemical Refrigeration. Next, he advanced to General Electric’s TV Tube Plant where he got into cleanrooms ,leading to his role of head of engineering for Clestra Cleanrooms where he met Sullivan, their New England distributor. “Vince Bongio is a phenomenal engineer. Formerly of Carrier, he grew up in California and went to Cal Poly,” Sullivan explained. “Carrier hired him right out of college and he moved to Syracuse. He is the reason we are in Syracuse today. He is retiring this year. We are very proud and his legacy is having brought Daldrop to Syracuse.” In 2000, Sullivan, Bazinet, Bongio Inc (SBB) was formed with engineering and manufacturing, based in Syracuse, and sales and construction based in Massachusetts as it is today. “SBB Inc. started in Syracuse. I had a design–build contracting firm out of Massachusetts that was primarily doing all the new technologies coming out of MIT,” Sullivan said. “I started a manufacturing side. A big thing for cleanrooms is the HVAC. Most cleanroom suppliers are architecturally focused people. The strength in Syracuse is HVAC. So, SBB developed with me running sales and construction out of Massachusetts and manufacturing out of Syracuse.” “Daldrop wanted to have a relationship in the States and of those who approached us, they were the only ones who really understood HVAC. So, we were the right fit for them. We did a joint venture focused out of Massachusetts from 2012 to 2018 leveraging their technologies,” Sullivan explained. “The commitment was if we brought their product to the States, we would do that if they built it here. “The pieces that had to be in place to make the investment, they wanted to acquire us, we were great with that. If you looked at business recommendations the general guidance was to build in a low labor area — something like North Carolina — but Syracuse had a strong background in HVAC and we chose Syracuse and Oswego County to be our headquarters in the States. So, it is built off of history, technology and the existing supply chain — bringing jobs back to the area.” During the initial discussions with Daldrop about coming to the U.S., SBB agreed to sell under the conditions Daldrop would manufacture in the U.S. There are many areas that offer incentives and economic packages, but the strength of HVAC expertise and skilled manufacturing was a big part of the discussions for site selection. Coming home [caption id=attachment_11078 align=alignright width=451] Construction moves forward in March at the L. Michael Treadwell Oswego County Industrial Park.[/caption] The second key person to building in Oswego County is Ben Morrow, Sullivan added. “Ben has been working with Daldrop SBB for more than 12 years and has advanced to COO of manufacturing and engineering. Ben grew up in Phoenix, so building a factory for the Germany company in Phoenix is a strong success for both his community and the appreciation of Ben’s skills as a team leader,” Sullivan said. “I went to high school in Phoenix. So, this is like full circle for me. It’s a small world,” Morrow said. “I hadn’t been back to Phoenix since graduation. This is one of the properties that John Trimble of C&S, he is the former president of C&S, he just retired, suggested. He and I were very good personal friends. John was from Mexico and I was from Phoenix. We knew each other from high school. And the architect of this building, Ed Smart of smartDESIGN Architecture in Batavia — I went to high school with him. So, this was a project that’s full circle a coming home kind of thing. The three of us knew each other — kind of like it was meant to be. Very serendipitous.” Schroeppel was one option for Daldrop to consider; the original intent was just to get a warehouse to store some product, he added. The facility is Daldrop’s largest outside of their native country. Total payroll at the facility will be approximately $2.4 million once fully staffed. “Here is 32,000 square feet and we plan to expand and put in an additional 10,000 square feet,” Morrow said. “We have 17.5 acres. We can put at least three more facilities here, just on this property. The master plan submitted for the current building is the first of possible three buildings on the campus.” “If we can find the right people and advance the production according to the plan, we should be able to grow for the next decade. One of the first jobs we filled was our new HR manager, with a primary focus posting and filling new positions,” Sullivan said. Stop the exodus, start hiring [caption id=attachment_11080 align=alignright width=452] Principals at the local Daldrop SBB headquarters, from left: Ben Morrow, Mike Sullivan and Jens Daldrop.[/caption] “I have been coming to Syracuse for 30 years. One of the things I had a hard time watching was the exodus of factories. One of the toughest things is to watch it with my partners’ kids who had to move away for jobs. It is important for us to give opportunity where people’s kids don’t have to leave the area to get work,” Sullivan said. “My responsibility is to find people who have skill sets that want to work and then I have to build opportunity for that work to happen. “After years of watching companies and Vince’s three sons all move out of the areas to get jobs, it is important to us to provide opportunities for the Syracuse region and help grow our company. We have been hiring for our new factory and will continue for the next few years.” “We are hiring and will continue to hire. Currently we have about 19 on staff right now,” Morrow said. “We expect to grow that by about 10 to 15 in the next 12 to 18 months or so. We are at 19 currently — one in the wings. It’s been great being able to hire locally. All these folks that we’ve been hiring, they all live within a few miles from here.” “We hired someone this past week (end of August). She grew up in the area, raised a family and is working down in Florida. She just took a job with us so she can move back and be with her family. We will be moving her back and she should be starting in October. We are very happy to see this happen,” Sullivan said. “I feel strongly about having a spot for the kids to not have to move out of the area. It is better to have people moving into the area.” Currently, Daldrop SBB has openings for finance manager, COO of construction and delivery, as well as mechanical, electrical designers and Revit modelers, construction managers, commissioning agents and many other skills that are needed. Along with Daldrop’s reputation in life science cleanrooms, there is a strong history in semiconductor, electronics, glass, photonics, aerospace and other markets. This may be helpful with any new technologies building in the market such as the Micron expansion and the support network, Sullivan said. “We acquired this property and closed on it two months before any announcement from Micron. It is serendipitous that they’re right down the street from us,” Morrow added. “Everybody started thinking ‘you guys are supporting Micron.’ We were here first. That is not a goal of ours. We may or may not … they are talking to us; it is an opportunity.” The long run [caption id=attachment_11079 align=alignright width=450] Benjamin Morrow, operations manager and control at Daldlrop, speaks during a recent ribbon-cutting event in Schroeppel.[/caption] “Long term, we will expand the Phoenix facility,” Sullivan said. “We built our facility with a campus approach. Sustainability is big. We designed our rooms to be more sustainable. Our building has no gas lines for heat. We put geothermal wells in the ground. We put heat pumps in for heating and cooling out of those wells and we put a large layer of solar panels up on the roof. We worked with National Grid for metering. Our building is a high efficiency model. We upgraded all the instillation and the glass filtering. So, it is a very green building. We will have a very minimal carbon footprint. It also adheres to LEED (Leadership in Energy and Environmental Design) construction standards.” “We are a bunch of HVAC engineers. We did a large scale geothermal and spent the money up front because we knew it made sense in the business sense in the environmental sense and sustainability,” Morrow said. “We have insulated metal panels on walls and roof; we are an envelope from the exterior.” Daldrop, as a global player, has a strong culture of sustainability that is found in all its products including the new facility. The building has been designed with (sixteen) 400-foot deep geothermal wells, high efficiency construction methods, approximately 70 kilowatt solar photovoltaic panels, electric vehicle chargers and 26% recycled content. “Daldrop thinks of long-term investing,” Sullivan said. “On the roof, photovoltaic panels supplement our power. Over half the energy that I use is coming from the sun. We have chargers up front for employee electric vehicles. This place is built to last. This slab that we are walking on, normal buildings are four inches, some go to six inches, we are nine inches all the way through — except where the heavy equipment is — that is 10 to 12 inches thick, solid concrete. It allows us to reconfigure for whatever type of equipment we want to bring in,” Morrow said. “We are authorized by Underwriters Laboratory to self-certify so we don’t need to have an inspector come out and recertify. We get audited often, but we certify our own electronics. The control system in this building is rather high-end. Our thermostat in every room is zoned, independent. We analyze the data; incorporate it with our solar panels.” “There is a lot of competition for people to work. It’s not just about how much salary they are going to make — it’s about the work environment, the ability for stability. We want to make sure our employees have the best environment to work in,” Morrow added. Similarities “One of the reasons I believe why Daldrop chose this area, Phoenix in particular, is because it is a village, a river-based village. Neckartailfingen in Germany where Daldrop is based is also a river-based village, manufacturing community. So, there is a lot of similarities — that smalltown feel,” Morrow said. “We have a lot of connections through multiple employees that lead back to Carrier, also. Everything came together, the timing everything.” “We are thankful for all the economic development support. Everyone has been helping make this happen. So, keep it up, it is working, that is all I got to say, Sullivan said. “If you look at historical industrial manufacturing, this region has skills that have been un-utilized. The northern industrial region has a lot of skills that if we can tap before they go away, we can leverage them. That is what we are trying to do. You’d be surprised at the supply chain left behind from Carrier — that supply chain is still there.” “Operation Oswego County has been fantastic,” Morrow added. “I can’t say enough good things about that group.” What Is Cleanroom Technology Cleanroom technology is a system of specialized engineering, filtration and operational controls used to maintain an extremely low concentration of airborne particles, microbes and chemical vapors. How It Works • Air Filtration: Uses HEPA or ULPA filters to remove 99.97% of tiny particles down to 0.3 microns. • Airflow Control: Directs air in a steady, unidirectional (laminar) or filtered turbulent pattern to push dust away from work areas. • Environmental Regulation: Maintains precise control over temperature, humidity and positive air pressure to block outside air leaks. • Specialized Attire: Requires personnel to wear full-body garments (“bunny suits”), gloves and masks to stop human shedding
Small group health insurance market rates announced
Media Release, Office of Superintendent of Insurance (OSI) Santa Fe, NM – The New Mexico Office of Superintendent of Insurance (OSI) has approved 2027 health insurance premium rates for the small group health insurance market. As of March 2026, over 31,000 New Mexicans were enrolled in a small group plan. The average increase across small group plans is 19.8%. These rates take effect on January 1, 2027. The carriers offering small group coverage in New Mexico in 2027 are: Blue Cross Blue Shield of New Mexico (HealthCare Service Corporation) Presbyterian Health Plan Presbyterian Insurance Company UnitedHealthcare of New Mexico UnitedHealthcare Insurance Company Key Factors Driving the Rate Increases The primary factors that contributed to the 2027 increases are: Claims Experience - Higher than expected 2025 New Mexico claims experience, which is the foundation for the 2027 rate development. Cost Trend - Higher utilization and inflation impacted healthcare costs services, which impacts medical services and pharmaceutical costs nationwide. Risk Pool Changes - Nationwide, businesses with healthier employees are opting for alternative health coverage not under the Affordable Care Act (ACA). This results ina smaller and less healthy small group ACA risk pool. Final approved rates will be posted on the OSI website. To view the carrier rate sheets and rate increase specifics, visit the Office of Superintendent of Insurance website here. The Rate Review Process Conducted by OSI The OSI rate review process focuses on approving rates for health insurance plans that are actuarially sound, not excessive, inadequate, or unfairly discriminatory and ensuring health insurance rates comply with all state and federal laws. For more information, visit the Office of Superintendent of Insurance website at https://osi.state.nm.us/en/. *** About the Office of Superintendent of Insurance The Office of Superintendent of Insurance (OSI) is New Mexico’s regulatory agency responsible for overseeing a wide range of insurance products, including private health and life insurance, auto, home, business, and title insurance. OSI regulates private health plans in the individual, small group, and large group markets, ensuring that premium rates are fair, companies are financially sound, and health care insurance coverage is reliable. While OSI does not have authority over self-funded health plans, where an employer assumes the financial responsibility for paying employee health care claims, Medicaid, Medicare, or TRICARE, OSI plays a vital role in protecting consumers by reviewing premium rates, monitoring insurance company conduct, and licensing producers (formerly known as insurance brokers and agents).
Business study story: From steering aircraft carriers to addiction centres
Alta DeRoo on her route from the navy to medicine and leadership via an executive MBA
I Flew in Condor Business Class From NYC to Germany: Is it Worth the Upgrade?
Traveler editor Charlie Hobbs takes flight with Condor, the Frankfurt-based carrier known for its relatively affordable transatlantic fares.
ACIC launches E&S carrier for coastal commercial property
ACES Specialty Insurance will begin writing in Florida, Texas and South Carolina on December 1, adding a direct market for catastrophe-exposed placements
Apple rolls out AT&T carrier update for iPhone 18 Pro Max on iOS 27.2 beta
Apple is rolling out a different carrier bundle update for devices running the iOS 27.2 beta. Here are the details.
Southwest Airlines weighs Boeing 787 for long-haul international push, sources say
Southwest Airlines is leaning toward Boeing's 787 Dreamliner as its first widebody jet as it weighs launching long-haul international flights, according to three people familiar with the carrier's fleet planning.
USS Lincoln carrier to return to port in San Diego after record-breaking deployment
Vessel spent over 260 consecutive days at sea without a port call, a US navy record
Long-Deployed Aircraft Carrier U.S.S. Abraham Lincoln Set for Homecoming
The ship, whose crew endured food shortages, spent much of its nearly 11-month deployment in combat without a day off.
Small businesses face tough choices as health insurance costs rise
Some businesses are exploring choice arrangements, which allow employers to set a defined benefit amount rather than selecting one carrier and set of plans for all employees.
Small businesses face tough choices as health insurance costs rise
Some businesses are exploring choice arrangements, which allow employers to set a defined benefit amount rather than selecting one carrier and set of plans for all employees.
Nearly 10 months at sea. Families now count the hours until USS Lincoln docks
Sailors went months without setting foot in a port after the carrier got called to the Middle East to fight the war in Iran
Health insurance costs continue to climb in Nevada, with 17% increase for 2027
Health insurance rates across all carriers in Nevada’s state exchange are set to increase by an average of 17% for the 2027 plan year starting November 1.
Amid Soaring Costs, Health Benefits Brokers Seek New Strategies
Affordability challenges are transforming the health benefits market, requiring brokers, carriers, and employers to make difficult decisions. In 2000,
AT&T and Apple Just Took Steps Toward Fixing iPhone 18 Pro Max Issue
AT&T and Apple are taking action today as they try to resolve iPhone 18 Pro Max cellular issues, according to MacRumors contributor Aaron Perris. Thousands of iPhone 18 Pro Max users have been unable to connect to the AT&T network for phone calls, text messages, and data. The underlying cause has yet to be disclosed, but AT&T and Apple continue to work toward a resolution. First, Apple today released an AT&T carrier settings update (version 72.1, up from 72.0.2) for iPhones.
Here are the “Coolest Thing Made in NC” winners
The voters have spoken in the NC Chamber’s annual contest for the “Coolest Thing Made in NC.” Carrier’s Chillers takes the prize in the large business category, American Honda Motor Co.’s FourTrax Foreman 4×4 in the medium business category and Old School Mill’s Old School Brand Hot Cocoa Mix in the small business category. Carrier’s […]
Alaska Airlines is moving to join American's transatlantic and transpacific revenue-sharing deals
The carriers plan to file for antitrust immunity with the U.S. Department of Transportation, with approval expected to take months
Unrated reinsurers creep into $30bn US fronting market
AM Best flags credit risk as fronting carriers lean on unauthorized and offshore reinsurance to support MGA growth
You Can 'Get Ready' for iPhone Duo Pre-Orders on October 12
People who plan to purchase an iPhone Duo can go through the "Get Ready" process starting on Monday, October 12. The new detail was added to the iPhone Duo product page yesterday, according to Reddit. Get Ready lets users select a preferred color and capacity, confirm their carrier status, choose accessories, choose an AppleCare+ plan, select a trade-in, add a payment method, and set a shipping and billing address.
American Airlines and Alaska Airlines announce plans for Alaska to join the Atlantic and Pacific Joint Businesses
The carriers anticipate filing for approval and antitrust immunity with the U.S. Department of Transportation and seeking other relevant approvals from international regulators in the coming months.
Proposed aircraft carrier redesign could delay NNS construction
The Trump administration is considering a potential redesign of the nation's aircraft carriers that could cost billions more dollars.
The Beclowning of Scott Bessent
One iron law of current politics is that nobody who associates themselves with Donald Trump emerges with a shred of credibility. For some, that’s not a big loss — it’s not as if anyone respected Pete Hegseth even before he decided that the key to military success in an age of drones and AI was more testosterone. For others, however, the costs are real. I’m old enough to remember when Marco Rubio was widely considered a reasonable, thoughtful politician. Right now, however, my candidate for the biggest loser is Scott Bessent, the Secretary of the Treasury. Bessent started out with significant reputation to lose: When Trump selected him, this was the headline in the Financial Times: Jason Furman, Barack Obama’s chief economist, described him as a “credible Treasury secretary who has a real understanding of the global economy”. But Bessent has now transformed himself into the Baghdad Bob of bonds. Three weeks ago, after intervening (for reasons that remain somewhat unclear) to support the Japanese yen, Bessent boasted about his ability to move markets and dared investors to bet against his, declaring “I am the house now.” He then tried to push long-term interest rates down, buying 30-year U.S. Treasuries in a move some have compared to paying down part of your mortgage by running up your credit card balance. Here’s how that’s going so far: To get some perspective on how high interest rates have gone, here’s a longer-term perspective: We haven’t seen interest rates this high since the fading days of the dotcom bubble. Why are interest rates hitting new records? The backdrop, as I argued in last Sunday’s primer, is the huge AI-driven investment boom; more on that next week. But the immediate cause of the latest interest rate spike was Trump’s rejection of an Iranian proposal to end the war. This rejection sent crude oil prices, which for a while had fallen considerably, shooting back up: It’s notable, by the way, that oil prices remain high even though a significant amount of oil is now being shuttled through the Strait of Hormuz by night, on smaller vessels. That’s an interesting story, which has a lot to do with the fact that oil from the Hormuz shuttle runs must be transferred to larger vessels before being shipped to markets in Europe and Asia; around 15 percent of the world’s large crude carriers are now parked off the coast of Oman, waiting to be tanked up. This is creating a shipping crunch: But that’s a topic for another day. For now, the point is that with oil still high and refined products, especially diesel, still close to record levels, inflation will remain elevated. And this in turn means that the Federal Reserve will keep short-term interest rates high, an expectation that is feeding into longer-term rates. Hence Bessent’s bond-market humiliation. The truth is that Bessent might not have been able to get interest rates down even in the best of circumstances. But he certainly won’t get anywhere as long as Trump keeps believing that he can somehow convert his Iran debacle into a triumphant victory. And Trump will keep believing that as long as he is surrounded by sycophants who tell him what he wants to hear. Sycophants like, for example, Scott Bessent, who is predicting the imminent collapse of the Iranian economy, possibly within two weeks. Bessent is right to say that the embargo on Iranian oil exports is placing the country under great economic strain. But his implicit prediction that this will quickly produce a deal that Trump can call victory looks no more plausible than his boasts about the bond market. The big question now is, why would anyone with a reputation to lose work for Donald Trump? As the beclowning of Bessent shows, joining the Trump team won’t just damage your reputation; it will utterly destroy it.
I'm Still Shocked at the Pixel 11 Pro Being 56% Off
There aren’t many deals that we find that seem too good to be true, yet basically are as good as advertised. When you throw a wireless carrier into the mix of the deal, you then almost always assume the worst. However, Verizon is still running a Pixel 11 Pro deal that really is as good...
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. [1] Intel, “Intel Tech Tour 2025 Panther Lake recap,” Doc. 866361, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/866361/ITT_2025_Panther_Lake_Recap1.pdf [2] Intel, “Core Ultra processors Series 3 datasheet, volume 1,” Doc. 872188-001, Jan. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/872188/872188-001.pdf [3] N. Horiguchi and E. Beyne, “Backside power delivery: How to power chips from the backside,” imec Reading Room, Nov. 25, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/how-power-chips-backside [4] W. Hafez et al., “Intel PowerVia technology: Backside power delivery for high density and high-performance computing,” in Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2, doi: 10.23919/vlsitechnologyandcir57934.2023.10185208. [5] K. Fischer et al., “Intel 18A platform technology featuring RibbonFET (GAA) and PowerVia for advanced high-performance computing,” in Proc. Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2025, pp. 1–3, doi: 10.23919/vlsitechnologyandcir65189.2025.11075006. [6] K.-F. Cheng, C.-L. Teng, H.-Y. Huang, and H.-C. Chen, “Metal oxide composite as etch stop layer,” U.S. Patent 12 176 247 B2, Dec. 24, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12176247B2/en [7] S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS J. Solid State Sci. Technol., vol. 4, no. 1, pp. N3029–N3047, 2015, doi: 10.1149/2.0051501jss. [8] A. V. Mule’, D. J. Towner, D. Seghete, C. R. Ryder, and A. A. Gonzalez, “Multi-layer etch stop layers for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20220102343 A1, Mar. 31, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20220102343A1/en [9] C.-C. Wang and J. H. Wang, “Interconnect structure with dielectric cap layer and etch stop layer stack,” U.S. Patent Appl. 20230253247 A1, Aug. 10, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20230253247A1/en [10] Y. J. Wu, K.-F. Cheng, C.-C. Lee, H.-K. Chang, and H.-Y. Huang, “Etch stop layer for interconnect structures,” U.S. Patent Appl. 20240332070 A1, Oct. 3, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240332070A1/en [11] M. G. Rainville, N. Shankar, K. S. Reddy, and D. M. Hausmann, “Deposition of aluminum oxide etch stop layers,” U.S. Patent Appl. 20180197770 A1, Jul. 12, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20180197770 [12] J. S. Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240112951A1/en [16] Applied Materials, “Applied Materials unveils chip wiring innovations for more energy-efficient computing,” Applied Materials Investor Relations, Jul. 8, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy [17] Samsung, “Samsung showcases AI-era vision and latest foundry technologies at SFF 2024,” Samsung Semiconductor, Jun. 13, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/ [18] C. W. Yeung et al., “Channel geometry impact and narrow sheet effect of stacked nanosheet,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2018, pp. 28.6.1–28.6.4, doi: 10.1109/iedm.2018.8614608. [19] S. Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
Kemper rebuilds its distribution structure as California diversification accelerates
Three leadership changes reflect a carrier managing a California correction while pursuing growth in Florida, Texas and specialty commercial auto
This US carrier doesn't want to let you use one phone number on two iPhones
It's an interesting strategy, holding off on supporting a new feature like this. iPhone Handoff is a new feature in the recently released iOS 27 which lets...
AT&T Responds to iOS 27's New iPhone Handoff Feature
Apple added a new iPhone Handoff feature to iOS 27 that allows you to switch between two iPhones while using the same phone number on each device. T-Mobile and Deutsche Telekom are the first carriers to offer iPhone Handoff, and Apple said Verizon and EE will add support later this year, but AT&T is noncommittal about the feature.
Sentara Health Plans raising premiums by 22.7% in Virginia’s individual market
Sentara Health Plans’ planned rate increase is the highest average increase of any carrier that will be offering comprehensive individual health insurance coverage in Virginia in 2027, according to the state insurance bureau.
One mobile number, two phones: What is iPhone handoff and which carriers support it?
Apple's new iPhone Handoff feature for iOS 27 allows users to share phone numbers, messages, wallets and more between two iPhones seamlessly. Let's set it up.
From Watts to L.A. wildfires: The rise of California's troubled FAIR Plan
As leading insurers have retreated from California, one carrier has stepped in to fill the gap.
Oscar Health (OSCR) Bets On Lucy As CEO Calls Time On Employer Coverage
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Iran war has cost $45.1 billion, Pentagon tells Congress
The US war with Iran has cost $45.1 billion, the Pentagon informed Congress on Friday, according to one source familiar with the matter.
Why life insurers are losing clients they already won
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House votes to limit Trump’s Iran war powers for the third time
The House on Tuesday voted to approve a measure that would require President Donald Trump to end his war with Iran, offering a potent political rebuke of the administration’s handling of the war just weeks before the midterms.
Press kit: Alaska Airlines unveils its international Business Class Suites experience - Alaska Airlines, Hawaiian Airlines and Horizon Air
Alaska Airlines has debuted its all-new International Business Class, a premium long-haul experience launching this spring as the airline expands to Europe and Asia. The unveiling marks a significant milestone in Alaska’s transformation into the West Coast’s global carrier and Seattle’s new leader in international travel — one that now connects guests to over 900 worldwide destinations through the oneworld alliance. International Premium Class also has an elevated guest experience, including an amenity kit designed in collaboration with Filson.
FOCUS Names Mark Phillips Senior Vice President of Business Development
FOCUS, the AI-enabled operations partner that has built and run the operations behind property and casualty carriers and MGAs for more than 25 years, today announced that Mark Phillips has joined the company as Senior Vice President of Business Development. Phillips will lead the FOCUS sales organization as the company expands its Launch, Grow, and Scale services and its new strategic partnerships, including its new listing in the Accelerant Marketplace.
Verizon Wireless, T-Mobile resolve lawsuits over ad campaigns
Verizon wireless and T-Mobile have resolved lawsuits accusing each other of misleading consumers with advertising claims about savings from switching carriers.
iOS 27's iPhone Handoff Feature Expanding to More Carriers This Year
Apple last week announced that Verizon and EE will support iOS 27's new iPhone Handoff feature later this year. The feature allows you to switch between any two iPhones running iOS 27 while using the same phone number on each device. iPhone Handoff is initially supported by T-Mobile (which is charging $5/month for it) and Deutsche Telekom. iPhone Handoff is initially supported by T-Mobile (which is charging $5/month for it) and Deutsche Telekom.
Amazon suspends use of 21 Air, cargo carrier whose plane careened off runway
The North Carolina carrier had flown packages for Amazon since 2024
Amazon suspends use of 21 Air, cargo carrier whose plane careened off runway
The North Carolina carrier had flown packages for Amazon since 2024
Amazon suspends use of 21 Air, cargo carrier whose plane careened off Miami runway
Amazon says it has suspended its partnership with 21 Air after one of the cargo carrier’s planes careened off a Miami runway last week and killed five people.
T-Mobile is giving away the Apple iPhone 18 Pro for free
The time has come. The iPhone 18 Pro has been announced, and mobile carriers are scrambling to offer you the best pre-order deals.
The Power of Shared Pregnancy: Parents Build Bonds Before Babies' Arrival
Soft squeals of joy interrupted the quiet at the Birth Center of Denver each time a new stroller pushed its way through the door.“You guys, look at us!” said new mom Courtney Allison, with her 6-week-old snuggled into her baby carrier.“Yeah, we’re like parents and stuff,” fellow new mom Riley Russell responded.Moms were beaming. After ...
Here are the iPhone 18 Pro (Max) and iPhone Duo offers from Apple and the big US carriers
Pre-orders for the iPhone 18 Pro and 18 Pro Max start tomorrow, while the foldable iPhone Duo won't be available until late October.
Gophers football adds new commercial logo on helmets
The Gophers athletic department has opened up a new revenue stream, via a sponsorship sticker for its football helmets this season, sources told the Pioneer Press. With a new NCAA rule allowing a few spaces for commercial logos on jerseys, apparel and equipment this year, the bottom rear “bumper” of Minnesota’s helmets will now have branding for Visible, a budget mobile phone carrier owned by ...
What a Business Owner’s Policy Covers and Leaves Out
Northern Nevada Insurance Agency, an independent agency in Reno, quotes business owner’s policies across multiple carriers for restaurants, retail stores, rental property owners, contractors and professional offices. The bundle covers commercial property, general liability and business interruption, while workers’ compensation, commercial auto and professional liability are separate policies the agency reviews alongside it. Reno, NV, Sept. 11, 2026 (GLOBE NEWSWIRE) -- A business owner's policy i
T-Mobile to Charge $5 a Month for iOS 27 iPhone Handoff
T-Mobile will charge customers $5 per month to use iPhone Handoff, an e-SIM feature that allows the same phone number to be used on two separate iPhones. iPhone Handoff requires carrier support, and at launch, only T-Mobile users in the U.S. and Deutsche Telekom users in Germany will be able to use it. T-Mobile says customers can use their number across two compatible iPhone models and elect which phone is active at any given time.
AT&T CEO drops a hot take on the new Apple iPhone Duo
The CEO of one of Apple’s biggest carrier partners did not mince words.
Buffalo River Aviation can fly under own authority
Bentonville-based Buffalo River Aviation Services LLC recently received its Federal Aviation Administration Part 135 air carrier certificate, enabling the company to operate on-demand private charter flights under its own authority....
Buffalo River Aviation can fly under own authority
Bentonville-based Buffalo River Aviation Services LLC recently received its Federal Aviation Administration Part 135 air carrier certificate, enabling the company to operate on-demand private charter flights under its own authority....
You Can Get Up to $1,200 Towards an iPhone 18 Pro with Apple's New Carrier Trade-in Incentives
Anxious to get your hands on the new iPhone 18 Pro? Apple announced new carrier trade-in offers and also recently boosted trade-in values. Just make sure you do this to get top dollar for your old device.
iPhone 18 Pro Models and iPhone Duo Feature Apple's New C2 Modem
Apple today unveiled new iPhone 18 Pro models and the iPhone Duo – the company's first foldable iPhone – and all three devices feature Apple's new custom-designed C2 modem for 5G connectivity. Prior to today's announcements, there was speculation that Apple's C2 in-house modem would not support mmWave 5G in the U.S., and that the company would once again rely on Qualcomm to fill the gap for American carriers. Apparently, that's not the case.
iPhone 18 Pro Details Purportedly Leaked By Verizon's AI Assistant
A series of screenshots shared with MacRumors today seemingly show Verizon's AI chat assistant answering detailed questions about the iPhone 18 Pro and iPhone 18 Pro Max, just hours before Apple's announcement event. The screenshots were shared privately with MacRumors by X user "mehrtosh," who says the responses came from the "Ask Verizon" AI assistant built into the carrier's app.
Explainer: Why Air India's funding call has come under political scrutiny in Singapore
Air India's request for about $1.5 billion in funds from its owners — Tata Sons and Singapore Airlines — has sparked a debate in Singapore over state investor Temasek's exposure to the Indian carrier.
Opinion: The Colorado Option is failing to meet the needs of small businesses for healthcare coverage
State must hold insurance carriers accountable to targeted premium reductions or fewer businesses will be able to afford healthcare for employees.
Opinion: The Colorado Option is failing to meet the needs of small businesses for healthcare coverage
State must hold insurance carriers accountable to targeted premium reductions or fewer businesses will be able to afford healthcare for employees.
Aviva launches fronting unit amid rising reinsurer demand for MGA business
Aviva believes demand from reinsurers for MGA business and heightened scrutiny of some specialist fronting carriers will support growth at its newly created hybrid fronting unit, chief commercial director Matthew Gordon and head of global hybrid fronting John Andrews told The Insurer.
CDL training school says closure by federal officials ‘political’
The Federal Motor Carrier Safety Administration cited graduates of United CDL for not having the requisite English language skills to earn their licenses.
T-Mobile customers will soon be able to use the same number on two iPhones
T-Mobile seems to be the only US carrier actively testing the feature.
Principal closes Beam deal, adding digital small business platform
The acquisition is less about premium volume and more about how carriers are competing for small employer relationships
American Airlines Bolsters Maintenance Workforce to Combat Broken Seats, Wonky Tray Tables And Defective In-Flight Entertainment Systems
American Airlines has hired more than 60 additional maintenance technicians to finally get to grips with what the carrier’s frequent flyers, pilots, and flight attendants know all too well… the upkeep of its airplane cabins hasn’t been a big enough priority for far too long, with broken seats, wonky tray tables, and defective in-flight entertainment…
Android 17 Adds OS-Wide ECH to Hide Website Visits From Network Providers
Android 17 adds OS-wide ECH, local network permissions, default certificate transparency, and carrier-controlled 2G blocking.
Android 17 boosts network security by hiding domain names, lets carriers disable 2G
Google is out with a blog post today recapping new network security measures in Android 17. These four features...
Submission friction now beats price in where agents place business, Ivans finds
Ninety per cent of agents have cut business with a carrier specifically because of submission friction. That figure is the data-backed version of what every commercial lines agent already knows: re-keying data costs real placements, and it is no longer just a frustration - it is a distribution strategy decision
Scientists discover asymmetric diffusion of magnetic skyrmions in simulations
Magnetic skyrmions are nanoscale spin textures that can behave like particles and move and diffuse in real space. This makes them promising information carriers for future memory and computing technologies. A new computational study in npj Spintronics shows how geometry and topology can guide asymmetric thermal diffusion of magnetic skyrmions, offering insights for unlocking unconventional computing paradigms, including future stochastic and neuromorphic computing devices for more efficient artificial intelligence (AI) applications.
iPhone 18 Pro Release Date Has Already Crushed The Competition
Apple’s September 9th release date for the iPhone 18 Pro squeezes Android rivals out of the holiday launch window and dominates carrier upgrade cycles.
There Are Carrier Pigeon Apps Now Because Pigeon Technology Is Actually Superior
The original wireless carriers.
As USS Lincoln heads home, mental health experts tally the stressors of life at sea
The USS Abraham Lincoln is now on its way home after spending nine months at sea. Experts weigh in on the mental-health challenges of prolonged confinement and isolation aboard an aircraft carrier.
As USS Lincoln heads home, mental health experts tally the stressors of life at sea
The USS Abraham Lincoln is now on its way home after spending nine months at sea. Experts weigh in on the mental-health challenges of prolonged confinement and isolation aboard an aircraft carrier.
Exclusive: Navy weighs renaming carrier slated to honor Black war hero, potentially switching it to Trump
The US Navy is working to rename an aircraft carrier under construction that was set to honor a Black sailor hailed for his heroic actions during the attack on Pearl Harbor, three sources familiar with internal discussions told CNN.
Anxiety grips Pacific allies as Trump pulls back
President Trump's move to curtail military drills with South Korea has stoked anxiety in Asia, as the region's sole U.S. aircraft carrier heads to the Mideast.
American to add seatback entertainment screens to narrowbody fleet
US carrier reverses a bet on personal devices as it races to close the cabin gap with Delta Air Lines and United Airlines.
USS Washington to relieve USS Lincoln after concerns about the crew's mental health
The carrier USS Washington is on its way to the Middle East to relieve the USS Lincoln. The Lincoln has been at the center of concerns over crew mental health and a lack of fresh food and supplies.
OPM's Health Claims Data Collection Raises Legal Questions
OPM's push to collect medical claims data from Federal Employees Health Benefits carriers raises privacy concerns. Affects 8M+ federal employees. Read the...
US Commander Says Mental Health a Priority Aboard USS Lincoln
A top US military commander said mental health is a valid concern after meeting crew deployed on the USS Abraham Lincoln, where conditions aboard the aircraft carrier have led to complaints during its long deployment in the Iran war.
USS Abraham Lincoln has among lowest mental health case levels: CENTCOM chief
Adm. Brad Cooper praises crew's resilience amid reports of concerns over sailors' well-being, conditions aboard aircraft carrier | Anadolu
US admiral praises USS Lincoln crew amid reported mental health concerns
Politicians voiced alarm over mental health struggles on carrier, with reports of sailors attempting to jump overboard.
Top Admiral Praises Sailors but Concedes Hardships After Visit to U.S.S. Lincoln
Admiral Brad Cooper, head of U.S. Central Command, acknowledged the difficulty of the carrier’s nearly nine-month deployment but said mental health issues were lower than on other vessels.
CENTCOM commander touts USS Abraham Lincoln mental health record after more than 260 days without port call
CENTCOM Adm. Brad Cooper said the Lincoln's leadership has prioritized mental health as the carrier nears the end of its extended deployment.
U.S. pulls last aircraft carrier in Asia as Trump focuses on other regions
The USS George Washington is departing the Pacific and expected to replace the USS Abraham Lincoln in the Middle East
Trump says USS Abraham Lincoln deployment 'not nearly long enough'
Lawmakers are pressing for answers amid reports that sailors aboard the San Diego-based carrier have endured food shortages, plumbing failures and severe fatigue.
‘Very outdated’: Trump’s directive to revert to steam catapults on new aircraft carrier baffles naval experts
President Donald Trump has directed the US Navy to scrap the modern electromagnetic launch system on an upcoming aircraft carrier and instead revert to an older, steam-powered catapult method — potentially adding billions to its price tag and delaying its deployment into the late 2030s.
Trump says USS Lincoln’s deployment was ‘not nearly long enough’
President Donald Trump on Friday dismissed claims that families of service members aboard the USS Abraham Lincoln have concerns about conditions aboard the aircraft carrier, which has been deployed for nearly nine months supporting operations in the Middle East.
'These reports are FALSE': Pentagon responds to mental health concerns on aircraft carrier involved with Iran War
Democrats are demanding answers following reports of supply shortages, poor living conditions and mental health concerns.
'These reports are FALSE': Pentagon responds to mental health concerns on aircraft carrier involved with Iran War
Democrats are demanding answers following reports of supply shortages, poor living conditions and mental health concerns.
'These reports are FALSE': Pentagon responds to mental health concerns on aircraft carrier involved with Iran War
Democrats are demanding answers following reports of supply shortages, poor living conditions and mental health concerns.
'These reports are FALSE': Pentagon responds to mental health concerns on aircraft carrier involved with Iran War
Democrats are demanding answers following reports of supply shortages, poor living conditions and mental health concerns.
Trump orders Navy to use older system of launching jets off aircraft carriers
The new mandate would likely cost billions of dollars and revert the Navy's most advanced ships to a system that takes more sailors to operate and is more difficult to maintain
Families concerned about reports of mental health crisis on USS Lincoln
Families of marines are voicing concern over reports about the USS Abraham Lincoln, a naval aircraft carrier based in San Diego that has been in the Middle East supporting the Iran war for over 200 days. Families say their loved ones onboard are dealing with food shortages, plumbing problems and mental health issues. NBC News’ Dan De Luce reports on the lawmakers demanding answers and the broader implication that the war in Iran is having on the military.
'iPhone Ultra' Could Face Staggered Country Rollout Like Vision Pro
Apple's foldable "iPhone Ultra" may get a Vision Pro-style staggered country-by-country launch over several months, with initial availability limited to the U.S. market, according to an Australian publication. In a report labeled "exclusive," ChannelNews said today it has been told by local carriers and one major retailer that Apple's first foldable iPhone will be a "no show" when the iPhone 18 Pro models launch in September, despite being unveiled together.
Jeff Lightner
Jeff Lightner has been appointed Chief Growth Officer for Marsh McLennan Agency’s Midwest Region, to help shape the region’s growth strategy across talent and growth capital, carrier economics and sales operations.
Navy meets with USS Abraham Lincoln families over mental health worries
Navy leadership has reportedly met with the family members of sailors aboard the USS Abraham Lincoln aircraft carrier over worries that the ongoing Middle East deployment will lead to worsening men…