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Hawaiʻi Pacific Health gives $100,000 to Family Promise of Hawaiʻi for security deposit program
Hawaiʻi Pacific Health has awarded $100,000 to Family Promise of Hawaiʻi to help families with children experiencing homelessness or housing instability cover security deposits, according to an Oct. 29 announcement. The nonprofit will use the money to launch its Move-In Advance Program. Under the program, Family Promise of Hawaiʻi will pay a family’s security deposit […]
Ministers confirms two new cancer drugs will not be covered by basic health insurance
The drug Enhertu will not be included in the basic health insurance package to help patients with metastatic stomach cancer. Negotiations with the manufacturers over the drug’s price have failed to produce a sufficient agreement, Health Minister Sophie Hermans wrote in a letter to the Tweede Kamer. The drug Skyclarys will also not be included in the basic insurance package.
Why salespeople should keep selling during the holidays
Expert: Holiday sales slowdowns create opportunities to build client relationships, strengthen connections and develop new business.
Tesla Cybertruck eulogy: I loved it. I was wrong about it.
I put down a $100 deposit on Tesla's Cybertruck, then bought a Model 3. Here's my eulogy for the pickup I loved and was wrong about.
NJBIA launches litigation center to defend businesses
NJBIA and NJ Civil Justice Institute launch the New Jersey Litigation Center to protect businesses from regulatory and legal challenges.
Telos promotes new CEO
Telos announced that its board of directors appointed Executive Vice President Mark Griffin as CEO effective Monday
Payroll processing issue leaves Novant Health employees waiting for pay
A technical issue has delayed pay deposits for thousands of Novant Health employees, according to emails shared with WECT.
Payroll processing issue leaves Novant Health employees waiting for pay
A technical issue has delayed pay deposits for thousands of Novant Health employees, according to emails shared with WECT.
Payroll processing issue leaves Novant Health employees waiting for pay
A technical issue has delayed pay deposits for thousands of Novant Health employees, according to emails shared with WECT.
Payroll processing issue leaves Novant Health employees waiting for pay
A technical issue has delayed pay deposits for thousands of Novant Health employees, according to emails shared with WECT.
Payroll processing issue leaves Novant Health employees waiting for pay
A technical issue has delayed pay deposits for thousands of Novant Health employees, according to emails shared with WECT.
Payroll processing issue leaves Novant Health employees waiting for pay
Novant Health says a technical issue delayed employee pay deposits. The health system says employees will be paid, though deposit times may vary by bank.
Novant Health Beaufort County employees report delayed paychecks
Novant Health says payroll delay in Beaufort County is fixed after employees miss Friday direct deposits
Jags fans can put down deposit now for shot to buy 2027 season tickets
Jacksonville will play home games at Orlando's Camping World Stadium that season while its stadium is undergoing renovations.
Ueno Bank liquidation triggers Paraguay political turmoil and impeachment move against Peña
The accounting black hole at Ueno Bank is wiping out public funds, leaving thousands without access to their deposits and pushing Paraguay into its worst institutional crisis in years.View on euronews
Nov. 5 talk: Using chemical vapor deposition to improve battery materials
Jeffrey Elam, senior chemist and Argonne Distinguished Fellow at Argonne National Laboratory, will present “Chemical vapor fictionization of battery materials” at 3:05 p.m. on Thursday, Nov. 5, in 10 Sparks Building on the University Park campus.
Vantage Launches Facultative Reinsurance Business, Names Pickard as President
Vantage Group Holdings Ltd., the Bermuda-based re/insurer, announced the launch of its Facultative Reinsurance line of business, led by industry executive
Wells Fargo to lay off 87 workers in Roanoke County
Wells Fargo will eliminate 87 positions in Roanoke County, with layoffs scheduled through November and December 2026.
Buitoni to close Danville plant, lay off 251 employees
Buitoni plans to close its Danville pasta plant Dec. 28, eliminating 251 jobs as the company prepares to shut down operations.Buitoni plans to close its Danville pasta plant Dec. 28, eliminating 251 jobs as the company prepares to shut down operations.
What First Business Financial Services (FBIZ) Said on Its Q3 Earnings Call
First Business Financial Services (NASDAQ:FBIZ) reported record third-quarter 2026 pre-tax, pre-provision and bottom-line earnings, supported by loan and deposit growth, an expanded net interest margin and lower expenses. President and CEO Dave Seiler said earnings per share increased 6% from the s
American Express Connects Cash Back to High Yield Savings Accounts and Business Checking Accounts
NEW YORK, October 29, 2026--Today, American Express introduced a new way for eligible U.S. Consumer and Business Cash Back Card Members to redeem rewards for a deposit into eligible American Express bank accounts, creating a more integrated experience across their Card and banking products and giving customers more options in how to redeem the rewards they earn.
Rize Credit Union Launches New Small Business Deposit Experience with Enable Technologies
On-schedule implementation expands Rize's ability to serve small businesses, deepen member relationships, and create new opportunities for growthSAN FRANCISCO, CA / ACCESS Newswire / October 27, 2026 / Rize Credit Union, with roughly $1.3B in assets based in Irwindale, CA, today announced the successful launch of its new small business deposit account opening experience, powered by ("Enable").
Business First Bancshares (BFST) Is Back In Focus, What Is The Market Weighing?
Business First Bancshares (BFST) is back in focus after third quarter results topped earnings expectations, accompanied by stronger loan and deposit trends, wider net interest margin, and tighter cost control following the Progressive Bank integration. Business First Bancshares’ latest update has arrived after a year of solid progress, with the share price at $31.82 and a clear shift in sentiment following the earnings beat, active buybacks, and fresh common and preferred dividend...
St. Joseph County shops warn of fake $50s after business owner loses money on deposit
Businesses in St. Joseph County are reporting counterfeit $50 bills, with one local business owner speaking out to warn others after discovering a bill she rece
Judge insists Trump must be deposed in his $10B lawsuit against the BBC, warns it could be tossed in fight over records
A federal judge warned President Donald Trump could see his $10 billion defamation lawsuit against the BBC dismissed if he does not work harder to produce information the news outlet it is entitled to in the case, including sitting for a deposition.
Judge directs President Trump to sit for deposition in his $10 billion lawsuit against the BBC
Trump had agreed to sit for a deposition on Oct. 16, but it was cancelled for what was described as a “matter of national importance.”
Forge Nano to Trade on NASDAQ as NANO After Completing Business Combination with Archimedes Tech SPAC Partners II Co.
Forge Nano common stock and warrants expected to begin trading on NASDAQ on October 22, 2026 under the symbols “NANO” and “NANOW,” respectivelyPublic listing positions Forge Nano to accelerate growth across semiconductor manufacturing equipment and advanced battery technologies DENVER, Oct. 21, 2026 (GLOBE NEWSWIRE) -- Forge Nano, Inc., a leading U.S.-based semiconductor equipment and advanced materials company pioneering Atomic Layer Deposition (“ALD”) technology for artificial intelligence (“A
What makes Troy Aikman such an appealing option for CBS?
ProShooter/Depositphotos Troy Aikman’s ESPN deal ends in 2027 Troy Kenneth Aikman works as an NFL analyst for ESPN after playing quarterback for the Dallas Cowboys. His current broadcasting agreement runs through Super Bowl LXI, scheduled for February 2027. During an October 15 radio interview in Dallas, Aikman said he expected to become a free agent.…
Rochester colleges expand mental health workforce training amid shortages
Rochester colleges like Nazareth and St. John Fisher expand mental health training programs to address workforce shortages and improve community access.
Kansas girls flag football championship halted following fatal crash
Depositphotos Kansas championship games suspended after fatal incident at soccer complex Kansas’ inaugural girls high school flag football championship was interrupted on October 17 after a fatal incident at Stryker Sports Complex in Wichita left 2 people dead and 10 others injured. The incident occurred on a nearby youth soccer field, prompting the Kansas State…
Tulsa Health Department to host 10th annual community baby shower
The Tulsa Health Department will host its 10th annual North Tulsa Community Baby Shower Oct. 24 for eligible families.
A director’s 9,271-unit stock grant at Tencent Music (TME) vests one year after the grant date.
Jeanette Kim Yum Chan received 3,155 American depositary shares from vested awards on October 15, 2026, with direct holdings afterward of 39,066.
Idaho receives $329,000 federal grant to boost small business exports
Idaho secures a $329,000 federal grant through the State Trade Expansion Program to help small businesses expand into international markets.
What a subscription business actually automates when it sets up recurring billing
The word "automatic" in subscription billing can mean two very different things depending on which part of the process it describes.
Oklahoma City, OKCPS receive $11.5M for youth mental health
Oklahoma City and OKC Public Schools received $11.5 million in federal grants to expand youth mental health services and school-based support.
NFL fans question Donald Trump’s choice of Week 6 game
Ale_Mi/Depositphotos Donald Trump cancels NFL game visit President Donald Trump was reportedly planning to attend the Pittsburgh Steelers game against the Tampa Bay Buccaneers on October 18, 2026. CNN correspondent Kristen Holmes first reported the expected visit on October 13. The game was scheduled for a Sunday afternoon kickoff at Raymond James Stadium in Tampa,…
How payment data connects Dogecoin transactions to business records
From transaction hashes to invoice IDs, payment systems need a way to connect blockchain activity with the commercial records Maryland businesses use every day.
WaPo to close Springfield printing plant, cut 118 jobs
The Washington Post plans to close its Springfield printing plant and lay off 118 employees by the end of 2026 or early January
76ers could explore an unexpected plan involving LeBron James
headlinephotos/Depositphotos Philadelphia 76ers consider James at center The Philadelphia 76ers are considering LeBron James as a possible backup center for the 2026–27 NBA season. Coach Nick Nurse discussed the option on October 7 following injuries within Philadelphia’s frontcourt. Nurse identified James among several players who could provide minutes at center when needed. James, who joined…
Battle Over the Pierre Ends in Defeat for the Buyer Pushed by Lutnick
Motasem Khashoggi, who hails from a prominent Saudi family, missed a Tuesday deadline to deliver a $100 million deposit to purchase the Manhattan landmark.
Litecoin Shows How Multi-Rail Business Payments Are Taking Shape
Payment infrastructure is becoming a broader business decision as companies collect money through digital channels and connect those transactions with established financial operations.
Why Immigration Policy Changes Matter to Virginia’s Workforce and Employers
Immigration policy changes may feel like a macro event to some, but they can have drastic effects on the micro-details of the workforce, especially in
Are Bank Lobbies Still Relevant?
Local banking leaders say technology is changing the way customers use their banks — and their lobbies By Deborah Jeanne Post [caption id=attachment_11109 align=alignright width=300] Steve Gorczynski is M&T Bank Central New York regional president.[/caption] When was the last time you entered the lobby of your bank? If it’s been a while, you’re part of a trend of eschewing the lobby in favor of ATMs, drive-thrus, online banking and remote deposit. A 2025 study performed by the American Bankers Association revealed that only 9% of consumers use bank branches as their preferred way to do banking and 76% prefer mobile banking. The trend away from the lobby reflects consumer behavior in other areas of doing business, including online shopping instead of perusing the mall, ordering fast food at a kiosk, not at the counter and selecting curbside pick-up rather than walking into the restaurant. Consumers want convenience and going in the lobby adds another layer to the task. It also places consumers face to face with one or more representatives of the business, something less favorable to people feeling burned out from interpersonal interactions. Nixing or at least minimizing the size of the lobby isn’t necessarily negative for banks. Fewer people passing through their doors reduces overhead for building maintenance, staffing and furnishing. Greater reliance on virtual banking can mean closing brick and mortar locations and hiring fewer staffers to cover roles like teller and lending officer. “Our focus is on meeting customers where they are and giving them flexibility in how they bank,” said Steve Gorczynski, M&T Bank Central New York regional president. “While many everyday transactions can be supported digitally and through ATMs, branches remain important for more complex financial needs, offering face-to-face guidance and a more personal banking experience.” Talking with a commercial lender or working on a home mortgage are two examples where meeting face-to-face is more desirable for many people. They can receive immediate feedback to questions and can possibly reach their goals more quickly. But there’s little need to have a large seating area, long counters and numerous tellers for routine banking that’s quicker to handle virtually. Online banking can also help people on the go more readily complete banking tasks such as depositing checks, transferring funds among accounts and checking balances. [caption id=attachment_11135 align=alignright width=300] Tina M. Stephens is the vice president branch administration for Fulton Savings Bank.[/caption] “The traditional bank lobby is certainly being evaluated by most institutions today, as the typical large, open and cavernous spaces do not necessarily meet the needs of today’s customers,” said Tina M. Stephens, vice president branch administration for Fulton Savings Bank. “Traditional lobbies often bisect traditional teller stations and customer service areas, which adds confusion, especially for the demographic who routinely use online banking and only access the lobby for customer service needs.” Despite the rollback in physical locations across the industry, Fulton Savings Bank began modernizing its six branch offices in Oswego and Onondaga counties about three years ago and have finished four offices so far in Baldwinsville, Fulton, Constantia, and Phoenix. “We made the decision to build a new branch across the street from our current office in Brewerton which will be completed by the end of 2026, and we will begin the retrofit of our Central Square office in early 2027,” Stephens said. “Our efforts specifically address where we think customers will be in the next three to five years and have greater flexibility to make changes out into the future.” The bank may be onto something, as numerous reports state that screen-weary Gen Z young adults crave more in-person interactions than virtual ones. If the pendulum continues to swing in that direction, it’s hard to see all physical bank areas disappear, even if they change somewhat. Fulton Savings Bank has also consolidated its teller and customer service representative areas to larger “universal banker” areas, where the bank representative can address all customer retail needs. A one-stop-shop experience appeals to busy banking customers who want to perform a few different banking tasks in one visit. Stephens also said that Fulton Savings Bank made additional technology and security enhancements and created flex spaces to accommodate bank meetings throughout the two-county branch footprint. At Solvay Bank, Elizabeth Lavier, vice president marketing and communications manager, lauded digital and online services as convenient and flexible for managing finances; however, “technology is not meant to replace what matters most: the relationships behind every account that have always been at the heart of community banking,” she said. “Even in today’s digital-first world, people of all ages still value the opportunity to sit down with a trusted banker for personalized guidance. We understand that some of life’s biggest moments call for more than a screen.” Lavier views digital banking as another way for the organization to serve customers rather than a replacement for branches, tellers and lenders, which tend to serve customers better for transactions like buying a first car, purchasing a home, saving for a child’s education, or planning for retirement. “Those conversations, built on understanding, experience and personal guidance, are what community banking is all about,” Lavier said. “At the end of the day, banking is about more than transactions. It’s about helping our customers achieve their goals and being there for them every step of the way. By combining the convenience of digital banking with the care, commitment, and personal service of a local community bank, Solvay Bank offers customers the best of both worlds.” Are Paper Checks Destined to Disappear? With the ubiquity of debit cards, online payments, virtual checks and peer-to-peer payment platforms like Venmo, Zelle and PayPal, will paper checks become passe? “In my view, paper checks are unlikely to disappear in the near future,” said Tina M. Stephens, vice president branch administration for Fulton Savings Bank. “They continue to serve a practical purpose by providing a clear paper trail and tangible proof of payment.” According to the American Banker, a leading trade publication that covers the banking and financial industry, in 2024, checks accounted for 65% of all payment fraud losses. Paper checks should be phased out, according to the publication. “The phrase, ‘The check’s in the mail’ probably sounds strange to younger people because the era of paper checks is rapidly drawing to a close. Put bluntly, checks are an expensive, insecure legacy that is a drag on the U.S. economy. Rather than wait for them to vanish slowly, the pragmatic choice is to strategically accelerate the transition to paperless payments.”
Maxx Crosby reveals what stands out when tackling Patrick Mahomes
Image Press Agency/Depositphotos Crosby shares a surprising detail about Mahomes’ reaction Maxx Crosby and Patrick Mahomes may be fierce rivals on the field, but their latest encounter has revealed a funny detail about their battles. The Las Vegas Raiders defensive end shared what he notices when he gets close enough to hit the Kansas City…
Georgia enters October undefeated as the challenging SEC schedule intensifies
ALesik/Depositphotos Georgia enters October with a perfect record Georgia’s 2026 football schedule brings a major change as the SEC moves to a nine-game conference slate. The Bulldogs face familiar rivals, new scheduling twists, and several challenging road trips, while the annual Florida matchup temporarily leaves Jacksonville. Alabama, Ole Miss, Oklahoma, Auburn, and South Carolina are…
Inside Ken Paxton’s private testimony about his money
The leaked deposition from a fraud inquiry in 2014 provides insight into the Senate candidate’s investments and his tactics for defending himself.
Virginia furniture retailer Haynes and The Dump to close
Virginia Beach-headquartered top 100 furniture retailer Haynes Furniture and The Dump will close permanently. Virginia Beach-headquartered top 100 furniture retailer Haynes Furniture and The Dump will close permanently.
NJ LLCs can end alternate business names early under new law
New Jersey LLCs can now terminate alternate business names before the five-year period ends, providing greater flexibility under a new law.
Gov. Moore insists Maryland’s budget is balanced; watchdog calls it 'political math'
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Trump bucks and the politics of mailing checks
The checks started going out last week, nearly one million of them, and mostly to battleground states. With a return address for the U.S. Treasury and a letter enclosed signed by President Donald Trump, these one-time checks for $500 were ostensibly government rebates for Obamacare enrollees who overpaid. In the accompanying letter, however, Trump attacks his predecessor and talks about his record in office on an important issue he’s not polling well on, which makes it seem more like the most expensive political mailer in U.S. history. The average piece of direct mail costs between 30 cents and $3, according to Mail Processing Associates, a print, mail, and fulfillment company. At $500 a pop plus roughly 50 cents each to issue the paper check, the cost of Trump’s healthcare mailer sent to more than 950,000 enrollees comes in at more than $475 million. Trump’s midterm healthcare message “For years, the Biden Administration overcharged you to fund the operation of HealthCare dot gov,” Trump wrote in the letter. “That money belongs to hard-working Americans, not the Government, and now, I am returning it to you!” In the letter, Trump makes false and misleading claims about his administration’s record on healthcare costs, an issue Democrats have a 20 point advantage on over Republicans, according to a recent poll from KFF, a nonpartisan health policy think tank. Trump touts his administration’s TrumpRX program, which he claims is “delivering massive discounts.” However, new research from KFF found that of a selection of drugs available on the TrumpRX platform, just five were the lowest price, while 13 were the highest price. Trump also falsely claims in the letter that he’s fighting to lower healthcare costs. In reality, average monthly premium payment costs for enrollees rose 58% under Trump while marketplace sign-ups declined 5%, per KFF. Under Trump’s One Big Beautiful Bill Act, it’s estimated 10 million more Americans will be uninsured by 2034. You get a check and you get a check and you get a check Trump’s long promised cash outs to his fans, from his days as a casino operator and gameshow host to his presidency. During the early days of the COVID-19 pandemic in 2020, the first Trump administration made the unprecedented move to put Trump’s name on checks that went out under the CARES Act (notably the $500 refund checks this time around don’t feature Trump’s name). Ever since, Trump’s been chasing that high. In his second term, Trump’s promised more stimulus that never arrived, like refund checks from DOGE cuts and tariffs, while he said at his party’s convention last month that he’d give out $5,000 checks to everyone if Republicans win in November. In reality, DOGE overstated its cost cutting and Trump’s government actually now spends more than former President Joe Biden’s, while Trump’s tariffs actually grew the trade deficit. His proposal for $5,000 checks would add about $1.2 trillion to the national debt. The problem is there’s no money to give. These $500 checks — plus $90 Medicare rebate checks also going out as well as $250 deposited this week in some Trump Accounts for kids courtesy Dell Technologies CEO Michael Dell and his wife Susan — represent the closest Trump’s going to get to making good on his promise to deliver cash fast. And the checks seem especially targeted. Though the $500 checks went out to enrollees in one of 30 states that use the federal HealthCare dot gov marketplace, a Reuters review found 71% of the payments, or $339 million, went to enrollees in 13 states that have the most competitive elections for governor and U.S. Senate. Most Americans don’t buy it Could Trump bucks sway the election? An Economist-YouGov poll found 57% of U.S. adults doubt Trump will deliver on his promise for $5,000 checks, compared to 21% who do. “I’m waiting on my DOGE check and I’m still waiting on my tariff check,” one 2024 Trump voter who’s since turned on him told a recent focus group. “It felt like kind of trying to buy people’s votes, which honestly felt like in elementary when the class president was like, hey we’re going to take you to the water park if you vote for me. It’s like, I don’t think it works like that.” But for voters in swing states who got a check, it could still matter. One survey published in 2022 found receiving a physically personalized check in the mail during the pandemic was associated with a much greater self-reported likelihood of voting for Trump in 2020, and those gains mainly came from out partisans. The issue for Trump comes if these checks are mostly going to Obamacare enrollees whose premiums have gone up by more than just $500 since he took office and who view the money as something like a bribe before the election rather than an actual long-term solution to lowering household costs. Spending $500.50 per mailer would be absurd as a normal campaign expenditure, but since Trump’s checks and letter are a government rebate, his campaign and super PAC didn’t have to spend a dime and he got out his message regardless. If enough voters in key states are swayed by the one-time payment, it could prove to be the best $0 the Trump campaign spent. Subscribe [ ](https://www.yellopolitics.com/p/why-independent-candidates-are-making) [ Why independent candidates are making independence central to their brand ](https://www.yellopolitics.com/p/why-independent-candidates-are-making) Hunter Schwarz · Oct 6 [ Read full story ](https://www.yellopolitics.com/p/why-independent-candidates-are-making) [ ](https://www.yellopolitics.com/p/these-designers-and-grocery-nerds) [ These designers and grocery nerds will brand Mamdani’s NYC grocery stores ](https://www.yellopolitics.com/p/these-designers-and-grocery-nerds) Hunter Schwarz · Oct 2 [ Read full story ](https://www.yellopolitics.com/p/these-designers-and-grocery-nerds) Trump wants to turn his first-ever golf course into a government course for presidents
Former Super Bowl champion changes tune on Patrick Mahomes
Image Press Agency/Depositphotos Jason McCourty reverses Chiefs opinion Former NFL defensive back and Super Bowl LIII champion Jason McCourty said he felt like an idiot for doubting Patrick Mahomes and Kansas City after watching the Chiefs open the 2026 season with 3 victories. McCourty made the admission during an ESPN discussion before Kansas City’s Week…
Insurance leaders in Rochester highlight common business coverage gaps
Rochester insurance leaders discuss common business coverage gaps and emerging risks like cyber threats and AI to help companies protect evolving operations.
Deposition Sciences, Inc. Expands Sunshade® Tape Offering with New 12" × 30" Format
Deposition Sciences, Inc. Expands Sunshade® Tape Offering with New 12" × 30" Format
ConnectOne Bank joins program for lower-rate business loans in NY
ConnectOne Bank is participating in New York's Linked Deposit Program, which provides small and middle-market businesses access to lower-interest commercial loans. This initiative supports business expansion and innovation by reducing borrowing costs and improving cash flow for eligible companies across Long Island and New York State.
Construction employment and spending still down from last year
Construction employment on Long Island fell 2 percent year-over-year, with national construction spending down 1.7 percent.
Taylor Farms and Mexico’s Health Ministry Now Make the Same Cyclospora Argument. The Produce Industry’s Own Association, FDA and CDC Rejected It in September. Here Is a Specific Request to Eight People Before the Industry Meets in Orlando.
I spent four hours Sunday morning taking the deposition of an expert retained by the defense in the E. coli O157:H7 outbreak of November 2024 – the one
NASA and IBM's open source lunar model turns 17 years of orbiter data into a foundation for lunar science
NASA and IBM have released the Lunar Foundation Model, one of the first open-source AI models for lunar science. Trained on nearly 2 million tile bundles, mostly from 17 years of Lunar Reconnaissance Orbiter data, it cuts the error in predicting polar ice deposits by up to 22 percent compared to the strongest model it was tested against.
At $1.30 a share, Fin Posillipo buys depositary shares in Genenta Science (Nasdaq: GNTA).
Reporting persons may be deemed to own about 11.5% of shares and 18.94% of voting power. Fin Posillipo bought 110,000 ADSs August 7–19, 2026.
Idaho ranks second nationwide for small business growth
Idaho ranks No. 2 in the U.S. for small business growth with a 3.53% increase and 1,595 new businesses, according to OnDeck and U.S. Census data.
Ocean Floor “Pools Of Death” Could Be Key To Explaining The Origins Of Life On Earth, And Possibly Further Afield
Besides their importance for the search for life on other planets, these pools could help us find major mineral deposits.
NFL pregame shows face growing criticism from fans in 2026
rafapress/Depositphotos Fans react to changing NFL pregame shows NFL pregame coverage is drawing fresh attention during the 2026 season. Familiar formats and longtime personalities are facing criticism from some viewers. FOX, ESPN, CBS, and Prime Video have also made lineup changes across their NFL coverage. Major programs continue to attract large audiences, adding another layer…
Lamine Yamal says ‘I don’t care’ after stunning England
Musiu0/Depositphotos Lamine Yamal posts message after Spain win Lamine Yamal, a Barcelona forward, posted “Hate me or love me, I don’t care” on Instagram after Spain beat England 3 to 2 in the UEFA Nations League at Wembley Stadium on Sept. 26, 2026. Yamal scored the opening goal of that match and then shared the…
Hampton Roads workforce and entrepreneur development
The Apprentice School at Newport News Shipbuilding Founded in 1919, The Apprentice School in Newport News has graduated more than 11,000 apprentices over
Department of Health: Segregated rate revision to change how redemption centers pay for recycled bottles and cans
Hawaiʻi’s Deposit Beverage Container Program will change how redemption centers convert container weight into container counts starting Oct. 1, the state Department of Health announced.
NFL considers rule change after Eagles exploit kickoff loophole
FellowNeko/Depositphotos Eagles’ kickoff tactic sparks NFL rule debate The Eagles have sparked fresh discussion around an unusual kickoff tactic involving a holder and no tee. The approach helped Philadelphia create a different angle for kicker Jake Elliott during its Week 2 win over Tennessee. The technique has raised questions about how the NFL’s 2026 kickoff…
New rates for state Health Department’s deposit beverage container program take effect Oct. 1
The most significant change is the adoption of a new single rate for plastic.
Bipartisan bill would protect MD small business deposits
Commentary: U.S. Senators introduce the Main Street Depositor Protection Act to raise deposit insurance for small business accounts.
Erling Haaland and Kylian Mbappé battle for international scoring milestones
thenews2.com/Depositphotos Erling Haaland and Kylian Mbappé lead world scoring Erling Haaland and Kylian Mbappé remain among international soccer’s leading scorers in 2026. Haaland is Norway’s career goals leader, while Mbappé holds the same distinction for France. As of September 27, Haaland has scored 64 goals in 56 senior appearances for Norway. Mbappé has scored 67…
CT man accused of stealing, forging checks from local business and paying juvenile to deposit them
Investigators allege that the man contacted the juvenile to deposit the checks for him at different bank locations and said he would pay him $5,000.
Texts link Justin Baldoni’s crisis PR pro to 'smear' sites, complaint alleges
Top Hollywood publicist Melissa Nathan faces allegations of playing a key role in running 'smear' sites for embattled celebrities amid the Justin Baldoni legal saga. In a deposition, Nathan denied she was the mastermind behind the now-defunct stephaniejonesleaks.com.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. [1] Intel, “Intel Tech Tour 2025 Panther Lake recap,” Doc. 866361, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/866361/ITT_2025_Panther_Lake_Recap1.pdf [2] Intel, “Core Ultra processors Series 3 datasheet, volume 1,” Doc. 872188-001, Jan. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/872188/872188-001.pdf [3] N. Horiguchi and E. Beyne, “Backside power delivery: How to power chips from the backside,” imec Reading Room, Nov. 25, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/how-power-chips-backside [4] W. Hafez et al., “Intel PowerVia technology: Backside power delivery for high density and high-performance computing,” in Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2, doi: 10.23919/vlsitechnologyandcir57934.2023.10185208. [5] K. Fischer et al., “Intel 18A platform technology featuring RibbonFET (GAA) and PowerVia for advanced high-performance computing,” in Proc. Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2025, pp. 1–3, doi: 10.23919/vlsitechnologyandcir65189.2025.11075006. [6] K.-F. Cheng, C.-L. Teng, H.-Y. Huang, and H.-C. Chen, “Metal oxide composite as etch stop layer,” U.S. Patent 12 176 247 B2, Dec. 24, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12176247B2/en [7] S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS J. Solid State Sci. Technol., vol. 4, no. 1, pp. N3029–N3047, 2015, doi: 10.1149/2.0051501jss. [8] A. V. Mule’, D. J. Towner, D. Seghete, C. R. Ryder, and A. A. Gonzalez, “Multi-layer etch stop layers for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20220102343 A1, Mar. 31, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20220102343A1/en [9] C.-C. Wang and J. H. Wang, “Interconnect structure with dielectric cap layer and etch stop layer stack,” U.S. Patent Appl. 20230253247 A1, Aug. 10, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20230253247A1/en [10] Y. J. Wu, K.-F. Cheng, C.-C. Lee, H.-K. Chang, and H.-Y. Huang, “Etch stop layer for interconnect structures,” U.S. Patent Appl. 20240332070 A1, Oct. 3, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240332070A1/en [11] M. G. Rainville, N. Shankar, K. S. Reddy, and D. M. Hausmann, “Deposition of aluminum oxide etch stop layers,” U.S. Patent Appl. 20180197770 A1, Jul. 12, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20180197770 [12] J. S. Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240112951A1/en [16] Applied Materials, “Applied Materials unveils chip wiring innovations for more energy-efficient computing,” Applied Materials Investor Relations, Jul. 8, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy [17] Samsung, “Samsung showcases AI-era vision and latest foundry technologies at SFF 2024,” Samsung Semiconductor, Jun. 13, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/ [18] C. W. Yeung et al., “Channel geometry impact and narrow sheet effect of stacked nanosheet,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2018, pp. 28.6.1–28.6.4, doi: 10.1109/iedm.2018.8614608. [19] S. Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
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