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Review: Silent Hill: Townfall Largely Delivers on PS5 and Pro, Falls Short on PC
This unique setting deserves better.
The New Call of Duty Black Ops Port Charges $40/£35 for a Basic 1080p Upgrade
And doesn't even include the DLC.
Carnegie Mellon's AI Science Foundry Selected by NSF To Help Build National Infrastructure for AI-Enabled Scientific Discovery
Carnegie Mellon University's AI Science Foundry, one of the world's most advanced AI-powered research facilities, has been selected as a node in the U.S. National Science Foundation's (NSF) Programmable Cloud Laboratory (PCL) Testbed, a national initiative to build a network of AI-enabled laboratories.
Hands On with Xbox Back-Compat for PC - a New Initiative That Begins with Four Classic Games
A vital step for game preservation - that still needs some work.
Valve Would "Love to Make the Steam Machine More Affordable" - Just Don't Expect It "Any Time Soon"
If memory prices go down - and that's a big if.
Valley National Bank launches new technology platform
Valley National Bank launched Valley Foundry, a new platform to connect with startups and fintechs, advancing technology innovation across its regional markets.
Inside Gears of War: E-Day: How The Coalition and Epic Pushed Console Visuals To New Heights
Unreal Engine 5 MegaLights, Nanite skinning and much more at 60fps on console.
Digital Foundry Shares Its Initial Analysis Of Black Ops 1 For PS5 Vs. Xbox
"This is a deeply odd state of affairs"
Intel Just Secured a Huge Customer for Its Foundry Business
The tech company recently landed Fortinet as a customer of its foundry service.
GTA 6's Worldwide Release Times Revealed - with New Zealand Set to Receive Access 19 Hours Before Mexico and Central America
Will you become an honorary Kiwi to play early?
Foundry Park developers break ground on North Side megaproject
The start of the $800 million initial phase is a sign of progress for a broader commercial real estate industry that has gone cold on the city in recent years.
Digital Foundry: Zelda Ocarina of Time remake is 1080p and 60fps, but no DLSS
The big title this holiday season for Nintendo Switch 2 owners is the gorgeous The Legend of Zelda: Ocarina of Time remake. Naturally the tech sleuths at Digital Foundry have taken a look at the game…
GTA 6 and the Mystery of the Missing Ferris Wheel Reflection
Our experts chime in on the latest Grand Theft Auto trailer.
Review: Final Fantasy Resonance: Impressive 2D-HD Visuals, Excellent Performance on Every Platform
But what's up with image quality on Xbox Series S?
Video: Digital Foundry Delivers Its Tech Analysis Of Fire Emblem: Fortune's Weave
Fire Emblem dedicated Switch 2 release is here
MBA Roundup: Harvard Business School Uses AI Faculty Avatars To Teach Entrepreneurship Bootcamp
Harvard Business School introduces AI clones of faculty members to help teach students in its HBS Foundry course.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Both Sony and Microsoft look ready to drop disc drives from their next-gen consoles.
GTA 6 Could Skip 60 FPS Entirely, as Rockstar’s Insane Detail Forces a 30 FPS Lock Even on PS5 Pro
With GTA 6, Rockstar Games is set to raise the bar for what is possible to achieve on PlayStation 5 and Xbox Series X|S much like the studio did with Red Dead Redemption 2, but this is likely coming at a price. Although the highly anticipated next entry in the series is rumored to feature a performance mode running at 60 FPS, it is extremely unlikely this is real, as, according to the tech experts at Digital Foundry, the level of detail shown in the latest footage would make it very difficult to scale everything down to allow for 60 […]
Monday, June 22, 2026: The Club says this legacy tech stock's foundry business presents a major opportunity
Go behind the scenes with Jim Cramer and Jeff Marks of the CNBC Investing Club as they talk candidly about the market's biggest headlines, analyst calls and holdings in the Charitable Trust—and see up close how they decide when, and if, to take action on stocks.
AMD Announces FSR 4.1 for Xbox Series X/S, Z2 Extreme and Z2A Handhelds, RX 6000 GPUs and More
Plus: FSR 4 will soon support Vulkan games.
Inside Call of Duty: Modern Warfare 4: The New Game-Changing Tech Powering Every Mode
Smoke, weather and animation have all seen huge upgrades.
'Working Lab' helps Norwich small business owners
Global City Norwich and Foundry66 are accepting applications for a 12-week program to help local businesses grow.
Halo: Campaign Evolved PC Looks Stunning
And we shouldn't require mods to add essential features.
Review: Asus ROG Xbox Ally X20: The OLED Upgrade We've Been Waiting For
The price premium is extraordinary.
City Foundry developer suggests entertainment may be the best use for The Armory
Steve Smith wants to get a conversation started about whether The Armory should be converted into office space or kept as an entertainment venue. And the CEO of New + Found says that can’t just be theoretical: Part of developer TerraWatt’s plan to build a data center at the Famous-Barr warehouse next door comes with […]
"A Colossal Upgrade" - Digital Foundry Delivers Its Tech Verdict For The Witcher 3 Remastered On Switch 2
"easy to recommend"
Review: Dragon's Dogma 2 On Switch 2: The First "Impossible Port" for the New Generation?
An impressive outing for a demanding game - but frame pacing needs fixing.
Xbox Forms Labs Group for Vibe-Coded Game Ports
We're approaching a critical mass - is Xbox putting itself on the right side of history?
Steam Hardware Survey: octa-core CPUs become most popular, RAM counts shrink, 1080p on the way out
What stories can you find in the data?
Intel's stock levels mean investors believe its foundry business will succeed: Bernstein's Rasgon
Stacy Rasgon, Bernstein, and Dan Ives, Wedbush Securities, join 'Power Lunch' to discuss Intel's prospects of building chips in the U.S., Apple price increases and much more.
BUSINESS UPDATE: A 138-year-old New York Manufacturer Gets Another Life in Fulton
E.J. Willis Co. was founded in New York City in 1888 and for generations it has made ship’s bells and other equipment for the U.S. Navy and American shipbuilders. This summer, the new owner moved the company’s equipment to Fulton By Stefan Yablonski E. J. Willis Co. cast brass ship’s bells — handcrafted in the United States since 1888. Ship bells, “built to last a lifetime at sea,” are now manufactured in Fulton. E.J. Willis Co. has moved its operation and manufacturing business to Fulton. They are currently operating out of N.E.T & Die. The company is now under the ownership of Jonathan Hyatt. He recently acquired the company after seeing a for sale note on Craigslist. [caption id=attachment_11110 align=alignright width=400] Entrepreneur Jonathan Hyatt is the new owner of E.J. Willis Co. He bought the business this summer after finding a listing on Craigslist by chance.[/caption] “I had been looking for something to do. I had been 20 years in corporate America and I was just tired of building someone else’s empire, you know what I mean? I was in consulting, pretty much a jack of all trades. I wanted to do something that I could call my own,” he explained. “I’d been on this path of trying to find a business to buy for about a year. One night I am on Craigslist about 11:30 in mid-April searching for something completely unrelated. At the bottom of Craigslist was a ‘things you might be interested in from outside of your area.’ There was an ad that said 138-year-old bell manufacturing company for sale. So, I clicked; why not, right? I wasn’t looking to buy a manufacturing company, but I went down the rabbit hole, absolutely fell in love with the history and ended up buying it.” He read the ad and responded. “I called and I am talking to the owner of the business for about two hours. We ended with, let’s have another chat and then come on out here and have a look. I figured, well I might wind up getting kidnapped and getting murdered or there is a real business here. But I gotta see it through,” he quipped. “And sure enough, there is a big machine shop operation there. The gentleman who owned it was retiring and in the corner of this shop is a little room where they make bells and they have been doing this ever since the company had started.” That’s the one constant thing that has survived the changes of the business. [caption id=attachment_11061 align=alignright width=300] Sales 1929 general catalog published by E. J. Willis Co, listing all the merchandise it sold. It’s like the Sears Roebuck and Co. catalog for marine parts.[/caption] “I drove home and told my wife, ‘This is what I am doing for the rest of whatever we are calling this — mid-life crisis.’ And she said, ‘absolutely you got to do it.’ I took out a loan and off we go.” He put in an offer on the business and they closed on July 1. He didn’t disclose what he paid for the company. “In terms of price, the seller and I have agreed to keep those terms private.” “I am finding that I am a business owner, an archeologist, opening files and cabinets that haven’t been opened in 100 years. It’s just amazing, just cool things that I am finding,” he said. “I want to build the business back. I want to be able to sell the bells to outsiders. I think they are beautiful. “It’s really a wild story about a company that started in lower Manhattan, exploded in the automotive space, sold parts to the Wright Brothers, moved into the aeronautical world and then landed in marine. The cool thing, I have been digging around and the gentleman who owned the company prior to me was not a digital guy. There is nothing out there. “Now I am sitting here with all the art from like the 1930s, the E.J. Willis boat catalog it’s like 250 pages of things this company used to make. It’s like the Sears-Roebuck and Co. catalog for marine parts. We are modernizing, we are staying true to the heritage of the business. It’s exciting to be the next steward of the whole business.” Initially he thought he’d move everything from the company’s plant in Middleville, Herkimer County, to Boston, out of convenience. “Then I thought let’s keep the foundry where it is. Let’s not move anything right away,” he said. “I want to get a good sense of what we’ve got, what works and what doesn’t. “I went to the foundry and met with the people there, lovely people, and said here is my position — I am buying a company where everyone is retiring. There is machining and polishing to be done, who would you work with around here? Without hesitation they said, ‘you need to go to NET Tool & Die and talk to Michelle [Shatrau]. She is a third-generation machinist and she runs the company now.’” So, he drove to Fulton. “I knocked on the door, they let me in. And she said, ‘how’d you get in here?’” he said with a laugh. “We became fast friends. I told her what I am doing. It must have struck a nerve. She has a very entrepreneurial background. I must have said something right because she came out and she said, ‘I’d love to help you. Why don’t we move the equipment that you have into my large building and I will give you a space to work at and use my team?’” [caption id=attachment_11058 align=alignleft width=300] Bell in progress awaiting assembly[/caption] It’s a great relationship so far. “We are bringing the business into the modern world. It’s been a lot of stuff all at once. But it has been very exciting,” he said. “We moved in a month ago [in July]. We closed on the business July 1. We moved a couple weeks later. We had all our equipment set up, electrical being run, everything. [caption id=attachment_11059 align=alignright width=300] Bell attached to a lathe going through the machining process[/caption] “We’re working with NET Tool & Die to rebuild production and preserve manufacturing processes that, in some cases, existed mostly in the heads and hands of the people who had been doing them for decades. We’re currently working on several 200-pound ship’s bells and bringing an old two-way manual bilge pump back into production.” He said he will be working with NET employees for the time being, adding, “I’d love to get to a point where I have so much growth that I need to hire people.” No one wakes up and says, ‘I am buying a bell today,’ Hyatt admitted. [caption id=attachment_11060 align=alignleft width=225] Bell after receiving a custom etching toward the bell mouth[/caption] “Everyone does wake up and has things that deserve acknowledgment and remembering — a promotion, a marriage, the birth of a child,” he said. “These are the things I feel like if there was something that could capture a particular moment in time and will literally outlast the person that bought it, a bell is that. We can engrave a bell if you get married or the birth of a child. We can put anything on a bell. “I have orders, yes. I am working on several orders right now. We have a little bit of busyness. But there are still some things to work out. I want to make things consistently and continue to move forward.”
Switch 2 Update Adds TV VRR Support - but It Only Works in One Game Right Now
Variable Refresh Rate tech is great - and was already supported on Xbox and PlayStation.
Review: Control Resonant: An Impressive PC Version With Superb Scalability
Plus: optimised settings, RT recommendations and much more.
Freya Industries raises SEK 6M to expand drone detection business
Swedish drone detection company Freya Industries has closed a SEK 6 million (approx. EUR 500k) round that will fund orders and expansion through Europe. Foundry ventures, Longswan Ventures, Propel Capital, Saminvest AB (via Annexstruktur), Schyssta Änglar, Sting and a small group of private investors contributed to the round. Freya’s sensors are designed to detect drones
TSCG promotes pair to C-suite; Colliers hire chases Philadelphia business; Foundry adds World Series winner as broker
New hires, promotions and other personnel changes
The Witcher 4 Release Date Confirmed, Gamescom Songs of the Past Showcase Announced
Wind's howling... in 2028.
Porting Half-Life: Alyx to Steam Frame: How Valve's Engineers Went from "There's No Way" to Shipping Standalone
Foveated rendering, lots of driver work and 16GB of RAM.
Updated PS6 Handheld Specs Leaked By KeplerL2: 24GB RAM, RDNA 5 GPU, PSSR 3.0
But pricing remains unknown.
"Don't Kill the Disc": Petition Against Sony PS5 and PS6 Digital Media Plans Reaches 120,000 Signatures
"We are not against digital. We are against digital being the only option."
GTA 6 Launch Trailer Analysis: Has a Long-Standing Tech Issue Been Fixed?
And is there any hint of Sony's new QSSR upscaler?
Review: Switch 2 Oblivion Remastered Frustrates as Much as It Impresses
Adeptly adapted visuals but performance remains as frustrating as ever.
Report: Limited Edition Xbox launches Black Friday for €900
Much more expensive than the launch Series X, but a small premium over current prices.
Review: Xenoblade Chronicles 2: Does Switch 2's Power Finally Fix This Ambitious Open-World RPG?
And is truly a 4K 60fps experience docked - as promised?
Assassin's Creed Black Flag Resynced: Our Optimised Settings For A Terrific PC Release
No storms face this port.
Stalker 2 Developers Announce Cost of Hope Expansion, Major 2.0 Update, Both Coming Soon
As a huge fan of the base game, I'm excited.
Report: Microsoft to bring Xbox 360 games to "Xbox PCs", handhelds and Project Helix
Plus: Microsoft's disc-to-digital programme dated.
DF Weekly: The GTA 6 60fps Debate Returns: Is There a Route Forward on Current-Gen Consoles Like Series X, PS5 or PS5 Pro?
Or is a 40fps mode for 120Hz displays the most we can hope for?
GTA 6 Platform Poll: 36% of DF Viewers to Play on PS5 Pro after 30,000 Votes
With only one in five planning to play on Xbox - and thousands of comments in favour of PC.
Third Coast Foundry opens San Francisco hub for Midwest startups
UChicago, Illinois and Northwestern have opened the Third Coast Foundry in San Francisco to help Midwest startups reach Silicon Valley investors.
DLSS 5 Mod Shifts Load to Second GPU, Doubling Frame-Rates and Latency
Plus, a second mod allows for sub-native rendering to boost performance.
Preview: Star Wars: Galactic Racer's physics-based destructive tech and high-speed DNA shows promise
Now this is podracing!
PSA: Steam Machine and Steam Controller Customers in Europe Hit by Cyber Attack
"Expect fake messages that mention your hardware order and appear to come from Valve."
Digital Foundry: Fire Emblem Fortune’s Weave is 720p docked, 540p handheld and 30fps, but uses DLSS
The tech-focussed team at Digital Foundry has been busy examining the recently released Fire Emblem Fortune’s Weave on the Nintendo Switch 2. The strategic RPG runs at 720p when played in docked mode…
Microsoft Starts Offering Free PC Versions of Your Ubisoft Games on Xbox
Some restrictions apply, read article for details.
Honors, UNMC host students for spotlight on behavioral health careers
Healing Nebraska: Talent Meets Need was held in partnership with The Foundry and gathered 200 University of Nebraska–Lincoln students to discuss community behavioral health needs and career pathways.
New Xbox Nano Controller is designed for "younger players, smaller hands, or anyone seeking something portable"
Shades of the "Xbox Cloud Controller" that leaked in May this year.
Report: Nintendo mulling Switch 2 OLED with Samsung Display panel
But it's not coming any time soon.
Valve's HDMI 2.1 Saga Is "Fully Resolved" with a Final FRL Update to Come For Full 4K 240Hz support
My monitor is ready.
Hands-On With QSSR: AI-Driven Upscaling for the Standard PS5
Plus: further details from Sony's graphics R&D team.
"We really squeezed the PS5 as much as we could": Ubisoft talks tech on Assassin's Creed Black Flag Resynced
How a 13-year-old game becomes a modern graphical showcase.
Microsoft: FSR 4.1 Coming "Very Soon" to Xbox Game Developers for Series X, Series S
How will FSR 4.1 stack up against PS5's QSSR and Pro's PSSR 2?
Preview: Metro 2039's Extreme Detail and Smart Visual Feature Set Has Us Wanting More
An early hands-on preview of the PC build running at ultra settings.
GTA 6: With 30FPS Seemingly Confirmed, Is 60FPS Actually Realistic?
Expectation management.
Dying Light: The Beast Cancelled for PS4 and Xbox One Consoles, 10 Months After Current-Gen Launch
This gruesome open world isn't making its way to last-gen machines.
Nintendo Switch 2 Docked VRR Leapfrogs PS5, but the Catch Falls Squarely on Game Developers
Nintendo Switch 2 gets docked VRR support, matching Xbox Series X|S and beating PS5 per Digital Foundry analysis
How Valley National's New 'Foundry' Merges Tech Innovation with Business Development
The bank's innovation function combines internal and external players to speed tech adoption — and discover opportunities in the tech sector.
Latest PS5 Pro Firmware Beta Automatically Enables PSSR 2.0 Override
Given how much better it is, this makes a lot of sense.
Windows 26H2 Is Nearly Here: 7 Features Worth Knowing About
The new version has hit the Release Preview Channel.
Report: RTX 5090 GPUs discontinued by Nvidia, as GB202 is reserved for AI workstation cards
Not that I could afford one anyway.