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From Animal Camouflage to AI: The Evolving Science of Staying Unseen
Nature’s game of hide and seek is entering the age of intelligent machines. A new article in National Science Review traces how animal camouflage, advanced materials and artificial intelligence are converging to reshape the contest between detecting an object and keeping it concealed.
Auburn's Georgia Upset Didn't Hide the Problems Alex Golesh Still Wants Fixed
Auburn head coach Alex Golesh isn't overlooking the Tigers' mistakes after their 27-24 upset of No. 1 Georgia. Ahead of Saturday's LSU matchup, Golesh emphasized fixing penalties and dropped passes, building on Byrum Brown's improved offensive role, and developing Auburn's young defense.
This Week: Politics 101, 20th Street Bikeway, Muni Trivia
Here is a list of events this week. Monday/Tonight! SF Politics 101 with Joel Engardio. Learn how local politics shaped San Francisco. Monday/tonight, October 19, 5:30-6:45 p.m. SPUR Urban Center, 654 Mission Street, S.F. Wednesday 20th Street Protected Bikeway Ribbon Cutting. The Oakland Department of Transportation, city officials, Bike East Bay and other community partners will celebrate the completion of the 19th Street BART to Lake Merritt Urban Greenway. Wednesday, October 21, 1:30 p.m. 400 Thomas L Berkley Way, Oakland. Thursday 2026 Silver SPUR Awards. This SPUR event brings together elected officials and business, civic, and philanthropic leaders to celebrate four individuals and their contributions. Thursday, October 22, 4-7:30 p.m. Blue Shield of California Theater at YBCA, 700 Howard Street, S.F. Get tickets here. Friday Woman and Non-Binary Morning Ride. Join the San Francisco Bicycle Coalition for a socially distanced bike ride for women and nonbinary cyclists. Friday, October 23, 7:15-8:45 a.m. McLaren Lodge, 501 Stanyan Street, S.F. Friday Muni Trivia Night. Bring your friends or come solo and make some new ones. Friday, October 23, 7:30 p.m. Standard Deviant Brewing, Pier 70, suite 195, 1070 Maryland Street, S.F. RSVP here. Saturday Fifth Annual Firefighter Family Ride. Join SFFD, SF Safe Routes to School, and the SF Bicycle Coalition for a fun, low-stress bike ride through one of the city’s most beautiful routes. Saturday, October 24, 10:30 a.m.-1 p.m. Panhandle Park Blacktop (Fell & Ashbury) to JFK Promenade (Whale’s Tail). Sunday Canvas for No on Prop G. Join the San Francisco Bicycle Coalition to canvas for No on ‘G’ to save Sunset Dunes Park. Sunday, October 25, 10 a.m.-12 p.m. Marina Blvd & Laguna Street, S.F. Got an event we should know about? Drop us a line.
Hackers hide dangerous fake AI downloads behind Google ads
A fake Claude AI download scam uses Google ads and Bing redirects to trick Mac users into pasting a hidden malicious command in their Terminal.
‘Those babies should be remembered.’ Sanford Health to hold infant remembrance service
This week, families are asked to remember, not hide, that pain. October is Infant and Pregnancy Loss Awareness Month, a month to recognize the unique grief families face.
Bruins Postgame: Six Goals Hide Problems in Third Straight Win
It was not the prettiest showing, but the Boston Bruins will gladly take the two points. The Bruins (5-2-0) won […]
Scientists discover how harmful “zombie cells” hide from the immune system
Scientists have discovered a protein that may help harmful aging cells hide from the immune system, allowing them to accumulate and fuel age-related health problems. Blocking the protein in mice reduced these cells and inflammation while improving blood sugar regulation and strength, offering a promising new direction for anti-aging research.
The iPhone Duo’s cooling system hides a clever trick inside its hinge
While a folding iPhone posed a new challenge for Apple’s thermal engineering team, they came up with a creative way to leverage the device’s hinge to their advantage.
Streaming vs. theaters: Where entertainment value hides
Skydance merger spotlights streaming vs theaters. Compare margins, valuations & Quant Ratings for NFLX, AMC, CNK, IMAX & more—read now to find stocks to...
Privacy and Pilates – Inside Duchess Meghan's reported UK hideaway
Duchess Meghan has reportedly found a new exclusive hangout.
Eminem appears on new track 'Madara' with rappers Ez Mil, Hideyoshi
DETROIT — Eminem appears on "Madara," a new track from Philippines-born rapper Ez Mil, released overnight on Friday, Oct. 9. "Madara" also features Tokyo rapper Hideyoshi and voice actor Neil
Cool chemistry trick allows new tattoos to 'turn on and off'
Researchers created multicolored tattoo inks that are activated by different wavelengths of light, allowing people to hide their tattoos in different scenarios.
How do we remember history through 'The Minutes'? Civic comedy tackles small town politics
“The Minutes” hides a misremembered town secret within the records of a typical town council meeting.
12 Years Later, Canceled Kojima Game 'P.T.' Makes A Comeback
Before Hideo Kojima began developing OD for Xbox, he made an iconic PlayStation horror game meant to kick off a new Silent Hill era
P.T. Native PC Port 1.0 Is Out Now With DLSS 4.5, Frame Generation, Ray Tracing, Mods, And More
Hideo Kojima,P.T.,PlayStation 4,LoreanXavier,Vulkan,Konami,NVIDIA DLSS 4.5,AMD FSR 3.1,Intel XeSS,Silent Hills
OCEAN CASINO RESORT DECKS THE HALLS FOR 2026 HOLIDAY SEASON WITH FESTIVE EXPERIENCES, ENTERTAINMENT, AND GIVING
/PRNewswire/ -- The holiday season officially arrives at Ocean Casino Resort this winter, bringing festive accommodations, seasonal dining, holiday shopping,...
How Enceladus' ocean spray becomes chemically diverse ice grains
Saturn's icy moon Enceladus hides a global ocean beneath its frozen surface. From fractures near its south pole, material from this ocean is ejected into space as a plume of water vapor and ice particles. ...
PlatinumGames boss hints he wants to expand Bayonetta as Stellar Blade director calls the series "indispensable"
PlatinumGames president Atsushi Inaba says he "strongly wants" to expand Bayonetta, three years after series creator Hideki Kamiya left the studio.
How Americans’ Financial Health Is Faring In The “K-Shaped” Economy
Hey all, Jason here. Money20/20 is still two weeks away, but I’ve already started packing (not procrastinating for once!). My calendar is already filling up with various sessions I want to catch, meetings, and of course happy hours, dinners, and other side events. If you’ll be in Vegas and want to catch up, let me know by replying to this email, and we can try to find a time amidst the chaos of the Venetian. A big if not totally unexpected piece of news dropped on Friday: the Independent Community Bankers of America, a trade group that represents smaller U.S. banks, filed a lawsuit against the OCC and Comptroller Jonathan Gould, arguing that the regulator’s move to grant trust bank charters to firms seeking to use them to conduct substantial non-fiduciary activities exceeds the authorities granted to the OCC by Congress. I haven’t had time to fully digest the legal filing or speak to folks in my network about it, but you can expect to see coverage and analysis on it in next week’s newsletter. Subscribe or Support by Upgrading The NerdCon agenda just dropped. It’s stacked. Partner content: Nubank built an AI-first bank. Chime built its own banking core. Figure and Valon are rebuilding the mortgage stack. At NerdCon, you’ll hear from the people behind those bets: what they chose, what they learned, and what they’re still figuring out. The agenda is live, with leaders from Nubank, Chime, OpenAI, Remitly, Mercury, Figure, Valon and more. Follow the mainstage conversations, bring the problem your team is wrestling with to a hands-on workshop, or pull up a chair at a roundtable. Pick your quests. Meet us in San Diego, November 18–20. Fintech Business Weekly readers save 20% with code FBW20. Explore the Agenda Things To Know & Other Good Reads Federal Reserve Board finalizes changes to enhance the transparency and public accountability of its stress test and reduce volatility in its stress test-related capital requirements (Federal Reserve Board of Governors) FDIC Announces Conclusion of Independent Monitorship (FDIC) Modernizing Financial Regulation: Initial Observations from eSLR (Fed Vice Chair for Supervision Michelle Bowman) The Data Version of Godzilla versus Kong: FRED Takes on AI (Fed Governor Christopher Waller) Financing the AI buildout (Brookings) Q3’26: Rules for Banks but Not for Crypto (Fintech Takes Banking) The Inevitability of Local Stablecoins (Lombard Notes) Delusions of AI Governance: The Human-in-the-Loop Comfort Blanket (Fintech Snark Tank) Stripe agrees to acquire Parafin to expand revenue opportunities for platforms and help small businesses grow (Stripe) Listen: Fighting Fraud in the Age of AI, with SEON’s Tamas Kadar (Fintech Business Weekly) How Americans’ Financial Health Is Faring In The “K-Shaped” Economy If there is one overarching theme across the economy and politics in the U.S. at the moment, it’s “affordability.” The term is vague enough to encompass a panoply of factors shaping Americans’ day-to-day lives: rising costs for the hallmarks of being “middle class,” including healthcare, housing, childcare, and education, inflation and rising interest rates, and a job market with the specter of AI hovering over it. At the same time, policy shifts under the Trump administration have resulted in reduced subsidies to those who get health insurance under the Affordable Care Act and new restrictions on qualifying for Medicaid and SNAP, the impacts of which have yet to be fully felt. These factors are contributing to declining consumer confidence and general dissatisfaction with the economy, despite continuing GDP growth and stock market records. This divergence is encapsulated in the idea of the “K-shaped” economy, in which a small proportion of Americans have seen their wealth balloon, while the majority of American households struggle to preserve the lifestyle they have. Perhaps the greatest determinant of which branch of the “K” a household is on is whether their wealth and income are primarily derived from employment vs. from assets. Nearly two decades of low interest rates and, more recently, elevated rates of inflation have benefited asset owners, while those whose income is primarily or solely derived from labor have largely seen real purchasing power stagnate or decline. This is reflected in recent Bureau of Labor Statistics data showing that labor share of U.S. GDP — the fraction of economic output that accrues to workers as compensation in exchange for their labor — dropped to just 52.8% in Q2 2026, the lowest since the BLS began keeping records. In 1947, approximately 2/3rds of economic output accrued to workers; even as recently as 2001, labor’s share of GDP was 64.1%. Against this backdrop, we’ve seen the rise of more credit and credit-like products: cash advance apps, “no-fee” overdraft, earned wage access, and buy now pay later, which are often used as small-dollar short-term borrowing mechanisms to meet immediate consumption needs or pay other bills (eg utilities, cell phone, other debt payments). With the markers of a middle class existence and, increasingly, basic financial stability seemingly out of reach for many, it should be no surprise there’s been an increase in “financial nihilism,” something industry peers like Alex Johnson and Frank Rotman have discussed and analyzed the roots of. The explosion of gambling and gambling-adjacent products and services — often marketed under the guise of being an “investment” — is inextricably intertwined with the rise of financial nihilism. Crypto, sports betting, and, more recently, prediction markets offer an escape or even hope of sorts, like a contemporary, digital version of a scratch-off lottery ticket, while leaving the overwhelming number of people who use such products worse off. Share of Households That Are Financially “Vulnerable” Ticks Up The Financial Health Network’s 2026 Financial Health Pulse® report adds context on how American households are faring. (I linked to this report in last week’s newsletter, but wanted to take time to further unpack the data in the report this week.) The Financial Health Network publishes the report annually, providing insight into how Americans’ financial circumstances are changing over time. The 2026 report is derived from a survey fielded in April and May 2026. The report leverages survey responses to assess indicators of financial health across spending, saving, borrowing, and planning/protecting and to determine a zero to 100 “FinHealth” score. Those with scores between 0 and 39 are considered “Financially Vulnerable,” consumers with scores ranging between 40 and 79 are defined as “Financially Coping,” and those with scores of 80 to 100 are “Financially Healthy.” The report found that moderate improvements in 2025 were reversed, with the share of respondents considered financially “vulnerable” rebounding to 17%. The longitudinal data reflect the impact of pandemic-era programs, like expanded unemployment, cash stimulus payments, and pauses of federal student loan payments. The positive impacts of those programs, as reflected in the Financial Health Pulse reports, had largely disappeared by 2023. While pandemic-era inflation — to be fair, in part caused by the various support and stimulus measures — had come down from as high as 9% in 2022, it has rebounded since the start of Trump’s second term, with tariffs and energy market disruptions owing to the war in Iran pushing prices back up. Specific indicators in the survey that deteriorated from 2025 to 2026 include the share of respondents spending less than their income over the past 12 months, the share paying all bills on time over the past 12 months, the share that have a manageable amount or no debt, the share that are “moderately” or “very” confident their insurance is adequate to cover them in an emergency, and the share that “somewhat” or “strongly” agree that their household plans ahead financially. Unsurprisingly, lower- and moderate-income households are more likely to struggle to pay their bills on time and have any funds leftover to save. The share of low-income households whose income exceeded their spending dropped from 35% in 2025 to 31% in 2026, while the share of upper-income households whose income exceeded expenses remained unchanged at 63%. Households with student loans or revolving credit card debt reported having “a bit more” or “far more” debt than was manageable at rates far higher than those not carrying these types of debts. The share of those with student loan debt indicating their debt load was too high to manage increased from 50% in 2025 to 55% in 2026, while the share of those with revolving credit card debt saying the same ticked up from 51% in 2025 to 54% in 2026. Households that had student loans were markedly more likely to be financially “coping” or “vulnerable” vs. those without student loans. In 2026, 27% of households with student loans were considered financially vulnerable, a jump of 6% points vs. 2025. Households without student loans saw just a 1% point increase (not statistically significant) in those considered financially vulnerable. Households’ perception of the affordability of categories of goods and services paints a stark picture, with less than one-fourth considering higher education affordable, about a third deeming childcare affordable, and less than half viewing healthcare as affordable. Fintech Business Weekly is made possible by the generous support of paying subscribers — bringing you independent analysis of banking, fintech, and crypto without fear or favor. You can support my work by becoming a paying subscriber if you aren’t already. Paying subscribers enjoy: access to the entire archive of nearly six years of newsletters extended versions of the weekly newsletter, with additional content and analysis and (for founding member tier) quarterly personal 1:1 fintech Q&A / strategy calls with me, tapping into my unparalleled knowledge of the intersection of banking and fintech and experience working in the sector, including helping to launch Goldman Sachs’ retail bank Marcus Support Fintech Business Weekly You can also support Fintech Business Weekly by sponsoring a newsletter or podcast, putting you in front of 93,000+ of the most influential decision makers in banking, fintech, and crypto. Learn more about sponsor opportunities or request a media kit by dropping me an email. Democratic Senate Report Highlights How Iran Uses Tether to Evade U.S. Sanctions Iran uses stablecoins, specifically Tether, to evade sanctions, fund regional proxies, and to purchase military drones, a report released last week by the Senate Permanent Subcommittee on Investigations says. The report was authored by committee ranking member Senator Richard Blumenthal (D-CT) and the minority staff. Crypto and stablecoin proponents will often push back on criticism that criminals make use of these assets by arguing that, on an absolute dollar basis, far more illicit funds flow through traditional banking systems and payment rails than via crypto and stablecoins. And while that is likely true, it elides the reality presented in news story after news story: whether state actors — Russia, Iran, North Korea — or criminal groups, those looking to engage in illicit transactions increasingly favor stablecoins and, specifically, Tether (USDT). The report from the Senate Permanent Subcommittee on Investigations released last week adds context to how Iran uses Tether has a lynchpin in its shadow banking system. The report analyzed 846 wallets that have been sanctioned or targeted for seizure, finding that 84% of them transacted exclusively or primarily in Tether. The ability to create near limitless, anonymous wallets and to move funds effectively instantaneously and irreversibly have made crypto a favored financial mechanism for bad actors. Stablecoins solved key drawbacks of bitcoin, namely, the original cryptocurrency’s highly volatile value in dollars. And while Tether (the company) has the technical ability to “freeze” or destroy funds, the company is often limited and reactive in its approach to doing so, the Senate report argues. Tether, which is nominally based in crypto-friendly El Salvador, “has stated that its compliance with OFAC sanctions is ‘voluntary’ and that it follows ‘OFAC guidelines,’” the Senate report says. Owing to these favorable attributes, Tether “became a primary cryptocurrency for Iran, Hamas, Hizballah, and the Houthis beginning in 2023 and has expanded in scale since,” according to the report. Tether’s role in Iran’s shadow banking system, the report says, is enhanced by crypto exchanges like Bybit, Kyrrex, OKX, Gate, and Binance, and through “over the counter” exchanges and hawala networks. The consequences of these financial flows aren’t hypothetical. The Senate report links Tether as a funds transfer mechanism to Iranian proxies in the region, including Hizballah, the Houthis, and Hamas. Tether has also been used to make payments to secure components necessary to manufacture drones, the report says. The report concludes by arguing that “[s]tablecoin issuers with a significant nexus to the United States, particularly those that offer dollar-denominated stablecoins, should be subject to American sanctions law rather than being allowed to hide behind foreign jurisdictions.” Stablecoin issuers like Tether must be held accountable for repeated failures to prevent illicit finance and sanctions violations by law enforcement, the Department of Justice, the Securities and Exchange Commission, and OFAC, the report argues. [Paying Subscriber Exclusive] OUSD Goes Live, Make Your Own Neobank, U.S. Sanctions Russia’s A7 Network As “Transnational Criminal Organization” OpenUSD, the stablecoin issued by the Open Standard consortium that includes Stripe, Visa, Mastercard, core providers, crypto firms, and numerous banks, went live last week. Social commerce platform Whop raised eyebrows in fintech by offering creators on its platform the ability to launch their own neobanks, which the company describes as “great businesses that are easy to run,” in just 15 minutes. And OFAC and FinCEN target Russia’s “shadow banking” A7 Network — more on these stories after the paywall.
Giants’ 2-1 start cannot hide Jameis Winston’s touchdown drought
The Giants beat Tennessee 12-7 last week. Every point came from a field goal. It counts as a win, and […]
Buccaneers QB Jalon Daniels on First Start: ‘It Means Everything’
Undrafted rookie Jalon Daniels is being thrust into an almost impossible situation, but he won't hide his excitement at realizing a dream come true.
Video Q&A: Why enrollment growth can hide years of risk for health plans
Health plans are moving past simple membership growth as the standard for success toward a model that brings pricing, network adequacy and acquisition cost information into one connected view. In this interview, a health payer strategy expert explores: Why enrollment is a leading indicator that can mask trailing risks for 12 to 24 months What […]
First Look: A new Burgundy Dial for the Oris Big Crown x Cervo Volante
Oris' classic Big Crown Pointer Date returns with a warm burgundy dial paired with a sustainably sourced deer hide strap by Cervo Volante.
Avex Increases Ownership of Brandon Silverstein's S10 Entertainment
Japanese entertainment giant Avex Inc. owns 85% of Brandon Silverstein's S10 Entertainment with a shared goal of reaching 100%.
This ancient fruit tree thrives with little water—and hides surprising health benefits - Futura-Sciences
An Overlooked Mediterranean Classic This fruit tree yields small “apples” that ripen from yellow to red in September, yet it’s been off the horticultural radar for a long time. That tree is the azarole (Crataegus azarolus), sometimes called the Spanish thorn or azarolier. Rare and seldom noticed, it’s high time...
No, Xbox didn't pay $400 million for Hideo Kojima's 'PHYSINT'
A new rumor going around this weekend has put Xbox's investment in Kojima Productions way above the real figure. But it remains to be seen just how spendy the projects will end up being.
Byron Donalds says he would have debated David Jolly at Sunshine Economy Summit
'He just wants to hide from the voters.'
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. 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Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. 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(ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. 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DraftKings Dips as Adjusted Data Narrows Kalshi's 76% Prediction-Market Lead; Robinhood and Flutter Entertainment Slip
Kalshi's grip on NFL prediction-market volume looks overwhelming until Needham adjusts for how professional traders inflate exchange counts, and that one tweak changes the stakes for DraftKings stock in ways the headline number hides.
Call Of Duty: Warzone Is Adding A Button To Hide All The Goofy Skins
No more Beavis and Butt-Head in your matches.
This ‘World of Warcraft: Forever’ Mod Blocks All Interactions With Asmongold Fans
The beta for the hotly anticipated World of Warcraft: Forever has been marred by fans of the streamer Asmongold who have filled the game’s public spaces with spam and slurs. To fix the issue, a player named Solastro created a mod called OlympusMute that hides any chats from players
Cameron Heyward refuses to hide behind Steelers defensive stats
Pittsburgh Steelers captain Cameron Heyward demanded accountability from the front seven, citing run-defense lapses after losing to New England.
Cooler weather can hide dehydration risk, health expert says
Dropping temperatures may mask the body’s need for water.
Cooler weather can hide dehydration risk, health expert says
Dropping temperatures may mask the body’s need for water.
Cooler weather can hide dehydration risk, health expert says
Dropping temperatures may mask the body’s need for water.
Cooler weather can hide dehydration risk, health expert says
Dropping temperatures may mask the body’s need for water.
Cooler weather can hide dehydration risk, health expert says
Dropping temperatures may mask the body’s need for water.
Cooler weather can hide dehydration risk, health expert says
Dropping temperatures may mask the body’s need for water.
Cooler weather can hide dehydration risk, health expert says
Dropping temperatures may mask the body’s need for water.
Cooler weather can hide dehydration risk, health expert says
Dropping temperatures may mask the body’s need for water.
This Week: Phone Bank for Transit, SF Politics, Transit Tales
Here is a list of events this week. Monday/today! Phone bank with SFBike to Save Transit. The San Francisco Bicycle Coalition is phone banking and connecting with voters, explaining how vital it is to pass the Regional Transit Measure this November. Join them to help make sure our regional transit survives and thrives. Monday/today, September 21, 5-7 p.m. San Francisco Bicycle Coalition Office, 1720 Market Street, S.F. Tuesday Historic Photo Exhibit Tour. Moving San Francisco is a collaboration between the SFMTA and San Francisco Arts Commission and is on view at City Hall through November 25. During this informal tour, they will take an in-depth look at selected photos from San Francisco transit history and learn more about the stories and people behind them. Tuesday, September 22, 5-7:45 p.m. North Light Court inside City Hall, One Dr. Carlton B. Goodlett Place, S.F. Tuesday San Francisco Bicycle Coalition Board Meeting. SF Bicycle Coalition members are invited to attend all board meetings. Tuesday, September 22, 6-8 p.m. Register for Zoom link. Tuesday SF Politics 101 with Joel Engardio. SF Politics 101 is a look at how local politics work and the history that shaped San Francisco—brought to life with visuals and narrative storytelling. Tuesday, September 22, 6-7:15 p.m. SPUR Urban Center, 654 Mission Street, S.F. Register to attend. Wednesday Transit Tales: A Storytelling Night. Join SPUR and Muni Diaries at Local Economy for an evening of true stories inspired by riding transit. From unexpected encounters and meet-cutes to funny mishaps and heartfelt moments, Transit Tales celebrates the experiences that make public transportation unforgettable. Wednesday, 5:30-7 p.m. Local Economy, 6028 College Ave, Oakland. Saturday Group Ride: Richmond BART to Point Pinole. Join Bike East Bay for a family-friendly, no-drop group ride to Point Pinole Regional Shoreline. Saturday, September 26, 10:30 a.m.-3 p.m. Starts at Richmond BART Plaza, 1600 Nevin Plaza, Richmond. Saturday Shipwreck Cove Opening. Come see Sunset Dunes’s newest playground. Saturday, September 26, 3 p.m., Sunset Dunes and Kirkham, S.F. Saturday 55 Wine Line Progressive. Ride between Horsies Market & Saloon, Bar Part Time and Ruby Wine on the 55 Dogpatch bus. Saturday, September 26. Three locations in Dogpatch. See SFMTA site for more details on locations and times. Got an event we should know about? Drop us a line.
Hideo Kojima doesn't know if Physint will be released on PS5, and he hasn't decided if it's going to use Sony's Decima game engine
Sony's sudden decision to drop Hideo Kojima's Metal Gear successor Physint has raised many questions about the game's future.
The Nurse Is Health Care’s Most Underpriced Founder
They see the problem first, build the fix, and decide whether it is ever adopted. The market has trained them to hide the one credential that de-risks the deal.
Hideo Kojima claims Sony dumped him in a Zoom call with no reason
Not even the creator of "Metal Gear" is safe from the dreaded video call layoff.
Hideo Kojima claims Sony dumped him in a Zoom call with no reason
Not even the creator of "Metal Gear" is safe from the dreaded video call layoff.
Warren backs TRIA renewal but flags cyber and NBCR as unfinished business
A unanimous committee vote hides a longer list of unresolved coverage gaps
Warren backs TRIA renewal but flags cyber and NBCR as unfinished business
A unanimous committee vote hides a longer list of unresolved coverage gaps
Hideo Kojima Says Sony Dropped PHYSINT During a Zoom Call and Gave No Reason
In a new interview with IGN, Hideo Kojima says PlayStation ended its involvement in PHYSINT during a Zoom call in June. He says Sony gave no reason, though he also admits he didn't ask many questions during the meeting, and that Sony hasn't been in touch since. Kojima stressed the two are "not in...
A film thinner than a human hair blocks electromagnetic waves—and hides heat!
CHANGWON, South Korea — A research team led by Dr. Taehoon Kim of the Composites & Convergence Materials Research Division at the Korea Institute of Materials Science (KIMS), headed by President Chul-jin Choi, has collaborated with research teams led by Dr. Seon Joon Kim and Dr. Jaewoo Kim of the Korea Institute of Science and Technology (KIST) to develop an ultrathin composite film that combines electromagnetic interference (EMI) shielding, infrared (IR) stealth, and high mechanical strength. The researchers achieved these multifunctional properties by combining carbon nanotube (CNT) fibers and MXene in a structure resembling “bricks and mortar.” The technology is expected to protect military systems and aerospace electronics while also reducing electromagnetic interference in 5G/6G communication devices and wearable electronics.
1977 Fleetwood Mac Hit, Written by Christine McVie, Wasn't About a Dog
Christine McVie tried to hide the inspiration behind one of her biggest songs.
1977 Fleetwood Mac Hit, Written by Christine McVie, Wasn't About a Dog
Christine McVie tried to hide the inspiration behind one of her biggest songs.
Hideo Kojima explains the surprise split with Sony
Celebrated game director Hideo Kojima wrestled with Sony’s surprise cancellation months before it went public, he said in an interview, fearing “our studio could collapse.”
Roma’s Soule on Inter: ‘Obviously they are the strongest’
Matias Soule could not hide his frustration at the Stadio Olimpico, where Roma led the champions by two goals and finished the evening with only a point.With quotes via TuttoMercatoWeb, the Argentine ...
Bill Skarsgård Sounds Very Excited To Be Starring In Hideo Kojima's Physint
The actor released a new video promoting the project
NASA’s Hubble Spots an Out-of-Sync Galaxy
Though the spiral galaxy in this new image from the NASA/ESA Hubble Space Telescope seems serene, it hides a chaotic secret. This galaxy is NGC
Random: Fire Emblem: Fortune's Weave Switch 2 Physical Hides A Neat Nod To Three Houses
Follow the Leda
Bill Skarsgård will lead Hideo Kojima's spiritual successor to Metal Gear Solid
Hideo Kojima's action-espionage game Physint has revealed its lead: Bill Skarsgård. Read more — and see the reveal teaser — at Empire.
XBOX @ Tokyo Game Show 2026: All the Announcements, Including an Appearance by Hideo Kojima
Tokyo Game Show is a celebration of the creators, developers, and communities shaping the future of gaming. As we celebrate 25 years of XBOX and over 20 years in Japan, Tokyo Game Show is an opportunity to recognize the players, creators, and developers who have helped define gaming culture. During the XBOX Tokyo Game Show […]
Physint: Bill Skarsgard to Star in Hideo Kojima Xbox Game
Bill Skarsgård will star as the lead in Hideo Kojima's upcoming video game "Physint" from publishing partner Xbox.
Murmurs: Fancy Mental Health Care Tracker Underwhelms Key Lawmaker
“I’m not going to hide my shock and disappointment at this.”
You can now hide your iPhone's location without anyone noticing
With a new iOS 27 feature, it just looks like your iPhone is turned off or in a bad service area.
Soft power insurance market hides a harder renewal problem
Rate cuts of up to 40% mask rising insurable values and equipment lead times that threaten BI coverage adequacy
XBOX CEO Message is Salt in Sony's Wound at Kojima Productions
XBOX CEO Asha Sharma has left a message on Kojima Productions wall that fans are taking as a shot against Sony, which tried to cancel PHYSINT.
Texans lose heartbreaker to Bills 36-31
It’s one game. It is really easy to overreact to the Texans’ performance on Sunday after losing a nailbiter. There was a lot to love about the game (the offense looked downright competent until the fourth quarter), there was a lot to hate (the secondary and Reed Blankenship in particular were hideous), and there was […]
Biologists drove 19 burrowing owls evicted by a Phoenix housing project 50 miles into a 10,000-acre solar complex and lowered them into 40 plastic burrows — every female laid eggs within a month, and 29 chicks fledged the first summer, because open ground under panels hides no predator from an owl
A solar farm designed to fight climate change became an unexpected refuge for an endangered owl when scientists discovered that panels cast the perfect shadow for ground-nesting predators to hunt.
Bloomberg states reasons why Sony decided to cancel Physint, Hideo Kojima's newest IP and Metal Gear Solid successor that's coming soon to Xbox and PC
Going over budget, not meeting deadlines, and fear of investment are the major reasons why Sony has recently tried to cancel Hideo Kojima's new IP, 'Physint',
Historical art can hide scientific secrets
Scientists are working closely with art historians to uncover scientific documentation in historic paintings.
PlayStation Ditched Hideo Kojima’s ‘Physint’ on Budget Concerns, Missed Deadlines
The legendary Japanese creator of ‘Death Stranding’ will take his new game to Xbox
Politics in the Therapy Session
Once upon a time, therapists took care to hide their ideological views from their patients, presenting instead a “blank screen” that allowed the therapeutic relationship to function as intended. Mark that down as one more casualty of the Age of Wokeness.
Sony Loses Hideo Kojima To Xbox In Its Latest Disaster
In a dramatic series of announcements, Hideo Kojima claimed that Sony was on the verge of canceling his new game, PHYSINT, and he's now left the brand for Xbox.
Xbox Will Now Publish Hideo Kojima’s Action Espionage Game Physint After PlayStation Partnership Ends
Xbox is already publishing Kojima's upcoming horror game, OD. - Game Informer
Hideo Kojima's Physint Game Moves to Xbox From PlayStation
Xbox is expanding its partnership with video game industry legend Hideo Kojima.
Xbox has acquired rights to publish Hideo Kojima's 'PHYSINT' from PlayStation — "We're honored that Kojima-san has chosen to work with Xbox."
In a major coup, Xbox has confirmed that it will be publishing Hideo Kojima's long-awaited action-espionage title "PHYSINT."
The lives of Idaho wilderness guides seem ideal but often hide pain
It’s an emotional let-down when the river runs end for the season and the wonderful people she met along the way are gone | Opinion
The core anti-Pangram constituency is phony writers
Welcome to The Closing Argument, our verdict on the news, plus everything The Argument published and appeared in this week. The Verdict, by Kelsey Piper A lot of people hate AI for drowning the internet in slop and displacing human creatives. You might think that these people would be thrilled by a program that can identify and flag AI-generated work. But many people who hate AI also hate Pangram, an impressively accurate AI detector that produces very few false positives, according to high-quality independent research. This loathing found its most recent expression in a bizarre Wired article that amplifies a wide range of false arguments from Pangram skeptics: that AI detectors are racist (they’re not) or ableist (they’re not)1 or don’t work (this one does)2. Rather than starting from the premise that it would be really valuable to have a working AI detector and scrutinizing Pangram to make sure it lives up to that promise, the article starts from the premise that Pangram obviously has bad vibes and sets out to discover why. (One answer: The CEO microwaved lunch during an interview!) Why aren’t writers who resent Pangram more eager to distinguish themselves from posters who are having ChatGPT ghostwrite all their work? There are a few different things at play, but I think one key dynamic is this: These are often the same people. A core constituency for arguments like Wired’s is “writers” who are using AI to write their posts but resent this fact being made public. They stand to lose from AI detectors because AI detectors call them out. Share When Substack announced a partnership with Pangram, a sizable fraction of the platform’s authors rose up in outrage. Some people had experience with other AI detectors that didn’t work, and some felt that AI writing ought to be encouraged — both of which are fair enough. But the fury was fueled by authors passionately insisting that Pangram kept wrongly accusing them on almost every post they published. Pangram can be wrong, especially on short passages. But in the overwhelming majority of cases where Pangram looked at a whole blog post rather than a single paragraph, the program correctly detected work as AI. Even if we can’t be 100% sure in any individual case, we can notice the trend in the aggregate. Wired quotes Sam Illingworth, a professor of critical AI literacy at Edinburgh Napier University, who said, “I don’t think [AI detectors] work. … I think that detectors are prejudiced against certain people.” This spring, he said that he used AI for research and editing; this summer he acknowledged that in addition to research and editing, he also uses it “now and then for a turn of phrase I keep.” Pangram informs us that most of his posts are 100% AI-written (some are mixed AI-and-human) and that 100% AI-written posts started appearing last year. The favorable interpretation is that, as someone whose recent work Pangram consistently mistakes for AI, Illingworth sees Pangram’s flaws firsthand. The unfavorable interpretation is that the tool’s credibility trades off against his own, because its account of who writes his posts is not consistent with his. Illingworth is not alone in insisting the detector does not work. “It’s a Monday night in late July, and I’m pasting my own Substack draft into an AI detector for the first time. Not because I’m worried. Because I’m curious. I wrote every word of it myself, the way I write everything, out loud in my head first, in a rhythm that still carries the accent of a language I learned to think in before I learned to write in this one,” begins one Substack post by an author indignant that Pangram flags her writing as AI. “That’s the part I had to sit with before I could write this.” If you, like me, have worked with AIs a lot, you won’t even need Pangram there. The author of that piece is AI. It is obviously AI! I checked 10 other posts on the blog, and they were also obviously AI! “I have spent 22 years as an award-winning author and essayist. And now this bullshit tool that learned from MY writing is going to accuse me of plagiarism,” popular Substack writer Carlyn Beccia wrote in an anti-Pangram post. “For the last and final time, AI DETECTORS DO NOT WORK.” Here’s what her writing sounded like in 2020: “Most success stories revolve around one person who believed enough in you to say — give it a try. We call these people muses, but they are so much more than that. They are the strong man giants whose shoulders we stand on so we can see the horizon. Throughout the editing process, I am sure my editor felt less like a giant of greatness and more like Atlas with the world on her shoulders.” Pangram says it was 100% human-written. (So were other articles of hers in 2020.) And here’s what it sounds like now: “And then there is the reshuffling, which sounds like paperwork until you remember that empires have always loved paperwork. The Trump regime recently moved special education oversight from the Education Department to HHS. That is not a minor bureaucratic transfer. It changes the frame.”3 Pangram says this is mostly AI. I am not convinced that Pangram is wrong. In my own experience, Pangram is very effective on long texts — if it marks a long essay as AI, the essay was either written by AI or deliberately written to sound like AI. On tweet-length or paragraph-length texts, it’s not perfectly reliable. It seems to work just as well for non-native English speakers as for native speakers. While I have seen dozens of claims of pre-2022 text returning a positive result on Pangram, I have tried repeatedly to corroborate those and have never once succeeded. To be clear, I’m absolutely not saying that complaining about Pangram suggests a writer is a cheat. There are plenty of other concerns. Most are mistakenly premised, such as the false claim that Pangram trains on work you put into it, but others are reasonable: It’s unreliable on sufficiently short text segments; it creates an internet witch-hunt mentality when there are defensible uses of AI; people who are open about their AI use are sometimes blamed, when the only people really doing something wrong are the ones who hide it; and it isn’t perfect, so a single positive result shouldn’t be taken as decisive proof of misconduct. I’m happy to concede that Pangram is imperfect and possible to over-rely on. If an author’s posts are mostly non-AI and one scans as partially AI, this could be a mistake. It’s also possible to defeat Pangram with intentional effort. If you think we need something more robust and more reliable, fine! But if you don’t like AI and don’t like Pangram, your attitude really ought to be that it’s a shame that our existing tools for AI detection are imperfect, and it’s important to invent better ones. If your stance is instead that AI is evil and so is looking for AI, then ultimately you’re contributing to the sloppification of the internet. You’re making it harder for people who write their own text to distinguish themselves, and providing cover for authors who are definitely not writing their own text. Subscribe Top stories this week, by Kobe Yank-Jacobs Commentators often worry that the decline of reading could mean the decline of liberal democracy — but deliberative governance actually predated widespread literacy. This week, Maibritt Henkel pointed out that many liberal cultures thrive on a culture of raucous, interactive debate, which can happen in-person as easily, if not more so, than in text. Read on, dear reader, to learn more. It may actually cheer you up: [ ](https://www.theargumentmag.com/p/reading-wont-save-liberalism) [ Reading won’t save liberalism ](https://www.theargumentmag.com/p/reading-wont-save-liberalism) Maibritt Henkel · Sep 1 [ Read full story ](https://www.theargumentmag.com/p/reading-wont-save-liberalism) It used to be bad to downplay climate change (if we mean denying its reality). Today, it’s actually good to downplay climate change (if we mean keeping the issue out of political fights so we can make real progress). This counterintuitive view is called “climate hushing,” and contributor Alex Trembath argued that it’s the key to enacting good policy going forward. Get up to speed on the latest in climate politics: [ ](https://www.theargumentmag.com/p/we-wont-stop-climate-change-by-talking) [ We won’t stop climate change by talking about it ](https://www.theargumentmag.com/p/we-wont-stop-climate-change-by-talking) Alex Trembath · Sep 2 [ Read full story ](https://www.theargumentmag.com/p/we-wont-stop-climate-change-by-talking) Canada’s Prime Minister Mark Carney is standing up for the forces of liberalism against Donald Trump’s assault on our closest ally. So, why is one prominent left-wing commenter attacking Carney? Columnist Matthew Yglesias explains: [ ](https://www.theargumentmag.com/p/when-economic-liberty-means-central) [ When "economic liberty" means central planning ](https://www.theargumentmag.com/p/when-economic-liberty-means-central) Matthew Yglesias · Aug 31 [ Read full story ](https://www.theargumentmag.com/p/when-economic-liberty-means-central) 🌟Abundance Wins of the Week🌟 Shout out to my home state of California, whose legislature passed two housing bills this week. One requires a housing density minimum in transit-oriented areas of the state’s most transit-rich cities (Los Angeles, Sacramento, San Francisco, Oakland, San Jose, San Diego, and Long Beach). Another bill closes two common loopholes used by third parties to delay housing projects, including an opportunity to challenge maps of a given lot created by the developer after a project has been approved. Shout out to our big-state rival, Texas, where pro-housing SB 785 took effect this week. The new state law requires municipalities to have at least one district permitted for manufactured housing without a special permit. This will promote zoning changes in 44% of municipalities. The company Fervo Energy signed a deal with Google for what is set to be the world’s largest enhanced geothermal facility, proving a technology can work at a scale that could be crucial to a decarbonized, energy-abundant economy. Share Worth watching… This week, forecasting legend Nate Silver joined Jerusalem, Matt, and Jeremiah on a crowded episode of the pod. It was a party. And speaking of parties, our round table debated the factional lines within the Democratic Party: Is it possible to be center-left and also anti-establishment? Watch or listen to find out: The Rio Grande Valley in Texas is one of the areas that swung hardest toward Trump in 2024, but musician Bobby Pulido is running to flip it back. Right now, The Argument/Split Ticket’s model has him running 1.1 points behind his Republican opponent in a district Trump won by 18 points. Tune in to find out how he differs from national Democrats and what he thinks he can to do win this seat. On Thursday, Bernie Sanders was among the first politicians to call for a ban on superintelligence. My guest this week, Andrea Miotti, has been lobbying to ban superintelligence for several years, most recently in the U.K., U.S., and Canada. I asked him how he gets legislators to take speculative risks seriously, and we dug into what plans might look like to actually pass a ban. Listen to learn more: What’s News with The Argument The Argument recommends, by Kobe Yank-Jacobs If we ever lose track of Justin Zuckerman, I’ll have the team split up and check all the movie theaters in the city. I’m shocked (and a little jealous) at how often he gets out to see good cinema. This week, he brings us It Ends, a “horror-ish movie,” which he described as a “Gen Z Waiting for Godot.” I was intrigued before he added that it was “funny, dark and existential” — at which point I was fully locked in. I guess I also had existential themes on the mind this week. One morning, a single line from a poem I read long ago just came to me: “Is death a stretch of time in which a life is just a flash?” The poem is called “From 20,000 Feet” by Heather McHugh. I suggest the version in The Vintage Book of Contemporary American Poetry, which, by tradition, my best friend and I always bring backpacking, extra weight be damned. We’ll stay thematically dark for just one more rec from senior editor John Robert Thomason, whose upcoming trip to Baltimore reminded him to suggest Michael Clune’s memoir White Out (about being addicted to heroin in Baltimore in the 1990s). Ben Lerner’s blurb called it _“_Disturbing, brilliant, hilarious—it’s as if Proust had written Jesus’ Son.” John told me this “seems accurate, with the caveat that I’ve never read Proust.” I, personally, have also shelved Proust until retirement. At this point, I was a little concerned for the team since all of us tossed out such psychologically grim material — maybe we’re all down about the end of summer — but thankfully, at least a few of us were into more upbeat selections. Milan Singh recommended Made In’s 5-quart stainless clad saucier, suggesting he had some fun in the kitchen. Jeremiah Johnson asked if he could recommend yet more Carly Rae Jepsen. Once denied, he offered up Game Changer instead_,_ calling it “the most wildly creative game show, maybe in the entire history of the genre.” Eli Richman mentioned _Lucky, “_a B-tier show with an A-tier cast and an S-tier theme song.” I suppose he was recommending the song, Horns of a Bull. Still, despite these cheerier recs, I couldn’t help but be concerned that we were subconsciously worried about racing toward summer’s end — the end of swim trunks and splashing around. Then a message landed reminding me of the three-day weekend to come. A whole extra day for sunshine. One more swim in the lake. I was grateful this called to mind yet another line from a poem, one by Mary Oliver, the patron saint of every gorgeous summer day (and about whom a documentary is now out). Speaking to God in the poem “Thirst,” she wrote: grant me, in your mercy,a little more time. Love for the earthand love for you are having such a longconversation in my heart. We have merch! We have quarter-zips, keychains, hats, and stickers. Each one is a great conversation starter in its own way. Buy them here. Subscribe More to read: [ The Opening Argument ](https://www.theargumentmag.com/p/seeing-like-an-elite)[ Seeing like an elite ](https://www.theargumentmag.com/p/seeing-like-an-elite) Kobe Yank-Jacobs · Sep 4 What do Americans hear when they watch Sen. Bernie Sanders or Vice President JD Vance rail against the elite? Are they thinking of right-wing tech billionaires? Imperious college professors? Liberal magazine writers? [ Read full story ](https://www.theargumentmag.com/p/seeing-like-an-elite) [ The Weekly Scroll ](https://www.theargumentmag.com/p/god-is-back-on-the-timeline)[ God is back on the timeline ](https://www.theargumentmag.com/p/god-is-back-on-the-timeline) Jeremiah Johnson · Sep 5 This week, we’re talking about Substack’s new religious debates, the continuing MAGA influencer scandal, how to retire from YouTube, and aura battles. [ Read full story ](https://www.theargumentmag.com/p/god-is-back-on-the-timeline) 1 This was a legitimate thing to worry about, but doesn’t seem to be a problem given the actual technology: Marijke Van Vlasselaer, Filip Van Droogenbroeck, and Bram Spruyt’s 2026 paper looks at whether Pangram is less accurate when evaluating the work of non-native speakers of English. It isn’t. That’s because Pangram isn’t really looking at how “unusual” a piece of writing is but whether it has the characteristic patterns of LLMs. The Wired article makes an odd gesture at a different Pangram-is-racist argument. There were several controversies this summer during which upcoming books were canceled after being discovered to be AI-written: “The three novels mentioned earlier — Shy Girl, Daggermouth, and Call Me, easily publishing’s biggest AI-detection scandals — were all written by writers of color.” But come on! As Zvi Mowshowitz put it: “They were not primarily written by people of color. They were primarily written by AIs.” That’s the whole problem! And as my colleague Jeremiah Johnson recently observed with respect to Cambridge’s Arday scandal, a community being unwilling to call out fraud if it’s perpetuated by people of color is not an anti-racist tendency; it is ultimately quite racist. 2 Many non-Pangram detectors don’t work, but many possible airplane designs also don’t work, and no one considers this a general argument against aviation; the thing that matters is whether any detection works. 3 The phrase “empires have always loved” mysteriously became all the rage in the last few years. See here, here, here, here and here. Before 2025, the only use of that phrase I have been able to find is a single Tweet. The logic of the sentence, too, is incoherent in an AI-characteristic way. “...sounds like paperwork, until you remember that empires have always loved paperwork”? Does remembering that make it sound less like paperwork? It’s a craft-ful sentence, but what is it actually saying??
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This Week: SF Politics, Bike East Bay Volunteer Night, SFMTA Photo Archive
Here is a list of events this week. Tuesday SF Politics 101 with Joel Engardio. SF Politics 101 is a look at how local politics work and the history that shaped San Francisco—brought to life with visuals and narrative storytelling. Tuesday, August 25, 6-7:15 p.m. SPUR Urban Center, 654 Mission Street, S.F. Register to attend. Tuesday Bike East Bay Volunteer Night. Tackle projects while socializing with fellow advocates. Snacks provided. Tuesday, August 25, 6-8 p.m. Bike East Bay Office, 466 Water Street, Oakland. Wednesday SFMTA Photo Archive and Peter Hartlaub. Go back in time for an evening of photos, stories and conversation with the Chronicle, Mayor Art Agnos, and S.F. Muni. Wednesday, August 26, 5:30 p.m. Gray Area Foundation / Grand Theatre, 2667 Mission Street, S.F. Get tickets. Wednesday Smart City Cycling. Join the San Francisco Bicycle Coalition for a presentation for people interested in biking but intimidated by urban traffic plus anyone already riding who wants to hone their skills. Wednesday, August 26, 6-7:30 p.m. Anza Branch Public Library, 550 37th Avenue, S.F. Thursday Member Repair Party. Join the San Francisco Bicycle Coalition and learn how to repair your bike. Thursday, August 27, 5-7 p.m. San Francisco Bicycle Coalition, 1720 Market Street, S.F. RSVP required. Saturday The Bay Ride. Circumnavigate the San Francisco Bay while raising funds for cycling infrastructure that makes streets safer for everyone. Saturday, August 29, 7 a.m.-5 p.m. Starts at Sports Basement Presidio, 610 Old Mason Street, S.F. Saturday Flat Fix Clinic for Students and Families. Join the Safe Routes to School team at the Marina Branch Branch Library for a hands-on flat fix clinic. Saturday, August 29, 2-3:30 p.m. Marina Branch Public Library, 1890 Chestnut Street, S.F. Got an event we should know about? Drop us a line.
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