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These underwater 'living pink rocks' help store carbon: Scientists just found four new species
Rhodoliths may look like small rocks on the seafloor, but they are actually living algae that create habitats for marine life and contribute to long-term carbon storage. A new study found that the deeper, ...
San Mateo County may require permit for businesses using humanoid robots
San Mateo County is considering a plan surrounding the use of humanoid robots to help firefighters put out fires caused by lithium-ion batteries.
7 essential moments from the 2026 Tony Awards
"Schmigadoon!" won best musical, during the 79th Tony Awards at Radio City Music Hall, Sunday, but fans were also buzzing about Pink's hosting skills, John Lithgow's not entirely expected win and Ali Louis Bourzgui's passionately political speech.
2026 National Defense Science and Engineering Graduate (NDSEG) Fellowship Award
First year Materials and Nanoscience graduate student Stéphane Miaule (Tolbert group) has been awarded the 2026 National Defense Science and Engineering Graduate (NDSEG) Fellowship, one of the country’s most prestigious honors for graduate students in the fields of Science, Technology, Engineering and Math (STEM). The program, jointly sponsored by the U.S. Army, Navy, and Air Force, supports doctoral students across a broad range of scientific and technological fields of strategic importance. This highly competitive fellowship provides full tuition, fees, and a monthly stipend for three years. In 2026, only 102 fellowships were awarded nationwide, and Stéphane is the sole recipient from UCLA. Before transferring from Santa Monica College to UCLA, Stéphane interned at NASA’s Kennedy Space Center and Marshall Space Flight Center, where he researched the mechanical and thermodynamic properties of lunar regolith, as well as radiation shielding materials for lunar habitation development. At UCLA, he joined the Soft Materials Research Laboratory under Professor Qibing Pei, focusing on the synthesis and characterization of hafnium oxide nanocomposite scintillators. After earning his bachelor’s degree in chemistry, he remained in the Soft Materials Research Laboratory as a post-baccalaureate researcher for one year before joining Professor Sarah Tolbert’s group as a Ph.D. student. Stéphane’s Ph.D. research is focused on improving the properties of conjugated polymers, which are a family of plastic materials that can conduct electricity. Stéphane is specifically looking at self-assembling polymers that can be processed in water to create light-weight, flexible, high-conductivity polymer devices without the need for toxic or volatile organic solvents. After completing his Ph.D., Stéphane hopes to work in a national laboratory, researching semiconducting polymers for applications in new electronic devices. “The Graduate (1967) featured a memorable scene in which the protagonist was told that ‘there’s a great future in plastics.’ We know this still holds true today, as polymer research has expanded rapidly due to the wide variety of applications these materials enable. Through my work on semiconducting polymers, I hope to contribute to the continued development of plastic electronics,” Stéphane said. Penny Jennings, UCLA Department of Chemistry & Biochemistry, penjen@g.ucla.edu.
New Business: Lithermans Limited Brewery adds pinball; NH Doughnuts coming to Londonderry
A brewery in Concord has a new offering for those of all ages: pinball machines. For those 21-plus, the machines are equipped with cup holders for a pint of favorites
Fuckin' Politics (2003) by Yoshitomo Nara
From Alpha 137 Gallery Gallery Auction, Yoshitomo Nara, Fuckin' Politics (2003), Offset Lithograph. Unframed., 54.1 × 72.9 cm
NASA fires up powerful lithium-fed thruster for trips to Mars
A technology that could propel crewed missions to Mars and robotic spacecraft throughout the solar system was recently put to the test at NASA's Jet Propulsion Laboratory in Southern California. On Feb. ...
Science Pub: Investigating the Lithium Rush
Lithium has been described as “white gold,” the next oil, or a kind of savior from climate change. Consumers are
Monolith Soft Talks Up Ganondorf's "Alluring Charm" In New Interview
"You witness a king's revival"
110,000-year-old discovery rewrites human history: Neanderthals and Homo sapiens worked together
The first-ever published research on Tinshemet Cave reveals that Neanderthals and Homo sapiens in the mid-Middle Paleolithic Levant not only coexisted but actively interacted, sharing technology, lifestyles, and burial customs. These interactions fostered cultural exchange, social complexity, and behavioral innovations, such as formal burial practices and the symbolic use of ochre for decoration. The findings suggest that human connections, rather than isolation, were key drivers of technological and cultural advancements, highlighting the Levant as a crucial crossroads in early human history.
Pro boxer, 20, opens up about his dad's impact
Armie Litherland says his father's work ethic and drive helped him to become a professional boxer.
New study changes what scientists know about lithium and bipolar disorder
Lithium is one of the most effective drugs for bipolar disorder. However, its narrow therapeutic window means the difference between an effective dose and a toxic one is small.
HOTWORX Franchise Expands to Alaska, Starting in Wasilla
Former Alaskans return with a new fitness trend: hot yoga, hot pilates, and hot cycle sessions held in saunas to keep muscles limber and lithe.
Juan Luis Arsuaga, paleontologist: ‘Corruption is very Paleolithic, very chimpanzee-like’
The co-director of the Atapuerca archaeological site shares with EL PAÍS the key points of his new book, ‘The Answer,’ a luminous text that exudes admiration for our own species and love for nature
Expansion of the security segment wholesale business through the acquisition of shares in companies
The security segment of TKM Grupp AS is expanding its operations across the Baltics by establishing a subsidiary in Latvia and acquiring companies engaged in the wholesale distribution of security systems in Estonia, Latvia and Lithuania. In 2023, TKM Grupp AS acquired a 100% shareholding in Walde AS, a company engaged in the wholesale distribution of security systems in Estonia (stock exchange announcement of 23 December 2022). On 16 October 2026, Walde SIA, a 100% subsidiary of Walde AS, was e
Gen Z isn't a monolith — and the data shows it
"There has been a tremendous backlash within this generation," one researcher tells Axios.
"Lost Civilizations" Linked by DNA: What Scientists Just Uncovered Changes Everything - Futura-Sciences
Megalithic Mysteries: A Shared Heritage Revealed At the closing of the Neolithic era, roughly between 4500 and 2800 BCE, vast megalithic monuments began to rise across Europe. These massive stone structures, often used as collective burial chambers, are a testament not only to strong local traditions but also hint at...
Chinese sodium battery surprised scientists by matching key Tesla benchmarks
Researchers found that a Chinese sodium-ion battery performs far better than expected, with production quality and design features comparable to Tesla’s batteries. If engineers can improve cold-weather charging and energy density, sodium could become a cheaper and more abundant alternative to lithium for EVs and large-scale energy storage.
Tony Awards 2026: Full list of winners
'The Lost Boys,' 'Schmigadoon!', 'Ragtime,' 'Death of a Salesman,' John Lithgow, Nathan Lane and Laurie Metcalf are among the top contenders for 2026 Tony Awards.
Shockwave Medical announces new studies evaluating carotid IVL platform
Carotid artery disease causes up to 30% of all strokes, but severely calcified lesions can make treatment quite complex. The hope is that IVL can be as successful in this area as it has been in the treatment of coronary and peripheral artery disease.
Chicago Sky waive Hailey Van Lith ahead of regular season
Van Lith, a second-year guard, was reportedly waived because of the Sky's preferred style of play.
Green Science Alliance Developed Stable Rechargeable Aqueous Aluminum Ion Battery with Conductive Carbon Rubber Sheet as Cathode Current Collector
/PRNewswire/ -- In modern society, rechargeable batteries, particularly lithium-ion batteries (LIBs), have become the most practical option for energy storage...
Southwest Airlines limits passengers to 1 portable charger per person over fire concerns
Southwest Airlines rolls out stricter portable charger rules, limiting passengers to one device per person amid rising lithium battery fire concerns.
Breakthrough could lead to ‘big leaps’ in battery performance, scientists say
Researchers studied lithium-ion batteries, which are used for electric vehicles as well as portable electronics such as mobile phones and laptops.
Activists detained at Oregon State Capitol protesting lithium mine
Activists from Portland, Eugene and southern Oregon were urging Gov. Tina Kotek to step in and stop a controversial lithium mining project.
Fuckin Politics (2003) by Yoshitomo Nara
Available for sale from uJung Art Center, Yoshitomo Nara, Fuckin Politics (2003), Color lithograph (open edition), 49 × 67.5 cm
Growlithe and Groudon Illustration Rares from "Storm Emeralda"! -...
Illustration rare versions of Growlithe and Groudon have just been revealed from Storm Emeralda! The set will release in Japan on July 31st as their sixth
Efzimfotase alfa demonstrated improvements in bone health in treatment-naïve pediatric patients with hypophosphatasia achieving median difference of 1.67 vs placebo in RGI-C Score at week 25 in MULBERRY Phase III trial
Positive results from the MULBERRY Phase III trial showed that efzimfotase alfa (ALXN1850), an investigational enzyme replacement therapy, demonstrated a statistically significant and clinically meaningful improvement in bone health in children (2 to
Scientists develop a way to restore aging EV batteries without breaking them down into raw materials
The work focuses on a common problem in aging lithium-ion batteries: buildup on the electrodes. As batteries are charged and discharged, a layer known as the solid...
Cannibalism returned to the menu multiple times in Neolithic Europe
Bones collected from three caves in Spain reveal how cannibalism came back over thousands of years.
PRESIDENT PAZ: Bolivia has rejected socialism and is open for business
Bolivia's leader outlines a shift from socialism to "capitalism for everyone," seeking United States investment in lithium, copper, and natural gas.
NASA's Lithium-Fed Nuclear Thruster Flares to Life in First of Its Kind Test
The next-generation thruster could one day propel humans to Mars.
Immortal snail meme turned into desktop game where you only get one life
Don’t Touch The Snail, developed by PlasticBagHandMan drops a snail onto your desktop as it slithers closer to your cursor with impending doom.
77 headless skeletons found in a field date back 7,000 years
The carefully arranged Neolithic remains show signs of skillful skull removal.
Los Alamos Faith & Science Forum Presents ‘Saved By The Spirits: Did Religion Rescue Paleolithic Humans From Extinction?’ June 24
Dr. Nels Hoffman/Courtesy photo LAF&S FORUM NEWS RELEASE The Los Alamos Faith and Science Forum 2026 Summer Series Presents ‘Saved by the Spirits: Did religion rescue paleolithic humans from ex…
Fool’s gold isn’t so foolish: Scientists find hidden treasure in pyrite
Researchers have discovered lithium hidden in pyrite within ancient shale rocks—an unexpected find that could reshape how we source this critical battery material. It raises the possibility of extracting lithium from existing waste, reducing the need for new mining.
High-level Lithuanian delegation visits Miami to strengthen links in tech and business
In the European Union, Lithuania stands out as the country that issues the most licenses for fintech companies and as a growing hub for diverse tech ventures.
New Tech Resurrects End-Of-Life Lithium Batteries Back To 95% Capacity
Scientists have developed a way of refurbishing lithium batteries by removing accumulated deposits on electrodes, returning them to 95% capacity.
50-foot ancient snake discovered in India may be one of the largest ever
A massive prehistoric snake discovered in India may rank among the largest ever to slither across Earth. Named Vasuki indicus, this ancient giant lived around 47 million years ago and is estimated to have stretched an astonishing 11 to 15 meters long—rivaling the legendary Titanoboa. Fossilized vertebrae unearthed from a lignite mine in Gujarat reveal a thick-bodied, powerful snake likely built for slow, stealthy ambush attacks, similar to modern anacondas.
Science Cafe returns Sept. 15 to discuss AI impacts
Science Cafe returns Sept. 15 at Litherman’s Brewery to discuss AI impacts with experts Nicholas Smith and James Dobson. Join the talk.
Xenoblade Chronicles: Definitive Edition - Nintendo Switch 2 Edition worked on by Baten Kaitos remaster dev
An interesting tidbit has come to light about Xenoblade Chronicles: Definitive Edition – Nintendo Switch 2 Edition, as it’s been revealed that Logicalbeat worked on the game. Monolith Soft, the team behind the original game, was involved as well. That said, it looks like Logicalbeat had a hand in getting the title to run at 60 frames per second and...
Stryker enters competitive IVL space with acquisition of Amplitude Vascular Systems
Stryker, one of the world’s largest medtech companies, has agreed to acquire a rising name in the field of intravascular lithotripsy.
China’s Chang’e-6 reveals why solar wind hits the Moon’s two sides differently
China’s Chang’e-6 samples have uncovered a surprising difference between the Moon’s two hemispheres. Solar wind particles penetrated deeper into the far-side soil because Earth’s magnetosphere slows the particles that reach the near side. Noble gases locked inside the lunar regolith preserved evidence of this uneven bombardment. These gases may even help scientists reconstruct the ancient history of Earth’s magnetic shield.
TSMC Has Enabled Smartphone SoCs To Approach 5GHz Frequencies Thanks To Advanced Lithography; Huawei The Biggest Loser In All Of This
With the exception of Huawei, every smartphone chipset manufacturer who chose TSMC is now able to reach a clock speed of 5.00GHz
Does public health *need* MAHA?
Last week, our friend Dr. Craig Spencer sparked an ongoing volatile discussion with his Atlantic article “Public Health Needs MAHA.” Some have come out in strong dissent, others are cheering, and others are simply lamenting that we find ourselves in such a divided world to begin with. We will dare to dip our toes in these controversial waters, too. Does public health need MAHA? We think in some ways yes, and in other ways, no. MAHA leaders versus the everyday MAHA supporter The vitriol in this debate mostly comes from one collapsed distinction: the leadership of MAHA is not necessarily the same as the people who support it. Say “MAHA” and most people picture RFK Jr. Fair enough, as he coined the term and holds most of the power. And, yes, some MAHA followers treat Kennedy as something close to a saint. But talk to the grassroots, and it’s not a monolith. They’re Republicans, Democrats, and Independents. People who distrust vaccines and vaccine supporters. It’s a wide, eclectic coalition. The data backs this too: 4 in 10 Americans support the movement—that’s a lot of people! But according to polls, vaccines and medical choice (the issues most tied to Kennedy personally) are cited by only 4% as their reason for supporting the movement. For many, the motivations are much broader. Many MAHA supporters are signing up for the idea that “something needs to change” with health in this country. They’re asking good-faith questions about corporate influence on our health systems, health care costs, nutrition, chemicals, and clean air and water. These are all questions that plenty of public health professionals recognize as legitimate and also care about very deeply. Blurring the lines between the leadership and grassroots does real damage in two important ways: It hands the 4 in 10 exactly the narrative already fed—that the health ecosystem doesn’t listen, doesn’t care, and paints every critic with the same brush. It gives the actual bad actor more power. RFK Jr. has done irreparable damage and can’t be trusted. What the MAHA movement gets right A healthy population is something the public health field was literally built on, and many of these topics are things we have dedicated our lives to. Yet the MAHA movement has captivated nearly half the country in a way the public health establishment has failed to achieve. So that means MAHA is doing something right. Some of it may be timing (after a Covid-19 pandemic and deep frustration and mistrust with institutions). The movement also does three other things really well: 1. It gives a new, louder voice to system failures. While MAHA is not a monolith, one theme stays consistent across their stories: the system failed them. For some, it was the system that flooded their communities with opioids and then walked away. For others, it was the system that let their business collapse during Covid with no safety net in sight. For others still, it was the system that failed to help them manage a complex chronic illness, bouncing them from physician to physician without any real answers. And in many ways, our health ecosystems are failing Americans. Why are medical bills so incomprehensible? Why do some kids get a healthy school lunch and others don’t? Why do an epidemiologist and a MD/PhD student have to start newsletters in the middle of the biggest public health emergency in a century, just so people can get straight information? Because the systems failed. This deep-seated frustration driving many Americans to search for solutions elsewhere needs to be recognized. 2. MAHA has brilliant comms central to their efforts. MAHA figured out something most health institutions still have not: the information landscape changed. It’s participatory now, not top-down; influence runs through many nodes in a community, not one institution; and storytelling and telling audiences “what you really think” moves people more than data dumps do. MAHA goes where audiences are listening, using podcasts, social media, and memes in ways most health institutions would scoff at—but it works. 3. They are very good at organizing. A MAHA meeting feels like a rally: energy, speakers, music, and most importantly, an action for everyone. Someone’s writing the next policy brief, someone’s seeding a narrative, someone knows the next legislative deadline, someone’s sending the text messages for a campaign. None of this is new (ask the civil rights movement), but MAHA knows it works and has capitalized on it. What MAHA gets wrong This list could be much longer, and this newsletter has spent a lot of time covering it, but here are a few things: Poor use of scientific evidence. This is the fundamental problem with many MAHA policies: the hype outpaces the science, and experts are often villainized for pointing this out. MAHA leadership has traded real solutions for cheap wins. For example, instead of taking on the powerful food industry and passing real reforms, it has celebrated french fries made of beef tallow and taken out artificial dyes from still very sugary children’s cereal. These changes won’t move the needle on America’s diet. MAHA leadership has tried to dismantle vaccine access in the U.S. While many MAHA supporters emphasize other issues, the effort to change vaccine policy has become MAHA’s signature effort. This is not surprising given RFK Jr.’s extensive track record campaigning against vaccines. It has rallied behind the wrong leader. RFK Jr. has a decades-long track record of villifying doctors, scientists, and public health workers, well before he became HHS secretary. He is known for his decades-long work sowing distrust in vaccines as well as life-saving treatments like antiretroviral therapy for HIV. This is not a serious person who can move the needle on health in the U.S, and he has already done serious damage. Public health needs more than defense Defending the evidence is absolutely necessary so health in the U.S. doesn’t move further backward. The public health establishment is very good at defense. The problem is this defense often sounds like defending the status quo, which has failed many people. Public health needs to offer an alternative to RFK Jr.’s MAHA—one that is rooted in evidence, truly listens to and addresses people’s frustrations, and has innovative solutions and the courage to change the systems. How do we get there? Find common ground. Do you know what most people care most about? The abysmal cost of healthcare. Start there. Fight for the human loudly. Too often, communications and engagement center on science with a capital S, funding mechanisms, or the CDC/FDA/NIH. Not the person. So the public doesn’t see themselves in it. Instead, they see people fighting for the very powerful systems that they feel negatively impact their health and well-being. Let the public feel and hear that you see their frustrations, you get it, and you’re fighting for them within the system. Recognize when pro-science messages are alienating people. Facts absolutely matter, but angrily venting only alienates people further. Our friend Elisabeth Marnik recently wrote a New York Times article about her experience growing up unvaccinated and how listening and empathetic conversation are the only ways to reach people that really work (a position backed by communication science). Her comments section was full of hateful comments from pro-vaccine individuals attacking her for daring to suggest we approach vaccine-hesitant individuals with empathy. It is possible to both stand firm behind scientific evidence and empathize with people who don’t trust it. Lean into politics smartly. Often, public health has shied away from politics: Don’t touch it, lest you get burned. But this fails to recognize that the third rail is what fuels the train: who is elected determines our budgets, our priorities, and our authority. Being political means being very savvy in strategy on both sides of the aisle, knowing your audience, and recognizing that political capital is as scarce as financial resources and needs to be allocated accordingly. Bottom line So does public health need MAHA? That’s not really the right question. Public health has a responsibility not to dismiss 40% of the country who feel heard by this movement and are frustrated that the system has failed them. And it has a responsibility to stick to the evidence and recognize MAHA leadership for what it is: a danger to our nation’s health. Both can, and should, be done. Love, YLE and KP A big thanks to Craig Spencer, who had the courage to put his neck out there to start a much-needed discussion at such a critical moment—one that is determining the identity of an entire field. Kristen Panthagani, MD, PhD is completing an emergency medicine residency and research fellowship focusing on health literacy and communication. In her free time, she writes the newsletters You Can Know Things debunking health myths and rumors and The Public Health Roundup. Views expressed belong to KP, not her employer. Your Local Epidemiologist (YLE) comprises a team of experts, ranging from physicians to immunologists to epidemiologists to nutritionists, working together with one goal: to “translate” ever-evolving public health science so that people are well-equipped to make evidence-based decisions. The YLE suite of newsletters reaches over 475,000 people across more than 132 countries. This newsletter is free to everyone, thanks to the generous support of fellow YLE community members. To support the effort, subscribe or upgrade below: Subscribe
Why does lithium work against bipolar disorder?
Lithium remains the gold standard for one of the most complex psychiatric conditions. Scientists are still getting to grips with why.
Ancient DNA reveals the mysterious collapse of Europe's megalith builders
DNA from a 5,000-year-old French megalithic tomb reveals that the people buried before and after a population collapse were genetically unrelated, pointing to a major migration after a devastating crisis. The shift coincided with new social traditions and the disappearance of the communities that built Europe's giant stone monuments.
Daisy Chain Fields is finally here. Follow along for live updates
Daisy Chain Fields, the all-women music festival created by Olivia Rodrigo and inspired by Lilith Fair, kicks off today. Here's what's happening.
Tony Awards 2026: 10 standout performances and shows
Moments that stand out from the 2025-2026 Broadway season include two performances by Laurie Metcalf, a radical reframing of 'Cats' and John Lithgow's towering performance in 'Giant.'
Ecobat Completes Sale of Lithium Recycling Business
/PRNewswire/ -- Ecobat, a global leader in battery recycling and resource recovery, today announced the closing of the sale of its lithium recycling business....
New Lithium-Plasma Engine Passes Key Mars Propulsion Test
You’re on the fourth human mission to Mars, and you’re told the Odyssey spacecraft designed to take you there will be the smoothest ride you’ll ever take. It features a newly christened electric propulsion engine which was in the late stages of testing during the first three missions. The mission starts and the spacecraft travels at a crawl, and you wonder if it’s broken. A week goes by and you’re now traveling at more than 400,000 kilometers (250,000 miles) per hour, and your mind is blown as to how fast you’re going, how quickly that happened, and that this mission might be more awesome than you thought.
Russia's neighbor reveals personal appeals to Trump as US weighs NATO troop pullback in Europe
Lithuanian President Gitanas Nausėda revealed he sent two letters to Trump urging U.S. troops to stay on NATO's eastern flank amid Russia threat.
Xenoblade Chronicles 2 – Nintendo Switch 2 Edition ‘Overview’ trailer
Publisher Nintendo and developer Monolith Soft have released a two-minute overview trailer for Xenoblade Chronicles 2 – Nintendo Switch 2 Edition, which is due out digitally on July 30 and ph…
Chinese scientists create battery that works comfortably way above boiling point
The tiny ceramic-based lithium-ion battery can withstand heat and still operate at up to 150 degrees Celsius, making it a safer power source.
Scientists just found a faster, cleaner way to extract lithium for EV batteries
A breakthrough lithium-extraction method could help solve one of clean energy’s dirtiest problems. Researchers at Columbia Engineering have developed a fast new technique that pulls lithium directly from salty underground brines using a temperature-sensitive solvent, avoiding the giant evaporation ponds that can take years and drain precious water supplies. Even better, the method works on low-quality lithium sources that current technologies struggle to use.
Baltic health ministers convene in Vilnius for 20th Baltic Policy Dialogue
Milestone anniversary edition focuses on long-term care investment as ageing populations place growing pressure on health and social systems across the region Vilnius, 6 May 2026 — Health ministers from Estonia, Latvia, and Lithuania are meeting in Vilnius today (5-6 May 2026) for the 20th edition of the Baltic Policy Dialogue (BPD), a milestone that marks two decades of structured, evidence-based health policy cooperation across the three Baltic States. Jointly organised by the governments of Estonia, Latvia and Lithuania, the European Observatory on Health Systems and Policies and the WHO Regional Office for Europe, the BPD has since 2004 served as a unique sub-regional platform where senior health decision-makers can candidly exchange experiences, examine comparative evidence, and explore policy options. Founded in the wake of the Baltic EU accession, the BPD series was born from a shared ambition: to open a wider window into health systems across Europe and to build lasting cooperation among countries with common aspirations and shared challenges.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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In Retrospect: Poland, Russia, Europe
In April I spent a few days with Zryw, a Polish non-profit organization that recruits young people to enter politics and public life. Their aim is to build a new generation of civic leaders in Poland. I’ve followed their evolution from the beginning; my son is one of the founders. (“Zryw” means “impulse” or “burst of speed” in Polish). Julie Chmielewska, one of Zryw’s leaders, interviewed me at the event. Here is the conversation, lightly edited for grammar and context: Julia Chmielewska: Assuming that culture shapes institutions, could we conclude that some cultures are more prone to authoritarianism? Anne Applebaum: I don’t think so. Every culture, every nation, and every country has the potential for change. When we look at history, we can see that nations do change. Poland has changed, for example, from the 1980s to today. There’s a completely different mentality here than the one I encountered when I first visited, in 1988. The current generation sees the world through a different frame. So no, I don’t believe that certain nations are doomed to authoritarianism, or to anything. Of course, there are political and cultural traditions, but they can always be challenged. JC: So do you think there’s something intrinsic in human nature that pushes people to democracy, freedom? AA: I think there is something in human nature, a deep instinct, that pushes people towards freedom, yes. People who live in authoritarian countries – and I’ve heard this from them over and over again – sooner or later find themselves angered by a feeling of helplessness. They can see the unfairness of crooked courts, irrational political decisions. They naturally dislike the fact that somebody has all the power while they have none. In those circumstances, people who have no political background at all sometimes are politicized just by that frustration. I’m thinking of Svetlana Tikhanovskaya, for example, who was a Belarusian housewife, until the circumstances of her husband’s arrest forced her to become a politician. I met a woman who is a Uyghur from China, and who had come to live in Turkey. After several of her family members were arrested, she too was propelled into a political role. These kinds of experiences make people interested in democracy or political reform, even if they thought they didn’t care. I also think that the opposite is true: some people instinctively prefer homogeneity, order, hierarchy. They don’t like the confrontation of opinions or the noise of debate, and they lean towards a single leader or a unified regime. I think that most of modern history is shaped by the clash between those two different sides of human nature. JC: Which force do you find more powerful today? AA: I think they both have a lot of power and there’s no way of predicting who wins. Even in countries that seem very shut off or stuck in an authoritarian system can change. We’ve seen that happen. And vice versa, I think democracies can also begin to fail and slide into authoritarianism. So it’s very important not to be complacent in either direction. JC: I want to go into your history and your experiences. You’ve lived in Russia during a time of incredible change in the late 80s, and then you came back to do research in post-Soviet Russia. AA: I was a student in Russia just before the collapse of the Soviet Union. I then traveled and worked there extensively in the 1990s, and I met people who really were full of hope. They hoped that Russia could become a democracy, or at least a place that guaranteed freedom of speech, freedom of the press. These weren’t ideas that came from Washington. Although now the narrative in the Kremlin is different, I met many people who were working towards exactly that kind of transformation. A friend of mine ran a series of seminars – once a year, and then later several times a year, in cities all over Russia – designed to get people to discuss politics in new ways. She invited young politicians and journalists, as well as foreigners. I went to many of them, in Moscow as well as Volgograd and Novosibirsk. Over two decades, hundreds of people came to these seminars, and all of them wanted Russia to be different. I remain convinced that many Russians still want Russia to be different. It’s just that the old system, in the form of Putin, a representative of that system, returned. The KGB reimposed their power. And this wasn’t because of something to do with culture, this was to do with money and politics, and who was in charge. JC: You’ve partially answered my question... I wanted to ask whether that excitement of the 1990s was an exception from the Russian historical norm which has been rather authoritarian? AA: Of course, if you look at the history of Russia since the 18th century, there have always been liberal groups, reformers and revolutionaries. There were the Decembrists, in the early 19th century, and the rural populists later on, who tried to organize the peasantry. A significant group of liberal Russians appeared at the turn of the 20th century, people like the father of the writer Vladimir Nabokov, who was a Russian politician before the revolution. These groups were small in number, but sometimes had a broader significance. The Russian dissident movement in the 1950s and 1960s actually invented the modern human rights movement. It was their idea to hold the leaders of the Soviet Union accountable for the language they used, to remind them of the treaties they had signed and the promised they had made. They created the Helsinki group, for example, that held Soviet leadership to the language of the Helsinki Treaty, which formally ended the Second World War and which contained guarantees of human rights, at least on paper. That idea spread to Eastern Europe, and similar tactics were used here in Poland. (Benjamin Nathans recently wrote a great book about the Soviet dissidents, To the Success of Our Hopeless Cause) JC: But seemingly, even if they do ever get power, they could never hold on to it. AA: We don’t know, because they have never really had power. But in any case, we also don’t know what will happen in the future. There is no reason to assume that Russia will forever be condemned to totalitarianism. Even during the first fifteen years of Putin’s regime there was some form of democratic politics. Only when the full-scale war began did he bring everything to an end: he shut down all remaining independent organizations and killed his most important opponent, Alexi Navalny. But does that mean he is popular, that he enjoys legitimacy? Even now, we don’t really know what Russians think about him, or about the war. There is no way of doing real polling in Russia because nobody will answer an independent pollster over the phone. JC: Do you think that the flock of young people, especially young men, who fled Russia after the start of the war represent a continuation of liberal movements that refuse to partake in the authoritarian state, or do you think they are moving for the sake of self-preservation – “I don’t want to go to the army, so I leave”? AA: I’m sure it’s both. I actually know many people who left Russia for political reasons either in the very last years before the war, or else just after the war began. JC: And do you see a change in the young generation versus the old one that have fled? AA: It’s hard for me to say because the people who I know were mostly already politicized. I do know some younger people who left, but most of them were already either active in the opposition, or working as journalists. Many of them very self-consciously think of themselves as maintaining Russian culture abroad, just as in the 20th century the Soviet dissidents or the anti-communist White Russians once thought of themselves as people who maintained the true Russian culture, outside of Bolshevik Russia. JC: Let’s move on to Poland. One of your first experiences with Poland was reporting on Margaret Thatcher’s first state visit, in the autumn of 1988. You followed her around the farmers’ market. AA: She was making a symbolic gesture. She wanted to welcome free markets, but the only one she could really visit was the farmers’ market at Hala Mirowska. JC: And I want to talk about this area because today you can look out of any window in that district, Mirów, and see rows and rows of skyscrapers. How does it feel to see a country built from the ground in such a short time, both politically and economically? AA: You know, when you’re living in a period of dramatic change, it’s always hard to know whether the change is positive or negative. The transformation in Poland created winners and losers, as well as new classes of people, new political movements of different kinds. At the time, it sometimes just felt like turbulence. Now, we can look back at the 1990s and early 2000s in Poland and see in retrospect that the country was headed in towards prosperity and European integration. In around 2009 or 2010, I remember speaking to a woman who worked cleaning government offices, and who asked me if her daughter should study in Amsterdam or in London. This seemed to me to be a real transformation, and it happened very fast: within a few years, Poles stopped feeling like second-class Europeans, and a generation of younger Poles appeared who had no qualms about crossing borders. JC: We again live in turbulent times. Do you think we’re heading towards positive outcomes? AA: I can’t make predictions, because everything that happens tomorrow depends on what people do today. Also, history doesn’t have a trajectory. It doesn’t move in a particular direction. You only think it does afterwards. As I said, you can look afterwards at Poland in the 1990s and you could say this was a period of great progress. But not everybody at the time saw that. Sometimes people are very wrong about a given country’s trajectory. I remember people writing about Ukraine in the 1990s, about how dangerous it was that Ukraine was independent, that this was going to be an anti-semitic state, that Ukrainian nationalism was going to come back... and although you can say many bad things about Ukraine, the country made many bad choices, actually it became a pretty tolerant state which now has a Jewish president and until recently a Muslim defense minister. JC: In the 1990s Poland’s and Ukraine’s GDP were roughly similar. Ukraine was even a bit richer. So the starting point was similar for both of these countries, but they’ve turned out very, very differently. Even if we stop in 2014. Why do you think Ukraine “chose East”? Was it external influence? AA: No, I think Ukraine was in a different position. First of all, central and eastern Ukraine had been part of the Soviet Union since the 1920s, and had therefore experienced a longer period of occupation, repression, Sovietization and even Russification. Ukraine did not have, as Poland did, an alternative elite: a large cadre of economists and politicians, who already had some experience in opposition politics and in independent thinking. In Poland, the transformative finance minister, Leszek Balcerowicz, had already thought about how an economy might be decentralized before he took office. We can argue about how successful he was, but at least he was prepared to try something new. In Ukraine, people weren’t prepared. For one, there hadn’t been much space even for an illegal opposition in the previous couple of decades. Ukraine was also in many ways still emerging from colonial occupation. For the previous couple of centuries, many of the most capable Ukrainians had moved to Russia, and the first generation of leaders in independent Ukraine tended to be former Soviet apparatchiks. They didn’t immediately seek to become closer to western Europe. Instead, they looked for some kind of economic and political “third way” and an accomodation with Russia. Ukraine became stuck in this position, half-in, half-out and became pretty profoundly corrupt. JC: The Polish alternative elite had a vision of where they wanted the country to go. I think the general perception now is that this vision ends with the next election, right? Is this a natural process of gaining power? AA: Their vision, and it was shared by the time by politicians who now call themselves both left and right, was that Poland should join the EU and NATO, as fast as possible. My husband (Radek Sikorski) was in the very first government that said it wanted to join NATO. At the time this was taken very badly in Washington: the demand for NATO membership absolutely came from Poland, not from the US. But even then, in the early 1990s, many Poles already understood that the Russian sphere of influence would grow once again, that it was important to become part of the transatlantic alliance and an integrated Europe as fast as possible: NATO, the EU, the Council of Europe, all of the trading and security alliances. That consensus lasted through several different governments and over many years, even governments containing former communists. For twenty years, right, left and center disagreed about many things, but they all agreed on the direction that the country should go. In retrospect, that consensus created the basis for prosperity in Poland. JC: And regarding the Polish-Ukrainian relations. We know that antagonisms, e.g. the myth of Wołyń [a massacre of Poles that took place in what is now Western Ukraine, in 1943] are increasingly used in Polish political discourse today. In Ukraine, nationalist historians make heroes out of UPA, the Ukrainian revolutionary army, which is held responsible for this tragedy. Where do you see a start for burying the hatchet? Is the reconciliation of our nations possible? AA: So here’s a strange thing: For more than a decade after they both gained independence, Poland and Ukraine participated in a number of projects that were designed to solve exactly these kinds of Polish-Ukrainian differences. Books were published that were jointly written by Polish and Ukrainian historians, monuments were built. These projects were successful: If you’d asked me this question in 2010, I would have said that there are no real historical issues between Poland and Ukraine, that the two countries had mostly reconciled. For a number of reasons, this began to shift. In Poland, children and grandchildren of victims of the Wołyń massacre felt their tragedy hadn’t been fully recognized. In Ukraine, nationalist groups wanted the UPA partisans who had fought against the Soviet Union recognized for their heroism, despite the fact that some in this broad and not well-defined group were also linked to Wołyń. In both eastern Poland and western Ukraine, the memory of the ethnic cleansing that took place there in the late 1940s - Poles were moved West, Ukrainians East - to accomodate new borders has left feelings of displacement and bitterness. The wave of Ukrainian immigration, which started before the war, may have provoked some of this. But don’t underestimate the role played by Russia, which has always wanted to create discord between Poland and Ukraine, and pumps out propaganda to that effect in both countries. Vandalism on both sides of the border, damage done to cemeteries and monuments, is sometimes carried out by provacateurs working for Russia, just to create bad feelings. The Polish-Ukrainian conflict also hides a different reality: although there are real grievances and bad memories, the truth is that the biggest tragedies both nations experienced in the twentieth century were inflicted by the Soviet Union and Nazi Germany. That should unite these two countries, not divide them. JC: This week (19.04.2026 – Ed.) in Hungary we saw that using historical narratives to create grievance has no longer worked. Are you optimistic about the direction after Orban’s loss? AA: The Hungarian election was really important because it shows that people can actually resist powerful, dominant propaganda. The ruling party Fidesz controlled all of the TV, 90% of the newspapers, the constitutional court, the bureaucracy... and yet people had the nerve to vote against it and resist it. It’s also an important election because Hungary created a huge network of well-funded think tanks and foundations that were funding other far right groups and projects. So that loss is going to have a knock-on effect in other places too, maybe even in Poland. JC: What you’ve said about resisting propaganda reminds me of one of the interviews you did about talking to Russians in the post-Soviet era who claimed that people knew that the system was lying. Why do people choose to believe in these regimes anyway? AA: Because it’s useful. Stephen Kotkin, an American historian, once described how people would learn how to “speak Bolshevik”: It was just a language that you needed to use in order to get by in society. If you didn’t talk the way the regime wanted you to talk, then you might have problems, or lose your job, or your kids would not get into university. It was a way of getting along. Communist Poland was similar, at least in the early years. When I was writing a book about the Sovietization of Eastern Europe after World War II, I met a lot of people who wanted to talk a lot about the war, when many of them had done really heroic things. But almost nobody wanted to talk about the decade afterwards, between 1945 and 1956. This was when you had the short period of terror, violence and Polish Stalinism. To stay safe, people felt the need to just go along with what others were saying, or stay out of politics, or use communist jargon without necessarily believing it. I don’t judge them for it, and I wouldn’t describe all of those people as collaborators. It’s easy to feel moral certainty in retrospect, because we know that communism ended. But if you were living in 1949, it might not have been clear to you that communism was going to end. In very repressive societies, maybe about 10% of people who are really evil – collaborators, torturers. Maybe 10% of people are really brave and who find ways to resist. And then around 80% of people have kids, they have parents, they have to have jobs and they’ve had to get through it somehow. Strange though it may sound, I’ve found that the work I did on that book is now very useful in explaining some of what’s going on in the United States today. There are plenty of members of the Republican Party in Congress who know perfectly well that Donald Trump says many things that aren’t true. But they avoid criticizing him because it’s inconvenient, because they would get in trouble, because someone would attack them on the internet. So actually you don’t even need mass terror to get people to conform. JC: Is Gen Z reinventing agency? AA: We’ll see. In any generation you can find groups of people who want agency. If you live in a society that’s unfair, for example where a tiny number of people have captured most of the wealth, then at a certain point people rebel. This is always easier for younger people, who have you have less to lose. The question now is how the internet will affect the relationships between citizens and the state, and how it will change organizations. The “Twitter revolutions” people spoke about as early as 2008-9, mass protests organized online, have often proved to be very superficial. Although you can easily join something just by clicking, the work of creating a real movement requires physical participation. Successful mass movements of the past, for example the Civil Rights movement in the United States, were built by people who had spent many years together. They had participated in non-violent workshops together. They practiced and prepared. Just using the you can get everybody to show up at a certain moment, but then when the protest is broken up, nothing happens. It’s also true that the repressive regimes have more recently learned how to use the internet to undermine leaders and movements. Most of all, they now understand how to make people cynical. The form of propaganda that most modern authoritarians use - and I think the Russians really pioneered this - deploys sneering cynicism. Instead of praising the rulers, the regime propagandists mock the opposition movement leadership for being supposedly corrupt or sexually degenerate, with the goal of undermining any kind of idealism. JC: MAGA grew on the internet? AA: MAGA is a real grassroots movement. They had symbols, red hats, they showed up at rallies. But you’re right that the cynicism, the sarcasm and the distrust that the movement embodies came originally from the internet, and this is different. Fifty years ago, most European political parties had a social base in real organizations, in trade unions for Social Democrats, in church groups for Christian Democrats. As people stopped going to church and as the trade unions became smaller, the social base of these parties disappeared. Now people who wouldn’t have known one another in the past meet on the internet and create new movements, many of which don’t last. JC: Is history ending? Going in stale circles? AA: History never ends. In truth, human beings want contradictory things at the same time: order and freedom, stability and change. These things are never resolved, and when a society swings too far in one direction, people always push it the other way. But each time that happens, the result is different. Certainly it is true that we are now in a period when old philosophers and ideas from the 1930s are undergoing a revival. Carl Schmitt, who was a philosopher who was very influential on the Nazis, is back as an influence on both the far left and the far right, once again inspiring people to think that all politics has to be existential, that all politics is about defining and defeating enemies. In the US, some are also bringing back dominionism, the idea that we need a Christian and not a secular state. It’s also true that we are living through a more fundamental shift. The old left-right divide, which was mostly about the size of the state, is much less important now. Instead, we are arguing about more fundamental things: what are our rights, what protects our freedom. Or how much power do we want to give small elites, versus how much power to give ordinary people. In America a small group of very wealthy people now control information, because they control the social media platforms and AI, which means they determine what people will read and learn. Finding a way to preserve preserve zones of autonomy and independent thinking, this is going to be the main task for the next generation. JC: What is the one book that a person interested in Central Europe should read? AA: You could read my book “Iron Curtain: the Crushing of Eastern Europe” which tells the story of how the Soviet Union imposed its culture on the region. Or read Tim Snyder’s history of the region, “The Reconstruction of Nations: Poland, Ukraine, Lithuania, Belarus 1569-1999.” And everyone should read “The Captive Mind” by Czesław Miłosz, which describes exactly the phenomenon we were talking about: why do people collaborate? I joined Scott Galloway and the brilliant Fiona Hill in a discussion about the wars in Ukraine and Iran, the future of global power, and what these conflicts reveal about America's role in the world. Scott told us that this was the 400th edition of his podcast, which is quite a number: My friend Francesco Chiamulera runs a brilliant series of literary events, Una Colline di Libri, A Hill of Books, in the Prosecco Hills, a region of vineyards and elegant hill towns in the Veneto, north of Venice. We did an event in Vittorio Veneto and also drove and biked around the countryside. Buy Autocracy Inc Buy Iron Curtain Open Letters, from Anne Applebaum is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
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A newly developed electrolyte additive could help lithium-ion batteries keep graphite anodes stable over prolonged cycling. Researchers synthesized pentafluorophenyl thiophene imine (FPTI), which forms a protective, LiF-rich solid electrolyte interphase on graphite. At 4 mg/mL, FPTI enabled 95.6% capacity retention after 1,000 cycles in graphite/Li half-cells and improved lithium-ion transport. NMC811/graphite full cells using FPTI-conditioned anodes reached an energy density of approximately 233 Wh/kg, highlighting its potential for longer-lasting battery systems.
Leak lists Zelda: Ocarina of Time remake developer as Xenoblade Chronicles studio
A retailer may have inadvertently leaked information about the Ocarina of Time remake. Elkjøp specifies Monolith Soft as the lead developer for the Switch 2 game. While the Xenoblade Chronicles studio has supported Nintendo EPD in recent Zelda projects, its leverage over the franchise has grown.