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10X Health Launches Metabolism Genetic Test
A saliva-based test provides genetic insights to help inform personalized nutrition and weight-management plansSCOTTSDALE, Ariz., Oct. 21, 2026 (GLOBE NEWSWIRE) -- 10X Health, a leader in personalized health optimization and performance-driven wellness solutions, today announced the launch of its Metabolism Genetic Test. For individuals looking to optimize their wellness routines, 10X Health’s Metabolism Genetic Test gets at the root of why and how your body responds to food, exercise and appeti
Four Red Flags and One Truth Amid the Peptide Hype
Experimental peptides are all the rage on longevity and “optimization” podcasts, but a lot of the chatter is misleading.
Registration is open for high school winter sports
Registration is now officially open for high school winter sports for the City School District of Albany! Any student in grades 9-12 who is interested in trying out for boys' basketball, girls' basketball, bowling, cheerleading, boys' indoor track, girls' indoor track, spirit team, boys' swimming and diving, boys' wrestling and girls' wrestling is invited to register via Final Forms. Important: please note that registration for winter sports ends on Friday, Nov. 13. Practices and tryouts for winter sports begin on Monday, Nov. 16. FINAL FORMS Each season, the following must be done prior to the first day of tryouts and practices: A parent or guardian must initiate the registration process for their student-athlete in Final Forms, filling out the required forms such as Interval Sports Health History and the Athletic Consent Form. The student-athlete must sign and complete their required forms. A reminder that all students who would like to play an interscholastic sport need to have a current physical conducted within a year on file. PHYSICALS A physical conducted within the last 12 months is mandatory for any student interested in trying out for an athletic team and must be uploaded into the Final Forms platform. Families are encouraged to get a completed physical from their child's physician. If you are unable to get a physical from your child's physician, you can schedule a free physical with Whitney Young's school-based health center by calling (518) 573-2556. Additionally, the district physician will also be available to facilitate sports physicals at Albany High in room 4253 on the following dates: Thursday, Nov. 12 from 10:30 a.m.-2:30 p.m. Friday, Nov. 13 from 10:30 a.m.-2:30 p.m. Sports physicals on Nov. 12 and 13 are free and no appointment is necessary. ACADEMIC ELIGIBILITY REQUIREMENTS Please note that students must have a good attendance record and be in good standing academically to be eligible to participate in an athletic team. Eligibility is determined based on quarterly grades, and interim progress reports will serve as an important academic checkpoint for all student‑athletes. For additional details about academic eligibility, please see our Athletic Code of Conduct. For our winter teams, academic eligibility to start the season will be based on final first-quarter grades. The first marking period ends Nov. 13. Albany High offers free tutoring facilitated by Albany High teachers Monday-Thursday from 3:30-5 p.m. for students who need extra help with their academics. See this flyer for additional details. IMPORTANT DATES Seniors, please mark your calendars for Senior Media Day for winter sports, which will take place on Monday, Nov. 30. All student-athletes playing winter sports will also participate in our winter sports picture days, which will take place Tuesday, Dec. 15–Thursday, Dec. 18. Specific dates and times for each team will be shared once rosters are finalized. OPEN GYM SESSIONS Student-athletes are encouraged to check out our open gym sessions as they prepare for upcoming sports seasons. We’re looking forward to a rewarding winter sports season this year! If you have any questions, please contact the Athletic Department at (518) 475-6310. Go Falcons!
ConocoPhillips Reviews Norway Business & UK Teesside Asset Divestment
COP is weighing a potential Norway and Teesside asset sale valued at about $7 billion, supporting portfolio optimization and capital flexibility.
Quantum in Business Conference Highlights Commercial Quantum Applications
EPB Quantum’s Chattanooga conference highlighted business use cases for quantum computing, networking, cybersecurity and energy optimization.
Open Machine CEO Allie K. Miller discusses using AI in her daily life
Allie K. Miller, the CEO of Open Machine, shares her daily routine, utilizing AI tools for productivity and personal lifestyle optimization.
Verana Health Introduces Significant Data and AI Enhancements to Support Ophthalmologic Research and Treatment Optimization
/PRNewswire/ -- Verana Health®, a digital health company dedicated to revolutionizing patient care and clinical research through real-world data (RWD),...
Microsoft Has A Mountain To Climb To Address Windows 11 Optimizations, But Newest 26H2 Update Tackles Memory Usage; 8GB RAM Systems Left Out
Microsoft has a mountain to climb on Windows 11 optimizations, but the newest 26H2 update tackles memory usage, though systems with 8GB of RAM are left out
Brian Grose, M.D., Joins Baptist Health Primary Care as a Family Medicine Physician
September 11, 2026 – Board-certified family medicine physician Brian Grose, M.D., has joined Baptist Health Primary Care. He provides comprehensive primary and preventive care, with clinical interests that include chronic disease management, health optimization and screening for obstructive sleep apnea, diabetes, heart disease and cancer. He is particularly interested in helping patients better understand their […]
Broward Health Names Kristina Fueyo Vice President of Growth and Physician Strategies
Broward Health is pleased to announce the appointment of Kristina Fueyo, as vice president of growth and physician strategies. Most recently, Fueyo served as assistant vice president of growth strategy and network optimization for HCA East Florida where she led initiatives to strengthen physician alignment, improve patient access and support service line growth across a […]
AMD Ryzen 7 9800X3D Memory Performance Scaling
The AMD Ryzen 7 9800X3D set new benchmarks in gaming performance with its impressive 96 MB L3 V-Cache. But how does memory latency factor into this powerhouse's performance? Our latest analysis dives deep into memory performance scaling, and could change how gamers approach system optimization.
Scientists want these 5 'maxxing' trends dead
The “-maxxing” trend promises that extreme optimization of your sleep, appearances, fitness, diet, or wellness routine will somehow unlock a better version of you. But when health advice becomes a competition to optimize every single thing, real science often gets lost. Our scientists break down the -maxxing trends they really want you to stop—and what the evidence actually says.
Huawei Pura X View hands-on reveals unusually wide smartphone
Huawei’s Pura X View pairs an unusually wide 16:9.5 OLED display with strong cameras, a 7,000 mAh battery and a design praised for comfortable typing, reading, video and gaming. However, importing the smartphone may not be ideal due to uncertain global software optimization and app compatibility.
A20 Pro’s Packaging Shift And New Vapor Chamber Unlocks Peak Performance; Liquid Nitrogen Cooling Brings Less Than 3% Increase Thanks To These Optimizations
Discover how the A20 Pro chip packaging shift and custom vapor chamber unlock massive peak performance upgrades, making liquid nitrogen cooling practically obsolete with under 3% gains
Engrams Embedding Entendre: Codesign for Efficient DRAM/SSD Offloading
Engram extends standard token embeddings with learned multi-token lookups. Recurring local patterns retrieve vectors directly, reducing the need to reconstruct them through attention and feed-forward layers. With Engram model architecture optimization, it allows for lower HBM capacity to be needed for models at the same quality. This does not mean there won’t be an insane demand for HBM but it just means that model architecture will continue to innovate around constraints. This model architecture design is naturally codesigned for parameter offloading: each token accesses a few embedding rows whose addresses depend on token IDs, not hidden states. The runtime can prefetch those rows from host DRAM while earlier layers compute, keeping the table outside HBM without transferring entire weight matrices. Our Memory model contains our latest estimates of quarter by quarter HBM, DRAM, & NAND supply and demand. Offloading frees HBM for model weights and KV cache, potentially supporting larger batches or more concurrent sessions. When DRAM becomes the next constraint, NVMe offers another tier. Recommendation systems already cache frequently or recently accessed embedding rows in faster memory while backing colder rows with SSDs. After NVIDIA roadmap had to change due to massively despec’ing Rubin Ultra from 1024GB to now ~200GB of HBM per chip, model architecture optimizations like emgram maybe helpful. Our DeepSeek-V4.1-Flash configuration uses roughly 189 GiB of memory for Engram. We replace it with a memory-mapped (mmap) file and measure serving performance with offload to SSD. Later on in our report, we will show our Engram offloading experiments along with the official InferenceX agentic inference serving results on Engram models like DeepSeekv4.1 Flash across all 6 NVIDIA GPU SKUs along with MI355X. Unsurprisingly, the CUDA Moat is still mogging MI355X on the ultra popular DeepSeekV4.1 Flash model. We also show how even on high capacity HBM SKUs, offloading emgrams to DRAM could result in even better performance for most of the pareto than keeping the emgram in HBM. Our benchmark has been widely reproduced, validated and/or supported by almost every major buyer of compute from Google Cloud to Microsoft Azure to Oracle, to Meta and many more. Furthermore, it has the support of the ML community including from vLLM, LMCache, SGLang, PyTorch, Huggingface and the support of major labs like OpenAI, MiniMax, ZAI, Qwen, Moonshot Kimi, etc. Star the InferenceX GitHub repository if you find the open-source benchmark and data useful!. InferenceX is the only inference benchmark in the world to have TPUv7, Jalapeño, Nvidia Rubin NVL72, AMD, and soon, SambaNova and Trainium. Due to how realistic AgentX scenario is to real world agentic inference workloads, AMD has committed to collaborating on MI455X UALoE72 too. DeepSeek did not release the original paper’s two trained Engram models. We replicated its setup on fineweb-edu using the released code and training hyperparameters, at an estimated 6E18 FLOPs per run. We observed the same U-shape scaling: Engram improved performance over pure MoE baselines. We also reproduced DeepSeek’s results, where earlier-layer representations with Engram resembled those of later layers. Like the original Engram paper, it is possible to probe Engram’s gate scores to see what n-grams DeepSeek-V4.1-Flash makes the most use of. Our gate scan finds names, code fragments, relational phrasing, and boilerplate. These examples prioritize interesting-ness over gate strength. One unexpected result was Wright : Ace Attorney. These examples suggest learned memory optimizes the training objective, not a judgment of which facts deserve storage. Licenses, bibliography fragments, API scaffolding, and website furniture can provide prediction shortcuts, so the value of additional Engram capacity may depend on what survives data preparation. This does not show that table capacity is “wasted”: the evaluation-corpus scan establishes neither training exposure nor the capacity occupied by each category. For offloading, strong gates do not identify cache-hot rows. Low gates do not automatically save reads either: computing the gate requires the retrieved key and undoes the performance gain of a fused kernel. Skipping reads would require a separate usefulness predictor before retrieval. In the original paper’s inference-time ablation, factual-knowledge benchmarks retained just 29–44% of their original performance, while reading comprehension retained 81–93%. This is due to the training–inference mismatch. The resulting degradation therefore measures this trained model’s dependence on Engram, not the performance difference between models trained with and without it. In our ablations, suppressing Engram worsens token likelihood across all evaluated domains, especially encyclopedia text and several code corpora. Surprisingly, GSM8K accuracy stays within measured run-to-run variation and removing Engram has no effect. Engram is not a detachable dictionary beside an unchanged MoE. Removing it changes downstream features and expert selection. We tested whether rerouting hurts or compensates by holding tokens fixed in a teacher-forced experiment on CRUXEval, a code-reasoning benchmark of small Python functions where the model predicts a function’s output from its code and an input, and scoring the reference answer. Removing Engram raised answer loss from 0.2848 to 0.3093 bits/token. Forcing the ablated model to use the original Engram-on expert choices made it worse still, at 0.3375 bits/token. Rerouting partially compensates for the missing memory. Memory features and expert selection work together, rather than following a clean “memory stores facts; experts reason” division. On the same CRUXeval, removing Engram during either phase reduced accuracy and increased generated tokens; removing it throughout produced the largest changes. Keeping Engram for prefill leads to more correct answers than keeping for decode likely due to semantically richer KV cache transferred to decode workers, allowing it to mitigate some of the performance loss. Engram’s table is large, but each lookup is small. DeepSeek-V4.1-Flash requests 24 rows at each of two Engram layers, about 12.4 KiB per processed token position across the model, or 3.1 KiB per GPU when split across four GPUs. Currently as of Day 7 since Model Release, MI355X is still 2-4x worse performance per dollar compared to B200 even when normalized by Mi355X’s lower TCO. Our full total cost of ownership breakdown comes from our AI Cloud TCO Model along with monthly market surveys of over 100+ gpu clouds & gpu cloud customers. On the Day 0 release of DeepSeekv4.1 Flash, NVIDIA vLLM works out of the box with zero issues across all 6 SKUs: H100, H200, B200, B300, GB200, GB300! This was thanks to the amazing work by the NVIDIA & Interact teams! In comparison, AMD vLLM did not work on day 0 for DeepSeekv4.1 Flash.Source: SemiAnalysis InferenceX AMD’s vLLM documentation points to using vllm/vllm-openai-rocm:deepseekv41-flash-0909, but from hour 0 of the model release to hour 23, AMD has not publicly released the image. AMD claims, “SPEED IS THE MOAT,” yet it has still not released it by the 23rd hour. We wish that, going forward, the AMD team has a better process for hour 0 model releases. Eventually when they did publicly release for “day 0” image support, performance-wise, it is currently up to 14.8x worse perf per dollar than H200 and up to 42x worse perf per dollar than B200/B300. The power of the CUDA MOAT is NVIDIA’s collaboration with its massive 6 million-developer community ecosystem including most of the vLLM & SGLang & Tokenspeed maintainers which means that CUDA is optimized on day 0. Overall, AMD did make significant improvements but the performance per dollar is still currently 2-4x worse than B200. AgentX Engram DRAM Offloading Improving Performance The HBM and DRAM offload use the same GPU kernel to select and dequantize rows. With HBM, it reads GPU memory; with Unified Virtual Addressing (UVA), it reads pinned host memory directly. Both support full decode graphs. Moving the table into HBM accelerates only the sparse lookup, leaving decoder computation and communication unchanged, resulting in little overall benefit while consuming memory otherwise available to KV cache. Another benefit of Engram offloaded to DRAM which means you can reduce the communication overhead by using less HBM GPUs per replica. For example, when enabling Engram offloading on B300, we are able to switch from TP4 to now TP2 which improves the pareto curve by up to 1.6x. When iso-model quality, less HBM is required as the engrams could be offloaded to host DRAM. Thus HBM bandwidth matters way more than HBM capacity. For inference workloads where memory bandwidth matters the most, 4-hi HBM provides the best $/bandwidth and therefore lowest cost per token. If China continues to make more and more revolutionary model architecture innovations, soon it could potentially 0Hi HBM stacks. [ ](https://newsletter.semianalysis.com/p/long-live-the-short-king-why-4-hi) [ Long Live the Short King: Why 4-hi HBM Wins ](https://newsletter.semianalysis.com/p/long-live-the-short-king-why-4-hi) Myron Xie, Bryan Shan, and 3 others · Sep 13 [ Read full story ](https://newsletter.semianalysis.com/p/long-live-the-short-king-why-4-hi) Moreover, on B300 and week-0 stack, moving the Engram table back to HBM did not improve results and stay within run-to-run variance. This is a result of the work optimizing DRAM offload, such as async, and overlap. SSD Offloading On B200, we created a unoptimized vLLM fork and stored the Engram tables in memory-mapped files on local SSDs. File backing lets the OS reclaim table pages when other applications need RAM. Pages already cached in memory can be served without reading the SSD again. Furthermore, note that we were unable to turn on GDS The unoptimized SSD implementation changes how rows reach the GPU. It copies row IDs to the CPU, deduplicates them, gathers the requested rows into pinned buffers, copies those rows back to the GPU and dequantizes them. This work runs between segments of the GPU execution graph. Native UVA performs row selection and dequantization directly on the GPU, avoiding the CPU round trip. A warm filesystem cache removes physical SSD reads, but leaves the coordination, row gathering and transfers. This is why a file already cached in RAM can still perform worse than a pinned DRAM table. The comparison measures the whole serving path; it does not separate the time spent on each of these operations. B200 DRAM dominates both measured SSD serving curves in total tokens per dollar and P90 interactivity. Near 125 tokens/s/user, DRAM delivers 121 million total tokens per dollar versus 52 million for SSD. For production serving, SSD offloading is likely not worth the tradeoff. On the B200 configurations we measured, SSD offloading loses on both measures: every observed SSD point has a DRAM alternative that delivers higher P90 interactivity and more total tokens per dollar. The only points where Cheaper storage does not automatically produce a cheaper inference service. Moving Engram to SSD leaves the same four expensive GPUs and the rest of the server in place. Reclaiming RAM only creates an economic benefit if it enables a cheaper server configuration or additional useful capacity. The current unoptimized path provides neither benefit, and the filesystem cache still consumes RAM when table pages are resident. Next we will look at the mechanisms and specific implementation of ngrams from DeepSeekv4.1 Flash, LongCat, Qwen3.8 Flash Next.
Can windows cool buildings without electricity?
Thermochromic smart windows can automatically adjust solar and thermal radiation in response to temperature, offering a passive route to reduce building energy demand and improve indoor comfort. A new review published in Science Bulletin examines why these windows have not yet achieved large-scale application, despite rapid materials progress. The authors identify key challenges in spectral regulation, switching temperature, response speed, durability, scalable fabrication, glazing integration, lifecycle impacts, and building control. They argue that future development should shift from isolated material optimization toward deployment-oriented design and system-integrated adaptive building envelopes.
FPL Gameweek 5 Top Transfers: The Best Players to Buy
As we head into Gameweek 5 of the 2026/27 Fantasy Premier League season, manager strategy shifts from early-season observation to targeted squad optimization. Favorable fixture swings and rising form assets present the perfect opportunity to use your free transfers to surge up your mini-league standings. Whether you are restructuring your defense or looking for explosive […]
Wilmington health tech founder launches new venture
Several years after launching his health tech startup Artemis Immersive, founder Adam Isley is setting his sights on new horizons. Co-founded in 2023 by husband-and-wife Adam Isley and Kaylan Barbrey, along with Matthew Raffa and Bill Blakesley, Artemis Immersive began as a spatial medtech company that created digital renderings of medical scans for viewing in augmented reality (AR). Isley said the firm, which won an NC Tech award in the Biotech + HealthTech Innovation category last year, has raised $1.2 million in total in seed funding since launching. Isley has since created a new venture, Research and Me, building on the Artemis platform. Like Artemis Immersive’s core software, VoxScan, Research and Me combines health data with artificial intelligence in a 3D interactive environment to help patients better understand health outcomes and provide integrative wellness support. While the Artemis product is no longer Isley’s primary focus, he said the company’s technology and ambitions have evolved into different ventures, like Research and Me. "It's a different venture building on the Artemis platform, and there'll probably be more,” Isley said. He added, "I was very disappointed in the quality of the information available to general patients about their healthcare... I wanted to give patients more and a better plate of choices." Research and Me is still in its beta phase, Isley said, with usability testing ongoing in partnership with the firm’s partner, Medicap Pharmacy and Wellness Center, owned by Barbrey. "As someone who's kind of dedicated their life to working in healthcare, I've tried to bring this spirit and passion to it,” he said, “and a lot of the resources that we'll be providing are free — like a base level of free care for any patients, or medical education if they've got specific conditions." Isley describes Research and Me as a “patient-first” platform designed to securely store and pseudonymize health data and use AI and medical literature to generate insights. The insights are presented in an interactive 3D environment for patients and providers to explore conditions, treatments and wellness plans together. "It's almost like a democratization of understanding medical information," Isley said. "We take a whole bunch of clinical data, we take a whole bunch of peer‑reviewed, published studies on PubMed, and we try to turn them into chunks of information that normal humans can understand." Like VoxScan, the Research and Me platform lets users interact with 3D anatomical models for visualization. The platform provides a space for tracking, notes and insights. The platform also supports video conferencing, Isley said, allowing providers or coaches to examine models and data together. "We wanted to create a safe environment where you can start to learn and experiment with new features about your health, using agents to do that,” Isley said. While Research and Me is in beta-phase testing with Medicap Pharmacy, Isley said he envisions the platform serving a wellness-oriented community, working with sports performance clinics and hormone optimization. Isley, who is working towards a wellness-coach board certification, also plans to offer functional wellness consults through the platform. Long‑term, Isley says he wants the platform to embody an “integrative health practitioner” approach, “connecting experts of different fields and specializations in a way that they can make a greater impact in people's lives.” “For people in the state of North Carolina, it's already a win,” Isley said of the Medicap rollout, noting that partner clinics get “immediate resources for learning about their health and wellness conditions… out of the box.” Isley plans to launch Research and Me’s provider portal in 2028 and begin pursuing integrations with larger systems, he said.
USC awarded $5.6 million from the National Science Foundation
The award would go towards AI optimization on campus.
Fastbreak AI is quietly becoming the scheduling engine for 50-plus pro leagues
Fastbreak AI says it schedules 50+ pro leagues. The ops implication: scheduling is now a multi-constraint optimization problem tied to travel, venues, and media
NVIDIA Confirms DLSS 5 Support Extends To RTX 40 GPUs, But First Focusing On Model Optimization on RTX 50 Series
NVIDIA DLSS 5 is going to be released on older RTX 40 GPUs and will be available once the model is fully tuned on RTX 50 series.
Home sports competitions kick off at The Nest
Albany High hosted its first home sports competition of the 2026-27 season at The Nest on Tuesday evening as our boys' soccer team faced off against Schalmont! Our Falcons delivered a thrilling win, defeating the Sabres 4-0. Ahadi Wangya, Adam Rouse, Garnett Ngome Ekiti and Rajanie Morgan each scored a goal, with Ngome Ekiti also delivering an assist. Evan Bermejo recorded five saves for Albany to record the shutout. Come to Albany High tonight, Sept. 2, to pack the stands with Falcon fans! Our girls' tennis team will face off against Guilderland at 4:15 p.m. and our girls' soccer team takes on Berne-Knox-Westerlo at 4:30 p.m. Let's go Falcons!
What two critical access hospitals learned about EHR optimization after go-live
Healthcare organizations commit significant resources to EHR implementation, then find they cannot sustain improvement once the project team disbands. The
NVIDIA DLSS 5 Performance Unveiled: 5x Faster Than Original Demo, 50% Perf Penalty on Average, But RTX 50 GPUs Offer “Hundreds of FPS” With MFG Enabled & More Optimizations On the Way
NVIDIA is sharing the first performance figures of its RTX 50 GPUs running DLSS 5, offering next-gen visuals at super-fast frame rates.
Cloudflare freed up 100TB of RAM behind its 1.1.1.1 DNS without adding a single server
The optimization work was centered on Big Pineapple, Cloudflare's DNS caching platform behind the popular 1.1.1.1 resolver, DNS Firewall, and several other DNS services they offer. In...
Juno Health and SlicedHealth Partner to Deliver Comprehensive Revenue Optimization for Rural and Critical Access Hospitals
Juno Health, a trusted healthcare technology partner for acute care, teams up with SlicedHealth, a leading healthcare revenue cycle and operations intelligence company, to offer SlicedHealth's revenue cycle tools as an integrated and included complement to Juno EHR's native revenue cycle management suite. This partnership delivers a more powerful, end-to-end financial health solution to the small hospitals and clinics the two companies serve.
Stanford GSB Tops New AI Readiness Index; 42% of Business Schools Require No AI Coursework
A PR firm's new index scores 60 global B-schools on AI readiness and finds none teaches generative engine optimization.
Crimson Desert dev comments on status of Nintendo Switch 2 port, targeting first half of 2027
Pearl Abyss has commented again on the Nintendo Switch 2 port of Crimson Desert, providing the most encouraging update we’ve had thus far. In its latest earnings letter, the company said that it’s now “currently playable at a foundational level, and technical evaluations are underway to ensure performance optimization and compliance with our quality standards.” The other piece of important...
Apple Releases iOS 26.6.1 and iPadOS 26.6.1 With Security Fixes
Apple today released iOS 26.6.1 and iPadOS 26.6.1, minor updates to the iOS and iPadOS 26 operating systems that came out in September. iOS 26.6.1 comes two weeks after the launch of iOS 26.6, an update that added Spotlight optimizations ahead of iOS 27. iOS 26.6.1 and iPadOS 26.6.1 can be downloaded on eligible iPhones and iPads over-the-air by going to Settings > General > Software Update.
Microsoft’s Efforts In Making Windows 11 More Efficient Isn’t Just Due To The DRAM Shortage; Analyst Believes MacBook Neo Played A Pivotal Role In This Decision
Microsoft’s RAM optimization push for Windows 11 isn't just about DRAM costs as analyst points to Apple’s budget MacBook Neo as a major catalyst
Entertainment Network (India) Ltd (BOM:532700) (Q1 2027) Earnings Call Highlights: Digital ...
Despite a 1.9% dip in domestic revenue, the company's strategic shift toward digital and aggressive cost optimization fueled a significant profitability boost.
High school sports tryouts and practices kick off Aug. 17
Our high school fall sports season will kick off on Monday, Aug. 17, with tryouts and practices beginning for high school football. Tryouts and practices for all other high school sports, including cheerleading, boys' soccer, girls' soccer, boys' cross country, girls' cross country, girls' tennis, girls' swimming and diving and volleyball, will begin on Monday, Aug. 24. Tryouts and practice schedules Tryout and practice schedules are available via the practice schedules button located on the fall sports page of our website. Please note that practice schedules are subject to change due to inclement weather or unanticipated circumstances. Registration information As a reminder, students and parents must fill out all required paperwork on Final Forms to participate in tryouts and practices. A physical conducted within the last 12 months is mandatory for any student interested in trying out for an athletic team and must be uploaded into Final Forms platform. Families are encouraged to get a completed physical from their child's physician. If you are unable to get a physical from your child's physician, you can schedule a free physical with Whitney Young's school-based health center by calling (518) 573-2556. Additionally, the district physician will also be available to facilitate sports physicals at Albany High in room 4253 on the following dates: Monday, Aug. 17 from 10:30 a.m.-3 p.m. Thursday, Aug. 20 from 10:30 a.m.-3 p.m. Sports physicals on Aug. 17 and 20 are free and no appointment is necessary. Academic Eligibility As a reminder, students must be in good academic standing to participate in athletics. Academic eligibility will start at the beginning of each academic year. Eligibility is determined based on quarterly grades, and interim progress reports will serve as an important academic checkpoint for all student‑athletes. For additional details about academic eligibility, please see our Athletic Code of Conduct. Falcons, we can't wait to see you soar this fall season!
Experts share MRI efficiency strategies that could raise revenue by upward of 60%
Workflow redesigns have the potential to improve MRI throughput by 20%, while AI-based protocol optimization could boost efficiencies by another 35%, experts write in Clinical Imaging.
Fall sports Senior Media Day
Seniors, mark your calendars for our fall sports Senior Media Day photo shoot, which will take place on Monday, Sept. 14, at 3:30 p.m.! All seniors playing a fall sport should report to the third-floor balcony area at Albany High promptly at 3:30 p.m. to get their photograph taken by John Wong Photography. Photographs taken on our fall sports Senior Media Day will be utilized for the creation of large, weatherproof senior banners. Each senior will be featured in their own individual banner. We extend our heartfelt thanks to the Albany Booster Club for funding our senior banners, which will be proudly displayed at our senior night events. Thanks to our booster club's support, each senior will get to keep their banner as a memento of their hard work and dedication as a Falcon student-athlete. There is no sitting fee for the Senior Media Day photo shoot. Students and families will be given the opportunity to purchase photos separately if they so choose. Senior Media Day photo shoots for winter and spring sports will be publicized leading up to each season. In addition to our Senior Media Day photo shoots, seniors will also be asked to participate in our sports photo sessions each season for all student-athletes in grades 9-12, facilitated by Upstate Images. Upstate Images provides our sports photography for our Albany High yearbook and students and families will be given the opportunity to purchase individual and/or team photos if they so choose. More details will be available at the start of the fall sports season.
Amid trend in health optimization, Berkeley scientists focus on brain optimization
What’s a healthy body without a healthy brain? Neurologists, neuroscientists and psychologists unite to find metrics for brain health and effective training to improve it.
Microsoft to optimize Windows 11 for PCs with 8GB of RAM
Microsoft is preparing Windows 11 optimizations designed to improve performance on PCs with 8GB of RAM, targeting high idle memory use. The updates will roll out gradually, with broader improvements expected by the end of 2026.
Science Inquiry Comes Alive for Jacket Middle Schoolers
Snails, sidewalks and Double Stuff Oreos... At Partnership Middle School, instructors are finding innovative ways to help students connect the classroom to what they see in the real world every day. By integrating hands-on experiences and scientific investigations into weekly lessons, 6th and 7th grade science teachers push their classes to explore the curriculum standards through the lens of critical thinking, communication with their peers, experimentation, and scientific inquiry. Last week, two different approaches for two different grade levels saw Jacket teachers ignite the same spark for learning. On Tuesday, 6th graders in Lydia Jones' science class took their lessons outside as they explored the school grounds to identify living and non-living things. Despite the warm temperatures, they engaged in discovering unexpected objects on the campus and connecting that to what they learned in class about the criteria for what qualifies a thing as "living". Ms. Jones tasked students with walking the grounds and listing as many living and non-living things they could find in just a few minutes. Students spotted a fire hydrant, construction vehicles, grass, trees, soccer equipment, rocks, sidewalks, and even a snail hidden in the plants. After they finished the exploration, students returned to the regular classroom to discuss their results and whether their objects were classified correctly. On Thursday, 7th graders in Omini Parks' science class participated in their first lab of the semester as they explored and identified the physical properties of a favorite snack -- Oreos. Ms. Parks identified the class objective before the lab activity began by writing the academic standard on the dry erase board in a declarative statement: "I can collect and evaluate qualitative data to describe substances using physical properties." Students watched a video about how Oreo sandwich cookies are made, and then engaged in a question and answer discussion to give observations on the manufacturing process, review various types of physical properties and their scientific terminology, and talk generally about how the lab inquiry would work. The Q&A ended with a predictable question from students... "Will we be able to eat the Oreos?" The hands-on lab exercise required the 7th grade scientists to observe and record the differences between regular Oreos and the Double Stuff variety based on their physical properties. They followed the instructions in their lab brief to chart a comparison between the two types of cookies by observing properties with their magnifying lenses, measuring the height and diameter of both, and weighing the cookies with and without their filling. The activity let students put their lessons about physical properties into practice with real objects while also practicing vocabulary and writing skills to record their observations and using math skills from the last school year like taking measurements and calculating averages. Of course, they ended the lab by charting the taste of the cookies as well! These types of activities allow students to see the science standards they are learning come to life in the real world and engage with the content in new ways. Beyond that, they serve as a foundation for encouraging and growing scientific inquiry. Later in the school year, students will use the scientific method they are learning to complete science projects that require real research and the ability to explain and answer questions about their process and results. At the school-level competitive Science Fair last year, 41 Partnership students earned a place in the 2026 regional Science Fair held at MSU. From there, 14 advanced to the State Science Fair conducted at Northeast Mississippi Community College in April.
Apple Releases iOS 26.6 and iPadOS 26.6 With iOS 27 Optimizations
Apple today released iOS 26.6 and iPadOS 26.6, updates to the iOS and iPadOS 26 operating systems that came out in September. iOS 26.6 comes a month after the launch of iOS 26.5.2, a security update. iOS 26.6 and iPadOS 26.6 can be downloaded on eligible iPhones and iPads over-the-air by going to Settings > General > Software Update. According to Apple's release notes, iOS 26.6 and iPadOS 26.6 include security fixes for the iPhone and iPad.
As Hegseth pursues a 'High-T' military, here's what to know about testosterone replacement
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Fall sports updates and information
The fall sports season will be here before we know it! Here are some key summer details for students and families as we look forward to the coming season. Registration begins: High school football (grades 9-12): July 17 All other high school fall sports (grades 9-12): July 24 Modified football (grades 7-8): July 27 All other modified fall sports (grades 7-8): July 31 Please register via Final Forms. Sports physicals: All student-athletes interested in trying out for a fall sport must have an up-to-date physical submitted to Final Forms in advance of the first day of tryouts and practices. Families are encouraged to get a completed physical from their child's physician. If you are unable to get a physical from your child's physician, you can schedule a physical with Whitney Young's school-based health center by calling (518) 573-2556. Appointments will be available at Albany High School in room 4253 during July on the following dates: Thursday, July 16 between 8:30 a.m. and 12:30 p.m. Tuesday, July 21 between 8:30 a.m. and 4:30 p.m. Tuesday, July 28 between 8:30 a.m. and 4:30 p.m. Thursday, July 30 between 8:30 a.m. and 4:30 p.m. Again, you must call (518) 573-2556 to schedule your appointment and receive instructions. Whitney Young does require paperwork that must be filled out by the child's parent or guardian in order for them to be seen by the provider. Tryouts & practices begin: High school football (grades 9-12): Aug. 17 All other high school fall sports (grades 9-12): Aug. 24 Modified football (grades 7-8): Aug. 27 All other modified fall sports (grades 7-8): Aug. 31 High school student-athletes are encouraged to take part in our open gym sessions during July and August in preparation for the fall sports season. Stay tuned for fall practice schedules and competition schedules, which will be posted on our Athletics page! If you have additional questions, please contact the Athletics Department at (518) 475-6310. Let's go Falcons!
A heart for health
Albany High retiree Mary Kelly has a heart for health that expands beyond her professional responsibilities. Not only did she serve the City School District of Albany for over 23 years as a nurse, she also has been a faithful supporter of our food pantry here at Albany High! Since June 2022, Kelly has given a monthly donation to the Regional Food Bank of Northeastern New York specifically designated for Albany High. Thanks to Kelly and other individual donors and partner organizations, our students and their families can have access to nutritious food, free of cost at the Falcon Market. As someone who raised three boys, she knows how hard it can be to keep one’s shelves stocked at home. “I remember when they would sit down, three teenagers, eating a box of cereal a piece as a snack,” Kelly reminisced with a laugh. “Who can afford that nowadays?” Known affectionately as Nurse Kelly throughout her career in the district, she served our students at the elementary, middle and high school levels, and was stationed at Albany High from 2019 until her retirement. By caring for students day in and day out, Kelly was keenly aware of the negative impact of food insecurity on the lives of young people. This is what motivated her to take a proactive step towards improving access to nutritious food for our students and families. Kelly’s generosity is a way to carry on the memory of her youngest son, who passed away in 2019. “The kindnesses that I do are always in his memory,” Kelly shared. On behalf of our Albany High staff, students and families, we thank Nurse Kelly for her incredible support and wish her all the best during her retirement. For more information about how to support the Falcon Market with in-kind or financial donations, please contact Joey DiPiazza at jdipiazza@albany.k12.ny.us.
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Serena Williams’ Wimbledon comeback and how elite athletes in their 40s return to the arena
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AI is rewriting the political competitive landscape
Artificial intelligence is rapidly becoming a central infrastructure layer in political campaigns, reshaping how elections are financed, contested and influenced, The New York Times reports. Campaigns and affiliated political groups are increasingly investing in AI-driven tools for voter targeting, message optimization and large-scale content generation, turning modern elections into capital-intensive, technology-enabled competition. This shift is […]
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GLP-1 and weight-loss drugs: How fast-track health solutions are reshaping FMCG
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Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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Science behind sobriety field tests
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Forum on harnessing Artificial Intelligence for health equity
Register to this forumOver the past decade, artificial intelligence (AI) has significantly evolved in complexity, performance, and utility. Its integration across a wide range of industrial sectors has accelerated, with healthcare emerging as one of the most transformative sectors. In this sector, AI has enabled high-impact applications – from enhancing the speed and accuracy of disease diagnosis and supporting clinical decision-making, to strengthening public health initiatives such as disease surveillance and workforce optimization. Moreover, AI holds immense potential to empower individuals, enabling them to take greater control of their personal health and well-being. Yet the central question remains: Who benefits, who is at risk, and do these innovations close or widen health inequities? While the potential of AI-enabled applications is substantial, many countries have approached their adoption with caution. This hesitancy stems from concerns about risks and benefits, including model bias, data breaches, privacy violations, and the erosion of professional skills due to over-reliance on AI. Additional barriers include inadequate data infrastructure and a lack of robust evidence on the most effective forms and interfaces of AI to enhance service delivery and system performance. Moreover, the rapid rise of Generative AI has introduced a heightened urgency for the development of comprehensive governance and ethical frameworks. The Asian Development Bank (ADB) Health Practice Team and Digital Sector, in collaboration with the World Health Organization (WHO) Regional Office for the Western Pacific, are convening the Forum on Harnessing AI for Health Equity on 25–26 March at ADB Headquarters. Senior health officials from 16 developing member countries (DMCs), alongside leading researchers, innovators, and policymakers from across Asia and the Pacific, will engage in discussions on how AI can be governed, financed, and scaled to deliver healthier lives for all. The forum is funded through the High-Level Technology Fund with support from the Government of Japan. Objectives The two-day forum aims to:Identify high-impact, evidence-based health AI use cases suitable for resource-constrained settings and map out a pipeline for potential supportIntroduce and validate the WHO's policy guidance on minimum necessary ecosystem for countries and institutions to self-assess readiness for AI adoptionObtain initial commitment from participating stakeholders to join a pilot regional initiative focused on data/model sharing for a priority health challengeEndorse a prioritized set of actionable policy recommendations focusing on governance, regulation, and sustainable financing necessary to scale high-impact health AI use cases in resource-constrained settings Target participants The forum will convene participants from 16 ADB DMCs including Bangladesh, Bhutan, Cambodia, Cook Islands, Fiji, Indonesia, Lao People's Democratic Republic, Mongolia, Nepal, Palau, Papua New Guinea, Philippines, Sri Lanka, Thailand, Uzbekistan, and Viet Nam. In addition, health system leaders and practitioners, private sector technologists, academic experts, representatives from civil society organizations, development partners, and philanthropic institutions engaged in AI for Health from Australia, the People’s Republic of China, Japan, Malaysia, New Zealand, Singapore, and the Republic of Korea will also be invited. SessionsDay 1 (25 March)Session 1: AI Use Cases for the Care Continuum: Improving Access and QualitySession 2: Adopting a risk-based approach for AI use case prioritizationSession 3: Establishing the Minimum Ecosystem for Implementation Risk ManagementSession 4: Future-Ready Health Workforce: Building Competency for Human-AI CollaborationDay 2 (26 March)Session 5: The Political Economy of AI in Health: Understanding Stakeholder Interests and their Impact on EquitySession 6: AI and Health Financing: Supporting Fair Coverage and ProtectionSession 7: AI Regulation and Oversight: Pathways for Different RealitiesSession 8: The Way Forward – Building Alliances and Regional Partnership How to registerThe forum will be held in a hybrid format. In-person attendance is by invitation only, while livestreaming of the forum will be available to the public. To register, please complete this form on or before 24 March 2026.Event organizers / partnersAsian Development Bank (ADB)WHO Regional Office for the Western Pacific High-Level Technology Fund (HLTF)ContactAkihito WatabeHealth Specialist, SD3-HSDawatabe@adb.org Jae Kyoun KimHealth Specialist, SD3-HSDjkkim@adb.org
Intel Launches "Arrow Lake Refresh": Core Ultra 5 250K Plus and Core Ultra 7 270K Plus, New Binary Optimization Tool
Intel today announced the Core Ultra 5 250K Plus and Core Ultra 7 270K Plus desktop processors in the Socket LGA1851 package. These chips are drop-in compatible with existing Intel 800-series chipset motherboards, with some boards needing UEFI firmware updates. Both chips are based on the current "A...
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Spring sports physicals for grades 7-12
All student-athletes interested in trying out for a spring sport must have an up-to-date physical submitted to FinalForms in advance of the March 9 start to the season for high school sports and in advance of the March 23 start to the season for modified sports. Families are encouraged to schedule a visit with their child's provider to secure a completed physical form. If this is not possible, the district physician will offer sports physicals at Albany High School, William S. Hackett Middle School, North Albany Middle School and Stephen and Harriet Myers Middle School. The schedule is outlined below. No appointment is necessary. If you have any questions or need additional assistance, please contact the Athletics Office at (518) 475-6310. Let's go Falcons! Sports physicals schedule: Albany High March 4 10:30 a.m. Room 1130 Albany High March 5 10:30 a.m. Room 1130 Myers March 17 10:30 a.m. Health Office Hackett March 18 10:30 a.m. Health Office North Albany March 19 10:30 a.m. Health Office
Around the MHS
The latest news from around the Military Health System for the week of Feb. 9-13, 2026, includes a new leader for the Defense Health Agency, a roadmap for leveraging artificial intelligence in military medical education, and the U.S. Navy’s human performance optimization initiative.
Rankpage Introduces Expanded AI-Driven SEO Offerings to Support Businesses of All Sizes Across Malaysia
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New program at UT Health San Antonio delivers breakthrough care for limb loss patients - UT Health San Antonio
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