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Trump reduces size of 2 national monuments in Utah
The move to shrink Bears Ears and Grand Staircase-Escalante national monuments by about 90% unravels protections established by former presidents for areas with unique archaeological and historical features
Idaho Senate passes rewritten health and welfare budget with additional budget cuts
Overall, Senate Bill 1435 reduces total Idaho health and human services funding by $351.7 million, or 5.8% in fiscal year 2027.
NCAA reduces NIT field to 24 teams
While one postseason college basketball tournament expands, another is contracting. The NCAA announced on Thursday it will reduce the NIT field to 24 teams for 2027, down from the 32-team format it has used for most of its modern history. The move coincides with the NCAA Tournament’s expansion to 76 teams, up from the 68-team…
MSI PinSafe motherboards promise smoother PCB backs and fewer cut fingers
MSI says its patented PinSafe design flattens rear solder points and reduces exposed metal on high-end motherboards. MSI has detailed PinSafe, a patented
Tirzepatide Boosts Metabolic Health in Partial Lipodystrophy
Tirzepatide significantly improves metabolic health and reduces insulin dependence in patients with partial lipodystrophy.
Dupont Circle businesses struggle amid construction
Some Dupont Circle businesses say they are struggling as construction on Connecticut Avenue reduces foot traffic. News4’s Jackie Bensen reports.
Windows 11's new update actually makes your PC faster. Here's how to get it
Windows 11's new optional May update KB5089573 reduces app launch lag and UI stutters. Here's what it does and how to get it early.
Marvel Rivals’ next update drastically reduces the game’s install size on PC and console
As of Season 9.5, Marvel Rivals is going to take up a lot less space on your platform of choice.
Forza Horizon 6 update reduces 1,000-hour grind for multiplayer Xbox achievement
Playground Games has rolled out a new update for Forza Horizon 6, which makes an achievement easier to unlock and balances the game's crazy AI racers.
This AI finds simple rules where humans see only chaos
A new AI developed at Duke University can uncover simple, readable rules behind extremely complex systems. It studies how systems evolve over time and reduces thousands of variables into compact equations that still capture real behavior. The method works across physics, engineering, climate science, and biology. Researchers say it could help scientists understand systems where traditional equations are missing or too complicated to write down.
Novant Health reduces retirement match amid cost pressures
Novant Health announced changes to its retirement benefits Tuesday that will take effect starting next year.
Hearthstone Cataclysm Card Reveal - Ultraxion Looks Like A Must-Have For Deathwing Decks
One of Deathwing's trusty lieutenants helps to Herald your Colossal minion and reduces Deathwing's cost in one fell swoop.
Patient-Owned Health Data Model Reduces Clinical Trial Recruitment Redundancy
Patient-owned health data model reduces clinical trial recruitment redundancy by enabling persistent consent and longitudinal data sharing across studies.
ServiceNow cuts jobs amid global restructuring and AI focus
Amid industry pressure, ServiceNow, overseen by CEO Bill McDermott, reduces workforce while focusing on AI investment and operational efficiency.
Top 5 Ways Broken Triage Increases Business Risk Instead of Reducing It
Execution-based triage cuts MTTR by 21 minutes, reduces escalations 30%, and exposes full attack chains in under 60 seconds.
Novant Health reduces retirement match amid cost pressures
Novant Health announced changes to its retirement benefits Tuesday that will take effect starting next year.
Google Home app brings battery-efficient widget, reduces gray device tiles
Google today is also rolling out Home app (especially for the homescreen widget) and Gemini for Home voice assistant updates.
Forest landscapes and birdsong soundscapes have independent physical health benefits
A new study finds that exposure to birdsong soundscapes or forest landscapes reduces physiological stress. These findings of physical health effects complement previous research showing mental health ...
City says closing nuisance businesses cuts crime. Some residents question the approach
Some city leaders say shutting down nuisance businesses reduces crime, but some residents argue the closures just shift problems elsewhere.
iOS 26.3 Adds Privacy Setting to Limit Carrier Location Tracking
With iOS 26.3, Apple is adding a new "limit precise location" setting that reduces the location data available to mobile networks to increase user privacy. Mobile networks determine location based on the cellular towers that a device connects to, but with the setting enabled, some of the data typically made available to mobile networks is being restricted.
Making Our Own Luck
We are cross-posting a piece that former NIH official Kris Willis wrote for Macroscience. Kris is now the President and Founder of the Woodley Park Institute, for which I’m a board member. Picking winners or hedging bets? Federal science agencies have long wrestled with the question of how to ensure their billions of dollars of grants and contracts result in maximum benefits for Americans. On the surface, it might seem that a goal-oriented, interventionist style of management would be the best policy: prioritize our most pressing problems and distribute funding accordingly.This top-down strategy creates a unique hazard, though: bad choices can send resources in the wrong direction, resulting in slow progress that impedes the delivery of tangible benefits to citizens. Moreover, if decision makers pursue an applied advance when the underlying scientific principles remain poorly understood, they risk costly failures and a loss of support for the research enterprise at large. Examples include Nixon’s 1971 War on Cancer, undertaken on the premise that a cure could be achieved in less than a decade, the drive to build an operational commercial fusion plant by the mid-1990s, and the National Plan to Address Alzheimer’s Disease, which failed to produce the effective treatments and prevention strategies promised by 2025. The contrasting laissez-faire approach is to hedge your bets. If the path to an advance is impossible to predict, then the wisest choice might be to distribute funding to as widely as possible. The main risk of this strategy is that spreading funding thinly may limit the resources available to the most promising research, resulting in the same negative outcomes as the interventionist approach: limited support for the most promising topics, slow progress, and delayed returns. In reality, at science agencies like the National Science Foundation and National Institutes of Health, program managers navigate between these two extremes, setting some funds aside to target high-priority areas and using the rest to cover the widest possible range of meritorious proposals. This middle path seems like the most rational way to proceed, but it still requires making choices. How much should be set aside for high priority topics? What should those topics be? How should we define merit? Expert opinion can provide a helpful guide, but leading experts can have remarkably different opinions about what matters and what should be prioritized. Moreover, experts and administrators alike can be risk averse, giving an edge to high-profile, well-established concepts. What’s really needed is a data-driven framework to help guide decision-making, one that doesn’t simply repackage prestige or incumbency. Recognizing breakthroughs years in advance Many breakthroughs fail to attract funding or recognition at the earliest stages of development. Katalin Karikó, for example, spent years struggling to win grants for work on mRNA that would eventually win her and Drew Weissman a Nobel Prize. Similar stories can be told about Jim Allison’s groundbreaking studies leading to the development of cancer immunotherapy, Stan Pruisner’s demonstration that prions can self-replicate without DNA, or Robin Warren and Barry Marshall’s proof that Helicobacter pylori, not stress, causes ulcers. Yet at some point, the scientific community recognizes and responds to transformative breakthroughs like these. How does that change happen? And what if science funders could identify the areas that are on the cusp of a breakthrough? Those questions led my collaborators and me to study how scientists responded to past breakthroughs. Based on patterns in that data, we developed a means of predicting future breakthroughs, using biomedicine as a proof of concept. It’s worth taking a moment to describe how our approach works. Briefly, our prediction process begins by grouping the 18 million or so peer-reviewed papers in PubMed, the authoritative database of biomedical research, into roughly 50,000 unique topics. A small subset of these topics are so widely acclaimed as breakthroughs that they have been recognized with a major prize like a Nobel or a Lasker Award. We theorized that studying the development of these outliers over time, especially before they gained acclaim, was the key to identifying future instances of them. After defining topics, we chose 21 representative breakthroughs and asked what they looked like before they won prestigious prizes. To answer that question, we re-ran our topic-mapping algorithm repeatedly, winding back the clock one year each time, stringing together the years to follow the progress of each field as it grew and advanced. We found that in each case, the years leading up to a discovery followed a pattern: a burst of papers on a new, rapidly evolving topic, many of which quickly became influential. These characteristics—the percent of papers that are new, the percentage of papers that are brought in from other topics, and the influence of each individual paper—can all be measured separately for any given topic. Together, they act as a predictive signal that is detectable an average of five years before a transformative discovery is made, and up to thirty years before the discovery receives a major prize. Scanning the current research landscape for topics that display this signal allows us to predict what work will likely produce a future breakthrough. Each year we analyzed includes four or five signals, a number that appears to have remained constant across a twenty year time frame. In their classic work on the sociology of science, Bruno Latour and Steve Woolgar established that the desire to participate in a major discovery is an important motivator for scientists as they consider whether they should take up (or abandon) a research problem. Although further work is needed, the simplest explanation for our results is that this behavior is widespread enough to detect at scale. A foundational advance, or something like it, draws the attention of scientists and causes them to change the direction of their research. They vote with their feet, staking their own reputation and careers by publishing on and citing the new idea. That upswell of interest is the foundation of our breakthrough signal. What kind of research does our model identify as a breakthrough? After building a model based on the patterns in our 21 preselected breakthroughs, we tested it by identifying all early signals of discovery from 1994 through 1997. Of the 18 signals we found in that time period, 17 can be traced forward in time to a breakthrough. Examples include super-resolution fluorescence microscopy (see the image above), the directed evolution of proteins and enzymes (Chemistry Nobel, 2018), and sequencing the human genome (National Medal of Science, 2008). The discovery of the role of leptin signaling in obesity is a particularly interesting case study. Around 1950, scientists noticed the existence of a type of lab mouse that suffered from a unique inherited form of obesity. When given the freedom to choose their own diet, these mice ate more than normal and preferred food that was high in fat. Researchers had few clues as to why the animals overate; early experiments pointed to the existence of a soluble ob factor found circulating in the bloodstream that regulated appetite, but its identity was unknown. In 1994, Jeffrey Friedman and colleagues identified and sequenced the ob gene, noting that the protein it encoded appeared to fit the profile of a circulating factor. A year later, a trio of high-profile publications demonstrated that ob was a hormone that regulated body weight and fat deposition by regulating appetite. One of these was co-authored by Friedman, who christened it leptin from the ancient Greek word for thin. Using our model, the data from 1996 make it clear this advance would become a breakthrough. Scientists had flocked to study the biology of the new hormone, generating the flurry of new papers and citations required to produce a signal. One of these demonstrated that serum leptin concentrations reflected the amount of adipose tissue in the human body, providing clinical validation of the earlier mouse studies. Before the identification of leptin, scientists were unable to point to a specific molecule that controlled appetite and adiposity, so that it was impossible to rule out non-physiological causes of obesity; its characterization fundamentally changed our concept of weight gain. In 2010, Friedman and fellow pioneer Douglas Coleman were awarded a Lasker for the discovery. Our work also identifies breakthroughs in clinical practice and behavioral and social sciences, even though these areas are less likely to draw the attention of major prize committees. One example that falls into this category is the introduction of endovascular aneurysm repair, a minimally invasive surgical procedure for the treatment of abdominal aortic aneurysm, a leading cause of death among Americans over the age of 65. Relative to the previous standard of care, it reduces in-hospital mortality by almost four-fold. In 2017, Timothy Chuter received the American College of Surgeons’ prestigious Jacobsen Innovation award for his multiple refinements to the technique. Another under-recognized breakthrough identified by our model is the development of standardized survey instruments to assess the quality of life for HIV+ patients. The antiretroviral cocktails introduced in the mid-1990s reduced AIDS mortality, but treatment came with serious side effects. The new evaluations showed that patients whose disease progressed had worse physical functioning than Americans with other chronic diseases, while those who were asymptomatic maintained a health-related quality of life on par with the overall US population. This evidence made it possible for patients and activists to argue that even in the absence of a total cure, and in spite of the side effects, alleviation of symptoms was a worthwhile priority for clinicians. My colleagues and I have failed to identify any significant recognition for the physicians and health policy experts who pioneered this advance, although in 2016, researchers called for the World Health Organization to set targets for good health-related quality of life as part of its framework to end the AIDS pandemic. From forecasting to funding How should science funders use our predictions? Any serious discussion of what we should do with this new capability needs to begin with an understanding of its limitations. We can’t (and shouldn’t) invest all of our resources in the small number of topics predicted to produce breakthroughs. Innovative new fields are born from existing ones; they rarely arise de novo. If funders don’t maintain a diverse portfolio, the breakthroughs of tomorrow will have no antecedents. Think of this as eating the seed corn, or killing the goose that lays the golden egg. There are also multiple goals of funding beyond basic scientific discovery, including translating discoveries into clinical practice, developing new technologies, supporting economic development, and training new scientists. The investments needed to accomplish these goals are likely different from those required to support emerging breakthroughs. Finally, we must be aware that we may not capture every instance of a breakthrough. The concept is fuzzy, and not every significant discovery is recognized with a major award. Further, breakthroughs are rare, meaning that our dataset is, by necessity, small. This makes formal estimates of accuracy challenging. Although our overall success rate appears to be high, any one signal may turn out to be a false positive. We found one apparent example: the development of the third generation COX-2 inhibitors, Vioxx and Celebrex, which were much celebrated in the early 2000s as effective but non-addictive pain relievers, meets all the algorithmic criteria of a breakthrough. Five years after it received FDA approval, researchers demonstrated that Vioxx was associated with serious cardiovascular complications, and the manufacturer voluntarily pulled the drug from the market. Celebrex remains available, although like other NSAIDs, it carries an FDA warning for increased cardiovascular risk. Decision makers who were overly focused on the breakthrough potential of this research might have wasted substantial resources nurturing an area that ultimately proved to be a failure—but so would those who relied on expert opinion at the time. That said, the potential benefits of funding the next mRNA vaccine or cancer immunotherapy years earlier than we might have are large. When we can’t assume the outcome of an action, it’s worth conducting an experiment. Can targeted support for areas that are poised to produce a breakthrough increase the return on scientific investment without cannibalizing future advances? With the necessary administrative infrastructure in place, conducting this experiment would be straightforward. First, identify all the breakthrough signals between 2018 and 2023, select half at random, and commit to a decade of investment. For biomedicine, a six year window should yield about 30 topics with the potential to produce a breakthrough. Providing strong support to half of these might be accomplished for $300 million a year. That’s roughly half of the recent annual budget of the NIH Common Fund or around 20% of the fiscal year 2025 budget for ARPA-H. After five years, then again at ten, compare to see which group — the one that was actively managed, or the control — produced more breakthroughs, and on what timescale. Although we used biomedicine as an example, the same experiment could just as well be run for physics, materials science, or any other discipline. Any attempt to undertake such an experiment should keep three points top of mind. First, we can predict the topic of future breakthroughs, but the people and vision for how to move the work forward are still important. In practice, this means success requires active program managers with the expertise to develop the science and the authority to do so, including by recruiting investigators. Second, we would be wise to learn from the failures of past attempts to fund transformative research. High among these are funding modestly repackaged work, confusing the genuinely novel with the merely unfamiliar, and relying too much on incumbent investigators. All of these risks can be mitigated by thoroughly and intelligently integrating high quality data into portfolio management. Finally, we need to have patience. Even with strong funding support, producing a breakthrough takes time. If supporting breakthroughs is the best way to nurture the birth of new fields, we also need to accurately describe and properly manage the other two stages, so that we invest wisely throughout the productive lifetime of ideas and divest once they reach the point of diminishing returns. We would benefit from more study of all of these phases, especially the transition from one to another. More research could answer questions like: When does a breakthrough become an established field? How do the availability of funding, the size and characteristics of the available workforce, and the accumulation of evidence that disagrees with prevailing models affect a field’s decline? Exactly how do old ideas give birth to new ones, and can we speed up the process? The more we understand about the dynamics of scientific progress, the better we can maximize the odds that our curiosity leads to results. I’d call that finding a way to make our own luck.
Iterative Health, US Heart & Vascular Partner to Advance Community-Based Cardiovascular Research
April 2, 2026 — Iterative Health and US Heart & Vascular (USHV) have announced a strategic partnership to advance research through community-based innovation in cardiovascular care. "Clinical research is one of the most powerful ways we expand access, improve patient outcomes, and shape the future of cardiovascular care," said Robbie Allen, chief executive officer of US Heart & Vascular. "By partnering with Iterative Health, we are strengthening our ability to bring innovative therapies directly into the communities we serve. This collaboration ensures our physicians and patients have access to leading-edge trials while allowing US Heart & Vascular to remain focused on delivering exceptional, physician-led care." Under the agreement, USHV research sites will join Iterative Health’s global site network, which now spans over 100 sites across three continents. The companies share a commitment to advancing clinical research as a driver of care innovation, and this collaboration represents a major milestone for both organizations, strengthening USHV's leadership in community-based cardiovascular research and expanding Iterative Health's multispecialty focus beyond GI, hepatology, and obesity into cardiology. USHV clinical research sites will gain access to Iterative Health's centralized operational backbone, providing end-to-end support across clinical research operations, services, business development, technology innovation, and corporate functions. The strategic partnership reduces operational complexity and unlocks growth potential for USHV research sites while enabling all USHV physicians to expand access to cutting-edge therapies to the thousands of patients they serve annually. "Innovation in cardiovascular medicine shouldn't be limited to a few academic centers," said Thomas Waggoner, DO, MD, RPVI, FACC, FSCAI, FSVM, RPVI, Structural Cardiologist and Medical Director for Clinical Research at Pima Heart & Vascular, and USHV Physician Champion for Clinical Research. "By expanding community-based research across USHV, we're ensuring more patients have access to clinical trials and breakthrough therapies close to home, where trusted relationships with their physicians already exist." This alliance reinforces Iterative Health's standing as the definitive research partner across specialized therapeutic areas, now spanning GI, hepatology, obesity, and cardiovascular care. Trusted by many of the nation's leading provider organizations and biopharma sponsors, Iterative Health's global site network delivers industry-leading trial performance, accelerating life-changing therapies to market at scale. "Entering cardiology through our strategic partnership with US Heart & Vascular is a defining moment for Iterative Health and reflects the strength of our site-serving model," said Jonathan Ng, founder and CEO of Iterative Health. "Together, we are ensuring that thousands of patients have access to the newest available therapies, and that sponsors have a credible, high-performing partner to accelerate cardiovascular trial success." For more information, visit www.iterative.health and https://usheartandvascular.com/.
Health Ministry announces restaurant sector reform, eases requirements
The reform dramatically reduces minimum space requirements, allowing existing restaurants to add more tables by repurposing operational space previously required under the regulations.
Your Business Probably Has More Data Than Insight by Nathan Tayloe
Most businesses know more about themselves than they ever have. Leaders have access to financial reports, sales pipelines, customer data, employee metrics, website analytics, and dashboards for almost every part of the organization. CRMs track every stage of the sales process. Marketing platforms report results in real time. AI can analyze and summarize enormous amounts of information in seconds. Yet I've sat in plenty of meetings where all of that information is available, and some of the most important questions are still surprisingly difficult to answer. What's actually working? Why are customers choosing us? Where are we losing opportunities? What should we do differently? Having the data and understanding what it means are two very different things. More Information Doesn't Always Create More Clarity Over the past decade, businesses have invested heavily in visibility, and that's a good thing. We can understand performance with a level of detail that would have been unimaginable not long ago. But there's an unintended consequence. The easier something becomes to measure, the easier it is to assume it must be important. Website traffic goes up, so that looks positive. Leads increase, so marketing appears to be working. Sales activity climbs, so the pipeline looks healthy. Maybe. The numbers tell us what happened. Understanding why it happened, whether it matters, and what we should do next still requires judgment. Not Everything That Matters Fits on a Dashboard Consider a customer who ultimately contacts your company through Google. The data may attribute that lead to search. What it may not show is that the customer heard about you from a colleague six months earlier, saw your company mentioned in an industry publication, followed one of your employees on LinkedIn, and read several reviews before finally searching for your company. Google may have produced the click. It didn't necessarily create the decision. This happens throughout a business. Some of the things that matter most are difficult to reduce to a single metric: Why your best customers stay Why talented employees choose your company Why a prospect trusts one provider over another Why one service is gaining momentum while another isn't Why the market perceives your business the way it does Data can help answer those questions, but it needs context. Better Decisions Start With Better Questions One of the easiest traps for leaders is starting with the information in front of them rather than the decision they're trying to make. Instead of opening a dashboard and asking, "What does the data show?" it can be more useful to start with a different set of questions: What are we trying to understand? What decision are we trying to make? What would we need to know to make that decision confidently? That changes the role of data. Instead of looking at every number available and searching for meaning, you're using information to understand something specific about the business. Information Still Requires Judgment More sophisticated analytics and AI will continue to give leaders access to better information, faster. That's valuable, but I don't think it reduces the importance of experience and judgment. If anything, it increases it. Someone still has to decide which numbers deserve attention, which patterns matter, what context might be missing, and when the data isn't telling the whole story. The goal isn't to know more about your business simply because you can. It's to understand your business well enough to make better decisions. Good data can tell you what happened. Good leadership has to decide what it means. — Learn more about how we help organizations turn business, customer, and marketing insights into smarter strategies at tayloegray.com, or reach out directly at nathan@tayloegray.com.
Simple treatment tweak drastically reduces blood loss from severe cuts
A procedure that could be done in half an hour, and prepared ahead of time, could seriously reduce blood loss from severe wounds, such as during surgery
Want to Feel Less Stressed or Anxious? Science Says Just Fake a Smile
Research shows a 20-second fake smile 'improves physiology during acute stress, improves stress recover, and reduces illness over time.' Can't beat that.
Trump reduces military exercises with South Korea, citing good ties with Kim Jong Un
The president cited the cost of the drills and said he did not want to send a signal that is "totally inappropriate and hostile" to North Korea. He also criticized South Korea for not helping him on Iran.
8 Ways to Boost Your Oral Health With Sjögren’s Disease
This autoimmune condition reduces saliva production, leaving teeth and gums vulnerable to decay. Stay on top of your oral health with these expert tips.
Better sleep, improved health, happier people: how ‘cool roofs’ could help millions avoid deadly heat
A project to measure how reflective paint reduces indoor temperatures is delivering tangible benefits across Africa
NFL Reduces Fine for Jahmyr Gibbs
The NFL has reduced Lions RB Jahmyr Gibbs' Week 1 illegal helmet fine from $23,027 to $18,422, according to Aaron Wilson.
Swallowing faecal capsules reduces peanut allergy in six adults
Altering the gut microbiomes of people with peanut allergy using faeces donated from an allergy-free individual improved their peanut tolerance in a clinical trial
Cornwall health initiative 'reduces pressure and saves money'
A charity says the project is "transformational" for people going through difficult times.
NVIDIA's Neural Texture Compression Cuts VRAM Use From 6.5 GB to 970 MB
NVIDIA has released more details about its Neural Texture Compression (NTC) technology, which significantly reduces GPU VRAM usage by up to seven times. In a technology demo presented during one of the GTC 2026 sessions, NVIDIA revealed that its Neural Texture Compression can reduce VRAM usage from ...
Executive Liquidates 2,900 Shares of Entertainment Stock, Valued at More Than $525,000
Capo's $534,000 liquidity event reduces his direct stake by 25%, leaving him with $1.6 million in remaining holdings as the stock maintains momentum.
This Week in Jacksonville - Business Edition: Franchise opportunities grow in River City
In this episode of This Week in Jacksonville: Business Edition, Kent Justice talks with David Montanez, vice president of franchise development for Authority Brands, about the growing franchise opportunities in Northeast Florida and beyond. Montanez explains how franchising offers a proven business model that reduces risk and supports entrepreneurs, including many veterans transitioning from military service.
Rowing Science: Effect of Boat Mass on Rowing Biomechanics
Did you know that each kg of added boat mass reduces rowing speed by 0.15%? This is about 2.5 times
Association Between Electronic Health Record Health Maintenance Topic and Lung Cancer Screening Completion in a Resident-Run Clinic
Introduction: Lung cancer screening (LCS) with low-dose computed tomography (LDCT) reduces lung cancer-specific mortality in high-risk populations, yet screening rates remain low nationwide. Ele...
AMD DGF SuperCompression cuts geometry storage size by up to 22%
AMD’s DGF SuperCompression reduces asset size for future GPU support AMD has released DGF SDK 1.2, adding a new feature called DGF SuperCompression. The
Nissan's in-factory AI cameras track employees to help worker safety
Nissan is using AI cameras to track how factory workers move. They say it reduces injuries and cut health and safety costs.
A new drug could stop Alzheimer’s before memory loss begins
New research suggests Alzheimer’s may start far earlier than previously thought, driven by a hidden toxic protein in the brain. Scientists found that an experimental drug, NU-9, blocks this early damage in mice and reduces inflammation linked to disease progression. The treatment was given before symptoms appeared, targeting the disease at its earliest stage. Researchers say this approach could reshape how Alzheimer’s is prevented and treated.
Scientists turn CO2 into fuel using breakthrough single-atom catalyst
Researchers have created a cutting-edge catalyst that turns CO2 into methanol more efficiently than ever before. Instead of using clumps of metal atoms, they engineered a system where each single indium atom actively drives the reaction. This dramatically reduces energy needs while making the process easier to study and optimize. The result could accelerate the shift toward cleaner fuels and sustainable chemical production.
I Found the Best Electric Toothbrush for My Sensitive Teeth
The best electric toothbrush reduces plaque and gingivitis, encourages you to brush long enough, and prevents overzealous scrubbing.
A busy cardiologist shares 4 habits for good heart health
Dr. Jake Kelly, a cardiologist in Alaska with three kids, shares how he reduces his risk of cardiovascular disease through exercise, diet, and sleep.
California Public Employees Retirement System Reduces Position in Tencent Music Entertainment Group Sponsored ADR $TME
California Public Employees Retirement System decreased its stake in shares of Tencent Music Entertainment Group Sponsored ADR (NYSE:TME - Free Report) by 18.1% during the first quarter, according to its most recent 13F filing with the Securities and Exchange Commission. The institutional investor
Uber Health Launches Self-Booking Feature to Empower Riders and Streamline Operations
Industry-first capability reduces administrative burden for providers, health systems, and I/DD organizations while boosting rider independenceSAN FRANCISCO, Feb. 24, 2026 (GLOBE NEWSWIRE) -- Uber Health today announced the launch of its rider self-booking feature, a new platform capability that enables healthcare and disability service organizations to offer their riders the ability to book their own organization-funded trips directly in the Uber app. The launch marks the latest milestone in Ub
VA reduces improper payments for private health care by 98% since 2020
The VA has slashed improper payments to private companies that provide medical care to veterans by 98% in the past five years.
Oblivion Remastered Mod Built Using Claude AI Boosts FPS By Over 40% And Drastically Reduces Stuttering Without Sacrificing Visual Quality.
AI-assisted mod Oblivion Remastered Performance Fix boosts FPS by over 40% while enhancing visuals on Ryzen 7 5800X/RX 9070 XT systems.
Nine mental-health tips for a happier 2026
Regardless of any resolutions you may have for 2026, one thing is for sure: Everyone wants to have a happy new year.While losing weight or saving money may be great goals, the most straightforward path to happiness is caring for your mental and emotional health. A robust body of research shows that simple cognitive and behavioral strategies can reliably boost happiness and reduce stress – and they’re generally free and accessible to all.These strategies don’t have to be super time-consuming, but they do require intention: They only work if you do them.Here, psychologist Valentina Ogaryan, PhD, clinical director of the Simms/Mann UCLA Center for Integrative Oncology, shares her top tips for cultivating more calm, centeredness and happiness in the new year (or anytime):Make time for playPlay isn’t just for kids, and it’s far from frivolous. The National Institute for Play says engaging in silliness, fun and just-for-pleasure activities reduces stress and increases optimism and resilience. A recent review also found that play improves mental health.“Adults can benefit from play as much as children,” Dr. Ogaryan says, “not just as a reward, but something that helps regulate.”So go ahead and dance with your dog, build something with Legos, tell a joke, sing karaoke or do anything else that feels like fun. Don’t worry about being productive, just enjoy yourself. And, if you can, opt for more analog play, Dr. Ogaryan suggests, as a respite from our ever-more-digital world. Move your bodyWhether you dance, ski, do yoga, play pickleball, ride a bike, roller-skate, hike or lift weights, physical movement benefits overall happiness and well-being. A 2018 review study of more than 1.2 million adults in the U.S. found that doing any kind of exercise was “significantly and meaningfully associated” with better self-reported mental health.The sweet spot was 45 minutes of movement three to five times a week, but even short bursts of physical activity can boost brain health, according to the Centers for Disease Control and Prevention.“Movement helps support mood and regulate the nervous system,” Dr. Ogaryan says.Plus: exercise can improve sleep quality, and sleep is essential for mental health.Prioritize sleep“Sleep plays a major role in managing stress,” Dr. Ogaryan says. Research shows that lack of sufficient sleep increases the risk of various diseases, including depression.While stress can interfere with sleep, practicing good sleep hygiene can make logging ZZ’s easier. That means maintaining a consistent bedtime; keeping the bedroom cool, dark and quiet; and avoiding social media, news and stimulating shows before bed.Consume lessWe live in a consumer culture, inundated by endless streams of content and advertising everywhere we go, which makes it easy to get overstimulated.“Something really helpful for stress reduction is to simply consume less,” Dr. Ogaryan says – less news, less social media, less information, less noise, less screen time. “It’s about reducing the input,” she says.Consider setting a maximum number of news articles per day, for example, or a time limit on scrolling. Maybe even go device free for an afternoon or a whole day.Practice present-moment awarenessWith so much coming at us all the time, focusing on the here and now can make life feel more manageable, Dr. Ogaryan says: “When everything feels super overwhelming, when everything feels larger than life, let’s make our world a little bit smaller for that moment in time.”She suggests taking things one day, or even one hour, at a time. Ask yourself: What’s my next right action? Release the need to know how everything turns out and liberate yourself from having to handle everything right now. Let the future take care of itself and just focus on the current moment. Then the next one. Have a daily anchorFrom work to the daily commute to family and life responsibilities, our days can feel jam-packed. Dr. Ogaryan recommends creating a centering daily anchor that can fit into even the busiest day.Maybe it’s a 10-minute walk during your lunch break or mindfully enjoying your coffee in the morning. Let your anchor adapt to your needs each day, she says, but be intentional about using that time to ground yourself and calm your nervous system. You might even say to yourself, “I choose this walk to help me become centered,” or “My day already feels stressful, so I’m going to take the next 10 minutes to enjoy this cup of coffee, feel the warm mug in my hand and just be present.” Having an anchor won’t erase the busy-ness from your day, but it will allow you to approach it more calmly.Be kind to yourselfMost of us have a harsh inner critic in our heads who works overtime. But that critical voice only increases our stress, triggering the same fight-or-flight response as caustic words from another person.To feel happier, we need to replace that inner critic with a kinder, more compassionate voice, Dr. Ogaryan says. Studies show that self-compassion is a source of eudaimonic happiness – the kind of happiness associated with purpose and meaning in life.While our knee-jerk reaction may be to self-criticize – “How could you let it get to this point? You didn’t manage your time well and now the project is going to be late. You’re so inept.” – we fare better mentally by treating ourselves with kindness, like we would a friend. That might sound like, “You’ve got a lot on your plate, but you are capable and you’ll get it done. I believe in you.”We may think that speaking kindly to ourselves means letting ourselves off the hook, so we end up becoming lazy do-nothings. But research shows the opposite: People who are self-compassionate are more likely to try harder in the face of failure and ultimately reach their goals.You can thank your inner critic for its good intentions, but resolve to talk to yourself in a kind, compassionate voice.Connect with othersHumans are social animals built for connection. Stress can be isolating and cause us to withdraw, but connecting with others is a salve for the psyche, Dr. Ogaryan says.“We know that not all relationships are always easy, but if we can think about intentional, nourishing connection – even in really small doses – it could really help center us,” she says.Take a moment to laugh with your colleagues, hug your pet, have a conversation with a friend or smile at the barista making your coffee. A study found that even tiny interactions with casual acquaintances and strangers decreases loneliness and improves happiness and well-being.Seek supportIf you try these practices and happiness remains elusive, or if you can’t access the wherewithal to follow these tips, seek support from your physician or a therapist. Mental health conditions are among the most common health issues in the U.S. and around the world – more prevalent than diabetes or heart disease. One in five people in the U.S. experiences a mental illness each year, with depression and anxiety the most common, according to the National Institute of Mental Health.“We can all think about these tips,” Dr. Ogaryan says. “But it’s important to recognize if you’ve done everything you can and you’re still really struggling, it’s really important to seek help.”
Shaky political "science": breakdown of the peer review process
[This article is the latest in our “Shaky Political Science” series. In our 38 page report, “Shaky political ‘science’ misses mark on ranked choice voting,” released in December 2025, we examined over 40 studies focused on ranked choice voting (RCV). Many of these studies suffered from puzzling research methodologies, poorly constructed surveys, unrealistic simulated elections, cherry picked data and faulty analyses that often were contradicted by results from real-world elections (a link to our full paper is here). Here are links to the first four articles in our series: the first one summarizing the overall results of our report; the second one analyzed a study co-authored by University of Minnesota academic Larry Jacobs, which was one of the most error-prone of all the research we reviewed in our report; a third article showing an admirable example of two political scientists holding two other political scientists accountable for their flawed, sloppy research; and a fourth article that analyzed seven studies sponsored by New America’s political reform program that deployed flawed methodology based on “simulated” elections instead of real-world elections, which when combined with some basic misunderstandings of RCV, produced odd and misleading results]. In this fifth article in our “Shaky Political Science” series, we examine two flawed studies on the impact of RCV on voter turnout authored by San Francisco State University professor Jason McDaniel. McDaniel’s research in these two papers stands out for its puzzling methodology, inadequate and cherry-picked data, and faulty analyses that not only misunderstands ranked choice voting but reflects a basic misunderstanding of politics in general. The first of the McDaniel studies actually passed through a peer review process and then was subsequently published by the Journal of Urban Affairs, despite its obvious errors. It is perplexing that a jury of peer political scientists did not catch the errors and send it back to McDaniel for a rewrite or outright rejection. This calls into question the credibility of the peer review process itself. The peer review process is supposed to represent the intellectual pinnacle of the profession – a way for academics to certify the quality of each other’s work, and to act as a check against sloppy research. In the case of the McDaniel study, the peer review process failed. Yet his flawed study has been cited dozens of times by other political scientists in their own flawed works — an unvirtuous circle of academic research. Here is the first Jason McDaniel study that we analyzed: “Writing the Rules to Rank the Candidates: Examining the Impact of Instant-Runoff Voting on Racial Group Turnout in San Francisco Mayoral Elections,” by Jason McDaniel, 2016, Journal of Urban Affairs. This study covered San Francisco’s use of ranked choice voting (RCV) in mayoral elections, purporting to show that RCV reduces voter turnout overall, increases voter errors, and has a negative impact on “marginal populations,” i.e. racial minorities, mainly as the result of the alleged complexity of RCV asking voters to rank candidates and having to be familiar with multiple candidates and related dynamics. McDaniel reached these conclusions by examining five San Francisco mayoral elections taking place in odd years (i.e. where there are no federal or state races on the ballot) from 1995 to 2011, comparing three earlier non-RCV races (in 1995, 1999 and 2003) with the later two RCV races (in 2007 and 2011). Only two RCV races were studied, and as McDaniel acknowledged, only the contest in 2011 was “competitive” (that contest in 2007 was the first mayoral election using RCV, and incumbent mayor Gavin Newsom won easily in the first round of counting, earning 74% of first choices and far ahead of the second place candidate who had just 6.3% of first choices). Yet even the allegedly competitive contest in 2011was won by an incumbent with a landslide margin of nearly 20 points. No other elections were studied by McDaniel, even though San Francisco elects 17 other offices besides mayor with RCV, including the 11 seats on the Board of Supervisors (the name for the city council) in even years, and six other citywide offices in odd years. Previous academic research has found that competitive elections can stimulate greater voter involvement and higher turnout. For unexplained reasons, this study ignored at least 34 other RCV races between the years 2004 to 2011, many of which were very competitive and had high voter turnout. Instead, McDaniel’s analysis based its conclusions on data from only a single, marginally-competitive mayor’s race using RCV. These 2007 and 2011 mayoral elections were the only two RCV elections that McDaniel used as the sole basis for his small data set to determine the impact of RCV on voter turnout. Despite having no meaningful data to inform his study, McDaniel nonetheless concluded that RCV lowered turnout when compared to the previous three mayoral non-RCV elections using two-round runoffs. Then, using the same inadequate database of San Francisco elections, McDaniel also found that “Instant-runoff voting is associated with a significant decline in Black voter turnout and White voter turnout…On average, Black voter turnout decreases by 18 points and White voter turnout decreases by 16 points …” But how could he credibly arrive at that conclusion when his study was based on voter turnout in two RCV contests that were not even remotely competitive? Beyond that, McDaniel tacitly admits that the key determining factor driving Black voter turnout was not RCV vs non-RCV elections, but the presence of a viable Black candidate. McDaniel wrote, “Black voter turnout was about 17 percentage points higher for the two elections that featured an African American candidate compared to the three elections that did not” — but one of those three elections did not use RCV. The same dynamic was present for White voter turnout, in which higher turnout was not correlated with RCV vs non-RCV elections, but the presence of a viable White candidate. Beyond that, McDaniel’s voter turnout results, whether correlated with the race of the candidates or RCV vs non-RCV elections, showed no clear patterns. In his Figure 1, he shows low Asian voter turnout in the non-RCV elections in 1999 and 2003 when there was no viable Asian candidate running, but in the 2007 mayoral election using RCV, there is still no viable Asian candidate, yet Asian turnout increases dramatically. For Latinos, voter turnout is virtually the same in 1999 (no viable Latino candidate, non-RCV elections), 2003 (leading Latino candidate, non-RCV elections), 2007 (no viable Latino candidate, RCV elections) and 2011 (leading Latino candidate, RCV elections). Meanwhile White voter turnout increased dramatically from a low in the 2007 mayoral election, in which the leading candidate was a white incumbent, to the 2011 election in which there were no leading white candidates that finished any higher than sixth place with 5.6% of the vote. Clearly other factors were determining voter turnout than either the race of the candidates or RCV vs non-RCV elections. Despite these inconsistent findings, McDaniel boldly marches forth to render conclusions about the impact of RCV on different groups of racial voters, even though his conclusions are not remotely supported by his data. This looks like the worst kind of “data cherry picking” to cover up a puzzling conclusion based on a poor data set involving only two RCV elections, neither of which were remotely competitive. McDaniel’s cherry picking didn’t stop there. In calculating voter turnout for the three non-RCV mayoral elections in 1995, 1999 and 2003, he failed to mention that in each of these years there was a two-round runoff election, with a first round election in November in which no candidate garnered a winning majority of the vote, followed by the decisive runoff in December. So there were two non-RCV elections in each election year. But McDaniel only decided to include one of the two elections in his data set, apparently the December runoff in each year (which had higher turnout in two out of the three mayor’s races, and lower turnout in the third). So he ignored the November 1995 election, the November 1999 election when turnout was only 45 percent, and the November 2003 election when turnout was only 45.7 percent. This is flawed methodology based on blatant cherry picking, since McDaniel simply omitted three elections worth of data that did not fit within his frame. His study should never have made it through a peer review process, and it is an embarrassment to political science that not only was it approved for publication, but it has been uncritically cited by dozens of other political scientists. Share A “study” without wider context or credible data Lacking a data set that included even a single competitive RCV mayoral race, McDaniel declared that RCV lowered voter turnout in 2011, when turnout was 42.5 percent. But he also ignored -- or did not realize -- that voter turnout in mayoral elections during 2011 had sharply declined in all big cities, including far more steeply in nearby Los Angeles and other cities. In fact, San Francisco’s election in 2011 had the second highest turnout of any mayoral election in the nation’s 22 largest cities from 2008-2011. Was 2011 just a particularly low turnout year all across the country, perhaps because the country was still reeling from the aftermath of the housing market collapse in 2008-2010? McDaniel ignored this factor and did not search for alternative explanations beyond his flawed thesis. Furthermore, while McDaniel suggested that RCV leads to more “overvotes” – which is an invalidated ballot in which a voter, in either a non-RCV or RCV race, makes a mistake and selects two candidates for a single choice – he failed to address that in the June 2012 US Senate primary contest, which used the typical “one-choice” plurality method and did not use RCV, there was more than five times as many overvotes in San Francisco and Oakland than in the RCV mayoral elections in those cities. Additionally, turnout had been significantly higher and more representative in RCV elections for the San Francisco Board of Supervisors races -- that McDaniel didn’t even bother to study -- as compared to previous “delayed two-round runoffs” for those offices, often higher by as much as 40% in the RCV races. Perhaps the most surprising irony was that an earlier study co-authored by McDaniel (Overvoting and the Equality of Voice under Instant-Runoff Voting in San Francisco by Francis Neely and Jason McDaniel, 2015, California Journal of Politics and Policy) found that overvotes are often more common in lower-income precincts, but that the pattern of overvoting is similar in both RCV and non-RCV contests. Wrote Neely and McDaniel: “[Overvote] errors appear to be a function of complexity in general and not IRV per se…. the pattern of overvoting is similar in both IRV and non-IRV contests…Even among votes cast in a top-of-the-ticket race like U.S. Senate, overvoting occurs in an uneven fashion” (IRV, or ‘instant runoff voting,’ is another name for ranked choice voting in single-winner contests). So McDaniel not only contradicted his own conclusion in his earlier study with Neely, but the earlier study had been an important corrective for one of the most frequently made mistakes made by anti-RCV political scientists – a continual failure to provide crucial context by pairing a comparative analysis of real world RCV elections with an analysis of real world plurality or other electoral methods. Unfortunately McDaniel’s earlier study does not get cited much by other researchers, and McDaniel did not even cite it in his own flawed study analyzed above. Incredibly, McDaniel cherrypicked McDaniel, even as his flawed study has been cited dozens of times. Despite being a textbook example of poor political “science,” featuring both inadequate as well as cherrypicked data, the shelf life of McDaniel’s study has been extended endlessly by other political scientists and media outlets who have cited it uncritically. Equally troubling, the Journal of Urban Affairs put this paper through its peer review process and published it despite its numerous flaws. McDaniel gets it wrong, Part II Not content with producing one shoddy, confused paper, McDaniel produced another one a few years later, here is the link: Electoral Rules and Voter Turnout in Mayoral Elections: An Analysis of Ranked-Choice Voting by Jason McDaniel. San Francisco State Univ. (McDaniel, 2019). In this paper, McDaniel extended his previous flawed research focused on San Francisco, about voter turnout and voter impact, to multiple RCV cities through the 2018 elections. In his data set he included San Francisco, Minneapolis, St Paul, Oakland, Berkeley, San Leandro and Santa Fe. He then compared their turnout in mayoral elections to non-RCV cities, and to mayoral elections in those cities held before first RCV usage, and concluded “a significant decrease in voter turnout of approximately 3–5 percentage points in RCV cities after the implementation of RCV.” But he replicated many of the same mistakes as his first study presented above. While in this study McDaniel attempted to distinguish between various factors, such as odd year vs. even year elections, competitive races vs. noncompetitive, contests with open seats and other factors, the analysis is superficial and inadequate. He attempts to incorporate so many often-conflicting variables that his conclusions are once again unsupported by the actual data, and ultimately unconvincing (this second study never underwent a peer review process). For example, McDaniel declared that for RCV cities “in elections that are more competitive than average (margin of victory less than 20%), there is no significant RCV effect on voter turnout.” Yet McDaniel is a professor in a city, San Francisco, in which the 2018 special election using RCV to fill a mayoral vacancy was exceedingly close, decided by a margin of only one percentage point, and resulted in the second highest turnout in San Francisco history for a mayoral election. Illustrating the complexity involved in assessing the critical factors in turnout, that special election was held on the same election day as federal and state offices, which tends to boost turnout. Yet more voters participated in that RCV mayoral election than voted on the same day in the non-RCV primary for governor in which former San Francisco mayor Gavin Newsom was running. Even more puzzling, in this study McDaniel inaccurately cited his own previous study from 2015 with Neely. McDaniel wrote, “Neely and McDaniel (2015) examine individual ballot image files within a natural experiment, and find higher rates of ballot errors in RCV elections compared to non-RCV elections” (emphasis added). However, we quoted from that 2015 study several paragraphs above, and in actual fact Neely and McDaniel actually concluded the opposite -- that the pattern of overvoting – which is the most common form of ballot error – is similar in both RCV and non-RCV contests. McDaniel also ignored the fact that in Bay Area RCV elections held in even years – at the same time as federal and state elections, when turnout is highest -- the “undervote” (that is, the dropoff in ballots cast for governor or mayor) has declined, which contradicts his thesis that the act of ranking ballots in RCV elections is too complex and presents a barrier for certain demographics of voters. To his credit, McDaniel actually acknowledged another contradiction in his own paper, which found a negative RCV turnout effect in some odd-year elections but not others, admitting that “may present a challenge to the theory that increased complexity [from RCV] will have a marginal negative effect on voter turnout.” But he tried to wallpaper over that contradiction by blaming it on an unlikely source -- bad election administration. McDaniels wrote, “This would suggest that the negative impact of RCV on voter participation may be alleviated by high quality election administration,” without presenting any data or even anecdotes to support such an unfounded theory. While competent election administration of any election, whether RCV or non-RCV, is crucially important, there is no credible research that supports the far-fetched notion that the quality of election administration has much of an impact on voter turnout in US elections, whether using RCV or otherwise. Upgrade to a $5 subscription The unvirtuous circle of academic research It is puzzling how McDaniel’s first study could have survived the peer review process for the Journal of Urban Affairs. The mistakes in McDaniel’s first study above should have been obvious to anyone with a basic understanding of ranked choice voting as well as elections in general, and elections in San Francisco specifically. It undermines faith in the credibility of the peer review process to think that a jury of peer political scientists did not catch the egregious errors and reject McDaniel’s sloppy research and paper. And it remains a black mark on political science that this thoroughly discredited study has been cited dozens of times by other researchers. Indeed, in our research paper it became apparent that many political scientists cite each other’s flawed research to pad their list of citations and to legitimize their own flawed research, creating an unvirtuous circle of political science. More broadly, McDaniel’s voter turnout studies, like other studies evaluating RCV’s impact on turnout, lacked a recognition that no credible opinion or research can claim that RCV increases voter turnout merely because so many voters are excited to vote for their favorite candidates instead of “lesser evil” candidates without worrying about spoilers. Instead, with respect to turnout, the advantage of RCV has always been that, in most places where it has been used, it has eliminated a pre-November primary or post-November runoff, which usually saw about half the turnout of the November general election. This is especially true during even years when there are state and federal elections on the ballot which substantially drive turnout more than local contests. Any study that does not adequately account for this non-November primary/runoff vs November general election dynamic, or odd year vs even year election factors, is simply not credible. Both of McDaniel’s studies largely failed on those grounds. Steven Hill and Paul Haughey Share Upgrade to a $5 subscription Thanks for reading DemocracySOS…your digital portal for the pro-democracy movement. Subscribe for only $5 per month to receive full benefits and to support our work. Subscribe
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In early 2024, Phil Spencer, then head of Xbox, told me that ““[w]e ship games physically and digitally, and we’re really just following what the customers are doing.” He added that the game industry had become an outlier in still supporting disc-based entertainment, even as movies and TV have bailed on discs in favor of downloads and steaming: “Gaming consoles themselves have kind of become the last consumer electronic device that has a drive. And this is a real issue, just in terms of the number of manufacturers that are actually building drives and the cost associated with those. And when you think about cogs that we’re going to go put in a console—and as you have fewer suppliers and fewer buyers—the cost of the drive does have an impact.” Last year, the Nintendo’s Switch 2, which uses cartridges rather than discs, introduced the concept of game-key cards, which are physical media that contain no game, just a prompt for a download. Even disc-based games aren’t what they once were, now frequently containing just stubs of games rather than the whole thing. The website Does It Play has tested over 3000 games and found that, for example, that the disc version of this year’s hit 007: First Light, only contained the game’s first mission, with the rest needing to be downloaded. Beyond all that, last week brought the news that Grand Theft Auto VI, likely the biggest game launch this decade, will debut for PS5 and Xbox Series without a disc-based version. Today’s big news comes to you for free. Game File is a reader-supported publication. To receive new posts and ensure more of my work is possible, please consider becoming a free or paid subscriber. Subscribe Discs helped define PlayStation However the trends in entertainment may be going, it is still remarkable to see PlayStation ditch discs given their importance in PlayStation history: In the late 1990s, the first PlayStation’s support for games on relatively cheap CD-ROMs instead of traditional game cartridges allowed the upstart console to outmaneuver cartridge-based systems from Nintendo and Sega, as it drove down game prices down in the process. (The cheaper disc format even prompted Final Fantasy VII maker Square to taunt Nintendo in a magazine ad, saying that if the game was “available on cartridge, it’d retail for around $1200.”) PlayStation devices often doubled as machines for watching movies and TV on the latest disc-based formats. In the late 2000s, for example, Sony’s pricy PS3 gained traction as a go-to device for playing then-novel Blu-Ray discs. In 2013, Sony effectively roasted the digital game-sharing restrictions proposed by rival Microsoft for its upcoming Xbox One console by showing how games could be shared for the then-upcoming PS4. In a 21-second clip that has over 20 million views on YouTube, one PlayStation executive simply handed a game box—presumably with disc inside—to another, who said “thanks.” Sony’s possible motivations The PlayStation announcement today cites “consumer preferences” and a shift away from discs among “the broader entertainment industry,” but does not delve into the decision-making process that brought Sony to this point. Sony is not discussing the economics of this move (I asked!), but there are a number of potential factors: Abandoning discs will spare Sony the cost of manufacturing and shipping them, which analysts and industry veterans I spoke to said could account for $1 or so of a game’s retail price. For first-party games, that’s direct savings for Sony, though the amount is limited by the winnowing percentage of people who were even buying the disc-based versions. For third-party games, Sony could pass the savings on to partners or just retain the better profit margin for themselves. As the 2024 comments from Phil Spencer alluded to, leaving discs behind could mean leaving disc-drives behind, allowing Sony to produce consoles more cheaply. Switching to digital-only for games could diminish the risks of copies of new games leaking. It would also seemingly make second-hand sales of used games impossible, pushing more people to buy their own copies of games. These economic benefits for Sony could be boons for the games industry overall, Ampere analyst Piers Harding-Rolls tells Game File. Among other things, it could free publishers and retailers from having to worry about securing an inventory of game discs when trying to sell games, he noted. “If there is a way to streamline the business of games retail, I generally think it’s a good thing for the industry as it removes unnecessary costs,” Harding-Rolls said. “This will help offset pressure on margins from other directions – development and staffing costs for example.” Should the industry shift from game boxes that contain discs to smaller, cheaper game cards, Harding-Rolls said, that reduces pressure on publishers and retailers. “The advantage of everything going digital for the industry is that sales can be tracked much more easily and there is less commercial risk for publishers wanting to continue selling via retail,” he said. The shift to no discs will also likely impact game development timelines, as developers will no longer face the same urgency to have a build ready to submit to PlayStation for the production of a disc, as industry experts noted around GTA VI’s no-disc news last week. Instead, projects may gain weeks of development time, in the event delivery deadlines for platform approval move closer to release date. Preservationists’ likely worries While millions of gamers have shifted to digital, there are still people who associate game discs—and only game discs—with actual ownership of PlayStation games. That portion of the gaming community spoke up last week about wanting to buy a version of GTA VI that they could hold in their hands, could lend to a friend and could potentially pop into a well-preserved PS5 console three decades from now and still see it run. Such gamers didn’t want to worry that they’d merely purchased a digital copy that could lose access to the game if, say, the company behind the game someday turns of the servers that transmit downloadable copies. Digital copies of games are inherently less long-lasting, because consumers aren’t actually buying a game (on a disc), just buying access to the game. The fine print in online gaming shops notes this, as does a recent law that went on the books in California in 2025. That lasw requires game publishers doing business in the state to refrain from words like “sell” when offering digital copies of games, unless they explicitly tell consumers that what’s being sold isn’t the game itself but a potentially revocable license to access it. A Sony spokesperson noted to Game File that “[w]ith all digital content, including games, movies, and music, players are purchasing a personal license for non-commercial use.” Regarding the fears of PlayStation games being lost to time in an all-digital era, the rep also noted that Sony remains “committed to delivering experiences from past generations to the new platforms our players are using.” They noted that PlayStation has used emulation and remasters to keep offering its classic games to modern gamers. It’s true that many consumers have become accustomed to not having physical copies of new music albums or movies, but the relative precariousness of digital copies of games is in fact being highlighted today by…. Sony’s other big announcement: the upcoming closure of the PS3 and PS Vita online stores Sony said today that it will be closing the online marketplaces for its PlayStation 3 console and PS Vita handheld in most countries in July 2027 (sooner elsewhere: August 2026 for the PS3 store Mexico, Honduras and Nicaragua; late 2026 for PS3 in other Latin American countries and the Middle East). “We know this news may be disappointing to PS3 and PS Vita players who hold a special place in their hearts for this generation of gaming,” Sony said in its announcement, saying the move “was not an easy decision for us to make.” Sony said that PS3 and Vita marketplaces “are no longer able” to support modern commerce systems, prompting a “need” to close the shops and focus on more modern PlayStation platform stores. The news may spark some deja vu. Sony announced back in March 2021 that it planned to take the PS3, Vita and PlayStation Portable marketplaces offline that summer. The move would have caused some 2,000 digital-only games to become unavailable for new purchasers, according to a VGC analysis at the time. Fans complained loudly. By April 2021, Sony walked back the PS3 and Vita shop closures, with then PlayStation boss Jim Ryan saying “it’s clear that we made the wrong decision here.” This time around, Sony is giving a longer notice period in most regions. The closure of those stores is still likely to cut off access to new purchases of digital-only PS3 and Vita games. The current PlayStation 5 marketplace sells PS5 and PS4 games, as well as a selection of PS1 and PS2 games. It does not sell PS3 games, because games for that platform can’t run on the system (some are offered via a PlayStation Plus streaming option). Vita games also aren’t sold via PS5. Sony says digitally purchased PS3 and Vita games will be downloadable after the stores’ shutdowns “for the foreseeable future.” Sony’s move contrasts with Microsoft’s Xbox platform, which continues to sell and support games from all four Xbox console generations. But it puts it in line with Nintendo, which disabled purchases in the marketplace for its Wii console (a contemporary of the PS3) in 2019. Nintendo discontinued purchases in the online shop for its 3DS portable (a contemporary of the Vita) in 2023. The big questions about Sony’s 2028 post-disc era Will Microsoft follow suit, ending support for new disc-based games on Xbox platforms and therefore all game consoles, too? Whether Microsoft does or not, will third-parties that can no longer release games on discs for PlayStation, simply ditch the disc options across the board? Given the GTA VI no-disc experiment launching this November, will more game publishers decide to forgo disc-based offerings even in 2027? How will no-disc PS5/6 games be packaged and sold in brick-and-mortar retail stores? What becomes of game sharing in an all-digital era? Will Sony modify its current set-up, which currently allows some sharing of digital games across a pair of consoles, to allow more casual lending? (See for example, Nintendo’s year-old system of letting players lend a digital game to another player in a “family group” for up to 14 days.) Will there be a version of a PS6 with a disc drive? Or will a drive be offered as an add-on? And how will gamers who want to retain access to PS4/PS5 disc-based games react to whichever configurations Sony chooses to offer? What will the final disc-based PlayStation game be?
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This Week in Jacksonville - Business Edition: Franchise opportunities grow in River City
In this episode of This Week in Jacksonville: Business Edition, Kent Justice talks with David Montanez, vice president of franchise development for Authority Brands, about the growing franchise opportunities in Northeast Florida and beyond. Montanez explains how franchising offers a proven business model that reduces risk and supports entrepreneurs, including many veterans transitioning from military service.
Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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How a UConn program reduces the stigma of mental health care. It’s designed to increase access.
Research at several universities in New York indicates that just having a conversation that promotes mental health on campus normalizes the idea that students will go out to seek help for themselves
Exercise-based cardiac rehabilitation offers lasting heart health benefits
Exercise-based cardiac rehabilitation reduces hospital admissions by a third and heart attack risk by more than a quarter, as well as remaining beneficial in the long term, a new Cochrane review finds.
Why bipartisanship is disappearing from Congress
The nationwide push to redraw congressional districts mid-decade has not led to a big advantage for either political party, but it has created less competitive districts. We discuss how that reduces bipartisanship on Capitol Hill, and we discuss one lawmaker who seems to buck that trend.This episode: voting correspondent Miles Parks, congressional reporter Sam Gringlas, and political correspondent Ashley Lopez.This podcast was produced by Casey Morell and Bria Suggs, and edited by Rachel Baye.Our executive producer is Muthoni Muturi.Listen to every episode of the NPR Politics Podcast sponsor-free, unlock access to bonus episodes with more from the NPR Politics team, and support public media when you sign up for The NPR Politics Podcast+ at plus.npr.org/politics.
Iron Galaxy lays off employees as it reduces company size
Co-development and porting firm Iron Galaxy Studios is adopting 'a new posture to accept these current market conditions as permanent.'
Roundup: Shift in NIL / BlackBerry transitions / Agriculture aid
More inclusive: A recent NCAA rule change is shifting name, image and likeness opportunities away from only the biggest star athletes to a wider range of student-athletes. The update gives schools more structured involvement in managing and facilitating NIL deals, which reduces some of the previous free-for-all environment. As a result, athletes who are not […]
Are Bank Lobbies Still Relevant?
Local banking leaders say technology is changing the way customers use their banks — and their lobbies By Deborah Jeanne Post [caption id=attachment_11109 align=alignright width=300] Steve Gorczynski is M&T Bank Central New York regional president.[/caption] When was the last time you entered the lobby of your bank? If it’s been a while, you’re part of a trend of eschewing the lobby in favor of ATMs, drive-thrus, online banking and remote deposit. A 2025 study performed by the American Bankers Association revealed that only 9% of consumers use bank branches as their preferred way to do banking and 76% prefer mobile banking. The trend away from the lobby reflects consumer behavior in other areas of doing business, including online shopping instead of perusing the mall, ordering fast food at a kiosk, not at the counter and selecting curbside pick-up rather than walking into the restaurant. Consumers want convenience and going in the lobby adds another layer to the task. It also places consumers face to face with one or more representatives of the business, something less favorable to people feeling burned out from interpersonal interactions. Nixing or at least minimizing the size of the lobby isn’t necessarily negative for banks. Fewer people passing through their doors reduces overhead for building maintenance, staffing and furnishing. Greater reliance on virtual banking can mean closing brick and mortar locations and hiring fewer staffers to cover roles like teller and lending officer. “Our focus is on meeting customers where they are and giving them flexibility in how they bank,” said Steve Gorczynski, M&T Bank Central New York regional president. “While many everyday transactions can be supported digitally and through ATMs, branches remain important for more complex financial needs, offering face-to-face guidance and a more personal banking experience.” Talking with a commercial lender or working on a home mortgage are two examples where meeting face-to-face is more desirable for many people. They can receive immediate feedback to questions and can possibly reach their goals more quickly. But there’s little need to have a large seating area, long counters and numerous tellers for routine banking that’s quicker to handle virtually. Online banking can also help people on the go more readily complete banking tasks such as depositing checks, transferring funds among accounts and checking balances. [caption id=attachment_11135 align=alignright width=300] Tina M. Stephens is the vice president branch administration for Fulton Savings Bank.[/caption] “The traditional bank lobby is certainly being evaluated by most institutions today, as the typical large, open and cavernous spaces do not necessarily meet the needs of today’s customers,” said Tina M. Stephens, vice president branch administration for Fulton Savings Bank. “Traditional lobbies often bisect traditional teller stations and customer service areas, which adds confusion, especially for the demographic who routinely use online banking and only access the lobby for customer service needs.” Despite the rollback in physical locations across the industry, Fulton Savings Bank began modernizing its six branch offices in Oswego and Onondaga counties about three years ago and have finished four offices so far in Baldwinsville, Fulton, Constantia, and Phoenix. “We made the decision to build a new branch across the street from our current office in Brewerton which will be completed by the end of 2026, and we will begin the retrofit of our Central Square office in early 2027,” Stephens said. “Our efforts specifically address where we think customers will be in the next three to five years and have greater flexibility to make changes out into the future.” The bank may be onto something, as numerous reports state that screen-weary Gen Z young adults crave more in-person interactions than virtual ones. If the pendulum continues to swing in that direction, it’s hard to see all physical bank areas disappear, even if they change somewhat. Fulton Savings Bank has also consolidated its teller and customer service representative areas to larger “universal banker” areas, where the bank representative can address all customer retail needs. A one-stop-shop experience appeals to busy banking customers who want to perform a few different banking tasks in one visit. Stephens also said that Fulton Savings Bank made additional technology and security enhancements and created flex spaces to accommodate bank meetings throughout the two-county branch footprint. At Solvay Bank, Elizabeth Lavier, vice president marketing and communications manager, lauded digital and online services as convenient and flexible for managing finances; however, “technology is not meant to replace what matters most: the relationships behind every account that have always been at the heart of community banking,” she said. “Even in today’s digital-first world, people of all ages still value the opportunity to sit down with a trusted banker for personalized guidance. We understand that some of life’s biggest moments call for more than a screen.” Lavier views digital banking as another way for the organization to serve customers rather than a replacement for branches, tellers and lenders, which tend to serve customers better for transactions like buying a first car, purchasing a home, saving for a child’s education, or planning for retirement. “Those conversations, built on understanding, experience and personal guidance, are what community banking is all about,” Lavier said. “At the end of the day, banking is about more than transactions. It’s about helping our customers achieve their goals and being there for them every step of the way. By combining the convenience of digital banking with the care, commitment, and personal service of a local community bank, Solvay Bank offers customers the best of both worlds.” Are Paper Checks Destined to Disappear? With the ubiquity of debit cards, online payments, virtual checks and peer-to-peer payment platforms like Venmo, Zelle and PayPal, will paper checks become passe? “In my view, paper checks are unlikely to disappear in the near future,” said Tina M. Stephens, vice president branch administration for Fulton Savings Bank. “They continue to serve a practical purpose by providing a clear paper trail and tangible proof of payment.” According to the American Banker, a leading trade publication that covers the banking and financial industry, in 2024, checks accounted for 65% of all payment fraud losses. Paper checks should be phased out, according to the publication. “The phrase, ‘The check’s in the mail’ probably sounds strange to younger people because the era of paper checks is rapidly drawing to a close. Put bluntly, checks are an expensive, insecure legacy that is a drag on the U.S. economy. Rather than wait for them to vanish slowly, the pragmatic choice is to strategically accelerate the transition to paperless payments.”