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The 2026 election could reshape healthcare
Why everyone who cares about healthcare reform should vote in the midterms.
From Animal Camouflage to AI: The Evolving Science of Staying Unseen
Nature’s game of hide and seek is entering the age of intelligent machines. A new article in National Science Review traces how animal camouflage, advanced materials and artificial intelligence are converging to reshape the contest between detecting an object and keeping it concealed.
Why Chinese pundits say France’s riots could reshape European politics
Protests stem from falling competitiveness with an eroded middle class, providing ‘fertile ground’ for polarisation, observers say.
Why Entertainment Industry Layoffs Are Accelerating
Hollywood layoffs are mounting as streaming competition, overseas production and shifting audience habits reshape the entertainment industry.
Will a Chance to Reshape Business Models Help Law Firms Compete With Silicon Valley For Tech Talent?
Technologists without law degrees can't secure equity when working at a law firm. But some observers say that firms offer more rewarding opportunities to build tech infrastructure from the ground up.
Bickerstaff’s Pistons Open Against a Reshaped Boston Celtics
Detroit tips off the NBA season Tuesday against a Boston team that remade itself this summer. #Pistons
What Does a Human Heart Need to Grow? Scientists Found the Answer in a Bioprinted Model
Heart problems that babies are born with, called congenital heart defects, often begin developing early in pregnancy. Approximately three weeks after fertilization, the human heart is still a simple, straight tube of cells and, over the course of about five weeks, this tiny structure must undergo a remarkable transformation to reshape itself into the complex organ that eventually pumps blood throughout the body.
REM Hotel Launch Might Change The Case For Investing In Melco Resorts And Entertainment Stock
Melco Resorts & Entertainment recently saw analysts reduce its fair value estimates after reassessing debt levels, margin assumptions and the outlook for Macau gaming revenue. The launch of REM, a privacy-focused luxury hotel brand at City of Dreams Macau, signals a push to reshape how higher-end guests experience the resort. We will now look at how Melco Resorts & Entertainment's investment narrative could be influenced by the REM hotel launch in Macau. Compare how Melco Resorts &...
Fair Value Cut Raises Fresh Questions For Flutter Entertainment Stock (FLUT)
Flutter Entertainment has recently seen analyst fair value estimates marked lower following repeated guidance resets and ongoing regulatory pressures across key betting markets. The split between confidence in FanDuel’s customer momentum and concern over heavier promotions and regulation highlights growing uncertainty around Flutter Entertainment’s near term profitability profile. We will now look at how this more cautious tone on regulation and costs could reshape Flutter Entertainment’s...
Live Nation Entertainment (LYV) Could Be 16% Undervalued As It Resets Its Debt Clock
Live Nation Entertainment (LYV) has just priced a sizeable dual currency bond offering that reshapes its debt calendar. Fresh 2032 USD and euro notes are earmarked to redeem 2027 secured bonds and support broader financing needs. Against this refinancing backdrop, Live Nation Entertainment’s share price has moved to $170.51, with a 30-day share price return of 2.03% and a year-to-date share price gain of 17.34%. The 3-year total shareholder return of 113.27% points to longer term momentum...
Is 99% Screening Adherence Altering The Investment Case For Guardant Health (GH)?
Guardant Health reported new data from its Shield blood-based colorectal cancer screening test, including modeling and rural clinic results, indicating very high real world adherence and meaningful impact on screening pathways for average risk adults. The 99% completion rate for Shield in two rural South Carolina clinics highlights how a simple blood draw can address screening gaps in medically underserved communities and reshape demand across Guardant Health's screening franchise. This...
Twenty Hours a Week at an Amazon Warehouse for Health Insurance at 60? Here Is the Math a Retired Paralegal Will Run
A 60-year-old paralegal with $350,000 saved and five years until Medicare faces a decision that could quietly reshape her entire retirement, and the answer turns on a warehouse job that pays less than half what she used to earn.
Is the brain actually 2 nervous systems smooshed together? A new study claims it is.
A recent study may reshape our understanding of brain evolution and open new avenues for studying neurological diseases.
Does Debt Refinancing Change The Bull Case For Live Nation Entertainment (LYV)?
Live Nation Entertainment has issued US$730 million of 7.125% senior notes and €600 million of 6.125% senior notes, both due 2032, with guarantees from key restricted subsidiaries and plans to redeem its 6.500% senior secured notes due 2027. The refinancing reshapes Live Nation Entertainment's debt profile by swapping secured 2027 obligations for longer dated unsecured bonds, which can influence interest costs, covenant flexibility, and how much cash stays available for venue investment and...
M42 CEO on AI, genomics and the future of healthcare
M42 Group CEO Dimitris Moulavasilis discusses how the Abu Dhabi-based healthcare company is combining artificial intelligence, genomics and clinical services to reshape healthcare. He explores the group’s international expansion, the Emirati Genome Programme and the potential for technology to help doctors identify health risks earlier and move healthcare towards prevention rather than treatment.
Scientists discover cell division does more than make new cells: It helps reshape tissues
Every time a tissue grows or renews itself, cells must divide inside an already crowded environment. That creates a fundamental problem that scientists have not fully understood: How does a tightly packed ...
Nvidia reshapes communications amid AI boom and departures
Nvidia's communications team has restructured amid the AI boom, with staff changes as the company sees increased growth and workloads.
The Blue Wave Could Reshape Politics in the South
Democrats could flip more than 400 legislative seats nationally and the governorships in Texas and Georgia.
Cleveland State University receives $10M gift to reshape business education
The gift will fund a comprehensive overhaul of all undergraduate and graduate business programs to reflect new developments and emerging technologies in the field.
Bucs' Veteran Credits Bowles for Keeping Things Together
Amid a rocky start and rampant outside noise, Alex Anzalone reveals how Todd Bowles reshaped the locker room mindset to spark a season-saving upset over the Cowboys.
Smith Entertainment Group shares vision for reimagined Salt Lake City downtown
Smith Entertainment Group has unveiled the plans for a 4-block, 35-acre development that’s linked to the renovation of Delta Center and will reshape Salt Lake City’s downtown.
MIPCOM Cannes Attendance Dips as AI, Creators and Vertical Dramas Reshape Global Entertainment Market
CANNES, France — Attendance at MIPCOM Cannes was down this year, but the world’s largest international television market is undergoing a transformation that organizers say reflects the dramatic changes sweeping through the global entertainment business. MIPCOM Cannes 2026 drew 10,100 delegates from 104 countries, down from approximately 10,600 attendees from 107 countries last year. The … Continue reading "MIPCOM Cannes Attendance Dips as AI, Creators and Vertical Dramas Reshape Global Entertainment Market"
New Payor Transparency Rules: Why Hospitals Should Pay Attention
New payor transparency rules could reshape hospital pricing, managed care contracting, competitive benchmarking, and site-of-care strategy.
Updated 2027 NFL Draft Order Following Titans Loss to Texans
Tennessee’s dismal 0-5 start and stagnant offense have vaulted them into the top draft slot. Discover how a blowout loss to Houston reshaped the race for No. 1.
WAMSI Westport Marine Science Program Reshapes Coastal Port Planning in Western Australia
The WAMSI Westport Marine Science Program united more than 150 researchers across 32 projects to shape the design of Western Australia's Kwinana container port, resulting in key changes including relocating the port footprint to protect critical seagrass beds in Cockburn Sound.
Scandal reshaped NC-11 race. Now, 3 candidates fight to represent WNC
After Chuck Edwards' censure, Jamie Ager, Jennifer Balkcom and Travis Groo offer sharply different visions for Western North Carolina.
S.C. Succession: History-Making Debate Could Reshape Palmetto State's Evolving Politics
Three female candidates take the stage in South Carolina amid shifting electoral sands...
Opinion: Kansas may surprise the nation and elect a Democrat to the US Senate. MAGA politics reshaped state.
Opinion from H. Edward Flentje: In 1932, Kansas voters elected Democrat George McGill to the U.S Senate. In the 32 senate elections since then, voters have consistently elected Republicans to represent them.This historic streak makes Democrat Adam Hamilton’s bid to prevail in his challenge to the reelection of U.S. Senator Roger Marshall an uphill climb. However, Marshall’s embrace of MAGA politics has changed the dynamics of the race and given Hamilton a credible shot at a dramatic upset.
Weather extremes could raise costs, reshape decisions for Indiana businesses
By Sam Stall
Russia Using Taliban Ties To Reshape Regional Politics, Says Pakistani Analyst
A Pakistani security analyst says Russia’s changing stance towards the Taliban and ISIS suggests Moscow is reshaping its Afghanistan policy and creating a new “Great Game” in the region.
As AI reshapes entertainment, can it ever replace human connection?
From gaming to live streaming, audiences are seeking authentic interactions in an increasingly automated digital world
How federal college sports regulation would impact USC student-athletes
A recently passed Senate bill could reshape the college sports landscape
How federal college sports regulation would impact USC student-athletes
A recently passed Senate bill could reshape the college sports landscape
Could a “blue wave” reshape Wisconsin politics?
With Election Day approaching, Wisconsin Democrats are eyeing something they have not had in nearly two decades: control of the governor’s office, state
Crypto billionaire seeking to reshape politics runs against zeitgeist — and donates to Sherrod Brown
“I’ve had a lot of conversations with him," Chris Larsen says of Brown, a candidate for U.S. Senate in Ohio. "He is not anti-crypto.”
The midterm maps changed–so could Black political power
New congressional maps in nine states could reshape Black voters’ ability to elect preferred candidates, raising concerns about diluted political influence in s...
Republican megadonors dominate 2026 midterm election as crypto and AI money surges, CNBC analysis finds
Fourteen of the 20 biggest donor groups CNBC analyzed are Republican-aligned as crypto, AI and betting money reshapes 2026 midterm spending.
Oct. 7 reshaped Israel. Three years on, its political map remains largely unchanged.
As Israelis head to the polls, analysts say Oct. 7 and the war that followed have hardened existing political divisions rather than fundamentally changing them.
How has Oct. 7 reshaped Israeli politics?
The Oct. 7 attack on Israel by Hamas has forced Israeli Prime Minister Benjamin Netanyahu to fight for political survival ahead of elections later this month.
Week 5 changes the picture for college football’s undefeated teams
Week 5 reshaped the college football landscape as several undefeated teams suffered their first losses. Alabama, Georgia, Notre Dame and Miami strengthened their playoff cases, while Texas remained No. 1. With 15 unbeaten teams left, Week 6 brings crucial matchups that could dramatically reshape the national championship race.
As tech reshapes workplaces, University of Tennessee rethinks education
The Institute for the Future of Business was born out of the growth of artificial intelligence, nuclear energy and quantum computing.
Half a billion dollars in GOP spending does little to move polls
Republicans’ massive money advantage has yet to reshape the midterm map, as Democrats keep expanding their ambitions.
Redoing Daubert: Are judges letting bad science back into the court room?
Daubert was meant to keep unreliable science out of the courtroom by making judges gatekeepers who ensure the reliability and relevance of expert testimony and the underlying research. A recent Second Circuit decision raises a harder question: how deeply may a judge examine the science when evaluating an expert’s methodology before determining the scientific dispute itself? The answer could reshape how courts translate epidemiological evidence into legal proof.
HubSpot cuts nearly 660 jobs as AI reshapes its business
The marketing software company is eliminating 7% of its workforce and creating a flatter organization as it shifts its strategy toward delivering customer outcomes with AI.
Ruben Amorim 'Interested' As Joshua Zirkzee Attracts January Interest
AC Milan and Juventus ignite a January transfer battle for Joshua Zirkzee as Ruben Amorim weighs a high-profile reunion to reshape his attack amid ongoing squad rotation.
Broker facilities expand as technology, alternative capital reshape placements
Broker facilities that automatically or rapidly provide following capacity are expanding as brokers seek to speed placements, use data to package portfolios of risks and tap additional sources of…
Paramount-WBD deal closes; here are top quant-rated entertainment stocks
Paramount Skydance–WBD merger reshapes entertainment—see 20 top quant-rated movies & broadcasting stocks (AMC, DIS, NFLX, ROKU).
Business Strategy: Oklahoma aerospace is entering its next chapter
Kenton Tsoodle argues Oklahoma can build on its aerospace legacy as autonomous aircraft, advanced air mobility and other technologies reshape the industry.
Former ASU swimmer Grant House helped reshape college sports
Five years after becoming the lead plaintiff in House v. NCAA, former Arizona State swimmer Grant House reflects on the lawsuit that helped reshape college athletics, the leadership lessons he learned and his continued fight for athletes’ voices and collective bargaining with the Protect College Sports Act making its way through Congress.
Inaugural Delbert E. Day Lecture to be held Oct. 15
The first Delbert E. Day Lecture on Glass Science and Technology will be presented by Dr. Claudio Mazzali, vice president of global research at Corning, Inc. The title of his lecture will be “Precision at Scale: Navigating the Science-to-Factory Continuum that Reshapes Industries for Glass Manufacturing and Beyond.” The lecture will be held at 3:30...Continue Reading Inaugural Delbert E. Day Lecture to be held Oct. 15
Tech billionaires are spending millions to reshape California’s Legislature
Tech billionaires funding PACs have enjoyed recent growth in personal and corporate wealth and are spending it to handpick the Legislature.
Integral Ad Science to Provide Brand Safety and Suitability Measurement in ChatGPT Ads
NEW YORK, October 05, 2026--As artificial intelligence rapidly reshapes digital advertising, marketers face a critical new challenge: ensuring brand safety and suitability within dynamic, generative AI-native environments. Without independent verification, advertising in conversational channels risks creating a blind spot for enterprise brands seeking reliable media quality standards.
25 Years of Business Income Insurance Coverage Claims Since the Attacks of Sept. 11, 2001
The 9/11 attacks reshaped business income insurance, spurring decades of litigation over loss calculations, restoration periods, expert evidence, and terrorism coverage. These disputes continue to influence claims and policyholder protections after major catastrophes.
Data centers become a new political battleground in Tennessee
As opposition grows, AI companies are spending heavily on campaigns and lobbying as data centers reshape Tennessee politics.
Data centers become a new political battleground in Tennessee
As opposition grows, AI companies are spending heavily on campaigns and lobbying as data centers reshape Tennessee politics.
Kate Mulgrew says being “Star Trek”’s ‘unprecedented’ first female captain ‘reshaped my life’
“I think what she allowed women in STEM to do as a result of her command was absolutely, deeply significant,” Mulgrew said.
Zay Flowers’ availability could reshape Ravens’ attack against Titans
If Zay Flowers plays, his motion and explosive receiving ability could create opportunities for Baltimore’s other weapons against Tennessee
Grading the Grizzlies' Busy Offseason Before the 2026-27 Season
Memphis reshaped its roster around Cameron Boozer, Zach Edey and Cedric Coward while moving on from Ja Morant. The Grizzlies' offseason deserves high marks.
Is AMC Entertainment Holdings (AMC) Fairly Valued As It Reshapes Debt And Governance?
AMC Entertainment Holdings (AMC) just pushed through a cluster of corporate moves, including board declassification, new debt financing and an equity shelf registration tied to employee stock plans, giving investors fresh governance and capital-structure information to assess. Recent price action suggests traders are reassessing AMC Entertainment Holdings after these capital moves. The 90-day share price return of 46.56% and year-to-date share price return of 72.05% came despite a 1-year...
Weather extremes could raise costs and reshape decisions for Indiana businesses
By Sam Stall | Indianapolis Business Journal
ESA’s Juice just used Earth as a slingshot to Jupiter
ESA’s Juice spacecraft raced past Earth on September 28, using our planet’s gravity to dramatically reshape its path toward Jupiter without burning much fuel. The flyby changed its direction by 20 degrees and increased its speed by 3.5 km/s, while also giving scientists a rare chance to test its instruments on Earth and the Moon.
Columbine Brutal Reminder on Epidemic of School Violence
Colorado Politics looks back at Ken Salazar’s reflections on the Columbine shooting and a landmark court ruling that reshaped election security standards for Colorado voting machines.
Why Is CVS Health (CVS) Reworking Primary Care Around Value Based Care?
CVS Health (NYSE:CVS) is expanding its primary care approach by integrating value-based care across its health system. The company intends to connect health plans, provider groups, clinics, and pharmacies under a single patient-centered care model. Management is targeting shared accountability for outcomes that include social determinants of health alongside traditional clinical metrics. This push to embed value-based care across CVS Health's operations reshapes how the group manages care,...
TGIF: Ian Donnis’ Rhode Island politics roundup for Oct 2, 2026
Time is dwindling as Ken Block tries to reshape the gov race
What the Protect College Sports Act would mean for Wisconsin schools and athletes
The Protect College Sports Act would reshape how college sports are governed under the NCAA in the NIL era.
Remembering Howard Stevenson, Who Transformed the Study of Entrepreneurship
Howard Stevenson transformed entrepreneurship from a study of founders’ personalities and business formation into a way of managing: pursuing opportunity beyond the resources currently controlled. His approach emphasized testing ideas, committing resources in stages, assembling teams, and rewarding value creation—practices that could benefit organizations of any size. His ideas reshaped business education and influenced generations of entrepreneurs and managers around the world.
CUDA engineers adapt as AI reshapes Nvidia chip expertise
Engineers who work with CUDA, used for programming Nvidia's chips, are increasingly managing AI coding agents. Demand for CUDA expertise remains high.
Nike plans job cuts under sweeping restructuring plan
CEO Elliott Hill said the restructuring will result in fewer roles as Nike reshapes its business to become "more agile, efficient and athlete-focused."
Could Congress Reshape the Next Round of Conference Realignment?
The Protect College Sports Act could limit the growth of the wealthiest conferences while making successful Mountain West programs more attractive for future expansion. By Roger A. Holien | Mountain West Connection College football realignment has largely been driven by television contracts, conference revenue, and schools seeking greater national exposure. Now, Congress could influence what […]
Artificial Intelligence Could Reshape Dealership Business Development Centers
Artificial intelligence could sharply reduce staffing inside automobile dealership Business Development Centers within the next two years, according to a prediction from Car Dealership Guy founder and CEO Yossi J. Levi.
As private equity, politics and prediction markets reshape sports, is the press box up to the task?
Sports journalism has sometimes been called the ‘toy department,’ since it was known for less serious reporting. But the sports page has an opportunity to take on a real watchdog
As private equity, politics and prediction markets reshape sports, is the press box up to the task?
Sports journalism has sometimes been called the ‘toy department,’ since it was known for less serious reporting. But the sports page has an opportunity to take on a real watchdog role.
As private equity, politics and prediction markets reshape sports, is the press box up to the task?
Sports journalism has sometimes been called the ‘toy department,’ since it was known for less serious reporting. But the sports page has an opportunity to take on a real watchdog role.
Sapphire discovery could reshape future brain-inspired electronics
Using X-ray beams from Argonne’s Advanced Photon Source, researchers discovered that a substrate beneath a vanadium dioxide film is not just a passive host. Data reveal mutual interactions that could shape future low-power, brain-inspired computing.
Helene flooding reshaped River Arts District; leaders say recovery is far from over
The River Arts District looks dramatically different two years after Helene, but local business owners and community leaders say rebuilding is far from over.
Book review: The shadow politics of US-Africa relations
Can Africa build a mutually beneficial relationship with the US that reshapes decades of transactional security relationships?
Regular exercise reshapes the immune system at a cellular level, study suggests
Regular exercise makes our immune cells more vigilant, potentially contributing to better long-term health, a new study finds.
Veteran white politician threatens ANC's grip on Johannesburg
Helen Zille, a 75-year-old white politician nicknamed "gogo", meaning grandmother, is running for mayor of Johannesburg in a high-stakes November race that analysts say could reshape South Africa's politics. Nina Liu has more.
Big Ten power rankings: Upsets and surprises reshape conference hierarchy
There's a new No. 1 this week.
Veteran white politician nicknamed 'grandmother' shakes up Johannesburg mayor race
A 75-year-old white politician nicknamed "gogo", meaning grandmother, is running for mayor of Johannesburg in a high-stakes November race that analysts say could reshape South Africa's politics.
Viewpoint: After firing the entire National Science Board, Trump reshapes funding initiatives. Here’s the good and the bad.
The National Science Foundation is steering most of its money away from grants for individual researchers’ best ideas and toward the Trump
Senate passes bill to reshape future of college sports
The U.S. Senate passed the Protect College Sports Act Monday night, with a final vote of 77 to 22, after a series of votes on seven different amendments.
Senate passes bill to reshape future of college sports
The U.S. Senate passed the Protect College Sports Act Monday night, with a final vote of 77 to 22, after a series of votes on seven different amendments.
Senate passes bill to reshape future of college sports
The U.S. Senate passed the Protect College Sports Act Monday night, with a final vote of 77 to 22, after a series of votes on seven different amendments.
AMC (AMC) Stock Looks Fully Priced After Its Debt Refinancing Plan
AMC Entertainment Holdings has more than doubled year to date, which puts a spotlight on a simple question for you as a shareholder or watcher: do the cash flows from this cinema business support where the stock now trades? With the share price up 104.3% year to date, a lot now hinges on whether the market is putting too much or too little weight on AMC Entertainment’s future cash generation. The planned US$3.97b debt refinancing can reshape interest costs and repayment schedules, which may...
MD business leaders report AI expansion, not expected job cuts, in Moore’s office survey
Maryland business leaders expect AI to reshape jobs rather than eliminate them, a forthcoming report from the Governor’s Office of Innovation reads.
Kon Knueppel Reveals Expanded Hornets Role After LaMelo Ball Trade
Kon Knueppel says Charlotte wants more ball-handling and secondary playmaking from him as the Hornets reshape their offense after trading LaMelo Ball.
Portrait of a congressional district redrawn, as told by its voters
Redistricting has reshaped a key Central Florida district. So we hit the road to talk to voters about the issues that matter to them.
Trump's mail voting crackdown tests Postal Service leader who says he's 'not political'
President Trump's effort to use the Postal Service as a tool to reshape American elections is testing whether U.S. Postmaster General David Steiner will follow a similar path.
BMW M2 Gets A Dramatic 3.0 CSL Makeover
Riverti Automobili reshapes the G87 BMW M2 with 3.0 CSL-inspired bodywork, while key specs like power and production remain under wraps.
Arizona defense contractors see business boost as low-cost drones reshape Iran conflict
The war in Iran has raised gas prices and fueled inflation, but it has been good for defense contractors, including many based in Arizona.
Arizona defense contractors see business boost as low-cost drones reshape Iran conflict
The war in Iran has driven up gas prices and fueled inflation, but it has also benefited defense contractors, including many based in Arizona.
Arizona defense contractors see business boost as low-cost drones reshape Iran conflict
The war in Iran has driven up gas prices and fueled inflation, but it has also benefited defense contractors, including many based in Arizona.
China unveils sweeping higher education reform
New guidelines urge universities to specialise as demographic change and a tougher job market reshape talent demand.
Scientists Watched a Deadly Cancer Physically Reshape The Brain as It Grew
"A major step forward in studying neuro-oncological processes."
Scientists Watched a Deadly Cancer Physically Reshape The Brain as It Grew
"A major step forward in studying neuro-oncological processes."
Trump's Greenland obsession isn’t random. Here’s what’s at stake
Greenland's untapped rare earth minerals, oil and gas reserves could reshape U.S. energy security as Trump's Denmark deal expands military presence.
Could AI Commerce Reshape Meta (META)’s Business Model?
Meta Platforms, Inc. (NASDAQ:META) is expanding the commercial capabilities of its Muse AI assistant through a strategic partnership with Shopify, giving investors another potential avenue for AI monetization beyond digital advertising. On September 21,Shopify CEO Tobias Lütke announced a partnership with Meta to bring Shop Pay agentic checkout to Muse, allowing users to shop from […]
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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