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This Week: Politics 101, 20th Street Bikeway, Muni Trivia
Here is a list of events this week. Monday/Tonight! SF Politics 101 with Joel Engardio. Learn how local politics shaped San Francisco. Monday/tonight, October 19, 5:30-6:45 p.m. SPUR Urban Center, 654 Mission Street, S.F. Wednesday 20th Street Protected Bikeway Ribbon Cutting. The Oakland Department of Transportation, city officials, Bike East Bay and other community partners will celebrate the completion of the 19th Street BART to Lake Merritt Urban Greenway. Wednesday, October 21, 1:30 p.m. 400 Thomas L Berkley Way, Oakland. Thursday 2026 Silver SPUR Awards. This SPUR event brings together elected officials and business, civic, and philanthropic leaders to celebrate four individuals and their contributions. Thursday, October 22, 4-7:30 p.m. Blue Shield of California Theater at YBCA, 700 Howard Street, S.F. Get tickets here. Friday Woman and Non-Binary Morning Ride. Join the San Francisco Bicycle Coalition for a socially distanced bike ride for women and nonbinary cyclists. Friday, October 23, 7:15-8:45 a.m. McLaren Lodge, 501 Stanyan Street, S.F. Friday Muni Trivia Night. Bring your friends or come solo and make some new ones. Friday, October 23, 7:30 p.m. Standard Deviant Brewing, Pier 70, suite 195, 1070 Maryland Street, S.F. RSVP here. Saturday Fifth Annual Firefighter Family Ride. Join SFFD, SF Safe Routes to School, and the SF Bicycle Coalition for a fun, low-stress bike ride through one of the city’s most beautiful routes. Saturday, October 24, 10:30 a.m.-1 p.m. Panhandle Park Blacktop (Fell & Ashbury) to JFK Promenade (Whale’s Tail). Sunday Canvas for No on Prop G. Join the San Francisco Bicycle Coalition to canvas for No on ‘G’ to save Sunset Dunes Park. Sunday, October 25, 10 a.m.-12 p.m. Marina Blvd & Laguna Street, S.F. Got an event we should know about? Drop us a line.
Vandalia Health to celebrate grand opening of Mon Harrison Neighborhood Hospital September 22
Vandalia Health will celebrate the grand opening of Mon Harrison Neighborhood Hospital in Bridgeport on September 22. The 11 a.m. ceremony will feature a ribbon cutting, refreshments and facility tours.
FOR BUSINESS: New ownership
Contributed Toronto Auto Parts, a longtime fixture in the community, celebrated nearly 50 years of serving local customers and a change in ownership during an Oct. 10 ribbon-cutting ceremony. Community members, customers, friends and local officials were on hand to mark the new ownership of Preston Zeigler, while recognizing the five decades of service of […]
Caesars casino visitor center opens in Danville with goal to increase local business customers
Guests can create custom digital itineraries there and send them to their phones, said Lisa Meriwether, Danville’s tourism director.
Orlando Health expands orthopedic care in West Orange County
A new Orlando Health Jewett Orthopedic Institute has opened inside Orlando Health — Health Central Hospital in Ocoee.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Lawndale Christian Health Center was recently joined by Mayor Brandon Johnson and other city officials to celebrate the ribbon cutting of the new Family and Senior Health Center at 3814 W. Ogden Ave. Located in North Lawndale, the facility expands LCHC’s Ogden Medical Corridor and will increase access to health care services for residents of North Lawndale and across Chicago’s West Side.
NYC Health + Hospitals/Metropolitan Opens Serenity Room to Provide Comfort for Patients and Families
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Hometown Health Center's new facility in Palmyra aims to expand access to health care and wellness services in rural Somerset County.
MAD Security Meets Cyber Challenges In Defending Businesses From Evil
On Wednesday, MAD Security cut the ribbon on its operations center, revealing its mission to visiting civic officials and customers.
HCA Healthcare opens clinical training center in Gainesville
New facility will support nursing and physician education at six North Florida hospitals.
New facility at K-State brings grain, food and animal science together
K-State's Western Star center brings grain, food and animal science programs together for research and hands-on education.
Port Wentworth holds ribbon cutting ceremony for new entertainment center
Members of the community joined Mayor Tracey Saunders in celebrating the city’s newest addition with live music, free ice skating and watching football on the big screen.
Pacific Engineering opens facility in North Omaha Business Park, lands Navy contract
Pacific Engineering cut the ribbon to open its brand new manufacturing facility along Abbott Drive.
Choctaw Nation opens third small business center in McAlester
The Choctaw Nation of Oklahoma has opened a small business center inside the renovated McAlester Public Library, expanding access to workspace, business advising and connections to lenders. The Chahtapreneur Business Center’s 3,500-square-foot McAlester location is the tribe’s third center under the tribe’s purview, joining existing locations in Durant and Idabel, according to a tribal news […]
Orlando Science Center opens renovated theater
A lot is happening at the Orlando Science Center. The organization recently reopened the Dome and hosted a series of sold-out laser shows this summer. A new exhibit called “Extreme Sports: Beyond Human Limits” opens in late September, showing visitors what it’s like to rock climb and use a flight suit. To top it off,
Mom-and-Pop Business Owners Grapple with Harsh Times
Report shows small business owners in NYS less optimistic about the economy. Taxes, inflation, labor costs and competition from larger businesses are major concerns right now, they say By Aaron Gifford [caption id=attachment_11067 align=alignright width=300] Ashley Ranslow is director for New York state at The National Federation of Independent Business (NFIB).[/caption] Owners of mom-and-pop businesses in New York state have been less optimistic lately than their peers in other parts of the country, a recent report indicates. The National Federation of Independent Business (NFIB), based on a survey of 11,000 of its members in the Empire State, reported that taxes, inflation, labor costs and competition from larger businesses are major concerns right now. “Indeed, while taxes are a major problem in New York and the United States overall, New York small businesses notably are struggling more with the state’s onerous, multi-level tax burden,” Ashley Ranslow, NFIB’s director for New York state, said in the July report. Compared with surveys of business owners in other states, far fewer New York respondents rated their businesses as in excellent or good health. The report also said labor costs here are about 25% higher than the national average and are the “single most important problem” facing businesses. One respondent to the New York-specific survey complained that too much red tape, taxes and laws that restrict high-yielding companies have stifled their operation’s growth. Others said high disability and workers’ compensation insurance costs, alarming increases in utility rates and excessive building regulations are discouraging. Statewide, New York has a gross domestic product of $2.53 trillion (third in the nation, followed by Texas, $2.90 trillion; and California, $4.25 trillion), a per capita income of $90,500 (sixth) and an unemployment rate of 4.6% (34th). There are 2.4 million small businesses that employ 3.9 million people. [caption id=attachment_11112 align=alignright width=451] Member of the Greater Liverpool Chamber of Commerce gather at one of the several functions the chamber organizes monthly. “Everyone in this business community encourages each other to shop local. Everyone just wants to see each other succeed,” says Megan Wilmot, the chamber director[/caption] “New York state boasts one of the largest, wealthiest and most diverse cities in the world — and that’s still only about half the state’s population,” the report said. “In other words, the state is both its iconic city and so much more — geographically, demographically, economically. But New York is not without its challenges, challenges that include notably high taxes and other weaknesses that impact the small business environment,” it said. The report includes an optimism index that compares responses from New York (NFIB) members with those of their peers in other states across several categories. This ranges from plans to increase employment to expectations for higher sales, to plans to increase inventory or expand. The scores for Empire State business owners were lower in most categories, but they did score higher than the national average in noting that they have current employment openings, and that they are hopeful that the economy will improve. “The metrics so far paint a picture of a state with a series of challenges for small businesses, from a slightly below national average Optimism Index to a more seriously below national business health to very substantially below national Employment Index. What is going on with businesses that are creating these differences?” the report stated. In Central New York, the regional labor force comprises nearly 398,000 workers. The median household income here is $71,463, and the gross domestic product for the region last year totaled $61.3 billion, according to the CenterState CEO economic development and research organization. About half of the region’s labor force works for small and mid-sized businesses, although the number of people employed in that sector has decreased by 7% since 2010, according to CenterState’s 2026 economic forecast report. “While record-high employment in large-scale enterprises provides a strong foundation for Central New York,” the report says, “the long-term health of communities depends on a thriving small business sector to serve as a stabilizer.” Area employers identify several barriers to Central New York’s anticipated growth, including lack of specialized or skilled workers, government regulations, unaffordable housing options and long-term construction disruptions. In the city of Syracuse, the number of jobs in retail trade decreased by 1,500 or 4.7% between July 2025 and this past July. By contrast, the number of jobs in the leisure and hospitality sector increased by 2.5% or 700 jobs, in the same annual period, according to the New York State Department of Labor. Still, there’s plenty of interest for new businesses across Central New York. U.S. Census figures show that the number of applications for new businesses in all four counties increased significantly in the past 20 years. In Cayuga County, there were 324 applications in 2005 compared to 470 last year. In Madison County, the number increased from 385 to 480; Onondaga County, from 2411 to 4132; and Oswego County, from 553 to 836. Downtown Cazenovia is exemplary of Madison County’s trend: In the past year, the village welcomed a bait shop, a thrift store, a vitamin infusion center, a pizzeria, a Pilates studio and an Italian restaurant. A candy store is scheduled to open on the main drag in the months ahead. Oswego’s list of interesting new businesses in the past year includes a bubble tea shop, a hot dog eatery in Fulton, a specialty grocery store that features New York state products in Mexico, a beauty and esthetics studio in Hannibal and a hardware and farm supply store in Sandy Creek. In Onondaga County, the Liverpool area has also enjoyed a steady stream of new shops and eateries in recent years. That suburban community is unique in that, unlike neighboring communities, most of the restaurants are family-owned and not part of a national chain. [caption id=attachment_11116 align=alignright width=300] Megan Wilmot is the executive director of the Greater Liverpool’s Chamber of Commerce.[/caption] Megan Wilmot, executive director of the Greater Liverpool Chamber of Commerce, said independent business owners in her community maintain a strong sense of pride in holding their own against national companies. The chamber helps boost morale with red carpet events, ribbon cuttings, coffee hours and five-year anniversary celebrations for participating businesses. “We have built such a strong community,” Wilmot said. “Everyone in this business community encourages each other to shop local. Everyone just wants to see each other succeed.” In Syracuse, the downtown retail occupancy rate last year was about 82%, a slight improvement from 2024, according to the Downtown Syracuse Committee’s most recent annual report. Buildings with the largest amount of vacant space included The Galleries, One Park Place, and Equitable Towers, though not all of those spaces are designated for retail use. New businesses that opened in downtown Syracuse last year: Better with Time Clothing, Dakshin Curry & Biriyani, Havana Tattoo Society, Milano Bean Café, Miss Daisy, Pausa Coffee, Sweets for Babe, The Society CNY and Yafah Beauty Studio. The Destiny USA mall’s occupancy rate decreased from 80% in 2023 to 72% by the end of 2024, according to Integra Realty Resources. That leaves more than a quarter of the mall’s retail space vacant. “Looking ahead, the retail market is expected to see minimal rent growth, with vacancy rates likely remaining stable in community and neighborhood centers but continuing to rise in enclosed malls,” Integra’s report said. “New construction activity is low and redevelopment plans for former malls like Shoppingtown and Great Northern are still in the planning stages. The proposed Micron chip plant may spur development, but challenges remain in finding co-developers for large-scale projects.” Nationally, the U.S. Chamber of Commerce expects that small businesses will remain resilient and see their sales and revenues eventually improve. That organization, in a recent national survey, found that 25% of small business owners expect the economy to improve in 2027, while 45% indicated that they plan to increase employment in the next 12 months. And 69% said they believe their small business is in good shape and 70% said they are comfortable with their current cash flow. Thirty-one percent of small businesses reported raising their prices in July and 28% are planning to raise their prices within the next three to four months, the report said. Twelve percent indicated that this is a good time to expand their business. “Small business owners voice optimism for future revenues and hiring,” the report said. “High costs continue to be a wet blanket on reinvestment.” The NFIB reported in July that Main Street, despite gas price hikes, “is OK … for now.” Its small business economics trend report said sales across the country have been strong compared to last year, but continued inflation and higher prices from mom-and-pop establishments are causing some “cracks” to show. “If costs stay this high for much longer, reduced investment will have a tangible economic impact,” the report said. “The status quo is OK, but the outlook? The outlook is uncertain.”
Panther Lake teardown reveals Intel 18A in detail — TSMC still leads in density
SemiAnalysis has taken Intel’s Panther Lake apart, showing how the company’s 18A process combines RibbonFET gate-all-around transistors with PowerVia backside power delivery. The analysis finds that 18A delivers logic density similar to TSMC’s N3E, but does not yet give Intel a clear manufacturing lead over TSMC’s newer nodes.
New Chapter of Care Opens in Pleasanton
By Joy Jernigan, Vitals contributor Sutter Health leaders, colleagues, and elected officials gathered Sept. 17 to celebrate the opening of the new Pleasanton Care Complex, an important milestone in Sutter Health’s commitment to expand access to care in the Tri-Valley area. The celebration recognized the many people whose vision, expertise and collaboration helped transform this […]
COA opens new $25M health sciences center
College of The Albemarle officially opened its new $25 million Regional Health Sciences Center, a 60,000-square-foot simulated hospital, with a grand opening and ribbon cutting that drew dozens of guests,
Medicaid changes impact, newest culinary trail: CT politics news
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MGCCC holds ribbon-cutting for Health Professions Building
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Holy Cross Health Opens $41 Million Deerfield Beach Center and Breaks Ground in Fort Lauderdale
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Vandalia Health celebrates grand opening of Mon Harrison Neighborhood Hospital
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Chicano Mural Cover-Up: Was Santa Ana’s New Pool Opening All About Politics?
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New Madison Facility Strengthens B&A’s Presence In The Region
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Trump inaugurates new White House helipad as networks skip coverage
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$6.4 Million Grant to Bolster Maternal, Child Health
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Baptist Health South Florida and Lifepoint Rehabilitation Celebrate Grand Opening of New Inpatient Rehabilitation Hospital in South Miami
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Little River Chamber to host 3 Ashdown business openings
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Broward Health Medical Center Dedicates Boyce Haller Family Cardiac Catheterization and Electrophysiology Suite, Made Possible by $5.2 Million Family Gift
(L-R): Michelle Thoman, chief operating officer, Broward Health Medical Center, Eileen LaMarca, consultant for the Broward Health Foundation, philanthropist Linda Haller, Shane Strum, president and CEO of Broward Health, Stacy Angier, commissioner on the North Broward Hospital District Board of Commissioners, and Lauri Littleton, associate chief nursing officer, Broward Health Medical Center, cut the ribbon […]
Ribbon Cut On Relocated Child Behavioral Health Hub
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Choptank Health celebrates expanded care in Chestertown
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Evolution Dental Science opens new facility
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Boise to hold celebration and ribbon cutting for McDevitt Youth Sports Complex
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Blue Ribbon Yearbook predicts Memphis will win the American
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‘It’s been transformational’ | Buffalo Museum of Science cuts ribbon on Science Stadium
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Daldrop Opens for Business in Southern Oswego County
$10 Million Facility in the L. Michael Treadwell Oswego County Industrial Park marks the largest expansion outside of Germany in the company’s 73-year history By Stefan Yablonski [caption id=attachment_11076 align=alignright width=450] Daldrop SBB CEO Jens Daldrop addresses attendees at the 2025 groundbreaking for the project. Daldrop also chairs the advisory board of Germany-based Daldrop Group.[/caption] A new era of cleanroom technology is underway in Central New York. The Daldrop Group’s advanced manufacturing facility and U.S. headquarters is physically built within the L. Michael Treadwell Oswego County Industrial Park. This industrial park is located in the town of Schroeppel. It marks the largest expansion outside of Germany in the company’s 73-year history. Daldrop SBB is based in Neckartailfingen, Germany. It is a global supplier of cleanroom technology, primarily to the pharmaceutical industry. It designs and builds advanced cleanroom environments for the pharmaceutical, biotechnology and medical technology industries. It nvested $10 million in the new project. “We broke ground in 2025; we were under construction all winter. We just opened this spring, early spring,” said Benjamin Morrow, operations manager and control. The company consolidated sites in Salina and DeWitt into the industrial park in Schroeppel, Morrow added. “The next move here is to maximize every square inch of this facility and then we are already looking at the expansion. So, it is more capital investment on equipment — definitely higher-end automation in additional equipment so we can produce more components and then to support the ever-growing base in North America,” Morrow continued. “We are the headquarters for service, maintenance and spare parts. So as Daldrop has more and more installations, they need more and more service, maintenance and spare parts. So that will come out of this facility as well — it already is.” “As a global leader in GMP (global manufacturing support) pharmaceutical cleanrooms for decades, I am very proud to bring manufacturing jobs to Upstate New York,” said Mike Sullivan, president of Daldrop US operations. Key to choosing Southern Oswego County [caption id=attachment_11077 align=alignright width=450] Daldrop SBB at the L. Michael Treadwell Oswego County Industrial Park when the company announced the start of construction.[/caption] Sullivan said that the selection of the Schroeppel industrial park was mainly due to the help of Operation Oswego County and two people in the organization. “Prior to being purchased by Daldrop International from the Stuttgart region of Germany, Vince Bongio was a founding partner in SBB Inc. as well as our head of engineering. We based out of Syracuse due to Vince’s skills in HVAC and the manufacturing capabilities found in Syracuse,” said Sullivan. Bongio moved to Syracuse from California in the 1970s to work in Carrier’s Industrial Division of Large-Scale Petrochemical Refrigeration. Next, he advanced to General Electric’s TV Tube Plant where he got into cleanrooms ,leading to his role of head of engineering for Clestra Cleanrooms where he met Sullivan, their New England distributor. “Vince Bongio is a phenomenal engineer. Formerly of Carrier, he grew up in California and went to Cal Poly,” Sullivan explained. “Carrier hired him right out of college and he moved to Syracuse. He is the reason we are in Syracuse today. He is retiring this year. We are very proud and his legacy is having brought Daldrop to Syracuse.” In 2000, Sullivan, Bazinet, Bongio Inc (SBB) was formed with engineering and manufacturing, based in Syracuse, and sales and construction based in Massachusetts as it is today. “SBB Inc. started in Syracuse. I had a design–build contracting firm out of Massachusetts that was primarily doing all the new technologies coming out of MIT,” Sullivan said. “I started a manufacturing side. A big thing for cleanrooms is the HVAC. Most cleanroom suppliers are architecturally focused people. The strength in Syracuse is HVAC. So, SBB developed with me running sales and construction out of Massachusetts and manufacturing out of Syracuse.” “Daldrop wanted to have a relationship in the States and of those who approached us, they were the only ones who really understood HVAC. So, we were the right fit for them. We did a joint venture focused out of Massachusetts from 2012 to 2018 leveraging their technologies,” Sullivan explained. “The commitment was if we brought their product to the States, we would do that if they built it here. “The pieces that had to be in place to make the investment, they wanted to acquire us, we were great with that. If you looked at business recommendations the general guidance was to build in a low labor area — something like North Carolina — but Syracuse had a strong background in HVAC and we chose Syracuse and Oswego County to be our headquarters in the States. So, it is built off of history, technology and the existing supply chain — bringing jobs back to the area.” During the initial discussions with Daldrop about coming to the U.S., SBB agreed to sell under the conditions Daldrop would manufacture in the U.S. There are many areas that offer incentives and economic packages, but the strength of HVAC expertise and skilled manufacturing was a big part of the discussions for site selection. Coming home [caption id=attachment_11078 align=alignright width=451] Construction moves forward in March at the L. Michael Treadwell Oswego County Industrial Park.[/caption] The second key person to building in Oswego County is Ben Morrow, Sullivan added. “Ben has been working with Daldrop SBB for more than 12 years and has advanced to COO of manufacturing and engineering. Ben grew up in Phoenix, so building a factory for the Germany company in Phoenix is a strong success for both his community and the appreciation of Ben’s skills as a team leader,” Sullivan said. “I went to high school in Phoenix. So, this is like full circle for me. It’s a small world,” Morrow said. “I hadn’t been back to Phoenix since graduation. This is one of the properties that John Trimble of C&S, he is the former president of C&S, he just retired, suggested. He and I were very good personal friends. John was from Mexico and I was from Phoenix. We knew each other from high school. And the architect of this building, Ed Smart of smartDESIGN Architecture in Batavia — I went to high school with him. So, this was a project that’s full circle a coming home kind of thing. The three of us knew each other — kind of like it was meant to be. Very serendipitous.” Schroeppel was one option for Daldrop to consider; the original intent was just to get a warehouse to store some product, he added. The facility is Daldrop’s largest outside of their native country. Total payroll at the facility will be approximately $2.4 million once fully staffed. “Here is 32,000 square feet and we plan to expand and put in an additional 10,000 square feet,” Morrow said. “We have 17.5 acres. We can put at least three more facilities here, just on this property. The master plan submitted for the current building is the first of possible three buildings on the campus.” “If we can find the right people and advance the production according to the plan, we should be able to grow for the next decade. One of the first jobs we filled was our new HR manager, with a primary focus posting and filling new positions,” Sullivan said. Stop the exodus, start hiring [caption id=attachment_11080 align=alignright width=452] Principals at the local Daldrop SBB headquarters, from left: Ben Morrow, Mike Sullivan and Jens Daldrop.[/caption] “I have been coming to Syracuse for 30 years. One of the things I had a hard time watching was the exodus of factories. One of the toughest things is to watch it with my partners’ kids who had to move away for jobs. It is important for us to give opportunity where people’s kids don’t have to leave the area to get work,” Sullivan said. “My responsibility is to find people who have skill sets that want to work and then I have to build opportunity for that work to happen. “After years of watching companies and Vince’s three sons all move out of the areas to get jobs, it is important to us to provide opportunities for the Syracuse region and help grow our company. We have been hiring for our new factory and will continue for the next few years.” “We are hiring and will continue to hire. Currently we have about 19 on staff right now,” Morrow said. “We expect to grow that by about 10 to 15 in the next 12 to 18 months or so. We are at 19 currently — one in the wings. It’s been great being able to hire locally. All these folks that we’ve been hiring, they all live within a few miles from here.” “We hired someone this past week (end of August). She grew up in the area, raised a family and is working down in Florida. She just took a job with us so she can move back and be with her family. We will be moving her back and she should be starting in October. We are very happy to see this happen,” Sullivan said. “I feel strongly about having a spot for the kids to not have to move out of the area. It is better to have people moving into the area.” Currently, Daldrop SBB has openings for finance manager, COO of construction and delivery, as well as mechanical, electrical designers and Revit modelers, construction managers, commissioning agents and many other skills that are needed. Along with Daldrop’s reputation in life science cleanrooms, there is a strong history in semiconductor, electronics, glass, photonics, aerospace and other markets. This may be helpful with any new technologies building in the market such as the Micron expansion and the support network, Sullivan said. “We acquired this property and closed on it two months before any announcement from Micron. It is serendipitous that they’re right down the street from us,” Morrow added. “Everybody started thinking ‘you guys are supporting Micron.’ We were here first. That is not a goal of ours. We may or may not … they are talking to us; it is an opportunity.” The long run [caption id=attachment_11079 align=alignright width=450] Benjamin Morrow, operations manager and control at Daldlrop, speaks during a recent ribbon-cutting event in Schroeppel.[/caption] “Long term, we will expand the Phoenix facility,” Sullivan said. “We built our facility with a campus approach. Sustainability is big. We designed our rooms to be more sustainable. Our building has no gas lines for heat. We put geothermal wells in the ground. We put heat pumps in for heating and cooling out of those wells and we put a large layer of solar panels up on the roof. We worked with National Grid for metering. Our building is a high efficiency model. We upgraded all the instillation and the glass filtering. So, it is a very green building. We will have a very minimal carbon footprint. It also adheres to LEED (Leadership in Energy and Environmental Design) construction standards.” “We are a bunch of HVAC engineers. We did a large scale geothermal and spent the money up front because we knew it made sense in the business sense in the environmental sense and sustainability,” Morrow said. “We have insulated metal panels on walls and roof; we are an envelope from the exterior.” Daldrop, as a global player, has a strong culture of sustainability that is found in all its products including the new facility. The building has been designed with (sixteen) 400-foot deep geothermal wells, high efficiency construction methods, approximately 70 kilowatt solar photovoltaic panels, electric vehicle chargers and 26% recycled content. “Daldrop thinks of long-term investing,” Sullivan said. “On the roof, photovoltaic panels supplement our power. Over half the energy that I use is coming from the sun. We have chargers up front for employee electric vehicles. This place is built to last. This slab that we are walking on, normal buildings are four inches, some go to six inches, we are nine inches all the way through — except where the heavy equipment is — that is 10 to 12 inches thick, solid concrete. It allows us to reconfigure for whatever type of equipment we want to bring in,” Morrow said. “We are authorized by Underwriters Laboratory to self-certify so we don’t need to have an inspector come out and recertify. We get audited often, but we certify our own electronics. The control system in this building is rather high-end. Our thermostat in every room is zoned, independent. We analyze the data; incorporate it with our solar panels.” “There is a lot of competition for people to work. It’s not just about how much salary they are going to make — it’s about the work environment, the ability for stability. We want to make sure our employees have the best environment to work in,” Morrow added. Similarities “One of the reasons I believe why Daldrop chose this area, Phoenix in particular, is because it is a village, a river-based village. Neckartailfingen in Germany where Daldrop is based is also a river-based village, manufacturing community. So, there is a lot of similarities — that smalltown feel,” Morrow said. “We have a lot of connections through multiple employees that lead back to Carrier, also. Everything came together, the timing everything.” “We are thankful for all the economic development support. Everyone has been helping make this happen. So, keep it up, it is working, that is all I got to say, Sullivan said. “If you look at historical industrial manufacturing, this region has skills that have been un-utilized. The northern industrial region has a lot of skills that if we can tap before they go away, we can leverage them. That is what we are trying to do. You’d be surprised at the supply chain left behind from Carrier — that supply chain is still there.” “Operation Oswego County has been fantastic,” Morrow added. “I can’t say enough good things about that group.” What Is Cleanroom Technology Cleanroom technology is a system of specialized engineering, filtration and operational controls used to maintain an extremely low concentration of airborne particles, microbes and chemical vapors. How It Works • Air Filtration: Uses HEPA or ULPA filters to remove 99.97% of tiny particles down to 0.3 microns. • Airflow Control: Directs air in a steady, unidirectional (laminar) or filtered turbulent pattern to push dust away from work areas. • Environmental Regulation: Maintains precise control over temperature, humidity and positive air pressure to block outside air leaks. • Specialized Attire: Requires personnel to wear full-body garments (“bunny suits”), gloves and masks to stop human shedding
UAMS Health Opens New Hospital in Saline County
LITTLE ROCK —The University of Arkansas for Medical Sciences (UAMS) held a ribbon-cutting ceremony today to celebrate the opening of a new comprehensive healthcare facility at 21514 I-30 Frontage Road (Exit 123) in Bryant.
Sorrell College of Business launches Corporate Partners program with ribbon cutting ceremony on Sept. 22
Troy University’s Sorrell College of Business is preparing to officially launch its Sorrell Corporate Partnership Program, an initiative designed to strengthen relationships between the college and businesses throughout the region while providing students with greater access to business leaders and career opportunities.
Nike Formally Announces UM Partnership – Extra Details Upon Agreed Deal
The Swoosh returns to Coral Gables in 2027, bringing exclusive Blue Ribbon Elite benefits, NIL opportunities, and heritage-inspired throwback collections to a surging Miami Hurricanes athletic department.
Big Top Xtreme Entertainment Complex Will Open in Pine Bluff with Ribbon Cutting Ceremony
After months of development and preparations, Pine Bluff’s Big Top Xtreme entertainment complex is preparing to celebrate its opening with a ribbon-cutting ceremony Wednesday, October 14th at 10 a.m. Located at 2100 East Harding Avenue, the family entertainment destination brings a variety of attractions to […]
Craven County Community Health Center cuts ribbon on Havelock expansion, adds VA clinic and pharmacy
Craven County officials celebrated the opening of an expanded community health clinic Monday, bringing essential medical, pharmacy, and behavioral health care closer to home for eastern county residents.
Students flock to Radford’s new $1.2 million, 10,000 sq. ft. e-sports facility
On Oct. 23, Radford University will hold a ribbon-cutting on its new state-of-the-art e-sports facility.
QC mom launches custom bag charms business for students, teams, teachers (or anyone)
From CLS creates custom bag charms for students, athletes, teachers and teams, offering personalized, affordable accessories that can be tailored with colors, ribbons, beads, initials and themes.
Players Sports Center Brings Indoor Sports Back To Logan Square
The center, located in the former The Windy City Fieldhouse, has six indoor sand volleyball courts, two basketball courts, two regulation pickleball courts and an indoor turf soccer field.
CHRISTUS Health holds ribbon cutting and blessing for new cancer center in Longview
CHRISTUS Health held a ribbon cutting and blessing for its new CHRISTUS Cancer Center in Longview.
New stationery business opens in the Midlands
Mayor Daniel Rickenmann also attended a ribbon-cutting ceremony for a new business Friday, October 2.
Expanded Havelock health center adds exam rooms, pharmacy and VA behavioral clinic space
HAVELOCK, Craven County — Craven County leaders will cut the ribbon Monday on an expansion of the Craven County Community Health Center in Havelock.The ceremony
Encompass Health celebrates opening of new Bangor rehabilitation hospital
The for-profit health organization has expanded its footprint in recent years with plans to open hospitals in several locations around the country.
Business Beat : Coldwater Direct Primary Care ribbon cutting scheduled for Monday
COLDWATER, MI (WTVB) - Healthcare accessibility in Branch County takes a major step forward as Coldwater Direc...
Sitrin Health Care Center cuts ribbon on 75 years serving the Mohawk Valley
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BUSINESS UPDATE: Attracting World-Renowned Piercing Educators to Oswego
Growing number of renowed piercers are coming to Oswego to share knowledge at newly opened Aqua Spa Float Center piercing suite Submited by Aqua Spa Float Center & Wellness Boutique [caption id=attachment_11066 align=alignright width=450] Recent opening of Aqua Spa Float Center piercing suite.[/caption] Professional piercers and educators from countries including France, Scotland and India have come to Oswego’s Aqua Spa Float Center & Wellness Boutique to share their knowledge In the past year and a half, the Port City has become a destination for some of the industry’s most respected educators through the efforts of the Aqua Spa Float Center & Wellness Boutique. Beginning in January of 2025, Aqua Spa Float Center envisioned a new version of body piercing, one where elegance, safety and personal expression could converge. According to the Aqua Spa, piercing is no longer just a trend — it’s a refined form of personal identity, luxury styling and self-investment. It’s not only about the jewelry — it’s about the entire experience. The team welcomed first guest piercer Ruben Triguero, a senior French piercer, piercing stylist and international educator, who has over two decades of experience and has worked in some of the world’s best studios, including Paris, Rome, New York, Miami, Los Angeles and Dubai. In those studios, he offered his expertise and refined styling skills. Triguero is a prominent figure and leader in the piercing community and shares his knowledge with piercers teaching classes for the industry’s most prestigious organizations, including Latinoamérica Body Piercing Association (LBP) and Association of Professional Piercers (APP). He is currently the senior international instructor of the APP. Triguero has a passion for creating stunning, personalized piercings for clients around the world. Education and Mentorship Following a year of success and popularity, Aqua Spa Float Center hosted the grand opening of its private dedicated piercing suite in March. Aqua Spa Float Center & Wellness celebrated this next chapter with a grand opening and ribbon-cutting ceremony attended by the Oswego Mayor Robert Corradino, members of the Greater Oswego-Fulton Chamber of Commerce, local business owners and community members. The educational focus, aligned with Aqua Spa Float Center’s vision and mission, had already begun expanding beyond clients. Aqua Spa has hosted multiple workshops and continuing education opportunities for professional piercers, inviting studios from across the region to gain hands-on experience from internationally recognized instructors without the expense of traveling to national or international conferences. These educational events have welcomed nationally and internationally recognized professional piercers and educators from countries including France, Scotland, India, and throughout the United States. Aqua Spa also continues to collaborate with talented regional and local professionals, creating opportunities for education and mentorship that benefit both industry peers and clients throughout Central New York. Aqua Spa Float Center & Wellness Boutique owners — Tammy Wilkinson and Terry LeRoi — have been deeply rooted in the piercing industry with over 30 years in business as LeRoi Fine Body Jewellery. Combining that experience with holistic wellness, self-care and self-expression is the new concept with the client Luxe Piercing Experience at the Aqua Spa Float Center. “At LeRoi Fine Body Jewellery and Aqua Spa Float Center, we’ve been fortunate to work with many of the world’s most respected piercers through our involvement with the Association of Professional Piercers and by attending conferences across North America and Europe,” said LeRoi, founder of LeRoi Fine Body Jewellery and co-owner of Aqua Spa Float Center & Wellness Boutique. “Those experiences have shown us that education is what drives our industry forward. “Not every piercer or studio can travel to major conferences like the APP Conference in Las Vegas or APP Benelux in the Netherlands, so we’re committed to bringing that level of education here. Hosting internationally respected educators like Jef Saunders allows our clients to experience the highest standards of professional piercing while giving piercers throughout the Northeast the opportunity to learn from some of the very best in the profession. That’s something we’re incredibly proud to offer our community.” When asked about the client experience, Wilkinson explained that education is at the heart of every appointment as well. “Our vision is to nurture and enhance wellness, balance and harmony through a multi-modality-centered facility, and we aspire to empower sustained, positive change, well-being and self-awareness; and educate to the benefits of natural health, holistic wellness and life balance,” Wilkison explains. “Piercing is no different. The piercing experience feels just as peaceful and rejuvenating as any other spa services. From the moment our clients arrive, they are in the very best hands with our kind and professional Wellness Ambassadors and experienced APP guest piercers.” Wilkinson also explained that piercing clients receive stellar care: every Luxe Piercing appointment includes a one-on-one private piercing in Aqua Spa’s dedicated piercing suite, their choice of custom jewellery by LeRoi Fine Body Jewellery, thorough after-care instructions and complementary check-up appointment, complementary whole-body red light therapy session in the Class II NovoTHOR medical device to promote healing, and access to many rejuvenating spa services. Piercing clients get 15% off during any event. According to Wilkinson, “Health and safety are always our highest priority when you come in for a piercing or jewelry installation. Before each appointment, all tools and jewelry are sterilized in a Statim autoclave, and every surface in the piercing room is carefully disinfected. During the procedure, your piercer will wear a mask and change gloves as needed to maintain a sterile environment. Once your piercing is complete, your piercer will go over detailed aftercare instructions with you. Following these steps is crucial to ensure proper healing before you leave our sanctuary.” As a part of the experience, guest piercers include a thorough anatomy review of the client’s desired piercing to ensure the new addition will work in harmony with the existing. “Our clients are enjoying building and creating ear curations with these international professionals. It’s a unique styling event and a chance to highlight self-expression,” Wilkinson said. Clients and piercers throughout the region are flocking to this piercing destination in Upstate New York. The Luxe Piercing Experience has welcomed clients and piercers alike from around the globe. Owners Wilkinson and LeRoi hope to continue the momentum with more educational seminars with industry experts to be a hub of knowledge and expertise. They hope to establish LeRoi Fine Body Jewellery and Aqua Spa Float Center as legacy businesses known for their lasting, positive impact on the piercing and holistic wellness industries.
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