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I thought I was dying but it was health anxiety - here's how to recognise the signs
Hollie Sharman shares her experience of health anxiety and a doctor advises on how to manage symptoms.
Xbox Game Pass Reportedly Getting 'Major Overhaul,' Will Feature 'À La Carte' Options
Microsoft is reportedly planning a substantial revamp of Xbox Game Pass that will allow subscribers to choose the features they want in an à la carte fashion. The report comes by way of a new Fortune profile piece on Xbox CEO Asha Sharma.
The non-gamer CEO racing to save Microsoft’s Xbox
Asha Sharma has cut thousands of jobs, consolidated studios, and rewritten the playbook. Insiders wonder if she’s saving the brand or preparing it for a non-Microsoft future.
Ubisoft plans cuts at German studios, adding to wave of workforce reductions
Ubisoft is planning to reduce its workforce in Germany, where it operates a trio of studios, by about 100 workers, Game File has learned. The company wants to offer employees buyouts to, should enough people accept, avoid having to lay anyone off. “In Germany, we initiated discussions with the Works Council last week regarding a proposed voluntary departure plan across Ubisoft Dusseldorf, Ubisoft Berlin & Ubisoft Mainz,” a company rep told Game File. A “works council” is a union-like group representing employees. “The voluntary plan is the primary measure being proposed to support the intended organizational changes,” the Ubisoft rep added. The company declined to confirm the scale of the potential headcount cut. Of the impacted studios, Mainz might be the best known to the public. It leads development of the Anno series and shipped the well-reviewed strategy game Anno 117: Pax Romana in November 2025. Berlin and Dusseldorf operate as support studios within Ubisoft’s creative network. Berlin recently supported the development of Rainbow Six Siege and the Rayman Legends Retold remake. Dusseldorf also contributed to those projects, as well as The Settlers and Ubisoft-branded escape rooms. Dusseldorf is the biggest of the three studios, with some 400+ workers, compared to just over 100 at the other two, a source familiar with the reductions and the teams told Game File. More than half of these new reductions of about 100 people are expected to happen at Dusseldorf. The planned cuts were announced at a town hall for the German studios on Tuesday of last week. In an email follow-up, the studio group’s managing director, Benedikt Grindel, said the cuts were intended to “best position our German studios for the future... with a clearer focus on their role, capabilities and organizational setup needed for the work ahead.” The email was an echo of the past. In January 2025, Grindel had emailed the Ubisoft developers in his region (or studio “zone”) to explain that a round of 185 cuts at the time, including about 65 at Dusseldorf, were “essential to improve our operational efficiency and ensure the long-term sustainability of our studios, the zone and the company.” A half-decade of continued job cuts Ubisoft has been aggressively cutting its headcount for years. At the end of September 2022, it had 20,729 workers. By the end of March 2026, that total was down to 16,590. Studio management is trying to trim costs as it grapples with a changing industry and a drought of releases, let alone hits. The company announced earlier this year that it had reduced its costs since 2022 by “nearly €325 million” ($362m) and planned to lower them through 2028 by another €180 million ($200m). In June the company said it was closing down its Winnipeg and Belgrade studios and cutting roles in its Barcelona team. Even commercial and creative success hasn’t spared studios from this ongoing company-wide contraction. As Game File was nailing down details around the proposed cuts in Germany, Ubisoft management was informing workers of cuts in its Singapore studio, which shipped a hit remake of Assassin’s Creed IV: Black Flag this past July. Some 70 positions in Singapore are being eliminated “to align the studio with upcoming production needs,” per a company rep’s statement to Game File. In early 2024, a large team in the Singapore studio launched the multiplayer pirate game Skull & Bones. It performed poorly but has been supported with regular content updates since. Many of Ubisoft’s studios around the world are heavily subsidized via regional grants and tax breaks. Singapore had been among them for years, but received no such local assistance in the 12 months ending this past March. News of the Singapore cuts broke today alongside word that Ubisoft is also proposing the closure of RedLynx, pending negotiations with officials. The Finnish studio behind the motorbike series Trials was founded in 2000 and sold to Ubisoft in 2011. As reported by VGC (and corroborated by Game File), Ubisoft management told employees it could not come up with a new, sustainable assignment for RedLynx. The 2025 workforce at Ubisoft Dusseldorf were straight-up cuts. This time, Ubisoft is hoping the reductions at its trio of German studios will largely come from workers taking a payout to leave. The company offered such voluntary dismissals at its Massive Entertainment studio (The Division) a year ago. For the German studios’ buyouts this time around, Ubisoft and the Works Council had discussed a formula that’d pay a worker’s monthly salary multiplied by 1.5 and by the number of years they’ve worked at the company, according to Game File sources. The formula is still subject to negotiations with the Works Council and has not yet been part of an official offer to workers. It could be adjusted up or down, and it could be supplemented with additional bonuses. Asked about the floated payout formula, a Ubisoft rep told Game File, “The terms of a potential voluntary departure program remain subject to negotiation with employee representatives. No final agreement has been reached, and we won’t comment on specific proposals while discussions are ongoing.” Game File is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe Item 2: Epic’s AI adventures Epic Games (Fortnite, the Unreal engine) is all-in on using AI to try to transform the way it makes video games and game-making tools. It’s leaders appear to be undeterred by any resistance among gamers and some game developers around generative AI—and instead emboldened by advances, particularly in AI-assisted programming. A recap of the last three days: On Monday, Bloomberg reported that Epic management told workers last week that development of an upcoming game combining Star Wars and Marvel characters would be “AI first.” Employees would be expected to use AI models such as Claude to code the game. A manager told Epic’s developers there would be “[n]o more hand-written code” and that art for the game would be “generated with full AI workflows,” per the outlet. Just ahead of that story running, Epic founder Tim Sweeney tweeted: “We have a huge pivot underway here at Epic, moving developers around to retool for maximum AI acceleration. The aim isn’t to do the same stuff with fewer people, but to enable everyone here to build MORE and BETTER stuff, and to bring the benefits to all teams using Unreal.” In a follow-up, Sweeney predicted that most game development processes would be at least three times faster a year from now than they were in January 2026, thanks to AI. To a person on X who told him he was failing to read the room, Sweeney said: “Much of the room wants it to be 2016 again, but it’s not. Our job, as the provider of tools and technology to much of the industry, is to design for the present that is and the future that will soon be.” On Wednesday, Epic announced it was releasing a faster launcher for its Epic Games Store marketplace. It did so by stating in a blog post as clear as could be that the launcher is an AI-enabled, vibe-coded project: Programming is hard. So, instead of doing that, we vibe coded a new Epic Games Launcher that’s way faster and more responsive than the current one, and has a new look. Programming is hard? That was unexpected phrasing from a company founded by a legendarily great programmer. Back in 2011, Sweeney told me that he’d picked up programming quickly as a kid and rejoiced at the power it gave him. “I could look at any program that anybody else had written and, with enough effort, build something cooler.” Item 3: The Xbox Labs experiment (and one of the people behind it) Microsoft’s Xbox division, which is flooding the zone with announcements lately, yesterday revealed a new internal tech-tinkering team called Xbox Labs. In the words of Xbox boss Asha Sharma Labs is “a small group of game makers, engineers and scientists whose job is to turn emerging ideas into things our players and developers can experience.” Conventional wisdom coming out of the announcement is that Labs is a team that’ll focus on ideas driven by generative AI. In her announcement, Sharma cited some of the dizzying achievements in tech and gaming over the past month as AI agents and other AI tools have been deployed to swiftly figure out how popular games work, then rebuild them and mix them up. She mentioned seeing ”games rapidly decompiled and rebuilt to run on hardware they were never originally designed to support” and said “[p]erhaps more surprisingly, we’ve seen many of the biggest games in the world have been remixed into the source code of another.” (Minecraft plus Elden Ring, for example, or Fortnite + Super Monkey Ball + Overwatch + Diablo + others.) Sharma also cited the work of Windows PC games being ported to run in browsers, a seeming reference to a recent AI-assisted fan port of Halo. Or perhaps Call of Duty or GTA. Sharma didn’t use the specific term “AI” in her memo, but she came close, citing AI “agents” and their potential for game-making tools that Labs could help craft: I think XBOX has an important role to play here. Coding became the first major workload for agents because they can write, run, and test software. Games share many of those same properties, and people spend more than 72 billion hours a year playing XBOX games, roughly five times the estimated time spent writing code worldwide. We’ve spent 25 years learning how to make great games, and I want our game makers to help shape what these new technologies make possible. As we learn, we’ll share the tools we build with developers across the industry, just as we always have. When I asked an Xbox rep if Labs was an AI-centric team, they said genAI was not the focus, describing it as having a broader mandate for using new tech in new ways in gaming. As an example, they pointed to Xbox’s recently launched disc-to-digital gaming usage rights program. Microsoft didn’t specifically name anyone involved full-time in Xbox Labs yesterday, but on social media and LinkedIn, I spotted Adrian Mato IDing himself as leading the creatio of tools at Labs and talking up the launch. Mato first caught my attention in late September, when he said on X that he was “starting to build a new team at Xbox focused on products and tools for how games get built and distributed as agentic tools become more capable.” At the time, he framed AI-based tools as a supplement to traditional game dev tools. “I don’t think we need to replace them,” he said. Since then, he’s publicly shown interest in AI and in games. He’s recently spent some of his X feed marveling at the power of AI agents and praising the lighting in the latest Gears of War. Following the Labs announcement yesterday, he enthused about the Xbox Labs’ stylish landing page. He wrote: “We built some fun tools to art-direct shaders in real time, experimented with interactive ASCII art, and sprinkled in lots of tiny details. “Move your mouse to leave a colorful trail that reveals the original footage, or interact with the video to trigger bursts of particles. “A lot of love went into making it all feel just right. “More to come”
Xbox CEO reportedly warns firm will "not survive" if it only relies on existing franchises
Platform needs to "find new ways, and courage, to have invention on new IP that reach new sets of audiences"
Xbox announces Xbox Labs, a new initiative to trial emerging ideas and "new technology"
New business unit is charged with testing new projects and judging them by user feedback
Xbox 'Won’t Survive' Without New IP, CEO Says
Xbox CEO Asha Sharma said in a town hall that the division needs to focus on new IP after divesting from many of its studios that made new IP.
Asha Sharma reportedly tells rattled Xbox employees: "We have to find new ways, and courage, to have invention on new IP"
There's still apparently an appetite at Xbox to create new gaming franchises. But where, in this bruised company, does it come from?
WBN, Xbox and the CXO Summit: This Week's Top Five Stories
This week's top stories include, WBN on Europe prioritising risk strategy, Asha Sharma's plans for Xbox and discussions around AI at the CXO Summit
Inside Microsoft's plan to boost Xbox, Battle.net on PC — "Right now, it is simply very hard to work with Xbox," said Asha Sharma, with plans to fix it
Microsoft has long identified Battle.net as a key part of its Activision-Blizzard acquisition, and at yesterday's Town Hall with Xbox CEO Asha Sharma, we got more hints about the future.
Asha Sharma reportedly informs staff that Xbox has "started to return to growth" during internal town hall
"We're making the right decisions to reinvest in the business," says Sharma as Xbox continues to undergo major restructuring
Xbox CEO Asha Sharma speaks at internal town hall — Discussing Xbox Series X|S as 'core,' Helix as a family of devices, boosting Game Pass, and more
EXCLUSIVE: In a recent town hall with Microsoft gaming staffers, Xbox CEO Asha Sharma described how Xbox was in "free fall" declines before this year's big restructure.
Xbox CEO Asha Sharma insists "Xbox is not for sale"
Xbox CEO Asha Sharma has pushed back on speculation that Microsoft could spin off its games division, telling the New Y…
‘Xbox is not for sale’ says Microsoft’s gaming chief
Xbox CEO Asha Sharma is taking a ‘long-term view’ of Microsoft’s gaming division.
Asha Sharma Says 'Xbox Is Not For Sale' Amid Concerns Microsoft's Gaming Business Is Being Streamlined For A Spin-Off
Xbox is already looking very different than it did a year ago
Xbox’s Millennial C.E.O., Asha Sharma, Isn’t Playing Around
“I think the industry will require disruption,” said Asha Sharma, who has overseen layoffs and divested studios since inheriting Microsoft’s flailing video game division.
Xbox CEO Asha Sharma Shares 'First Look' At Unlocking The Mythic In Gears Of War: E-Day
Here's what'll happen when you complete all 55 achievements
Microsoft CEO Says Xbox's "Streamlining" Is "Great To See" Following Recent Layoffs
Microsoft CEO Satya Nadella called Xbox's ongoing job cuts "great to see," commenting on the restructuring led by Xbox CEO Asha Sharma. The remark follows Xbox's latest layoffs, which cut 268 more jobs on top of the 1,600 eliminated earlier this year, part of a plan that has already folded...
Microsoft CEO says Xbox's "streamlining" is "great to see" despite cuts and layoffs
Speaking on the Sources podcast, Satya Nadella called Xbox's ongoing restructuring under Asha Sharma "great to see", despite fresh layoffs this week.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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"It genuinely breaks my heart"- Confusion and frustration reign as gaming communities react to Xbox's drastic restructuring this week
Rare, Obsidian, Age of Empires, and Ninja Theory communities are reckoning with the fallout from Xbox's latest restructuring.
Microsoft lays off 300 employees in WA
Microsoft cuts 268 Xbox roles as new CEO Asha Sharma tries to revamp the gaming division.
Exclusive: Xbox to Cut Hundreds of Jobs, Consolidate Game Studios
Xbox is planning to lay off hundreds of employees this week in its second major staff reduction this year, according to someone briefed on the plans. The Microsoft-owned firm also plans to consolidate several of its game studios, this person said. Xbox CEO Asha Sharma in July told staff she would eliminate 1,600 roles by the end of the year on top of 1,600 roles the company cut that month.
Rating and TRP for Rohit Sharma's TV show: Family Full House with Rohit Sharma
Family Full House with Rohit Sharma rating: Check the latest IMDb score, TRP rating and official television viewership figure.
Rohit Sharma TV debut: What is the show called? Who were the first guests?
With Rohit Sharma making his television debut, here's a look at the show and who his first guests will be today.
Booming Business: Atlanta Firm Creates Cleaner Way to Sop Up Oil Spills
After the Deepwater Horizon spill, o-founder and CEO Sudhir Sharma, a Georgia Tech Ph.D. and chemical engineer, started wrestling with how to actually clean up spilled oil instead of just moving the problem from the ocean to the landfill.
Rapper Santy Sharma Makes Viral Joke And Meme About The New iPhone Duo’s Insane Price Tag
After Apple announced the iPhone Duo, it's first foldable phone, Indian rapper Santy Sharma posted an AI-generated image of himself holding the smartphone and a scar on his stomach, implying he would ...
Rapper Santy Sharma Makes Viral Joke And Meme About The New iPhone Duo’s Insane Price Tag
After Apple announced the iPhone Duo, it's first foldable phone, Indian rapper Santy Sharma posted an AI-generated image of himself holding the smartphone and a scar on his stomach, implying he would ...
Xbox CEO Asha Sharma May Have Personally Responded to Your Customer Support Ticket
New-ish Xbox CEO Asha Sharma has had a busy first six months on the job, including killing the divisive "This is Xbox" marketing campaign, slashing Xbox Game Pass Ultimate's subscription price, and unfortunately also overseeing mass layoffs and development studio spin-outs. But as Sharma has gotten settled in her job, she's also been spending time understanding Xbox's products and customers in another way: by fielding customer support tickets.
XBOX CEO Message is Salt in Sony's Wound at Kojima Productions
XBOX CEO Asha Sharma has left a message on Kojima Productions wall that fans are taking as a shot against Sony, which tried to cancel PHYSINT.
Bone Health Without the Hype
I am at the Australasian Menopause Society meeting and we had a fantastic lecture on Bone Health on Day 2, called, “Everything you need to know about bones - except the boring bits!” Spoiler alert, there were no boring bits. The lecture was given by Dr. Amanda Beech, who is a senior staff specialist in Obstetric Medicine and Endocrinology at the Royal Hospital for Women, where she is director of the Bone Density Unit. I want to summarize my top 10 take-aways for you. Share Osteoporosis is a disease of low bone mass, disruption of bone microarchitecture, and fragility of the skeleton. It is a silent disease…until someone develops a fracture. The diagnosis of osteoporosis is based on either fragility/minimal trauma fractures or a T-score of less than -2.5 on a DXA (Dual-Energy X-ray Absorptiometry) or bone scan. It is important to recognize that about 50% of minimal trauma fractures occur when women have low bone mass (often referred to as osteopenia), but not osteoporosis. This tells us that bone strength is more complicated than a number on a DXA report. I am going to add a little here that wasn’t in the talk (one can only include so much in 25 minutes), as many women might read the above paragraph and think, “Shouldn’t we be treating everyone with low bone mass if this is when 50% of the fractures occur?” Many fractures happen for women with low bone mass because there are so many women with low bone mass –it is a statement about the population on a whole, not about the fracture risk of low bone mass. For you as an individual, bone density is only one component of fracture risk and many women with lower bone mass will not have a significantly elevated fracture risk. This is why individualized risk assessment matters. Subscribe We build bone in our teens and twenties, and by the time we are about thirty we have reached peak bone mass. This is why, when we discuss risk factors for osteoporosis, it is important to consider factors that might have affected us in our teens and twenties when we were actively building bone, such as nutritional restriction/energy imbalance. It is important to ask women about a history of eating disorders, and for those with such a history, getting a bone scan in perimenopause or at age 50 is likely warranted. (This image below isn’t from the talk, but is similar to one that was). Bone mass is relatively stable until about two years before the final menstrual period, and perimenopause marks a time of rapid bone loss for women. Using urinary markers of bone loss we know that the time of significantly accelerated bone loss starts about 1 year before the final period and ends about 2 years after the final period. The Study of Women’s Health Across the Nation (SWAN) shows that over the menopause transition women lose an average of 10.6% of the bone at their lumbar spine and 9.1% at the femoral neck While this wasn’t covered in the lecture, I want to add that the rapid bone loss during perimenopause is clearly related to more than estradiol, because during this time estradiol levels can be erratic and not uniformly low. Bone loss during perimenopause is likely a multi-hormone event. For example, rising FSH (follicle stimulating hormone) tracks with bone loss better than estradiol, and there is evidence that FSH may act directly on bone. While decreased estrogen matters, there is clearly more going on. FSH and bone is an active area of research. Subscribe Screening for osteoporosis was recommended fairly broadly before age 65, and was taken from the “Practitioner’s Toolkit for Managing Menopause,” from Monash University. Here is a screenshot from the toolkit that was used as a slide: I am going to add a little bit more about body weight here for clarification. Low body mass (typically 152.1 lb): 0 points (risk neutral) 60–69 kg (132.3–152.1 lb): 3 points (adds some risk)
Rohit Sharma show on Sony: Trailer, start date, show timings and how to watch
With Rohit Sharma's TV show finally about to air on the Sony Network, here's everything you will need to know about the timings and where to watch it.
NYU Courant inducts Indian American computer science scholars
Gautam Kamath, Pratyusha Sharma bring expertise from MIT, and IIT Delhi to advance reliable machine learning.
Xbox CEO Reacts To The Irony Of Rising Console Prices Being An Issue That Microsoft Itself Contributed To
Xbox CEO Asha Sharma believes it is "wonderful" that GPUs have use beyond gaming.
Xbox CEO says next-gen Project Helix will be a “family of devices,” hinting at another Xbox Series S|X-style lineup
Xbox CEO Asha Sharma says the next-generation Project Helix will launch as a “family of devices,” suggesting a tiered lineup similar to the Xbox Series S and X. Microsoft has confirmed AMD-powered hardware supporting Xbox and PC games but has yet to disclose pricing, release timing, or disc-drive options.
Xbox Not Ready To Say If The Elder Scrolls 6 Will Be Exclusive
Microsoft's gaming division was tight-lipped at Gamescom
Project Helix will be a ‘family of devices,’ Xbox CEO confirms
Xbox CEO Asha Sharma says Project Helix will focus on affordability…
"All of the industry needs to start to innovate on affordability and efficiency" - Xbox's Asha Sharma wants change and "more choice" for people buying consoles
As console prices skyrocket, Xbox leader Asha Sharma has called for change in the way companies sell them.
Xbox CEO Asha Sharma re: PlayStation's disc backlash — "I know players love physical media," but what about next-gen Helix plans?
Xbox CEO Asha Sharma recently spoke with the BBC about the next-gen Xbox Helix console, but stopped short of confirming a commitment to disc-based games longer term.
KKR to buy 6% stake in India’s BookMyShow for up to $50 million, source says
By Vibhuti Sharma Aug 19 (Reuters) - Global investment firm KKR will buy a stake of about 6% in Indian ticketing and entertainment platform BookMyShow for $40 million to $50 million, a source told Reuters on Wednesday, as demand for live events soars...
Medical center must pay $500,000 after radiologist, resident both miss hip fracture on X-ray
The case dates to April 11, 2021, when 41-year-old Ruchi Sharma, living in Iowa City at the time, visited the University of Iowa Health Care ER following a head-on car collision.
Fans Try To Decipher The Elder Scrolls VI’s Censored Subtitle
Xbox CEO Asha Sharma just played 'The Elder Scrols VI' and both she and Bethesda are censoring its subtitle with a specific number of letters.
Xbox CEO Asha Sharma's internal playthrough of The Elder Scrolls 6 disrupted by a giant inflatable rat, as Bethesda union protests cuts
The CWA video games union brought a giant inflatable rat as well as red flags marking each laid off employee.
Union members stage massive protest for Xbox boss Asha Sharma
It would be hard to miss the giant inflatable rat on the lawn.
Xbox CEO Asha Sharma Gushes About Elder Scrolls VI, Does Not Seem To Notice Giant Rat On Bethesda Office Lawn
Please clap (instead of talking about layoffs)
Xbox CEO Gets Elder Scrolls 6 Demo, Teases the Subtitle
Xbox CEO Asha Sharma got to see a "live playthrough" of The Elder Scrolls 6, and she posted her reactions on social media afterwards. She also teased – in the vaguest of ways – the subtitle for the upcoming RPG.
When will Rohit Sharma make his TV debut? India star to feature in entertainment show on Sony
With Rohit Sharma set to appear on Sony TV, here's how you can grab his TV debut live without missing a single moment.
A new survey shows the scale of Xbox's fall vs. PlayStation — and the scale of Asha Sharma's opportunity
New data from Statista Research shows how much Xbox has fallen against PlayStation in the U.S., but also the scale of the opportunity.
Confirmed: Xbox 'Platinum' completion achievements are coming "later this year"
Xbox CEO Asha Sharma just confirmed that the team is working on "Platinum"-style achievement completion recognition, slated for later this year.
Xbox's FanFest world tour is still going ahead, for some reason, even after Microsoft fired the guy who created it
"How about those layoffs!" One can only imagine the atmosphere there.
"We will not live on past successes or be trapped by past failures" – Xbox CEO outlines priorities to turn platform around in FY27
Asha Sharma expects growth to return to Xbox by "investing in what players value"
Xbox's Four Priorities Detailed By Asha Sharma After Major 'Reset'
Core, Content, Creation, and Connection
Asha Sharma-appointed Xbox VP of engineering leaves just three months after moving over from Microsoft's CoreAI team
Xbox engineering boss, who only joined the team three months ago, is leaving for an AI startup.
Xbox VP Leaves Just 3 Months After Joining Asha Sharma's Team
Jared Palmer had joined Xbox from Microsoft's CoreAI division
"I was verbally blasted by Pierre." Xbox and Halo Studios' Pierre Hintze has reportedly 'repeatedly' been referred to HR. Is he the right person to lead Halo?
Xbox has a new CEO, Asha Sharma, and one of her stated goals is to boost the Halo franchise. Is Pierre Hintze the right person for the job?
Microsoft defends Asha Sharma, says she is an American CEO and Xbox layoff had nothing to do with H-1B
As Asha Sharm, the CEO of Xbox, came under vicious trolling after the gaming division of Microsoft announced the elimination of 3,200 positions, Microsoft came to her rescue and clarified that it had nothing to do with replacing Americans with foreign workers. Frank X Shaw, the lead for the communications for Microsoft, also addressed the 'Indian-origin' angle of the immigration debate and called Asha an American born, educated CEO from Wisconsin.
Unionized Bethesda Workers Plan Strike Over Xbox Mass Layoffs
Following the recent confirmation that layoffs related to Asha Sharma's Xbox reset have resulted in significant layoffs at ZeniMax-run studios—amounting to 50% of Id Software's workers and 25% of Bethesda's—OneBGS, the CWA-affiliated Bethesda Game Studios Union, has announced that its workers has...
Asha Sharma, the outsider handed the Xbox controls
Elevated to fix Microsoft’s struggling gaming division, she is making tough decisions about its future
Fed appoints task forces led by Marc Andreessen, Asha Sharma
Economists, researchers, and industry insiders like Marc Andreessen and Asha Sharma have joined Fed task forces to revamp economic policies.
Report: Microsoft will make even more of its games exclusive to Xbox — as multiplatform strategy totally fails. What's going on?
Xbox's loathed "Project Latitude" strategy which saw Microsoft support its biggest rival with content is ending, with CEO Asha Sharma doubling down on exclusives.
Microsoft cuts 4,800 jobs as Xbox studios spin off in gaming reset
The Xbox restructuring will involve divestment of four studios, Xbox's new head, Asha Sharma, said in a note to employees.
Xbox CEO Asha Sharma wants the company to "entertain more than a billion people" every day: here's why that's a deeply unrealistic thing to say
The company will have to do so with four less studios under its belt.
No debut, but loud cheers: Belfast crowd shows love for Vaibhav Sooryavanshi
Teenage sensation Vaibhav Sooryavanshi's India debut is still pending, but the focus shifted to Ireland's historic 34-run victory in the first T20I. Despite the loss, Shreyas Iyer vowed a strong comeback. Ireland's debutants impressed, with Jai Moondra and Matt Hollard making immediate impacts, while Abhishek Sharma's quickfire fifty wasn't enough for India.
Meet the ‘extraordinary’ women who donated their hearts to science
Katie James, Kara Terol and Hannah Sharma had heart transplants before turning 35.
Analyst says Xbox CEO Asha Sharma’s Next 100 Days will be about “the job she was Actually Hired to do,” with Mass Layoffs Looming
Xbox chief executive officer Asha Sharma went from being the new face of Team Green, leading the platform into a new era, to being no different from the last in the eyes of players in the blink of an eye. After making Game Pass cheaper, re-centering console hardware and bringing exclusives back, Xbox fans praised her quick action and transparency. Now, however, with multiple studios reportedly being closed and more mass layoffs looming, she and her regime are no different from Spencer's. Industry veteran and analyst Joost van Dreunen calls it "the job she was actually hired to do." Van […]
Community Conversations: Black Business Expo to showcase local black-owned businesses
Dave Hunter spoke with Sharmain Cooper-Richardson about the upcoming Black Business Expo.
Xbox turmoil continues with a studio closure and executive departures
More big changes under Asha Sharma’s leadership.
Report: Microsoft weighing up spinning off Xbox
Company management has reportedly approved a plan by new CEO Asha Sharma to increase spending on Halo, Fallout and The Elder Scrolls to speed up development, to
Xbox Boss Asha Sharma Asked Her Chief Strategy Officer if The Brand Was 'Fixable'
Xbox's new chief strategy officer Matthew Ball says he was asked a direct question about the brand's future by recently-installed CEO Asha Sharma: "Is it fixable?"
Xbox layoffs planned as CEO Asha Sharma orders business reset
The Microsoft gaming unit's accountability margin has fallen to 3%, and revenue declined nearly half a billion dollars over five years
Xbox CEO Openly Floats the Need for Third-Party Exclusives and “Potential M&A” to Win in Hardware, PC, Mobile, and Streaming
Xbox’s CEO says the platform may need third-party exclusives and potential M&A to compete across hardware, PC, mobile, and streaming.
Xbox Exclusives, Showcase Without Blade, Elder Scrolls 6, More From Matt Booty
Xbox leadership shook up its strategy this week with the reveal that "Gears of War: E-Day" and "Clockwork Revolution" would be Xbox exclusives.
Xbox CEO Ties Future Exclusives to Business Health, Signaling a Possible Return to Multiplatform if Sales Slip
Xbox CEO said the business isn't currently healthy, which is why there are 2 exclusives. To do more, the business would have to get healthier
Xbox Boss Says a Mass Audience Can't Afford 'Thousands of Dollars' to Spend on a Next-Gen Console, So Microsoft Must 'Look at New Business Models'
The spiralling cost of new and existing consoles will require "radically different business models" over the coming generation, Xbox boss Asha Sharma has said.
Xbox CEO Asha Sharma teases "radically different business models", hints at potentially cheaper console to arrive this year
Xbox's newly-appointed CEO has hinted at what could be a major shakeup to the console model business that could help it navigate the RAM apocalypse
Xbox CEO outlines strategy to prioritise cost-efficiency and exclusive titles over premium hardware
"We will continue to look at new business models – that's what is needed rather than premium, high-performance consoles," says Asha Sharma
Xbox Getting Creative About Next-Gen Consoles To Deal With Cost
Asha Sharma keeps hinting at a big problem
Xbox Fans Go Wild As Asha Sharma Gives Free Consoles To Everyone At FanFest LA
Watch the reaction here
Xbox Games Showcase 2026 live report - all the news and announcements as Asha Sharma presents for the first time
Will we see The Elder Scrolls 6? Will we see Arkane's game based on Marvel's Blade? What has Microsoft got that will convince us? Find out this evening.
Xbox wants to become “number one gaming company” by 2030
Xbox CEO Asha Sharma has lofty ambitious for the company as she said that she wants to become the number one gaming and entertainment company by 2030. It is unclear whether she is talking about as a…
E-bike safety; lung cancer treatment and prevention; keeping CMA Festival attendees safe; plus other stories with Vanderbilt Health sources
WKRN News 2 interviewed Jeffrey Upperman, MD, FACS, Professor and Chair of the Department of Pediatric Surgery and Surgeon-in-Chief of Monroe Carell Jr. Children’s Hospital at Vanderbilt, about e-bike related injuries following the recent death of a Brentwood High student and a proposal to require safety training before students could ride a bike on a school campus in Williamson County. Fabien Maldonado, MD, MSc,Professor of Medicine and Thoracic Surgery, was on WTVF News Channel 5‘s live studio show, “Openline,” with host Ben Hall, to discuss lung cancer, treatment and prevention. WSMV’s “Today In Nashville” program hosted Vanderbilt LifeFlight paramedic/flight nurse practitioner Tony Smith to talk about safety for the CMA Festival. The New York Times reporter Carl Zimmer interviewed James Crowe, MD, Director of the Vanderbilt Center for Antibody Therapeutics, for a story about the race to find vaccines and treatments as Ebola spreads. The Vanderbilt Health News release about the pilot clinical trial conducted by Vanderbilt Health and Cumberland Pharmaceuticals Inc., that confirms the safety of ifetroban and supports the further development of the drug to prevent cancer metastasis, was picked up by Reuters, Stock Titan,and others. Women We Admire has named Lee Ann Liska, President and Chief Operating Officer, to its list of top women leaders of Nashville for 2026. Radiology Business, Aunt Minnie, Bioengineer, and Imaging Technology News covered the study from Consuelo Wilkins, MD, MSCI, the Mildred Thornton Stahlman Professor in Rural Health and professor of Medicine in the Division of Geriatric Medicine, that found Black and Hispanic people, while known to be far more apt to have dementia, are significantly less apt than other racial and ethnic groups to show Alzheimer’s pathology on brain scans. STAT News interviewed Deva Sharma, MD, Transfusion Medicine & Hematology-Oncology, for a story about more patients requesting unvaccinated blood and what it means for the medical system at large. Yahoo! Health reporter Korin Miller interviewed Gitanjali Srivastava, MD, Director of Obesity Medicine, for a story about how semaglutide and tirzepatide compare. William Schaffner, MD, Professor of Preventive Medicine, was quoted by several news outlets about public health issues, including: NBC News (new COVID vaccinations); Medscape (pneumonia and sepsis); and CNN (protection from contagious viruses). Shelbyville Times-Gazette is repurposing Jessica Pasley’s July 2025 Vanderbilt Health News story on tick-borne illnesses as a front-page story.
Asha Sharma commits to "resetting" Xbox, prioritising exclusivity and addressing AI in new strategy
Xbox CEO outlines plans to become "the number one gaming and entertainment company" amid rising component costs and platform competition
Xbox boss Asha Sharma still can't seem to decide on a stance regarding console exclusivity
The Xbox exclusivity conversation continues, and it doesn't look like much is actually changing.
Xbox Will 'Innovate' To Reduce The Price Of Project Helix, Suggests Asha Sharma
They're working on it as we speak
Xbox CEO doubles down on exclusives, saying they remain central to defining the Xbox platform
Asha Sharma doubles down on exclusives, saying they remain central to defining the Xbox platform even as Xbox expands to more devices and services.
Xbox will "adjust" its promotional materials after fans slam decision to use rival logos in its showcases
Xbox boss Asha Sharma has admitted that including competitor logos in Xbox teasers and showcase presentations is "a miss", confirming this will be "adjusted".
The Xbox Game Pass price cut is working, Asha Sharma reportedly tells staff, but "we will not solve this in one moment or one launch"
"We are building a stronger Xbox," the company's new leader says.
Xbox CEO Asha Sharma warns tough decisions are ahead, raising questions about Helix, Xbox Game Studios, and exclusives
We break down what "tough decisions" could mean for the future of Xbox and gaming at Microsoft.
'We Are Building A Stronger Xbox' - Asha Sharma Updates Employees On Progress In 2026
The Xbox CEO says hard choices are still ahead
Xbox Game Pass Price Cut Is Working, CEO Says
One of the first decisions that Xbox CEO Asha Sharma made after becoming the new boss earlier this year was to cut the price of Xbox Game Pass significantly. In a memo to staff recently, Sharma explained the thinking behind the price cut and talked about the impact it’s making so far, saying it’s helping...
Top 10: CEOs in Media & Entertainment
Business Chief looks at the top 10 CEOs in media and entertainment, including AMC's Kristin Dolan, Xbox’s Asha Sharma and Comcast's Michael Cavanagh
Xbox expands leadership team with major hires
Xbox has added two big names to its leadership team: Matthew Ball and Scott Van Vliet. The new recruits are part of an on-going drive from Xbox CEO Asha Sharma to move faster, build better products, and make more focused business decisions. The Game Business can reveal that Ball is joining as Chief Strategy Officer. He is a popular industry analyst who is responsible for the annual The State of Video Gaming report, which is widely read across the business. His first job will be to strengthen the console side of Xbox, which is facing significant pressures, not least from the rising costs of memory and storage. In an interview with The Game Business earlier in the year, he admitted he was “pretty frightened” by the situation for the console sector. Ball had previously worked as head of strategy and planning for Amazon Studios, and wrote the 2022 international best-seller The Metaverse. He is currently CEO of Epyllion, a venture partner at investment group Makers Fund and senior advisor at KKR & Co. Meanwhile, Scott Van Vliet joins as Chief Technology Officer. He was previously in charge of Azure OpenAI and AI Core infrastructure at Microsoft, and he also led engineering for Microsoft Teams during the COVID 19 pandemic. But he has a games background. He previously worked across games for Amazon, including Alexa, Amazon Game Studios and the Amazon App Store. He directly worked on the Minecraft: Fire TV Edition. Prior to that, he was VP of Digital Play at Mattel, and worked across brands such as Batman, Barbie, Angry Birds, Fruit Ninja and Cut The Rope. His job will be to improve how Xbox builds products so teams can move faster and deliver stronger results. For more breaking stories, sign-up to The Game Business today Subscribe In addition to these new hires, Xbox has promoted Chris Schnakenberg to Corporate Vice President, Partnerships & Business Development. He was previously VP of partnerships and business development, and joined from Activision Blizzard, where he spent 12 years in various strategy, business development and partner relations role. His focus is on third-party games, publishers and developers working with Xbox. The news follows a number of new hires and promotions earlier in the month, including Jason Ronald taking leadership over Xbox’s upcoming Project Helix console. “These changes are about strengthening our foundation by creating more clarity and improving execution,” Sharma said in an email to staff. “As we head toward Showcase and beyond, we’ll continue making the changes needed to position XBOX for the future.” Matthew Ball is speaking with Christopher Dring at The Game Business Live on Monday, June 8. More details on the event can be found here.
Xbox expands leadership team with major hires
Xbox has added two big names to its leadership team: Matthew Ball and Scott Van Vliet. The new recruits are part of an on-going drive from Xbox CEO Asha Sharma to move faster, build better products, and make more focused business decisions. The Game Business can reveal that Ball is joining as Chief Strategy Officer. He is a popular industry analyst who is responsible for the annual The State of Video Gaming report, which is widely read across the business. His first job will be to strengthen the console side of Xbox, which is facing significant pressures, not least from the rising costs of memory and storage. In an interview with The Game Business earlier in the year, he admitted he was “pretty frightened” by the situation for the console sector. Ball had previously worked as head of strategy and planning for Amazon Studios, and wrote the 2022 international best-seller The Metaverse. He is currently CEO of Epyllion, a venture partner at investment group Makers Fund and senior advisor at KKR & Co. Meanwhile, Scott Van Vliet joins as Chief Technology Officer. He was previously in charge of Azure OpenAI and AI Core infrastructure at Microsoft, and he also led engineering for Microsoft Teams during the COVID 19 pandemic. But he has a games background. He previously worked across games for Amazon, including Alexa, Amazon Game Studios and the Amazon App Store. He directly worked on the Minecraft: Fire TV Edition. Prior to that, he was VP of Digital Play at Mattel, and worked across brands such as Batman, Barbie, Angry Birds, Fruit Ninja and Cut The Rope. His job will be to improve how Xbox builds products so teams can move faster and deliver stronger results. For more breaking stories, sign-up to The Game Business today Subscribe In addition to these new hires, Xbox has promoted Chris Schnakenberg to Corporate Vice President, Partnerships & Business Development. He was previously VP of partnerships and business development, and joined from Activision Blizzard, where he spent 12 years in various strategy, business development and partner relations role. His focus is on third-party games, publishers and developers working with Xbox. The news follows a number of new hires and promotions earlier in the month, including Jason Ronald taking leadership over Xbox’s upcoming Project Helix console. “These changes are about strengthening our foundation by creating more clarity and improving execution,” Sharma said in an email to staff. “As we head toward Showcase and beyond, we’ll continue making the changes needed to position XBOX for the future.” Matthew Ball is speaking with Christopher Dring at The Game Business Live on Monday, June 8. More details on the event can be found here.
Hitman on TV! Rohit Sharma gears up for exciting television debut
Cricket star Rohit Sharma is venturing into television. A teaser for his new show has been released. Details about the show's format and title will be announced soon. Sharma is currently playing in IP...
The Material Science Behind A Spacecraft's Impact Armor
Aerospace engineers have to consider numerous factors when designing a spacecraft, but one that comes up more and more often is the need to design against Micro-Meteoroids and Orbital Debris (MMOD). While most designers understand the threat, designing structural solutions capable of withstanding the hypervelocity impacts these undercontrolled pieces of material can cause can take a significant bite out of a mission’s mass budget. A new paper from Binkal Kumar Sharma of the University of Bremen and Harshitha Baskar, an independent researcher, provides a detailed review of cutting-edge options for defending against those deadly particles.
Xbox Needs To 'Sweat Every Detail' In Winning Over 'Frustrated' Players, Says Asha Sharma
She's certainly committed to the cause
Xbox consoles are getting a new boot animation next week
Xbox CEO Asha Sharma has announced that Xbox consoles will receive an updated boot-up animation next week featuring the new Xbox logo.
Xbox announces leadership changes as it stops development of Gaming Copilot for console
"As part of this shift, you'll see us begin to retire features that don’t align with where we're headed," says Asha Sharma
Asha Sharma admits "Xbox needs to move faster", as new CEO begins "winding down Copilot on mobile" and ceases its development on consoles
Xbox's newly-appointed head Asha Sharma is sunsetting the company's Copilot initiative, which was once envisioned as an AI-driven "personal gaming sidekick".