SCROLL NEWS / DISCOVERY
Search headlines
Find the stories shaping the conversation.
Results for " sierra " 88 found 🔀 AI-powered Shuffle
Sign in to save shuffle history.
Can AI solve our mental health access problem?
Last week I asked you what worries you most about AI in health. It was close, but your top answer was “AI giving bad health advice.” Last week’s poll results: You’re in good company. This concern was top of mind at a conference I joined at Stanford last week, where researchers, clinicians, and people who build AI systems spent a day debating trust and safety in health AI. Stepping back, I’m also hearing your emerging concerns about AI’s impact on our well-being generally. I see this as a matter of public health, and we’ll take it in pieces as we learn together. Today we’ll focus on AI chatbots used for therapy for mental health. Early this month, Governor Newsom vetoed Senate Bill 903, California’s most ambitious attempt to regulate AI use for mental health. It’s at the center of active debate, and raises the questions patients, family members, citizens, and voters will face as AI moves deeper into health care. Let’s work through it. What is “AI-based therapy”? It’s really two things: purpose-built mental health apps designed to deliver structured support, and general chatbots like ChatGPT, Claude, and Gemini that people increasingly use for emotional support—even if they weren’t built for it. Spoiler alert: I don’t know whether the shift toward AI therapy is good or bad. The evidence isn’t there yet. But I do know it’s already happening, and I have some ideas about how we can roll it out with safety in mind. The therapy dilemma, in a nutshell Mental health challenges are common, and strain health and well-being across populations. Therapy (interactive dialogue with a trained, empathetic practitioner) helps many people heal. The demand for licensed therapists far exceeds the supply in California, and AI-based therapy can narrow that gap. AI-based therapy remains novel, unproven, and not well tested. Right off the bat, we can see we’re dealing with trade-offs here. Since the main driver of demand for therapy from a robot is lack of access to therapy from a human, we’ll start there. It’s too hard to find and afford a human therapist California is short roughly 55,000 licensed, non-prescribing therapists and counselors, about 40% of what we need. Psychiatrists, who rely on talk therapy as a complement to prescribed medications, are even more scarce. Eight counties have none, and density ranges from 1.7 per 100,000 residents in San Benito County, to 68.1 in Marin County. My wife is a psychiatrist in Marin, and even here access is tight. If it’s hard in the best-supplied county, imagine rural Sierra County, or the San Joaquin Valley. In 2024, more than half of Californians who tried to make a mental health appointment struggled to find a provider who took their insurance, compared with 14% for physical health care. When Senate staff posed as “secret shopper” patients and called 120 mental health providers in Medicare Advantage networks, they landed an appointment less than once for every five tries. Insurers pay behavioral health clinicians about 22% less than medical and surgical clinicians for comparable office visits. On top of that, billing denials and prior authorizations hit hardest at the solo and small practices common in mental health. Psychiatrists opt out of Medicare at the highest rate of any specialty. In many places, a cash practice for therapy fills quickly with patients paying $250 or more an hour, with no insurance paperwork at all. Families who can pay cash find providers more easily. Those who rely on insurance, including Medi-Cal enrollees, older adults, rural residents, and non-English speakers, compete for what’s left. So we can’t pretend the human system works, and we can’t blame people for turning to AI for support when they’re in distress. AI is filling the gap It’s estimated that roughly a quarter of AI users use it for mental health support. If you have internet, it’s available 24/7, it’s cheap, and it speaks your language. Uninsured adults are about twice as likely as insured adults to do it (30% vs. 14%). It feels anonymous in ways that may enable people to ask things they’re unsure or embarrassed about. The largely hidden, personal use makes it hard to study whether it’s actually helping people with their mental health issues, but researchers are trying. Does AI therapy work? A 2026 analysis of nearly 40 randomized trials found chatbots showed a real but small reduction in depression symptoms. But most of these trials were compared to an alternative of no therapy, not a human therapist. So the benefit of AI therapy is probably real, but modest, and mostly untested against the alternative of human contact. We need more studies. Serious concerns OpenAI’s own estimate is that more than a million ChatGPT users each week show signs of suicidal planning or intent. These are high stakes encounters, and AI doesn’t always get it right. That’s partly because a chatbot can sound like a therapist, but it has no license, no duty of care, and it’s not clear who to hold accountable when it gets things wrong. AI is also designed to help users in whatever task they’re seeking to accomplish. People may feel like they’re getting therapy, but they’re mainly getting a convincing conversation. It’s easy for an AI companion to wander into gray areas, like playing along with “creative writing” that may be about the user’s own suicidal intent. Courts are driving safety conversations A wave of lawsuits have been filed on behalf of families claiming that chatbots pushed people they loved toward self-harm, including teens who died by suicide. The first settlements came this year. OpenAI is headquartered in San Francisco, and dozens of cases alleging that ChatGPT drove users to suicide or self-harm are now before a San Francisco judge. Character.ai has filed for bankruptcy after several states brought lawsuits accusing the chatbot of pushing dangerous content to kids. But the technology seems to be improving. Last month, an independent evaluation found that newer AI models “almost never endorse suicide.” That’s progress, but our societal appetite for even one preventable death is very low. So how do we move forward? Finding a middle ground Earlier this month the governor vetoed Senate Bill 903, a bill designed to place guardrails on the use of AI for therapy. The bill would have prohibited any AI-based platform from being advertised as psychotherapy, and would have required a licensed professional to review and approve each encounter where AI was used to support therapeutic decisions. Newsom called it overly broad, since even routine screening questions would have needed clinician sign-off. Knowing we’re already short on mental health providers, requiring human review of AI encounters may not relieve our access problems. Still, the answer isn’t no oversight. Here’s one feasible short term solution. Rather than reviewing each encounter, a licensed clinician can design the guardrails: what counts as a crisis, what triggers an immediate handoff to a human, and what gets sampled for audit each month. The AI runs inside that structure. Conversations get checked, failures get reported, and a real clinician owns the framework. Medicine already has models to learn from. The FDA process for rolling out newly approved medications is an example. After a product reaches patients, we keep watching for adverse events. Patient-facing AI needs the same “digital pharmacovigilance”: systematic tracking of harms, near misses, and the types of groups that get hurt and why. It’s also critical that users know that they can reach a human if they’re in crisis. Most chatbots now include messages like these: Bottom line The rush to use unproven AI tools for mental health support is mostly a workaround, a sign of a health system people can’t get into. We need better access to proven care from licensed clinicians. That takes reimbursement that makes accepting insurance viable, and a bigger workforce. But, built and tested well, AI could be part of the answer. It could be the 2 a.m. check-in when no one else is awake, or a way for patients to practice skills their therapist taught them. It could be the first step to get someone the right level of care, and take paperwork off clinicians’ plates so they spend more time with patients. None of this is simple. The SB 903 veto doesn’t end the debate, and the legislature will be back. In the meantime, those of us using these tools need to stay informed, ask hard questions, and hold the companies building them accountable. I’ll try to do my part, and we’ll keep learning together. Love,Matt P.S. If you or someone you know is struggling with mental health challenges, emotional distress, substance use problems, or just needs to talk, call or text 988- you’ll reach a real person— or chat at 988lifeline.org 24/7. Dr. Matt Willis is the author of Your Local Epidemiologist in California. A California native, he’s served as a primary care physician, CDC epidemiologist, and public health officer for Marin County, where he guided the pandemic response. He lives in Marin with his family and their dogs, Teddy and Ramona. Thank you Cynthia He, MD, PhD, and Parnika Saxena, MD, for their guidance in preparing this article. Cynthia works in an outpatient mental health clinic, treating patients who have Medi-Cal or, sometimes, no insurance. Parnika works in an inpatient psychiatric unit, treating patients with public or private insurance or self-pay ability. All opinions are their own and do not represent their employers.
How Hemp-THC businesses are bracing for a near total ban
Follow us to Tennessee where hemp farmers are already pivoting in the face of a state ban and soon, a looming federal ban on basically all THC-derived hemp products. Will Congress step in to save this $28 billion industry? Fact checking by Sierra Juarez.Your Next Listen — How would-be weed merchants hit a ‘grass ceiling’ Connect with The Indicator — Sign up for The Indicator’s weekly newsletter! — Buy the Planet Money book — Find our socials, YouTube and more! — For sponsor-free episodes, subscribe to NPR+ Support public media with NPR+ and enjoy perks for over 25 podcasts like this one. This show’s perks include sponsor-free listening. Learn more at plus.npr.org.
When music becomes eternal: InConcert Sierra’s 80th anniversary begins
There are sounds that are beautiful. And then there are sounds that seem to reach somewhere beyond words—sounds that quiet the mind, stir the heart and leave you changed, even
Personnel note: Sierra Club Florida taps Cris Costello as State Campaign Director
Sierra Club Florida is elevating Cris Costello to State Campaign Director. Costello has been on Sierra Club’s roster since 2007 and most recently served
Nature center hosts art show, rangeland science talk
Feather River Land Trust announces two events during October at its Sierra Valley Preserve Nature Center. "The Full Chase of Beauty," an art show with
U.S. Forging a Healthier Oceania Through Trump Administration's America First Global Health Strategy Through Bilateral Health Memorandum of Understanding with Papua New Guinea - U.S. Embassy & Consulates in China
United States Forging a Healthier Oceania Through Trump Administration’s America First Global Health Strategy Through Bilateral Health Memorandum of Understanding with Papua New Guinea Press Statement Thomas “Tommy” Pigott, Principal Deputy Spokesperson April 23, 2026 Yesterday the United States and Papua New Guinea signed a five-year bilateral Memorandum of Understanding (MOU) through the Trump Administration’s America First Global Health Strategy. The landmark health MOU focuses on effectively addressing emerging infectious diseases and ongoing outbreaks, building and maintaining surge-response capacities, and enabling Papua New Guinea’s government to independently manage new health threats before they spread internationally. Working with Congress, the United States intends to provide $15 million through December 2030 through the jointly decided health MOU, building on decades of progress in reducing HIV infections and transmissions in Papua New Guinea. The government of Papua New Guinea intends to allocate up to $3 million to disease control programs and strengthen health systems at the national and provincial levels. Up to $5 million under the health MOU will directly support global health security funding, advancing our shared commitment to health security in the region. Through the signing of this $18 million MOU, we are bolstering infectious disease prevention and response by leveraging cost-effective, nationally-driven approaches, with the goal of increasing Papua New Guinea’s health system self-sufficiency. America First Global Health Strategy Memoranda of Understanding (MOUs) signed so far represent more than $20.6 billion in new health funding, including more than $12.8 billion in U.S. assistance alongside $7.8 billion in co-investment from recipient countries, building on decades of progress fighting HIV/AIDS, malaria, tuberculosis, and other infectious diseases around the world. As of April 22, the State Department has signed 32 bilateral global health MOUs with Angola, Bolivia, Botswana, Burkina Faso, Burundi, Cambodia, Cameroon, Côte d’Ivoire, the Democratic Republic of the Congo, the Dominican Republic, El Salvador, Eswatini, Ethiopia, Guatemala, Guinea, Honduras, Kenya, Lesotho, Liberia, Madagascar, Malawi, Mozambique, Niger, Nigeria, Panama, Papua New Guinea, the Philippines, Rwanda, Senegal, Sierra Leone, Tajikistan, and Uganda.
Raducanu beaten in French Open first round
Emma Raducanu's French Open campaign comes to an early end as she suffers a frustrating first-round defeat by Argentina's Solana Sierra.
Scientists seek new ways to protect Sierra Nevada meadows
Sierra Nevada meadows may cover a relatively small portion of the landscape, but scientists say they play an important role in supporting wildlife, storing water and maintaining biodiversity. Researchers and conservationists recently gathered at the...
Your Weekly Michigan Political Brief
Democratic U.S. Senate nominee Abdul El-Sayed has been endorsed by the Michigan Chapter of the Sierra Club, the Michigan Farmers Union and Detroit City Council President James E. Tate Jr. Republican Michael Bouchard Jr. was endorsed by the Southeastern Michigan Association of Chiefs of Police in his run for the 10th Congressional District. The American Federation […]
Which questions do peatland scientists want to answer most?
Peatlands are poorly understood worldwide, but have important implications for the climate. Nevada scientists compiled the 50 most urgent questions about them.
Brookdale Community College Announces Spring 2026 Science Mondays Lecture Series
Brookdale Community College invites the community to its Spring 2026 Science Mondays lecture series, a long-standing program presented in collaboration with the Jersey Shore Chapter of the New Jersey Sierra Club. The series brings leading
Local business raising money for families who lost everything in mobile home fire in Sparks
It happened at the Sierra Sol mobile home park
How college sports juiced Olympic development : The Indicator from Planet Money
How did the U.S. become the Olympic powerhouse it is today? Cold War competition. The Soviet Union sponsored their athletes. But America wanted its athletes to pull themselves up by their bootstraps. It birthed an unexpected accelerator of Olympic development: College football. Stay with us now.On today’s show, how college football became an Olympic development engine. And how that engine might not be running as smoothly as it once did.Related episodes: Why the Olympics cost so muchYou can't spell Olympics without IPA huge EU-India deal, Heated Rivalry, and a hefty $200k to OlympiansWhy Host The Olympics?The monetization of college sportsFor sponsor-free episodes of The Indicator from Planet Money, subscribe to Planet Money+ via Apple Podcasts or at plus.npr.org. Fact-checking by Sierra Juarez. Music by Drop Electric. Find us: TikTok, Instagram, Facebook, Newsletter.
Vicariously hike the Appalachian in the gorgeous A Trail Tale
A Trail Tale is an interactive trail journal inspired by Sierra point-and-click adventures and Oregon Trail.
Businesses on Maryland Parkway say road construction is hurting revenue
Business owners near Maryland Parkway and Sierra Vista say ongoing road construction is decimating their revenue.
Prep sports roundup: Harvard-Westlake pulls out 5-4 baseball win over Sierra Canyon
Ira Rootman delivers two-run single in the seventh to rally Harvard-Westlake in Mission League opener.
Caltech Students Host Science Olympiad State Tournament
Caltech students' years of leadership and service with Science Olympiad inspire younger people to explore science and engineering
Computer Science Student Deemed 'Wizard' For Tech Acumen
Seeing Sierra Brandt’s technological magic in action led Erica Cullwell to dub Brandt “The Departmental Wizard” of the Career Center.Not only was Brandt able to resolve a longstanding problem for the Career Center, her solution will support Cal State San Marcos students for years to come.Brandt is a transfer student from MiraCosta Communit...
Can Sacramento become a chip hub? Business leaders make their pitch to global firms
Energized by a string of investments by semiconductor firms, business officials pitched the region to a group of global companies.
Ecophysiologist shares science behind hibernation Jan. 24
Feather River Land Trust announces that ecophysiologist Hannah Carey will present a talk on hibernation Saturday, Jan. 24, at the Sierra Valley Nature
Overwatch’s New Hero Is So Strong She Kills Most Heroes Instantly
Sierra’s ultimate probably needs a nerf or two
'August: Osage County' is an A+ production
Although no play or production is perfect, “August: Osage County” and Sierra Theatre Company’s production of it come pretty darn close. The playwriting—concept, characters and dialogue—is dynamic, smart and real
Meta joins with group of companies to tame ‘chaos’ of doing business with AI bots
Meta and OpenAI Chairman Bret Taylor’s startup Sierra are building a set of tech standards to make it easier to do business with AI bots.
Monterrey Amid Mountains
Mexico’s second-largest metropolitan area borders on folded rock layers of the Sierra Madre Oriental.
Truckee Chamber celebrates business community at the ‘Top of the Town’
TRUCKEE, Calif. – The Truckee Chamber of Commerce presented six awards at Top of the Town, its 73rd Annual Awards Celebration on Friday, September 25 at Alder Creek Adventure Center in Tahoe Donner. “The Top of...
Comings & Goings
Here’s a look at recent changes in the business landscape in the Sioux Falls area.
Is gambling the reason we have pro sports?
To hear author David Bockino tell it, gambling has always been a key ingredient of pro sports in the U.S.—it’s as American as apple pie. Bockino is the author of the new book Over/Under: An Unexpected History of Sports Betting. So what gave rise to this new wave of sports gambling? And what are we risking placing so many bets on games? Fact checking by Sierra Juarez. Your Next Listen — Prediction markets are threatening national security. Who’s gonna fix it? Connect with The Indicator — Sign up for The Indicator’s brand new newsletter — Buy the Planet Money book — Find our socials, YouTube and more! — For sponsor-free episodes, subscribe to NPR+
Girls basketball: Ontario Christian to play Sage Hill in regional final
Ontario Christian defeats Etiwanda and will play Sage Hill in the girls' basketball Southern California regional final after the Lightning's upset over Sierra Canyon.
Sierra Link joins Essentia Health-South University Clinic to practice pulmonology
Sierra Link, an advanced practice registered nurse and certified nurse practitioner, is excited to join the Essentia Health-South University Clinic to practice pulmonology.
'The most expensive choice on the ballot': Sierra Club opposes 'devastating' Amendment 3
The proposal could take away money needed to deal with climate change.
Sierra Canyon’s (CA) Jaxson Davis voted USA TODAY Sports Super 25 Playmaker of the Week
Jaxoson Davis was all over the field in Sierra Canyon's win over Chaminade. That earned him Super 25 Playmaker of the Week honors.
Overwatch's Next Season Looks Dope Except For One Thing
Season 2 adds Sierra to the roster, but also gives some spotlight to Soldier: 76
Science, music, and stream bugs: Sierra Streams celebrates 30 years at Pioneer Park
Sierra Streams Institute will celebrate its 30th anniversary with a free community event on Saturday, May 16 from 1 to 5 p.m. at Pioneer Park in Nevada City, bringing together
The Times' final top 25 high school boys' basketball rankings
Sierra Canyon, the state Open Division champion, finishes No. 1 in The Times' final 2025-26 high school boys' basketball rankings.
Advancing the America First Global Health Strategy Through Landmark Bilateral Global Health MOUs - United States Department of State
On December 22 and 23, the United States signed four additional new, landmark global health Memorandums of Understanding (MOUs) with Madagascar, Sierra Leone, Botswana, and Ethiopia, reinforcing U.S. leadership that delivers measurable results for the American people and puts America First by directly countering global infectious disease threats and reducing foreign dependence on U.S. taxpayers. […]
Sierra Commons Opens Fall Business Ignitor Course at Sierra College
Sierra Commons launches its fall Business Ignitor Course at Sierra College on Sept. 8, for aspiring entrepreneurs.
Entertainment this week: Skate the Lake, Bee Gees Tribute and more
Thursday, July 30 History Talk Photography of Nome’s Gold Rush from 1900 to1905 – 4:30-6 p.m., Gatekeeper’s Museum, 130 W Lake Blvd. On the heels of the Sierra Nevada and Yukon Gold Rushes, the beaches...
Official | Auxerre loan Francisco Sierralta to Gliwice
Bought for just under €2m last summer, Francisco Sierralta (29) has joined Polish club Gliwice on a season-long loan. The deal, concluded on Wednesday, ahead of the closure of the transfer window in...
Snow surge in Sierra sparks business boom in Truckee
Along Donner Pass Road, the Wagon Train diner—an area staple established in the 1940s—has been especially busy as residents and visitors look for a warm place to gather.
Could politics put your city's funding at risk?
The Trump administration recently admitted to pulling grants over politics. This practice could become more common. How do cities use grant money, and how will they adapt?Fact checking by Sierra Juarez.Your Next Listen — How far can philanthropy go to fill government gaps?Connect with The Indicator — Sign up for The Indicator’s weekly newsletter! — Buy the Planet Money book — Find our socials, YouTube and more! — For sponsor-free episodes, subscribe to NPR+ Support public media with NPR+ and enjoy perks for over 25 podcasts like this one. This show’s perks include sponsor-free listening. Learn more at plus.npr.org.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. [1] Intel, “Intel Tech Tour 2025 Panther Lake recap,” Doc. 866361, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/866361/ITT_2025_Panther_Lake_Recap1.pdf [2] Intel, “Core Ultra processors Series 3 datasheet, volume 1,” Doc. 872188-001, Jan. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/872188/872188-001.pdf [3] N. Horiguchi and E. Beyne, “Backside power delivery: How to power chips from the backside,” imec Reading Room, Nov. 25, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/how-power-chips-backside [4] W. Hafez et al., “Intel PowerVia technology: Backside power delivery for high density and high-performance computing,” in Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2, doi: 10.23919/vlsitechnologyandcir57934.2023.10185208. [5] K. Fischer et al., “Intel 18A platform technology featuring RibbonFET (GAA) and PowerVia for advanced high-performance computing,” in Proc. Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2025, pp. 1–3, doi: 10.23919/vlsitechnologyandcir65189.2025.11075006. [6] K.-F. Cheng, C.-L. Teng, H.-Y. Huang, and H.-C. Chen, “Metal oxide composite as etch stop layer,” U.S. Patent 12 176 247 B2, Dec. 24, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12176247B2/en [7] S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS J. Solid State Sci. Technol., vol. 4, no. 1, pp. N3029–N3047, 2015, doi: 10.1149/2.0051501jss. [8] A. V. Mule’, D. J. Towner, D. Seghete, C. R. Ryder, and A. A. Gonzalez, “Multi-layer etch stop layers for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20220102343 A1, Mar. 31, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20220102343A1/en [9] C.-C. Wang and J. H. Wang, “Interconnect structure with dielectric cap layer and etch stop layer stack,” U.S. Patent Appl. 20230253247 A1, Aug. 10, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20230253247A1/en [10] Y. J. Wu, K.-F. Cheng, C.-C. Lee, H.-K. Chang, and H.-Y. Huang, “Etch stop layer for interconnect structures,” U.S. Patent Appl. 20240332070 A1, Oct. 3, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240332070A1/en [11] M. G. Rainville, N. Shankar, K. S. Reddy, and D. M. Hausmann, “Deposition of aluminum oxide etch stop layers,” U.S. Patent Appl. 20180197770 A1, Jul. 12, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20180197770 [12] J. S. Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240112951A1/en [16] Applied Materials, “Applied Materials unveils chip wiring innovations for more energy-efficient computing,” Applied Materials Investor Relations, Jul. 8, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy [17] Samsung, “Samsung showcases AI-era vision and latest foundry technologies at SFF 2024,” Samsung Semiconductor, Jun. 13, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/ [18] C. W. Yeung et al., “Channel geometry impact and narrow sheet effect of stacked nanosheet,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2018, pp. 28.6.1–28.6.4, doi: 10.1109/iedm.2018.8614608. [19] S. Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
Crim, Nowak and Sierra Named Among St. Louis’s Top Business Leaders
STL Partnership trio makes St. Louis Magazine’s 2026 Business 500 list Rodney Crim, CEO and president of St. Louis Economic Development Partnership, Tim Nowak, executive director of World Trade Center…
Girls' basketball coach of the year: Alicia Komaki of Sierra Canyon
She came up with a winning formula to defeat Etiwanda and No. 1 Ontario Christian in the Southern Section Open Division championship.
Is winter warmer in Sacramento than it was 50 years ago? What the science says
Climate change has warmed Sacramento’s winters, shrinking Sierra snowpack and threatening water supplies statewide.
Entertainment this week: Handel’s Messiah, Tahoe Philharmonic, Curtis Woodman’s Wayfinder Tour and more!
Friday, December 19 Friday Night Music at Cottonwood Restaurant – 6:30-8:30 p.m., Cottonwood Restaurant & Bar, 10142 Rue Hilltop. Join us each Friday at Cottonwood Restaurant & Bar in Truckee for a fun night of...
How Pixar Got the Science Right in Hoppers
Meet the researcher who informed the writers about beaver behavior and threats to their habitat
Happy Birthday John McDonald
And Jim Acker, Paul Spoljaric, Moises Sierra and Kevin Millar
Ernest Bai Koroma returns home: Who be di former Sierra Leone former president wey dey Nigeria for two years and why e bin dey on exile?
More dan two years afta e run comot for Sierra Leone sake of accuse say e plan coup, Ernest Bai Koroma don return to im kontri following diplomatic intervention.
A look back at the year in local art and entertainment
From stellar concerts to funny films and sad farewells, these stories resonated in 2025.
Local business feels the impact of diesel prices
Sierra Feed received 100% of its inventory through diesel powered transportation, they say the price of diesel has doubled and they have to get tough and creative to continue business.
Clinica Sierra Vista opens new health center on Brimhall Road
Clinica Sierra Vista opened a new health center in Bakersfield on Thursday, marked by a ribbon-cutting ceremony held in the afternoon in northwest Bakersfield.
No healthcare premiums? In this economy?! Here's how.
It turns out healthcare in America CAN be cheaper. If your employer wants it to be. Today on the show, we speak with a Canadian-founded startup that has unusually generous benefits for their employees. Come see Planet Money live on stage in April! 12 cities. Details and tix here: https://tix.to/pm-book-tour. Related episodes: Health insurance premiums are going up next year — unless you work at these companiesHealth care costs are soaring. Blame insurers, drug companies — and your employerThe hidden costs of healthcare churnFor sponsor-free episodes of The Indicator from Planet Money, subscribe to Planet Money+ via Apple Podcasts or at plus.npr.org. Fact-checking by Sierra Juarez. Music by Drop Electric. Find us: TikTok, Instagram, Facebook, Newsletter.
Partnership expands access to kids' mental health services
First 5 Plumas announces it is working with Lost Sierra Family Integration Center to provide easier access to infant and early childhood mental health and
Southland top 20 high school girls' basketball rankings
Ontario Christian and Sierra Canyon remain No. 1 and No. 2 in high school girls' basketball rankings
Entertainment this week: Once Upon A One More Time, DJ Bowie Jane and more!
Friday, March 20 Friday Night Music at Cottonwood Restaurant – 6:30-8:30 p.m., Cottonwood Restaurant & Bar, 10142 Rue Hilltop. Join us each Friday at Cottonwood Restaurant & Bar in Truckee for a fun night of...
Ontario Christian, Sierra Canyon, JSerra top Southland girls' basketball rankings
Unbeaten Ontario Christian is ranked No. 1 in girls basketball rankings
Build a Forest-Related Business Fast: Free Sierra Commons Training in Auburn This July
Nevada City, Calif. — As demand grows for skilled forest management businesses across California, a Northern California nonprofit is helping entrepreneurs turn that opportunity into a livelihood. Sierra Commons, in partnership with the Sierra Business Council, will host a Forest Entrepreneurship Bootcamp July 18–19 in the Community Room at BriarPatch Co-op’s Auburn location. The two-day […]
How did political campaigns get so expensive?
The 2026 midterm elections are fast approaching, and it’s gearing up to be the most expensive election in American history. So how did we get here, where every election feels more expensive than the last? Today on the show, we’re exploring what’s causing the flood of money into our politics. Fact checking by Sierra Juarez.Your Next Listen –Bad economics, smart politics –Over 2,000 episodes in our archive on the NPR AppConnect with The Indicator from Planet Money–The Indicator newsletter — a weekly roundup of news, ideas and staff picks. –Instagram, TikTok and YouTube –Find the Planet Money book –Find the Planet Money game, Sell Me A Sasquatch, and other merch at the NPR Shop!Support public media by subscribing to NPR+ and enjoy perks for over 25 podcasts like this one. This show’s perks include sponsor-free listening. Learn more at plus.npr.org.
Dignity Health Sierra Nevada Memorial Hospital Lights Up Pink in Honor of Breast Cancer Awareness Month
Sierra Nevada Memorial Hospital glows pink for Breast Cancer Awareness Month and hosts Moonlight Mammograms on Oct 8, offering relaxed screenings for women over 40.
Unsecured Business Property Tax Bills to Be Mailed in July
Nevada County Treasurer-Tax Collector Michelle Bodley and Assessor Rolf Kleinhans remind local business owners that annual Unsecured Business Property Tax bills will be mailed in July, with payments due by August 31. Businesses are encouraged...
Kudos to Cheer Club, College of Business faculty, Cybersecurity team and more
Becky Cottrell, Ph.D., Department of Social Work, and Bridget Arend, Ph.D., School of Education Becky Cottrell from the Department of Social Work and Bridget Arend, Ph.D., from the School of Education co-authored an article recently published in an international journal. Read the article. Biff Baker, Ph.D., College of Business Biff Baker, Ph.D., received a Best in Track award from the Society for Advancement of Management for research examining bureaucratic inefficiencies within Section 8 subsidized housing programs. The study focuses on how administrative delays and communication breakdowns can create housing instability for families and discourage landlord participation. It also offers recommendations to improve accountability and trust in public housing systems. Brendan Fry, Ph.D., Department of Mathematics and Statistics Brendan Fry, Ph.D., professor in the Department of Mathematics and Statistics, co-authored the article “Modeling the Impact of Venous Collapsibility on Retinal Oxygenation,” published in the Journal of Theoretical Biology. The interdisciplinary research brought together scholars from the University of Delaware, Indiana University Indianapolis, McGill University and the Icahn School of Medicine at Mount Sinai Hospital. Access the article. Bridget Arend, Ph.D., School of Education Bridget Arend, Ph.D., professor in the School of Education, co-published the book “Facilitating Seven Ways of Learning: A Resource for More Purposeful, Effective, and Enjoyable College Teaching, Second Edition” with James R. Davis. The book explores practical approaches to improving college teaching and student learning experiences. Buy the book. College of Business Faculty At the 2026 Western Decision Sciences Institute international conference, Sally Baalbaki-Yassine, Ph.D., Debora Gilliard, Ph.D., and David Lynn Hoffman, Ph.D., from the College of Business received the Best Case Study Paper Award for “Oreo: A Global Success Story in Brand Evolution and Market Leadership.” Lisa McVicker, Ph.D., and Apryl Brodersen, Ph.D., also had their paper, “Electronic Performance Monitoring: Employer Panacea or Legal Quagmire?” accepted for publication in the Journal of Business Leadership. Community Engagement Exchange Program Metropolitan State University of Denver was selected to host international Fellow Aleja Henao Espitia of Bogotá, Colombia through the Community Engagement Exchange program funded by the U.S. Department of State. View Espitia's LinkedIn profile. David Varel, Ph.D., College of Letters, Arts and Sciences MSU Denver historian David Varel, Ph.D., has been awarded a 2026 ACLS Fellowship by the American Council of Learned Societies. The fellowship program supports outstanding scholarship in the humanities and social sciences, and selected just 63 scholars from more than 2,000 applicants this year. Varel’s project, “The Black Chicago School: Academic Activism in the Age of American Apartheid,” explores the work of Black scholars who challenged scientific racism, built alternative institutions and helped lay the foundation for the modern civil rights movement. The fellowship provides up to $60,000 to support full-time research and writing. Learn more about the fellowship. MSU Denver Office of Financial Aid Team Several MSU Denver employees were recognized for leadership and service during the Colorado Association of Financial Aid Administrators (CAFAA) conference held in May in Crested Butte. Don Holtzen, interim associate director of systems, chaired the conference and was recognized for his service as CAFAA conference chair and technology chair during the 2025-26 term. Holtzen also received the Postsecondary Institution Professional of the Year award, which recognizes financial-aid professionals who have made significant contributions to their institutions and to CAFAA. Tori Pacheco, associate director of Student Services, helped design décor and facilitate the conference and was recognized for her service as CAFAA secretary during the 2025-26 term. Destiny Candelaria, call center coordinator, served on the conference planning committee and presented on One Stops during the event. Michael Nguyen, executive director of Financial Aid and Scholarships, assisted as a CAFAA board member and was recognized for serving as president-elect during the 2025-26 term. Richard Balbag, program assistant I, received the Distinguished Support Staff Member of the Year award, honoring staff members who have made exceptional contributions to their financial-aid offices. Military Friendly Recognition Military Friendly has awarded MSU Denver Gold Status as a military-friendly university and ranked the University No. 7 nationally for military spouses. The recognition reflects MSU Denver’s strong support systems for veterans and military spouses, including transfer credit assistance and retention-focused resources. As of 2026, 1,050 military-connected students are enrolled at the University, advancing institutional priorities around serving veterans and supporting student retention. MSU Denver Cheer Club The MSU Denver Cheer Club earned third place in the 4-Year College Small Coed Intermediate division at the USA Spirit Nationals. Celebrate the win on Instagram. MSU Denver Cybersecurity Team An MSU Denver cybersecurity team earned first place in the Strategist category at the 2026 CYBER RECon National Competition hosted at Fort Meade, Maryland, by U.S. Cyber Command. Led by Jeffrey London, Ph.D., and undergraduate student Matthew Bopp, the team competed against universities and law schools nationwide with its 30-page legal analysis on cybersecurity and free speech titled “Freedom of Speech and MDM: Misinformation, Disinformation, and Malinformation.” The paper also earned Bopp a personal invitation to apply to the University of Maryland School of Law. MSU Denver Debate Team MSU Denver Debate won the 2026 Sierra Sustainability Summit hosted at Yosemite National Park in April. Students Kat Conte and Simon Bernhard bested teams from George Washington University, Gallaudet University, Cal Poly San Luis Obispo, the University of San Francisco and Tennessee Tech in the modified present-and-defend style competition. Their proposal recommended adapting Colorado’s Keep Colorado Wild Pass model to support California state parks facing budget constraints. Learn about the summit. MSU Denver Women’s Golf MSU Denver Women’s Golf was represented on the national stage this month as junior Neige Dunn competed as an individual at the NCAA West Regional. She became the first Roadrunner in 10 years to qualify for NCAA Regionals as an individual. Get the details.
Trump administration foreign aid cuts are having an impact on maternal health in Sierra Leone
Sierra Leone had reduced its maternal mortality by nearly 80 percent since 2000. That process is now in danger as the country grapples with the lack of international funding including from the United States, which cut aid in 2025. NBC News’ Zinhle Essamuah in partnership with the non-profit newsroom the Fuller Project show us how doctors in the ground are trying to save lives as resources dwindle.
US signs health agreements with African nations, warns against nonperformance
The U.S. signed four new global health memorandums of understanding (MOUs) with Madagascar, Sierra Leone, Botswana, and Ethiopia, which total nearly $2.3 billion in funding, the State Department said on Tuesday.
Pierce Thompson delivers key baskets to send Harvard-Westlake to regional final
Harvard-Westlake defeats St. Joseph 56-52 to earn rematch against Sierra Canyon in Open Division regional final
Brookdale, Sierra Club Present Free Science Monday Lectures on Stormwater and Endangered Species
Brookdale Community College, in collaboration with the Sierra Club of the Jersey Shore, will present two free Science Monday programs this fall examining environmental issues affecting New Jersey, including stormwater management and the conservation of
TC Business Council Leaders Hear Update From Waste Management
The monthly luncheon of the Tuolumne County Business Council featured an overview of the operations of CAL Sierra Waste Management, one of the newest members to recently join the business group.
Nevada County and Sierra Business Council’s SBDC to Host Free Capital Summit
On Thursday, Aug. 27 at 1 p.m., the Sierra SBDC at Sierra Business Council and Nevada County are hosting a free Capital Summit at the LOVE Building (660 Minnie St., Grass Valley) in partnership with b
Your Weekly Michigan Political Brief
The Detroit Free Press endorsed Democratic U.S. Senate nominee Abdul El-Sayed. He also received endorsements this week from Sierra Club Michigan and the Michigan Laborers’ International Union of North America, or LiUNA. Republican U.S. Senate nominee Mike Rogers was endorsed by the Michigan Corn Growers Association. The Michigan Professional Firefighters Union and National Security Leaders […]
Isha Johansen on the promise and politics of football
The first female president of the Sierra Leone Football Association discusses her new memoir, corruption in the game, and rebuilding through sport.
San Diego County issues health warning over recalled cheese
Officials issued a warning this weekend urging residents not to eat Northern California-based Sierra Nevada Graziers raw milk cheese.
In Arizona, an Electric Utility Holds an Election, Open Only to Property Owners
Turning Point is involved, as is the Sierra Club. But voting rules that seem to echo feudalism exclude renters, favor large landowners and limit who can influence a Phoenix utility board.
Sexual And Reproductive Health Is ‘On The Frontline’ Of Anti-Science Attacks
The defenders of sexual and reproductive health and rights are on the frontline of the “heightened hostility to science, fact, and truth, directly facing the
4 more African nations secure $2.3bn US health funding under America First strategy
The United States has signed four new Global Health Cooperation Memorandums of Understanding (MOUs) with Ethiopia, Botswana, Sierra Leone and Madagascar, marking a major expansion of Washington’s health engagement in Africa under President Donald Trump’s America First Global Health Strategy
Science, Music, and Stream Bugs: Sierra Streams Celebrates 30 Years at Pioneer Park on May 16
NEVADA CITY, CA — Sierra Streams Institute will celebrate its 30th anniversary with a free community event on Saturday, May 16 from 1:00 to 5:00 PM at Pioneer Park in Nevada City, bringing together art, music, and hands-on science to highlight three decades of watershed research, restoration, and education across the Sierra Nevada. The Sierra […]
Sexual And Reproductive Health Is ‘On The Frontline’ Of Anti-Science Attacks
The defenders of sexual and reproductive health and rights are on the frontline of the “heightened hostility to science, fact, and truth, directly facing the
Dignity Health Sierra Nevada Memorial Hospital Achieves 6th Consecutive Hospital ‘A’ Safety Grade in Patient Safety
GRASS VALLEY, Calif. MAY 9, 2026 – Dignity Health Sierra Nevada Memorial Hospital (SNMH), a member of CommonSpirit, earned an “A” Hospital Safety Grade for the sixth consecutive grading round by The Leapfrog Group, an independent national nonprofit watchdog focused on patient safety. This recent award continues the Hospital’s “Straight A” designation, defined as hospitals […]
How to watch Sierra Canyon vs Loyola High School football
You can watch Sierra Canyon football all season long with NFHS Network, including this week’s game against Loyola High School.
When Indigenous Knowledge and Climate Science Meet, Good Things Happen
Tribal leaders and climate coordinators are working together to protect lands and waterways
Nevada County & Sierra Business Council’s SBDC to Host Free Capital Summit
On Thursday, Aug. 27 at 1 p.m., the Sierra SBDC at Sierra Business Council and Nevada County are hosting a free Capital Summit at the LOVE Building (660 Minnie St., Grass Valley) in partnership with b
In Sierra Leone, a New Maternal Hospital Aims to be the Blueprint
The country has one of the highest maternal mortality rates in the world. Isata Dumbuya, a nurse and midwife, has made it her mission to change that.
JSerra looks to repeat as Southern Section flag football champions
The Lions went undefeated in 2025, but former champion Orange Lutheran and Sierra Canyon, with talented transfers, will be among formidable challengers.
MLB legend uses late teammate's story to spread awareness on heart health, high cholesterol
Albert Pujols teamed up with Sierra Kile to honor late St. Louis Cardinals pitcher Darryl Kile's legacy and spread awareness about high cholesterol risks.
Open for Business: Osteria Sierra, Tahoe Provisions inside Hyatt Regency Lake Tahoe
Osteria Sierra offers a modern take on Italian cuisine.
Sierra Canyon basketball teams to play in regional double-header
The Sierra Canyon boys' and girls' basketball teams will open Southern California regional play at home in a double-header on Saturday.
A Volcanic Medley Near Mammoth Lakes
A massive, old caldera and more recently formed craters shape the landscape in the eastern Sierra Nevada.
Sierra Canyon wins 2026 Open Division girls' basketball title
Behind a standout performance from Jerzy Robinson, the Sierra Canyon girls' basketball team defeats defending champion Ontario Christian for the Southern Section Open Division crown.
Scientists seek new ways to protect Sierra Nevada meadows
Sierra Nevada meadows may cover a relatively small portion of the landscape, but scientists say they play an important role in supporting wildlife, storing water and maintaining biodiversity.