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Slice of Martian Meteorite Teghaza 001
This slice of Teghaza 001, one of the most ancient Martian meteorites ever found on Earth, was used to determine the age of the rock. Reflected light images
Try These Spooky Science Experiments Just in Time for Halloween!
Get into the Halloween spirit with these hands-on science activities that combine learning and fun! Also, learn tips to help your pumpkin last longer!
Nursing home industry group publicly cited 'travel' for advisory panel no-show. Privately, it cited ‘politics’
After a nursing home industry group was a no-show for a presentation before a panel on nursing home oversight, the group blamed its absence on "travel complications." Texts reveal a different reason.
Workers are getting a shrinking slice of America’s economic pie
The US economy continues to grow at a relatively healthy pace, but American workers aren’t fully reaping the financial rewards.
Economy, 'political homelessness' is top of mind for Ohio voters
Morning Edition Host Amy Eddings is back with another installment of the Ideastream election series that interviews voters from the Mahoning Valley ahead of the midterms.
Padre Island business matches candy donations to keep Hawksnest, Eagles Nest bowls full for Halloween
Island Tire Automotive has collected more than 400 pounds of candy for Hawksnest and Eagles Nest neighbors, matching every pound donated as candy prices climb.
Samsung slices into Apple's iPhone Duo troubles with a cheeky new ad
A Samsung Galaxy Z Fold 8 ad pokes fun at Apple's iPhone Duo as early screen cracking reports fuel the foldable rivalry.
Race Results: 2026 NASCAR Cup Series YellaWood 500 at Talladega
Kyle Larson took a thrilling win in a wild last-lap rally that led to a photo-finish with William Byron, his Hendrick Motorsports teammate. Larson, who was eighth heading down the backstretch of the final lap, had everything go his way ahead of him, as he sliced and diced his way back to the front. Ricky […] The post Race Results: 2026 NASCAR Cup Series YellaWood 500 at Talladega appeared first on TobyChristie.com.
Halloween fun with a slice of science
Halloween can be many things: spooky, enchanting, fun, creative, mysterious and…scientific? That last word is what Walking Mountains Science Center hopes to bring to light when kids and families attend Fright at the Museum on...
PG&E power shutoff impacts Morro Bay-area residents and businesses
"I was concerned for my neighbors because I'm only 67 and I'm a youngster in this area,” said a resident at Silver City in Morro Bay. The mobile home park was part of a Public Safety Power Shutoff.
'AI slop' or a boost for business?: How online AI promos are changing jobs in Sarpy County
As small businesses turn to generative AI for labels, menus and advertising, an Omaha-area graphic designer says the technology is reducing opportunities for human creatives.
How Rockmaster Entertainment Group tailors DJ services to every single need on Coast Live
Marshall Everett, VP of Entertainment for Rockmaster Entertainment Group, shares how the company helps create memorable events of all kinds with professional service, flexibility, trust & dedication.
Science Museum of Virginia Opens “Rescue” Exhibit
Watch Virginia This Morning each weekday from 9 to 10 a.m. Find the show on Facebook and Instagram at @VirginiaThisMorning.
NASA Langley shows off new airborne science lab as first mission nears
NASA Langley Research Center in Hampton offered a look Thursday at the agency's newest airborne science lab as the first mission was about three months away.
New downtown Salt Lake entertainment district plans raise hopes, questions in Japantown
Smith Entertainment Group’s new three-block downtown Salt Lake City district would replace Japantown Street loading docks with shops and offices.
Ohio Attorney General sues 2 home-improvement companies, including Lorain County business
The Ohio Attorney General's Office filed separate lawsuits against two Ohio home-improvement companies, including one based in Lorain County.
Ryan Smith, SEG unveil new details on downtown Salt Lake City entertainment district
A new concert venue, restaurants, shopping experiences and pedestrian walkways were among the new details revealed by the Smith Entertainment Group for its proposed transformation of Salt Lake City.
Major Rochester Road construction project sparks concern for local businesses
From the month of March to July, one northbound lane will be open. From the month of July to November, one southbound lane will be open.
UVM Health watchdog turns its sights to Vermont’s broader healthcare system
Regulators can put pressure on a narrow slice of Vermont’s healthcare costs, but in their last report, independent liaisons open a conversation of how Vermont can reduce costs more evenly across the healthcare sector.
Entertainment News: October 12, 2026
Get caught up on the latest in Hollywood, technology, and more with FOX 17 Morning Mix's Entertainment News.
Think your dog is ruining your sleep? Science says it might be you
Can sleeping with your dog help you get a better night's sleep? New research suggests it might. There's nothing better than waking up with a pup curled up next to you. (Scripps News)
Baton Rouge gets a slice of New York with Prince St. Pizza
Prince St. Pizza, the New York City-born chain known for its thick Sicilian “SoHo” squares and traditional New York Neapolitan-style round pies, is opening its first Louisiana location in Baton Rouge, 225 reports. The restaurant, 6556 Siegen Lane, will open Friday, Oct. 9, with a “pizza cutting” celebration and meet-and-greet featuring former MMA fighter Jon […]
Small businesses face tough choices as health insurance costs rise
Some businesses are exploring choice arrangements, which allow employers to set a defined benefit amount rather than selecting one carrier and set of plans for all employees.
Small businesses face tough choices as health insurance costs rise
Some businesses are exploring choice arrangements, which allow employers to set a defined benefit amount rather than selecting one carrier and set of plans for all employees.
‘Revive the business’: Candlelight Curated awarded $1 million state grant
12 weeks into production at Candlelight Curated in Lockport, the state has awarded the company $1 million in grant money as it aims to rebuild from the now-closed Candlelight Cabinetry.
Spectrum streaming bundle makes entertainment affordable on Coast Live
With so many plans and packages to choose from, how do you know if you are really getting the most for your money? Experts say there are some simple ways you may be able to save.
A Slice of Joy: In Conversation With 'Mystic Pizza' Performer Teisha Thomas
We caught up with powerhouse performer Teisha Thomas, who serves up heart, hits, and hospitality in 'Mystic Pizza' at the Ordway.
Entertainment News: October 6, 2026
Get caught up on the latest in Hollywood, technology, and more with FOX 17 Morning Mix's Entertainment News.
Burglars hit 4 Chatham businesses, steal empty cash drawer and cake slices from Soul Veg City: VIDEO
Burglars hit four South Side businesses, and they were caught on camera stealing an empty cash drawer and cake slices from Soul Veg City, according to the restaurant.
New Small Business Alliances Signal Competitive Positioning by 18+ IT and Consulting Leaders Across FedCiv, FedHealth, and DoD
In the GovCon IT and consulting market, some companies react to opportunities. Others shape the board well before the game begins. Mentor-protégé agreements fall squarely into the latter category. These partnerships are not administrative check-the-box exercises. They require sustained commitment, alignment at the leadership level, and a clear view of where the market is heading. […]
Whole Fruits vs. Juice? Study Finds Differences in Heart Health
Whether you slice fruit into your cereal or drink a glass of juice apparently makes a difference for the heart. A large U.S. study shows that adults with high blood pressure, elevated cholesterol, or ...
Sacramento sisters honor family legacy with dried fruit business
Three sisters in Sacramento have launched Stained Glass Fruit, a company that turns California-grown citrus into dried slices, blending their family’s agricultural history with entrepreneurship.
Kansas City artist uses public installation to spark mental health conversations during awareness week
A Kansas City artist will pop up at Mill Creek Fountain during Mental Health Awareness Week to help people confront trauma and find help.
Kansas City artist uses public installation to spark mental health conversations during awareness week
A Kansas City artist will pop up at Mill Creek Fountain during Mental Health Awareness Week to help people confront trauma and find help.
LAUP connects Latino families with mental health support in Holland
LAUP in Holland connects Latino families with mental health care through therapy and monthly workshops, addressing stigma, language barriers and cost while helping participants rebuild confidence.
Retired Navy SEAL to first responders at Chesterfield mental health event: 'Trauma is trauma'
Operation Yellow Tape hosted a mental health conference for first responders in Chesterfield, bringing together speakers to break the stigma of seeking help.
FAU graduate student uses Miss Fort Lauderdale crown to turn science into action
FAU graduate student and Miss Fort Lauderdale Paige Aldred is combining marine science with community outreach, using her platform to raise awareness about water quality, Sargassum ,and sustainability.
New in Home Entertainment: "Wonka's The Golden Ticket" & "Family"
Screen Chatter Film Critic reviews the game show "Wonka's The Golden Ticket" and "Family", a horror/ thriller.
Bend cheesecake business launches vending machine
Little Slice of Hell Cheesecakes launched its vending machine of cheesecakes earlier this month at Midtown Yacht Club, giving Bend a new way to grab local, homemade cheesecakes on the […]
Science Museum of Virginia Opens Interactive “Rescue” Exhibit
Watch Virginia This Morning each weekday from 9 to 10 a.m. Find the show on Facebook and Instagram at @VirginiaThisMorning.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
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There are three types of China shock discourse. Each has a distinct temporal register. China shock 1.0 was a phrase coined by US academics in the 2010s to retrospectively summarize the impact on particular US labour markets, which they identified through painstaking empirical investigation. China shock 2.0 on everyone’s lips in Europe in the mid 2020s is an alarm raised by trans-Atlantic policy thinkers warning of a coming disaster which they project onto Europe’s ailing car industry. The third type of China shock discourse - commonly known as the “China squeeze” launched most recently by Indian economists Shoumitro Chatterjee and Arvind Subramanian in the pages of Foreign Affairs - mobilizes a different, more speculative temporal register: the counterfactual realm of alternate history. The China squeeze argument asks not what has happened, or what is going to happen, but what might have been. Specifically, what options for economic development might have been open to Global South economies like India or the economies of sub-Saharan Africa, had it not been for China’s spectacular industrialization since the late 1990s and the persistent competitiveness of China’s manufacture in low-skilled segments. Chatterjee and Subramanian’s argument is that whilst China has built a powerful position in electrical machinery and other high-skill manufacturing, which is now delivering China Shock 2.0, it also continues to run a trade surplus in low-skill, labour-intensive manufacturing. This surplus is large and has remained largely unchanged in fifteen years. Indeed, in the 2010s, in trade with low-income countries, China’s surplus rapidly increased. On their reading, this squeezes low-income producers in low-skill sectors in which they “should” be able to compete. Source: “China’s Mercantilist Squeeze on Developing Countries” Shoumitro Chatterjee and Arvind Subramanian. Peterson Institute for International Economics 26-7 May 2026 Chatterjee and Subramanian’s wording is telling: (emphasis mine) The canonical trajectory of economic development in the post-World War II period is for countries to transition from agriculture to manufacturing, first in low-skilled manufacturing and then later on to high-skill manufacturing (Herrendorf, Rogerson, and Valentinyi 2013). At the global level, this implies that high-income countries (HICs) that once specialized in low-skilled activities cede manufacturing export space to poorer countries that come along to occupy that space. In 1965, advanced economies accounted for about 60 percent of global value-added exports in four key low-skilled manufacturing sectors, i.e., apparel, leather, textiles, and footwear. Over time this share declined and began to be occupied first by the East Asian tigers and, beginning in the late 1990s, by China. Today China accounts for about 50 percent of the global market. The question is whether China, with its rising prosperity, is continuing to behave like its richer counterparts and ceding export space to poorer followers or to behave unlike them and continuing to occupy space. In terms of the conceptual maneuvers it performs, of the three China shock discourses, the “China squeeze” argument is by far the most ambitious. After all, it bases its critique of China on a counterfactual imagining of the world. Like any counterfactual argument, to construct this alternative reality it must rely on a heuristic model. To make their argument Chatterjee and Subramanian mobilize two key claims. The first reference point is the actual history of rich-country industrialization, what they refer to as the “canonical path”. The idea is that countries transition from agriculture to light industry and low-skilled manufacturing and from there up the value chain. To make this useful as a standard of comparison and a means to construct a normative standard, they adjust sectoral export shares for two factors: 1. the underlying level of economic development of the exporting country, as measured by national income and 2. the degree to which the sector in question is internationalized. The idea being that for a high income country to have a high export share in low-skill sectors is anomalous and even more so if that particular product is highly internationalized and thus suitable for being “conceded” to lower-income competitors. Where should this process end? Here Chatterjee and Subramanian introduce their second benchmark. Their normative idea of a global development path is one in which, in due course, low-skill manufacturing exports are distributed in proportion to a country’s share in the global labour force. They imagine, in other words, a world of proportional, polycentric global development without much national specialization in low-skill manufacturing. A useful benchmark is that, in labor-intensive manufacturing sectors, a country’s share of world exports should be broadly commensurate with its share of the world’s low-skilled labor endowment. … In the Heckscher-Ohlin model, this would be true if value added per worker and export propensities, i.e., fraction of output that is exported, are the same across countries. It is this pleasant liberal vista of orderly global development, progressing towards a general distribution of low-skilled manufacturing against which they judge reality and conclude that the low-income countries are suffering a “China squeeze”. China is not exiting low-skill sectors fast enough Allowing for its gdp level and the degree of globalization, China’s share of low-skill manufacturing exports is far higher than it “should” be. Relative to population, its low-skill share of exports is far too high. That in turn yields the conclusion that huge numbers of jobs - the authors suggest tens of millions - are being hoarded by China. For the four sectors captured in figure 4, this excess in value-added exports is $110 billion in 2022. For all low-skilled sectors overall captured in appendix figure D.1, excess value-added exports amount to $365 billion. The crowding out of LMIC exports by China is therefore substantial. Both these claims have in common that they are strong structuralisms. The first is that development paths ought to resemble each other. The second is that broadly speaking as far as low-skilled manufacturing is concerned, all countries are alike. If the world currently diverges from the distribution of trade implied by these assumptions, if China is not following the advanced economy path and has huge exports, this must be the result of “policy”, which the authors then put in question as illegitimate or unfair. Thus the naturalistic construction of a canonical path leading to a “level” distribution of low-skilled manufacturing reveals itself to be a polemical tool. From the point of view of China shock polemics, this discourse is no doubt welcome. But as an account of economic history, it must surely be regarded as nothing short of bamboozling. Development paths do not follow a regular, natural sequence. As David Fishman put it aptly, “development is not a queue”. They are always and everywhere, through and through political. Development is not so much a process, as a project. Each such project is more or less well adjusted to its context. As Gerschenkron taught uneven and combined development implies differentiation rather than simple imitation on a single parth. It may be true that Europe and the US exited relatively early from low-skill work. But clearly technology has changed. As C&S themselves point out, China no longer enjoys a low wage environment. Do they really believe that such huge differences can be accounted for either by industrial policy, which as they admit does not operate powerfully in low-skill sectors, or by exchange rate manipulation? What is overwhelmingly dominant in explaining the persistence of “low-skill” manufacturing in China are surely the network effects of complex supply chains. Indeed the label of “low-skill” may miss the point. The degree of globalization which Chatterjee and Subramanian decide to conjure away in their model of the development path - to allow for the fact that Europe and American textiles exporters did not enjoy just-in-time logistics in the 1950s - obscures the point that the networks through which Chinese factories supply the world are themselves key parts of the low-skill industrialization project. China isn’t knocking out 1970s style “cheap”. It has redefined the entire product cycle. C&S’s casual reference to “T-shirts” is telling. In today’s “fast fashion”, there is weight on both terms. Fashion and fast. China’s success in delivering on both at unprecedentedly high speed and at unprecedentedly low cost, isn’t a low-skill operation at all. If we see development trajectories not as the serial repetition of the same, but as distinctive, crafted projects that cumulate in complex agglomerations of skill, technology and labor, then this explains why the assumption that low-skilled manufacturing should follow the distribution of population flies in the face of all experience. As countless cases attest, low-wage, low-income developed economies are not by themselves the makings of a competitive production base. As Leon Liao puts it quite fairly: “International trade has never been allocated according to population. A country’s population gives it no natural claim to an equivalent share of global exports." And the remarkable fact is that Subramanian alone and with co-authors has long been making this point, not to pillory China, as is the case of the tendentious _Foreign Affair_s and Peterson pieces, but to highlight the great counterpart to China’s industrial success, namely India’s relative failure. The much-quoted Foreign Affairs piece showed low-skill export shares only for China, not for India. If you put both countries in the picture as Chaterjee and Subramanian have done on other occasions, the picture looks like this. China is far above the line, but India, almost as large in terms of population, is no less anomalous, just in the opposite direction. As far as global populations are concerned, and the imagining of tens of millions of “squeezed” jobs, it is this Sino-Indian pair that account for a huge share of the action. What this graph reveals is not China’s cheating, but India’s “greatest development failure”, at least this is the argument made Arvind Subramanian, this time in co-authorship with Devesh Kapur, in their major book, A Sixth of Humanity. Independent India’s Development Odyssey which appeared with Oxford University Press earlier this year. In this highly critical work on India’s development, China is repeatedly evoked, not to criticize but as a benchmark against which to illuminate what India’s political economy has not delivered i.e. large-scale formal employment for hundreds of millions of citizens. Kapur and Subramanian leave no doubt, if you want to understand why China, not India was the main driver of manufacturing globalization from the 1980s, don’t look to slots opening up in the division of labour thanks to the liberal mindedness of advanced economies, look to the contrasting political economy of the Maoist PRC and India’s post-independence political economy. As Kapur and Subramian note: The great divergence between China and India did not begin in 1978 with the Deng reforms—it was well underway by then. In one of the great ironies of modern history, the conditions created by Maoism turned out to be a great launching pad for industrial globalization. As the comparison of India and China in 1980 makes clear, to imagine manufacturing would be equally distributed when populations are so differently endowed in terms of educational and nutritional is fanciful. Here is the data from Kapur and Subramanian, data which I explored back at the very beginning of Chartbook. As Kapur and Subramanian insist, the striking fact is that even as India’s growth accelerated from the 1980s, structural change has not. Formal employment in India lags woefully behind. Why? As Kapur and Subramanian note, the path-dependent impact of India’s poor early start was devastating. The list of factors they mention is long and weighty: We argue for a new five-fold explanation applicable at different stages of Indian history: in the initial stages, the legacy of two key pre-1980s policies, the neglect of agriculture and the strangling of the domestic private sector, were critical. The failure of broad-based agricultural growth militated against rural industrialization, which would have been devoted to satisfying local needs that would have necessarily been labour intensive. Then, when the boom came after 1980, the thicket of regulation and broader labour protections that were legislated prematurely in a nascent democracy, underpinned by a deep ideological aversion to private capital in general and big capital specifically, became a barrier to attaining the size that would be necessary to compete globally. Similarly, the reforms after 1991, while wide-ranging, did not quite encompass non-tradeable inputs critical to manufacturing, namely, land, logistics infrastructure and power. A combination of low investment (logistics infrastructure), regulation (land) and the continued monopoly supply by state governments (power), combined with residual socialism, kept costs at 75–100 per cent above efficient supply. These factors were compounded on the supply side by the government, which dominated the formal labour market and established exorbitantly high wages at the lower end of the skill spectrum. This made their employment in the labour-intensive sector by the private sector less attractive. Finally, when the services sector and its exports boomed, wages soared even further via a Dutch Disease effect: one successful tradeable sector killed and cannibalized another less-skilled tradable sector, namely, manufacturing. Thus, scarcity-inducing policies of the planning era, precocious democracy and a Gandhian aversion to size; inefficient, monopolistic supply of critical non-tradable inputs; the behemoth of government; and super-successful skill-intensive services successively undermined India’s unskilled labour employment opportunities. The employment failure seems to have been over-determined. … Less quantifiable but no less important are some of the sociological factors that have undermined manufacturing and factory jobs. Take the impact of the success of the IT sector—located in urban areas with better working conditions, such as air-conditioned offices, good schools for children and attractive entertainment options. It became a more attractive place for engineering and management graduates to flock to. … Consider manufacturing and female employment. Indian society makes it difficult for women to work, reflected in India’s unusually low female labour force participation (elaborated in Chapter XIII). Indian society, in particular the routine harassment of women in public spaces, makes it even more difficult for them to travel long distances to take up work.37 Combined with onerous regulations on creating hostels and dormitories for women—which, in turn, prevents multiple shifts of operation—factories need to be located in areas with a large female labour pool. While firms can take apparel plants to female labour or bring them to the plants by building large-scale dormitories, this raises costs. If there was a case for subsidies to encourage labour-intensive manufacturing, housing subsidies to build dormitories for women workers would be a good place to start. All of this meant, that when opportunities did open up, in part thanks to adjustments in China, India was in no position to take advantage. Here is the account of the 2020s from Kapur and Subramanian. It stands in dizzying contrast to the one-sided, “China squeeze” argument delivered in the Peterson and Foreign Affairs pieces: In 2022, for example, India’s share of global exports in clothing (the canonical labour-intensive sector) was 3.1 per cent compared to 32 per cent for China. This is extremely disappointing because China started vacating export space in this sector after the Global Financial Crisis as its wages started rising; it then vacated further space in the aftermath of geopolitical developments that led investors to seek alternative investment locations. Between its peak and today, China lost about 7.5 percentage points of global export share (worth about $43 billion in 2022); over this period, India’s export share remained stagnant at 3 per cent, while that of Vietnam and Bangladesh rose by 3.5 to 4 percentage points. China’s loss did not translate into any gain for India in terms of low-skill exports and employment. Put differently, when the conditions for dynamism and prosperity were established after 1991, and even more tantalizingly when the global export opportunities opened up, it was as if India was a high-wage economy and only skilled labour could benefit from the dynamism. It had converted its physically abundant unskilled workforce into an economically expensive resource, penalizing its use. It is not my mission here to argue for or against Kapur and Subramanian’s interpretation of India’s development trajectory. The point in this context is simply that the “China squeeze” such as it is can only be understood, in relation to the heavy burden of domestic constraints that Kapur and Subramanian so unsparingly enumerate. I am concentrating here on India because it is the great counterpart to China and the unspoken reference point of the “China squeeze” discourse. But the point is more general. Can anyone with a straight face suggest that the main problems afflicting the development of South Africa or Nigeria, the great centers of mass underemployment in sub-saharan Africa, are cheap competition from China driven by Beijing’s industrial policy and an undervalued RMB? Likewise, is the main problem of the American working-class the threat of Chinese competition or the manifest crisis of social reproduction in the United States itself? The point here, as in the discourse around China shock 2.0 in Europe, is to insist that we should not normalize the world and pathologize China, without actually investigating what is going on in America’s industrial wastelands, the German car industry, or India’s lopsided labour market. One-sided pathologization should be understood for what it is, a polemical gesture. Concepts like China shock and China squeeze are, what Reinhart Koselleck, following Carl Schmitt, would have described as “asymmetrische Kampfbegriffe”, or “asymmetrical counter-concepts” or “asymmetrical combat concepts”. If the function of arguments like the “China squeeze” is to alert elites in the rest of the world of the need to rejuvenate and energize their development projects, so be it. But let us see the resulting discourses as the mobilizing interventions that they are. Interestingly, a significant slice of China’s public sphere - the so-called industrial party - have been obsessed for the last twenty years with precisely these questions of counterfactual economic history. Since the mid 2000s, a massive online discourse developed around an alternative history in which Chinese techno-patriots were asked to imagine how they would proceed if they had the possibility of traveling back in time to transport modern technology into the Ming dynasty (1368-1644) thus averting the “great divergence” of the 18th and 19th centuries. It is a fantasy of course, but also a goad. The point was not directed at Westerners. The alternate history is dramatically nationalist, but few n the West had even heard of it until recently. The adherents of the industrial party are not liberal moralists. They don’t project natural ladders of international development and ask why others don’t cede space. They take the Realpolitik of global economic development for granted. Their pointe was directed against fellow Chinese. The rallying cry of the alternative narrative was this: Now that we are beginning to gain steam and push forward on our national development path, now that we are breaking out of the inferior position assigned to us even in the early years following WTO accession, do not lose yourself in humanistic imaginings about better futures. In the spirit of Deng, they called on China to embrace the hard truth of development. Perhaps one might of the Industrial Party as a cultural trend born out of desire for symbolic revenge against those who had inflicted the century of humiliation. In terms of the various temporalities of the “China shock” - retrospective, prospective and counterfactual - one might think of the Industrial Policy discourse as truly speculative, conjuring up the China shock that never was. Or perhaps one might better think of it as imagining a world in which a powerful China was no shock at all, but simply a defining fact of modern history. I love putting out Chartbook. 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