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‘Standing on Business,’ ‘Squabble on Day 1’ — NBA World Reacts As LeBron James Snaps Back at Knicks Heckler in 76ers Debut
The new NBA season saw LeBron James stealing some of the New York Knicks’ thunder during their championship ring and banner-raising ceremony. James played a solid all-around game to help the Philadelphia 76ers’ newly stacked team secure an impressive opening-night win at Madison Square Garden against a subdued, sloppy Knicks team that still looked hungover from celebrating their championship.
Delancey Street Launches Free Two-Minute Self-Assessment for Business Owners Carrying Stacked MCA Debt
Delancey Street, a New York based MCA relief company, today released a free self-assessment that shows small business owners their exposure to merchant cash advance debt in about two minutes. It requires no credit check and carries no obligation.
'Peak', The Beloved Indie Climber, Scales October's Stacked Switch 2 Release Schedule
Launching next week!
Devious Arc Raiders Griefers Are Having Fun in PvE, Camping Locked Loot Rooms and Pulling Enemy Robots Into Extraction Points
Arc Raiders PvE lobbies are already stacked with griefers, using the relative safety of the mode, where your bullets don’t affect other raiders, to put other players in dangerous spots via other means, whether that be manipulating the AI, using tools, or simply getting in the way.
Elsevier Commits to Accelerate AI-Driven Science Across Europe
/PRNewswire/ -- Elsevier, a global leader in advanced information and decision support in science and healthcare, today announced its pledge to the European...
Duke Health and CaroMont Health Partner to Develop Two New Hospitals in Mecklenburg County
CHARLOTTE, N.C. – Duke Health and CaroMont Health today announced they are forming a new partnership to expand healthcare access and capacity in Mecklenburg County, beginning with plans for two new hospitals. With the region’s continued growth, the organizations are planning now to help ensure healthcare infrastructure and services can keep pace with the needs of patients and families.
Flo Health and Google Health Join Forces to Put Women's Health at the Center of Wearable Tracking and Personalized Coaching
/PRNewswire/ -- Flo Health, the #1 women's health platform worldwide, announces today a multi-year strategic partnership with Google Health to create a more...
Fox Tells DC Circ. Worker Wasn't Fired Over Leave, Politics
Fox News urged the D.C. Circuit to reject a former Capitol Hill producer's bid to revive claims that he was fired over his political views and use of sick leave, arguing he was terminated instead for insubordination and unprofessional conduct.
How Americans’ Financial Health Is Faring In The “K-Shaped” Economy
Hey all, Jason here. Money20/20 is still two weeks away, but I’ve already started packing (not procrastinating for once!). My calendar is already filling up with various sessions I want to catch, meetings, and of course happy hours, dinners, and other side events. If you’ll be in Vegas and want to catch up, let me know by replying to this email, and we can try to find a time amidst the chaos of the Venetian. A big if not totally unexpected piece of news dropped on Friday: the Independent Community Bankers of America, a trade group that represents smaller U.S. banks, filed a lawsuit against the OCC and Comptroller Jonathan Gould, arguing that the regulator’s move to grant trust bank charters to firms seeking to use them to conduct substantial non-fiduciary activities exceeds the authorities granted to the OCC by Congress. I haven’t had time to fully digest the legal filing or speak to folks in my network about it, but you can expect to see coverage and analysis on it in next week’s newsletter. Subscribe or Support by Upgrading The NerdCon agenda just dropped. It’s stacked. Partner content: Nubank built an AI-first bank. Chime built its own banking core. Figure and Valon are rebuilding the mortgage stack. At NerdCon, you’ll hear from the people behind those bets: what they chose, what they learned, and what they’re still figuring out. The agenda is live, with leaders from Nubank, Chime, OpenAI, Remitly, Mercury, Figure, Valon and more. Follow the mainstage conversations, bring the problem your team is wrestling with to a hands-on workshop, or pull up a chair at a roundtable. Pick your quests. Meet us in San Diego, November 18–20. Fintech Business Weekly readers save 20% with code FBW20. Explore the Agenda Things To Know & Other Good Reads Federal Reserve Board finalizes changes to enhance the transparency and public accountability of its stress test and reduce volatility in its stress test-related capital requirements (Federal Reserve Board of Governors) FDIC Announces Conclusion of Independent Monitorship (FDIC) Modernizing Financial Regulation: Initial Observations from eSLR (Fed Vice Chair for Supervision Michelle Bowman) The Data Version of Godzilla versus Kong: FRED Takes on AI (Fed Governor Christopher Waller) Financing the AI buildout (Brookings) Q3’26: Rules for Banks but Not for Crypto (Fintech Takes Banking) The Inevitability of Local Stablecoins (Lombard Notes) Delusions of AI Governance: The Human-in-the-Loop Comfort Blanket (Fintech Snark Tank) Stripe agrees to acquire Parafin to expand revenue opportunities for platforms and help small businesses grow (Stripe) Listen: Fighting Fraud in the Age of AI, with SEON’s Tamas Kadar (Fintech Business Weekly) How Americans’ Financial Health Is Faring In The “K-Shaped” Economy If there is one overarching theme across the economy and politics in the U.S. at the moment, it’s “affordability.” The term is vague enough to encompass a panoply of factors shaping Americans’ day-to-day lives: rising costs for the hallmarks of being “middle class,” including healthcare, housing, childcare, and education, inflation and rising interest rates, and a job market with the specter of AI hovering over it. At the same time, policy shifts under the Trump administration have resulted in reduced subsidies to those who get health insurance under the Affordable Care Act and new restrictions on qualifying for Medicaid and SNAP, the impacts of which have yet to be fully felt. These factors are contributing to declining consumer confidence and general dissatisfaction with the economy, despite continuing GDP growth and stock market records. This divergence is encapsulated in the idea of the “K-shaped” economy, in which a small proportion of Americans have seen their wealth balloon, while the majority of American households struggle to preserve the lifestyle they have. Perhaps the greatest determinant of which branch of the “K” a household is on is whether their wealth and income are primarily derived from employment vs. from assets. Nearly two decades of low interest rates and, more recently, elevated rates of inflation have benefited asset owners, while those whose income is primarily or solely derived from labor have largely seen real purchasing power stagnate or decline. This is reflected in recent Bureau of Labor Statistics data showing that labor share of U.S. GDP — the fraction of economic output that accrues to workers as compensation in exchange for their labor — dropped to just 52.8% in Q2 2026, the lowest since the BLS began keeping records. In 1947, approximately 2/3rds of economic output accrued to workers; even as recently as 2001, labor’s share of GDP was 64.1%. Against this backdrop, we’ve seen the rise of more credit and credit-like products: cash advance apps, “no-fee” overdraft, earned wage access, and buy now pay later, which are often used as small-dollar short-term borrowing mechanisms to meet immediate consumption needs or pay other bills (eg utilities, cell phone, other debt payments). With the markers of a middle class existence and, increasingly, basic financial stability seemingly out of reach for many, it should be no surprise there’s been an increase in “financial nihilism,” something industry peers like Alex Johnson and Frank Rotman have discussed and analyzed the roots of. The explosion of gambling and gambling-adjacent products and services — often marketed under the guise of being an “investment” — is inextricably intertwined with the rise of financial nihilism. Crypto, sports betting, and, more recently, prediction markets offer an escape or even hope of sorts, like a contemporary, digital version of a scratch-off lottery ticket, while leaving the overwhelming number of people who use such products worse off. Share of Households That Are Financially “Vulnerable” Ticks Up The Financial Health Network’s 2026 Financial Health Pulse® report adds context on how American households are faring. (I linked to this report in last week’s newsletter, but wanted to take time to further unpack the data in the report this week.) The Financial Health Network publishes the report annually, providing insight into how Americans’ financial circumstances are changing over time. The 2026 report is derived from a survey fielded in April and May 2026. The report leverages survey responses to assess indicators of financial health across spending, saving, borrowing, and planning/protecting and to determine a zero to 100 “FinHealth” score. Those with scores between 0 and 39 are considered “Financially Vulnerable,” consumers with scores ranging between 40 and 79 are defined as “Financially Coping,” and those with scores of 80 to 100 are “Financially Healthy.” The report found that moderate improvements in 2025 were reversed, with the share of respondents considered financially “vulnerable” rebounding to 17%. The longitudinal data reflect the impact of pandemic-era programs, like expanded unemployment, cash stimulus payments, and pauses of federal student loan payments. The positive impacts of those programs, as reflected in the Financial Health Pulse reports, had largely disappeared by 2023. While pandemic-era inflation — to be fair, in part caused by the various support and stimulus measures — had come down from as high as 9% in 2022, it has rebounded since the start of Trump’s second term, with tariffs and energy market disruptions owing to the war in Iran pushing prices back up. Specific indicators in the survey that deteriorated from 2025 to 2026 include the share of respondents spending less than their income over the past 12 months, the share paying all bills on time over the past 12 months, the share that have a manageable amount or no debt, the share that are “moderately” or “very” confident their insurance is adequate to cover them in an emergency, and the share that “somewhat” or “strongly” agree that their household plans ahead financially. Unsurprisingly, lower- and moderate-income households are more likely to struggle to pay their bills on time and have any funds leftover to save. The share of low-income households whose income exceeded their spending dropped from 35% in 2025 to 31% in 2026, while the share of upper-income households whose income exceeded expenses remained unchanged at 63%. Households with student loans or revolving credit card debt reported having “a bit more” or “far more” debt than was manageable at rates far higher than those not carrying these types of debts. The share of those with student loan debt indicating their debt load was too high to manage increased from 50% in 2025 to 55% in 2026, while the share of those with revolving credit card debt saying the same ticked up from 51% in 2025 to 54% in 2026. Households that had student loans were markedly more likely to be financially “coping” or “vulnerable” vs. those without student loans. In 2026, 27% of households with student loans were considered financially vulnerable, a jump of 6% points vs. 2025. Households without student loans saw just a 1% point increase (not statistically significant) in those considered financially vulnerable. Households’ perception of the affordability of categories of goods and services paints a stark picture, with less than one-fourth considering higher education affordable, about a third deeming childcare affordable, and less than half viewing healthcare as affordable. Fintech Business Weekly is made possible by the generous support of paying subscribers — bringing you independent analysis of banking, fintech, and crypto without fear or favor. You can support my work by becoming a paying subscriber if you aren’t already. Paying subscribers enjoy: access to the entire archive of nearly six years of newsletters extended versions of the weekly newsletter, with additional content and analysis and (for founding member tier) quarterly personal 1:1 fintech Q&A / strategy calls with me, tapping into my unparalleled knowledge of the intersection of banking and fintech and experience working in the sector, including helping to launch Goldman Sachs’ retail bank Marcus Support Fintech Business Weekly You can also support Fintech Business Weekly by sponsoring a newsletter or podcast, putting you in front of 93,000+ of the most influential decision makers in banking, fintech, and crypto. Learn more about sponsor opportunities or request a media kit by dropping me an email. Democratic Senate Report Highlights How Iran Uses Tether to Evade U.S. Sanctions Iran uses stablecoins, specifically Tether, to evade sanctions, fund regional proxies, and to purchase military drones, a report released last week by the Senate Permanent Subcommittee on Investigations says. The report was authored by committee ranking member Senator Richard Blumenthal (D-CT) and the minority staff. Crypto and stablecoin proponents will often push back on criticism that criminals make use of these assets by arguing that, on an absolute dollar basis, far more illicit funds flow through traditional banking systems and payment rails than via crypto and stablecoins. And while that is likely true, it elides the reality presented in news story after news story: whether state actors — Russia, Iran, North Korea — or criminal groups, those looking to engage in illicit transactions increasingly favor stablecoins and, specifically, Tether (USDT). The report from the Senate Permanent Subcommittee on Investigations released last week adds context to how Iran uses Tether has a lynchpin in its shadow banking system. The report analyzed 846 wallets that have been sanctioned or targeted for seizure, finding that 84% of them transacted exclusively or primarily in Tether. The ability to create near limitless, anonymous wallets and to move funds effectively instantaneously and irreversibly have made crypto a favored financial mechanism for bad actors. Stablecoins solved key drawbacks of bitcoin, namely, the original cryptocurrency’s highly volatile value in dollars. And while Tether (the company) has the technical ability to “freeze” or destroy funds, the company is often limited and reactive in its approach to doing so, the Senate report argues. Tether, which is nominally based in crypto-friendly El Salvador, “has stated that its compliance with OFAC sanctions is ‘voluntary’ and that it follows ‘OFAC guidelines,’” the Senate report says. Owing to these favorable attributes, Tether “became a primary cryptocurrency for Iran, Hamas, Hizballah, and the Houthis beginning in 2023 and has expanded in scale since,” according to the report. Tether’s role in Iran’s shadow banking system, the report says, is enhanced by crypto exchanges like Bybit, Kyrrex, OKX, Gate, and Binance, and through “over the counter” exchanges and hawala networks. The consequences of these financial flows aren’t hypothetical. The Senate report links Tether as a funds transfer mechanism to Iranian proxies in the region, including Hizballah, the Houthis, and Hamas. Tether has also been used to make payments to secure components necessary to manufacture drones, the report says. The report concludes by arguing that “[s]tablecoin issuers with a significant nexus to the United States, particularly those that offer dollar-denominated stablecoins, should be subject to American sanctions law rather than being allowed to hide behind foreign jurisdictions.” Stablecoin issuers like Tether must be held accountable for repeated failures to prevent illicit finance and sanctions violations by law enforcement, the Department of Justice, the Securities and Exchange Commission, and OFAC, the report argues. [Paying Subscriber Exclusive] OUSD Goes Live, Make Your Own Neobank, U.S. Sanctions Russia’s A7 Network As “Transnational Criminal Organization” OpenUSD, the stablecoin issued by the Open Standard consortium that includes Stripe, Visa, Mastercard, core providers, crypto firms, and numerous banks, went live last week. Social commerce platform Whop raised eyebrows in fintech by offering creators on its platform the ability to launch their own neobanks, which the company describes as “great businesses that are easy to run,” in just 15 minutes. And OFAC and FinCEN target Russia’s “shadow banking” A7 Network — more on these stories after the paywall.
Full Saturday slate of baseball as Division Series begin
Four playoff games stacked back to back as the MLB playoffs continue in earnest!
Stacked contests impact Cincinnati girls volleyball power rankings
After a consequential night of matches on Sept. 29, here is the latest power rankings for Greater Cincinnati girls volleyball.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Pascal Groß Tipped Favourite To Win Premier League Star Award
The German veteran’s red-hot scoring streak and vital leadership at Brighton make him a frontrunner for Player of the Month honors against a stacked field of nominees.
Valor Mortis is only $40 because its developer knows you'll be choosing from a lot of big games over this "stacked" autumn
Valor Mortis, previously delayed to avoid a busy September, has today revealed it won't be as expensive as many of the games releasing around the same time.
Haverkamp Group breaks ground on 387-unit residential community in Ankeny
Ames-based Haverkamp Group recently celebrated the groundbreaking of the Sloane, a new 387-unit residential community in north Ankeny. The Sloane, located on about 28 acres near the southwest corner of Northeast Delaware Avenue and Northeast 70th Street, will feature apartments, stacked flats and townhomes. The development will also include a clubhouse, swimming pool and other…
Google Wallet for Android getting vertically stacked card list
Following the homepage redesign and fullscreen passes revamp this year, Google Wallet is trialing a vertically stacked card list.
After questions about Black support, Black leaders surge to boost David Jolly
'This team is stacked with talent and wisdom, and it’s connected to every part of Florida.'
Ochsner Lafayette General Welcomes New Physicians
Ochsner Lafayette General welcomes new physicians in infectious diseases, orthopedics, psychiatry, pediatrics and pediatric neurosurgery across Acadiana.
Ochsner Children’s Earns Newsweek National Recognition
Ochsner Children’s Hospital earned national recognition on Newsweek’s America’s Best Children’s Hospitals 2026 list, ranking among the nation’s top 50 hospitals in four pediatric specialties.
In 1942, scientists stacked roughly 45,000 graphite blocks beneath the stands of a Chicago football stadium and started the world’s first nuclear reactor — while one physicist waited nearby with an axe, ready to cut a rope and drop an emergency rod if the reaction ran out of control
The architect of the atomic age had no emergency button, no computer failsafe—just a physicist with an axe and steady nerves standing between Chicago and catastrophe.
Will Lampard change the way Coventry play this season?
Coventry City's style of play has been the subject of several questions sent in via our Sky Blues Ask Me Anything form, with some of you wondering whether Frank Lampard will adjust it this season as a result of facing higher-level opposition. Coventry's shape under Lampard is never fixed and that tactical flexibility is going to be a major theme of their Premier League return. The Premier League is unforgiving, stacked with world‑class players, and there will be times where a more conservative approach is simply the smartest route.
Healey Won't Rule Out Tax Hikes Despite Business Demands
Chancellor of the Exchequer John Healey declined on Monday to rule out tax hikes in the autumn budget statement despite demands from industry groups to reduce the fiscal pressure on businesses.
Nvidia wants to turn your house of gaming PCs into an AI supercomputer
Nvidia's free RTX PAIR app spreads local AI workloads across multiple GPUs on your network, dramatically cutting down on processing times.
August Monthly Review: ChatGPT In Epic
Death, taxes, another frontier lab healthcare launch inspiring truly insane LinkedIn takes. As much as I want to stay away, I repeatedly am the crewman unplugging his ears whenever we pass these sirens. So it’s not the first and probably not the last time we dial up the typewriter rather than tie ourselves to the mast. The full blow-by-blow timeline: Health API Guy is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe The End of the Standalone PHR (Jan 8): ChatGPT Health arrives for consumers, at the time powered by b.well. I was bullish on the approach in that the best way for the PHR to finally solve distribution was to meet consumers were they already are (i.e. When Horizontal Meets Healthcare (Jan 9): OpenAI for Healthcare puts out the shingle for enterprises, with SharePoint ingestion standing in for the EHR integration the product actually needed. Another One: Anthropic’s Healthcare Debut (Jan 16): Claude's version, on HealthEx rails instead of b.well, with Agent Skills for FHIR development as the one true vertical-specific investment. ChatGPT for Clinicians: The Trap Sprung (Apr 24): OpenAI filled in the missing GTM middle with a free product for verified clinicians, effectively peeling the enterprise wrapper off ChatGPT for Healthcare and taking the PLG fight directly to OpenEvidence. OpenAI’s Second Attempt at Health (Jul 31): a relaunch of their patient specific app, now branded Health in ChatGPT, where the privacy partition came out, the connectors thinned, and b.well disappeared in favor of first-party FHIR work against a smaller network Beyond a Shingle So what was announced now? Today, we’re introducing a new electronic health record integration that brings authorized patient context from Epic into ChatGPT for Healthcare, along with the Healthcare Public Data plugin for direct, structured access to official healthcare datasets like PubMed, DailyMed, and CMS Coverage. Together, these capabilities bring ChatGPT closer to the systems and sources healthcare teams trust, while supporting the controls and compliance healthcare work requires. The core portfolio is unchanged from prior announcements we delineated and discussed (aside from the relaunch of patient-facing). Since trade publications still seem to be confusing them by using the wrong names: Enterprise sales motion: ChatGPT for Healthcare Protecting their core product / PLG: ChatGPT for Clinicians Consumer/patient-facing product: Health in ChatGPT So really, this is a feature release (specifically for ChatGPT for Healthcare when it comes to EHR integration). What’s cool about it, though, is that we are moving beyond just putting out a shingle. Everything in the January enterprise launch was horizontalizable: Horizontal tech companies thus generally start verticalization with their “putting out a shingle phase”. Telling the world you’re open for business as a horizontal tech company reliably attracts early inbound interest from buyers who are already trying to force-fit horizontal tools into domain-specific workflows and are eager for any signal that the vendor intends to support their use case more directly. Nothing was really vertical specific, which is exactly what you'd expect from the ultimate hypergrowth horizontal company dipping their toes into specific industries. But eventually you have to stop changing the sign on the door and start changing the product. Can you guess where the horizontal product was going to run out of road? This is the core dilemma writ large: verticalization requires differentiation, while scale economics of consumer and horizontal push toward unification. I’ve buried the lede so deep here it will be painful to some readers, but what should be shocking to no one is that my perspective is that EHR integration is the only path that meaningfully resolves this tension for ChatGPT for Healthcare. Integration with Microsoft Sharepoint is fine, but it is categorically insufficient for any product that hopes to influence clinical decision-making. SMART Money Well here we are, eight months later! Real vertical investment has begun, which surprised a few people. One friend in the industry messaged me: “Absolutely no way Epic gave ChatGPT API access.” Looking forensically at the announcements, the integration is notably read-only across appointment notes, laboratory results, medications, and specialist documentation. So while I’m not a betting man, I'd wager the house this is a SMART on FHIR launch: That sounds a lot like USCDI! The recommended path for the workflow they outline would be SMART on FHIR Their Health AI lead’s post is evocative of both standalone and EHR launch SMART, which another termed “ChartGPT” and “EHR Plugin” The implementation burden for SMART on FHIR is the lowest of the available integrative paths This is the team who literally did patient-facing SMART on FHIR with Epic last month Most importantly, if you’re a horizontal company, you generally still haven’t taken the full plunge and thus (overly) value reusability. SMART on FHIR is the logical compromise: healthcare-specific enough to matter, but standardized enough to reuse. Nobody Asked Judy Another friend asked “I thought they had to go to each health system, or did they go direct to Epic and now health systems opt in?” Given the trust paradigms in healthcare, this functionally cannot be Epic hoovering up all the data for OpenAI and shoving ChatGPT in their customers’ faces (or they would revolt). However, I do believe the aforementioned terrible coverage by TechCrunch and other outlets is probably responsible for that question, given the 325 million reference. When using FHIR as a business associate to an Epic customer, there is no EHR gatekeeping to speak of, as that isn’t how fhir.epic.com works: You register an app You pick your APIs You test against the sandbox APIs You list as “Ready for Production” Hospitals pick your app You test and go live with them Bluntly, nobody had to say yes or no in Verona (nor were they given the chance). Vendor Services (their next developer tier up that I doubt OpenAI is using quite yet in this initial release) certainly has contractual paperwork that some resent, but even there, the twin pressures of mounting antitrust and information blocking make outright gatekeeping increasingly fraught. My friend’s sentiment is, to me, representative of a broader industry neurosis, perhaps a sort of scar tissue of prior eras: people assume the gate is still there and never actually try the door. There are certainly other ways Epic (and any EHR) can put its thumb on the scale, but they are not so dumb as to stand in front of a federally mandated API and play bouncer at this exact moment in time. So I think they can and probably should go deeper, as this release is at best parity and at worst behind vertical-specific competition. OpenEvidence did a basic SMART launch with Sutter Health in February, allowing for more convenient evidence search by providers. They then add patient-context (the equivalent SMART on FHIR flow to what we see here) when Cedars-Sinai went enterprise-wide in May. UpToDate has four distinct applications across deeper workflows like patient engagement listed in Epic Showroom and announced a partnership with Epic to power Art at UGM Abridge and other ambient scribes have invested deeply into the deepest bidirectional clinical copilot workflow with integrations well beyond SMART on FHIR. In that light, the “Who is OpenAI primarily targeting here?” is clear. This release brings them into striking distance of OpenEvidence, but not the others quite yet. They are the only one of the three you can reach without building something truly Epic-specific. When will they go further? Competition is a great motivator to overcome the horizontal demons and start building things that can’t be reused: not across industries, not across EHRs, maybe not past the customer you built them for. That’s the price of actually verticalizing. The question is if and when OpenAI will be willing to pay it. Month in Review Here is the monthly review. As a reminder, this is a regular round-up of the month’s posts and other content to surface things you may have missed across regulation, litigation, interoperability, and beyond. AI assistance is used in these bullet summaries so I can focus on articles. Articles Published: None this month Video Content: The Information Exchange: Standards-based Thruple Edition (Aug 14): Back to school for us too, with Brad reporting in from the CMS Health Tech Ecosystem’s one year anniversary in DC. We get into the January CMS-0057 deadline, the fall rulemaking reading list, and why enrollment still keeps most apps off FHIR. The Information Exchange: Epic Dúnadan Edition (Aug 25): A UGM roundup with Ryan Brickner joining for the first time to check our takes against what the building actually thinks. Rangers, Ergo sitting on top of EHI, and a down-market lineup that needs some cuts. Regulatory: Stacked Deck, Bad Hand (Aug 05): ONC’s website refresh took the entire HIT Policy Committee record with it, so I rebuilt the archive and went looking for the regulatory capture story everyone assumes is buried in there. Stacking the deck and winning the hand turn out to be very different things. The Sixth Generation of Patient Access (Aug 19): A quick catalog of the five generations of patient access we’ve layered on since HIPAA, and the two candidates now competing to be the sixth. One is planned. The other is the market routing around the plan entirely. Court cases: Three Cases Walk Into a Docket (Aug 06): Two surprise settlements cleared the board in a single week, and then Judge Maddox dropped ninety-four pages on Vyne v. Henry Schein. The sleeper is a DMCA holding that makes direct-to-database a considerably riskier business model. Epic v. Health Gorilla: Into the MDL (Aug 10): Nine class actions are headed to Miami, and the Panel signaled it wants to bring the case that spawned them along too. That would leave Epic arguing the requests were obviously fraudulent in one courtroom and unknowable in the other. Amazon v. Perplexity: Agents Are Legalized! (Aug 11): The Ninth Circuit vacated the injunction against Comet, holding that the user is the one accessing the servers rather than the company that built the agent. A real win for agentic access, and a much narrower one than the headline suggests. Veeva v. Epic: Come At Me, Bro (Aug 26): Epic’s response brief wants the dismissal affirmed and, unusually, wants the opinion published as precedent. Buried in it is Epic’s own description of what its non-competes actually prohibit, which current and former employees should read closely. EHRs: The Contract Epic Would Never Sign Today (Aug 04): A 1999 SEC exhibit catches Epic licensing nearly its entire product line, Tapestry included, to the company that became TriZetto. The marketing services menu attached to it is the part that will make you blink. Forecast from Verona (Aug 07): The Epic Almanac makes one argument six different ways: the AI is only as good as the networks behind it. Emmie headlines, Art’s context stack is the most ambitious part, and Penny finally gets an autonomous coding date on the calendar. Works With Epic MyChart (Aug 17): Epic’s first new Showroom category since the death of Workshop certifies hardware instead of software, badge on the box and all. Made for iPhone, but for blood pressure cuffs, and rough news for anyone selling the RPM stack sitting in between. UGM Hot Takes 2026 (Aug 20): Everyone else covered the AI announcements, so I went after Savvy deleting the payment gateway, Rangers as Boost with the timer removed, and a down-market lineup with too many entries. Plus the Health Grid tidbits I cannot help myself on. MyChart Central Grows Up (Aug 24): Device data and Emmie turn Epic’s identity hub into a full consumer platform, which is both a logical answer to ChatGPT and a bit of a mistake. It also happens to be the best scraping target Epic has ever shipped. Industry Analysis: The Wrong Yardstick (Aug 12): Vertical software keeps getting judged against Superhuman and Notion, which is the wrong bar entirely. Your user is comparing your product to a whiteboard and forty phone calls before lunch. Primitives vs. Abstractions (Aug 27): Developers want building blocks, systems of record prefer to hand out business logic, and both sides have a real case. There’s no test from the outside that separates the engineering reason from the competitive one, which is why this keeps ending up in court. Cross-industry Comparisons: The Two Kinds of Platform Power (Aug 18): Attention power and record power are different problems that keep getting handed the same regulatory toolkit. Congress’s latest swing at Big Tech shows both what’s possible and where it falls apart. The Dogs of (Platform) War (Aug 21): A CourtListener alert turned up a property management fight with healthcare’s exact shape and none of the Cures Act. Shell prospects, ghost accounts, a notetaker bot that came back to haunt someone, and a lawyer arguing both sides of the same theory in two states. Fractals All the Way Down (Aug 31): Yardi dominates property management right up until you zoom into one segment, where AppFolio owns it outright and Yardi doesn’t appear at all. Where you draw the line around a B2B software market is about to decide an awful lot of cases. Other News: If Judy Had the Courage (Aug 13): A short eulogy for the era when software was allowed to look insane: WinAMP, bold colors, and everything the grey chatbot era has taken from us. External Media: Portland Monthly Health Tech Meetup: Erin O’Brien channeled my own feelings - maybe it’s just because it’s August and beautiful, but the monthly edition of the PDX Health community meetup was a ripper. Make sure to reach out if interested to join for the next one. STAT’s Coverage of Epic This Month: Brittany Trang of STAT did a fantastic job of breaking the FTC investigation that’s been lurking, as well as UGM related coverage, so I had to give her her wish of a meme. Fall Conferences: I’m pumped to be kicking off my fall conference season in NYC at Nabla Accelerate next month, which Chrissy provided the link to apply for. Here’s the rest of my schedule in case you want to meet up: Commonwell (Redwood Shores, CA): Oct 13-14 Open@Epic (Madison, WI): Oct 21-22 eHealthExchange (Austin, TX): Oct 27 Sequoia Project (Austin, TX): Oct 28-29 HLTH (Vegas): Nov 15-18 RSNA (Chicago): Nov 29-Dec 3 Posts I Liked: HTI-6 Should Unbundle API Certification: Josh Mandel makes the case that HTI-6 should split (g)(10) into separate authorization and data certifications, so a PACS or a genomics platform can certify only the role it actually performs. Imaging is the urgent example, but the structure solves a much bigger problem. On implementing ePrior Auth with Epic: Scott Rossignol’s field notes from a live ePrior Auth build on Epic, including the two app registrations nobody warns you about and the CPT mapping problem waiting at the end. CMS-0057 implementations are going to be such a beast. Healthcare point solutions are starting to look a lot like streaming services: Spencer Dorn runs the cable-to-streaming arc against health IT and lands squarely on the bundling half of the cycle. Bundling can be good! It can also be bad! Life is nuanced. Health API Guy is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
Scientists challenge a 70-year-old “lizard brain” myth
A long-standing picture of brain evolution as newer, rational layers stacked on top of an ancient “lizard brain” may be deeply misleading. Researchers found that evolution instead appears to balance two competing styles of brain wiring, expanding one while shrinking the other depending on what an animal needs to survive.
RFK Jr. packs health agencies with political appointees
Eighteen months into Robert F. Kennedy Jr.’s tenure leading the Health Department, he’s stacked his agencies with more political appointees than any other recent administration, while reducing staffing to a 20-year low.
RFK Jr. packs health agencies with political appointees
Eighteen months into Robert F. Kennedy Jr.’s tenure leading the Health Department, he’s stacked his agencies with more political appointees than any other recent administration, while reducing staffing to a 20-year low.
16 mummies and a dog reveal a hidden order inside an ancient Egyptian tomb
A tomb in Egypt’s Theban Necropolis reveals a surprisingly organized story of burial, reuse, and changing beliefs spanning hundreds of years. Researchers found 16 mummified people, the remains of at least four more, and a mummified dog, with burials ranging from wealthy individuals laid in coffins with amulets and imported goods to later bodies carefully stacked in increasingly crowded spaces.
'Sterling Point' is Prime Video's best YA show, and its biggest outlier
How "Sterling Point" sets itself apart from Prime's stacked YA catalog.
Applications Now Accepted for Business on Main Street Accelerator
Applications are now being accepted for the Business on Main Street Accelerator, a joint initiative between the Delaware Division of Small Business and Launcher.
2026 40 Under 40 includes standouts in tech, health care, aviation and finance
The Tampa Bay Business Journal honors 40 business leaders under 40 making an impact across the seven-county area in its annual recognition program.
Islanders a possible trade match with the Penguins?
Came across this little note, and since it is August, why not sink into it a little bit? We all know the Penguins are really weak on the left side of their defense, enter a division rival over on Long Island who happen to be stacked at the position to at least make a fun […]
2026 Elevating Women honorees announced
The Rochester Business Journal announced that 24 organizations have been selected as 2026 Elevating Women honorees.
Crunchyroll Store to Become Exclusive to Mega/Ultimate Fan Tiers in August
Open orders will continue to process, including those for items released after store transitions
The Quintessential Trump-era Politician
In 2020, I wrote an article about collaboration and collaborators. The title was History Will Judge the Complicit, and it started with the story of two famous East Germans, Markus Wolf and Wolfgang Leonhard, who both landed in East Berlin just after the end of the war. Although they came from very similar backgrounds, the former stuck with the regime, eventually becoming its spy boss; the latter, horrified by the brutal reality of Soviet-style communism, escaped. By way of juxtaposition, I also wrote about Lyndsey Graham and Mitt Romney. These two men also made very different decisions when confronted by Donald Trump’s assault on the ideals that they had both grown up believing: A glance at their biographies would not have led many to predict what happened next. On paper, Graham would have seemed, in 2016, like the man with deeper ties to the military, to the rule of law, and to an old-fashioned idea of American patriotism and American responsibility in the world. Romney, by contrast, with his shifts between the center and the right, with his multiple careers in business and politics, would have seemed less deeply attached to those same old-fashioned patriotic ideals. Most of us register soldiers as loyal patriots, and management consultants as self-interested. We assume people from small towns in South Carolina are more likely to resist political pressure than people who have lived in many places. Intuitively, we think that loyalty to a particular place implies loyalty to a set of values. But in this case the clichés were wrong. It was Graham who made excuses for Trump’s abuse of power. It was Graham—a JAG Corps lawyer—who downplayed the evidence that the president had attempted to manipulate foreign courts and blackmail a foreign leader into launching a phony investigation into a political rival. It was Graham who abandoned his own stated support for bipartisanship and instead pushed for a hyperpartisan Senate Judiciary Committee investigation into former Vice President Joe Biden’s son. It was Graham who played golf with Trump, who made excuses for him on television, who supported the president even as he slowly destroyed the American alliances—with Europeans, with the Kurds—that Graham had defended all his life. By contrast, it was Romney who, in February, became the only Republican senator to break ranks with his colleagues, voting to impeach the president. “Corrupting an election to keep oneself in office,” he said, is “perhaps the most abusive and destructive violation of one’s oath of office that I can imagine.” In the wake of Graham’s unexpected death on Saturday, I wrote about him again. He was, in many ways, the quintessential politician of Trump’s Washington, a man who shifted 180 degrees. Graham had been a fervent American patriot, proud reserve officer and military lawyer; he became one of the most important defenders of a president who believes soldiers are “suckers and losers” and shows no respect for law of any kind. As his politics changed, his language grew coarser and his behavior grew worse: He urged Israel to “level the place” in Gaza, and insulted the Danish prime minister in Munich, prompting a colleague, Senator Elissa Slotkin, to issue an apology. Here’s an excerpt from the article, which you can read in The Atlantic (gift link here) Like his close friend John McCain, Graham believed that America should stand at the center of a broad democratic alliance. The few times I met him were in that context, at the Munich Security Conference or at other European-American gatherings, which he once attended with great regularity. He also took seriously the practice of American democracy at home. In a 2014 conversation with The Atlantic, he described himself as a pragmatic politician who eschewed populist slogans. “I know Washington is broken, but what’s broken about it is everybody yelling and nobody trying to fix it,” he said. “I’m trying.” When Donald Trump first appeared in U.S. politics, Graham recognized him immediately for what he was: the spokesman for an alien ideology, one radically different from the idealistic patriotism that Graham had practiced and preached since childhood. Trump privately mocked the military that Graham loved as nothing but “suckers and losers.” He put falsehoods, cynicism, and personal greed at the center of his politics, while expressing disdain for transparency, accountability, and democracy itself. In 2015, Graham described Trump as a “race-baiting, xenophobic, religious bigot” who should “go to hell.” Also as a “nutjob.” When Trump won, Graham understood, as did so many others, that he would have to make some important choices. For a while, he went silent. In the spring of 2016, I saw him at one of those conferences in Europe. He seemed too depressed to speak. But then, like many other Republicans—and, more important, like many other people who have lived under political occupation or experienced radical regime change—he made the decision to abandon his previous ideals, to bury the patriotism that was once so important to him, and to become, instead, a loud, opportunistic collaborator. As I wrote in 2020, it’s very hard to look in to anyone’s heart and to understand their motivations from the outside. But it does seem that Graham had a deep need to be relevant, to be in the game, to be a player, at any cost. And that, rather than any particular achievement, is what he will be remembered for. Continuing to monitor conflicts of interest, ostentatious emoluments, outright corruption and policy changes that will facilitate outright corruption. (Read my original article, Kleptocracy Inc and check out the SNF Agora Institute chart) June 27 Trump diverted funds from more than 900 projects nationwide—including safety upgrades at national parks—to finance beautification projects around Washington, including $700,000 used to fix a White House walkway. June 28 After a years-long Department of Justice investigation into Abbott Laboratories over its management of a baby formula facility where potentially deadly bacteria turned up enough evidence to criminally charge the firm, top department officials instead opted for a financial penalty—illustrating the department’s move away from strict corporate enforcement under the Trump administration. June 29 Defense Secretary Pete Hegseth stacked the Defense Policy Board—which is charged with providing independent national security recommendations to the Office of the Secretary of Defense—with Trump allies, including tech billionaire Marc Andreessen, who has invested in defense contractors like OpenAI and SpaceX, after purging the panel last year. Trump purchased between $1 million and $5 million worth of stock in Axon—which makes about 90% of US tasers—two weeks before ICE solicited bids for a $220 million taser contract. The White House unveiled limited-edition US passports for America’s 250th birthday, featuring a portrait of Trump overlaid on the Declaration of Independence. June 30 Trump made around $1.2 billion from his various crypto companies last year, including more than $500 million from World Liberty Financial and $600 million from sales of his meme coin. Trump is considering issuing 250 pardons to commemorate America’s 250th birthday. These are expected to be largely doled out through the Office of the Pardon Attorney’s informal network of intermediaries. White-collar defense attorneys say they can typically win pardons for clients for $2 million. Last year, Trump administration officials awarded a no-bid contract worth up to $500 million to Clark Construction for the White House ballroom—negotiations in which the president was directly involved. July 1 The Amazon MGM Studios documentary about Melania Trump earned the First Lady more than $10 million. Trump made hundreds of individual stock purchases worth as much as $12.8 million the day before his announcement pausing “Liberation Day” tariffs for 90 days sent the S&P 500 soaring nearly 10%—one of the largest single-day gains ever. Mar-a-Lago and Trump National Doral saw record surges in revenue during Trump’s first year in office, earning $77.5 million and $121.9 million respectively, compared to average annual revenues of $25 million and $75 million during Trump’s first term. Entities across the Persian Gulf paid more than $300 million to Trump’s businesses last year, including $263 million from the sale of half his stake in World Liberty Financial to a firm backed by Sheikh Tahnoon bin Zayed Al Nahyan, a top UAE royal and brother of the country’s president. Kash Patel failed to properly disclose his stock purchase of a Department of Justice contractor, MicroStrategy, worth up to $250,000 last year, despite laws requiring disclosure within 45 days of the trade. July 2 Trump has been directing administration officials to steer more government contracts—so far worth more than $2.4 billion—to Jeff Bezos’s Blue Origin aerospace firm, after Amazon gave $1 million to Trump’s inaugural fund, donated to the White House ballroom project, and reached a $40 million deal to license a Melania Trump documentary. Alongside the billions he made from cryptocurrency last year, Trump earned millions of dollars from real estate licensing fees, including $21 million from organizations in the UAE and $9.2 million in Saudi Arabia, along with smaller sums from merchandise sales, including $4.7 million from Trump Watches and $35,920 from 45 Guitar, a guitar brand endorsed by the president. House Democrats accused consultants tied to the Trump administration of financial fraud, alleging they gave prospective donors to America250—the bipartisan committee created by Congress to celebrate the nation’s semiquincentennial—the banking and routing numbers for Freedom 250, the White House’s fund for events like the UFC cage fight. Democrats also allege that Freedom 250’s CEO traveled to the World Economic Forum in Davos to solicit donations from foreign government officials and business leaders. The Trump administration’s proposed rollback of gun regulations would lift the prohibition on mailing handguns to individuals, a significant win for GrabAGun—the direct-to-consumer firearm retailer on whose board Donald Trump Jr. sits and in which he holds a 1.1% ownership stake. GrabAGun currently must rely on a middleman to transfer firearms to customers. Trump’s financial disclosure revealed that he made more than 21,000 securities trades during his first year back in office, growing his investment account to at least $858 million across stakes in around 1,600 companies, compared to the 13 total trades Joe Biden made during his entire presidency. July 4 Nearly 1 million people who bought the president’s meme coin—Trump Coin—collectively lost $3.8 billion on the token, while he walked away with $636 million. July 6 Shares of Dell closed up 4.4% after Trump recommended people buy the firm’s computers during a speech announcing the launch of Trump investment accounts for children, boosting the more than $1 million worth of shares the president owns in the company. July 9 Federal Reserve Chair Kevin Warsh named crypto investor and Trump ally Marc Andreessen to a task force aimed at modernizing the Federal Reserve, including rethinking its approach to inflation—a key factor keeping interest rates elevated. Palm Beach International Airport has officially changed its name to Trump International Airport—a move that will require Florida to pay royalties to the president’s family for licensing his name. I was there a few months ago, during a trip to Barcelona. The sculptures were a revelation, I’d never seen so many together before. Each one has its own personality. Enjoy the good weather, if you are lucky enough to have it. History Will Judge the Complicit The Quintessential Politician Autocracy Inc Open Letters, from Anne Applebaum is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
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Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
Round Up: Every Switch 1 & 2 Announcement From Summer Game Fest's Weekend Showcases
Stacked showcases
21 Game Pass Titles Get New Announcements At The Xbox Showcase 2026
Talk about a stacked lineup!
LEGO Batman: Legacy Of The Dark Knight Finally Punches Up Switch 2 Release Date
Joining a particularly stacked month
Indie Selects for June 2026: Absolutely Stacked Indie Games
The ID@XBOX team handpicked a bold, genre-hopping lineup of six titles for May's Indie Selects where nothing plays it safe.
Checking in on the NL Cy Young race: Shohei Ohtani, Jacob Misiorowski, Cristopher Sánchez lead a stacked field of contenders
Odds stacked against hosts Fulham for Craven Cottage finale?
Can Fulham be effective against with their last game of the season at Craven Cottage Stadium on Sunday? Both sides have secured Premier League status next season, with the Whites sitting in 13th, level on points but two places behind the Magpies. Fulham have lost six of their past eight Premier League games against Newcastle, although the did manage the double over them last season.
Sony ups its new A7R VI to 66.8 megapixels and jumps the price to $4,500
It now features a fully stacked sensor for faster shooting and 8K video, making it a more do-it-all high-resolution camera.
Sony Alpha 7R VI Announced – 66.8MP Stacked Sensor, 8K 30p, 4K 120p and Sensor-Level Dual Gain
Sony Alpha 7R VI announced with 66.8MP stacked Exmor RS sensor, 8K 30p, 4K 120p video, and new sensor-level Dual Gain mode.
Sony a7R VI Has a Stacked 66.8MP Sensor and Captures 30 FPS Bursts
You got your speed in my resolution! You got your resolution in my speed!
Canon's Full-Frame R6 V Vlogging Camera Shoots Up To 7K RAW Video
It comes with a flip-out display and in-body stabilization, but no stacked sensor or electronic viewfinder.
AMD Ryzen 9 9950X3D2 Dual Edition CPU Is Now Available – The Fastest Dual X3D Stacked Chip On The Planet
AMD launches Ryzen 9 9950X3D2 Dual Edition with 16 cores, 208 MB cache, and 5.6 GHz boost for $899, targeting developers and creators.
UFC Winnipeg: Mike Malott scores 3rd-round TKO of Gilbert Burns, who calls it a career
With the victory, the 34-year-old Malott declared himself a contender in the stacked welterweight division, guaranteeing himself a spot in the top 15 when the rankings come out.
Texas Sports Hall of Fame inducts Class of 2026
Von Miller, Zack Martin, Gary Patterson, and Clint Dempsey headline a stacked 2026 Texas Sports Hall of Fame class.
Sabres seeking two more wins, starting with Blackhawks Monday
With two games remaining in the regular season, the playoff-bound Buffalo Sabres can finish anywhere from first to third in a stacked Atlantic Division.
Arsenal Ratings vs. Bournemouth: Gabriel Martinelli, Kai Havertz Drop Stinkers
Arsenal was second best all over the pitch on a dismal afternoon, who missed out on the opportunity to open up a 12 point gap over rivals Manchester City.
Pension Case Offers Entertainment Work Exception Insights
A recent Ninth Circuit decision clarified that any amount of entertainment work can satisfy the entertainment industry exception under the Multiemployer Pension Plan Amendments Act, reinforcing that statutory language, rather than evolving business models, dictates withdrawal liability outcomes, say attorneys at Seyfarth.
Trump’s ballroom gets the green light from loyalist-stacked commission
President Donald Trump’s sprawling ballroom project officially got the green light on Thursday from a board that oversees planning for federal buildings and land, marking the latest step in an accelerated process that now faces some legal uncertainty.
EU's Ribera: Antitrust Must 'Stay Strong' Against Politics
European Union antitrust chief Teresa Ribera had a word of caution Friday for competition enforcers who let political considerations influence their enforcement decisions, arguing in Washington, D.C., remarks that enforcement should remain stable against shifting political winds.
AMD's Ryzen 9 9950X3D2 Dual Edition crams 208MB of cache into a single chip
Both of the chip's CPU dies will include 64MB of extra cache stacked beneath.
SBJ’s Business of Soccer has stacked lineup
MLS Commissioner Don Garber, FIFA VP and Concacaf President Victor Montagliani and U.S. Soccer President Cindy Parlow Cone will kick off SBJ’s Business of Soccer today at Mercedes-Benz Stadium in Atlanta.
We disagreed on politics. We agreed on wine. That was enough.
At the Virginia Governor’s Cup Gala in Richmond earlier this month, a very dapper gentleman approached me and introduced himself. In his light-colored suit and bowtie, he looked very Southern in a classical sense, the sort of Virginia Gentleman you used to see south of the Rappahannock as recently as my college days. “I’m a longtime reader and fan of your writing, if not your politics,” he said. His comment was the proverbial iron fist in a velvet glove, simultaneously conveying praise and disapproval while establishing boundaries. Man, I wish we still discoursed like this instead of shouting bromides and insults to try and “own” our opponents with a funny meme and a furrowed brow. Subscribe “Well, we’ll always have wine to share together,” I said, and thanked him for his kind words. We clinked glasses, exchanged pleasantries about the delicious gold medal-winning wines being poured that evening, and went our separate ways. Our exchange reminded me that more unites us than divides us. Wine brings people together to share a meal and a few hours of joy despite our differences.1 That’s why I refer to the wine community — including readers and consumers — rather than the wine industry. Together, we are so much more than production, distribution and sales statistics. A few minutes later the evening’s awards ceremony began. Applause grew as the 12 winemakers who made the top-scoring wines for the Governor’s Case took the stage, including a loud cheer for Jonathan Wheeler of Trump Winery and his 2018 Blanc de Noir sparkling wine. All the winemakers on stage had reason to be proud, Wheeler perhaps more so. Trump Winery was the only winery to win six gold medals in the competition this year. (Wineries are limited to six entries.) Two of Wheeler’s ciders also won gold medals in a separate competition. When you cover the labels and take the sour taste of politics off your palate, the wines are pretty darn good.2 Then Gov. Abigail Spanberger, newly elected Democrat and Virginia’s first female governor, was introduced to great applause to announce which of the 12 wines had won the Governor’s Cup. She spoke for a few minutes about the importance of wine to Virginia’s economy and tourism and the international acclaim Virginia wine has received. Just two weeks earlier, she gave the Democrats’ response to Trump’s State of the Union speech, but this night wasn’t about politics. That didn’t stop several people in the crowd from speculating on the irony should she have to present the trophy to Trump Winery. In the end, Valley Road Vineyards was displayed on the screen behind Spanberger as the winning winery. Blue Bee Cidery in Richmond took top honors for that category. The crowd cheered a female governor presenting the state’s highest trophy to a female winemaker and then resumed the evening’s festivities, united by their mutual love of wine. A whiff of politics couldn’t dim the cheer of celebration and a community united by its love of wine. In Memoriam: Michel Rolland The global wine community lost a giant March 20, with the passing of Michel Rolland. He was 78. Rolland was the original “flying winemaker,” a globe-trotting consultant who helped Bordeaux regain its mojo in the 1970s and then shaped the rise of Napa Valley cult Cabernet as consultant to Simi, Harlan, Newton, Screaming Eagle, Araujo, Dalle Valle and other wineries. He was instrumental in Argentina’s rise to prominence and even had his own winery, Clos de los Siete, in a partnership with other wine families. Rolland’s career arc paralleled that of Robert Parker, the world’s most influential critic. Parker championed many of the wines Rolland consulted on, helping build his reputation and demand for his services. It also made him a target for Parker’s critics. As W. Blake Gray wrote on Wine-Searcher in his excellent tribute to Rolland: Rolland created the type of wines Parker loved: rich body, plenty of fruit, soft tannins. He sometimes faced the accusation of creating a generic international style of red wine, where the great wines he made in Argentina were indistinguishable from the great wines he made in France. Rolland chafed at that critique, as did many of his fans. He was credited with championing green harvesting and leaf pulling, as well as careful selection of grapes in the winery, practices we nearly universally think of today for high-quality winemaking. “Michel was an incredible innovator who changed how wine was made and how grapes were grown,” Napa Valley winemaker Aaron Pott wrote on Facebook. “His work has transformed the wine trade. He created new ways of looking at wine, tasting wine, evaluating ripeness and quality. … This was not just a man with a ‘style’ that he imposed on vineyards but a man that understood how to make great wine from great sites.” Rolland started his consulting company in 1973 in Libourne, in Bordeaux, with his wife, Dany. Both had graduated the year before from Bordeaux’s Institute d’Oenologie. The couple sold their majority share in the business in 2020, according to Wine Spectator. Over his career, Rolland reportedly worked with more than 100 wineries in 20 countries. He even made it to Virginia, where he consulted for Kluge Estate in the mid-2000s. (Kluge Estate is now Trump Winery.) Reader feedback, please! Last week, I did my first WineLine Live! with Dr. Laura Catena of Catena Zapata winery in Argentina. We enjoyed a fascinating discussion about her efforts to preserve the genetic heritage of old vineyards in Mendoza. I conceived of WineLine Live! for paid subscribers, as a thank you for your financial support. And while only a few people joined live, the video now has more views than I have paid subscribers, so I guess that’s pretty good. Even so, I’m considering opening future installments to anyone on Substack to reach a broader audience. So my questions to you: Should these be public? And what format do you prefer? Live gives a chat feature with the potential for viewers to interact with me and the guest, while a video post would just be that. Another alternative is a podcast, which would just be audio, without video of my chins. Please let me know in the comments. Leave a comment In the Glass A few wines I’ve enjoyed recently: Bonny Doon Vineyard Take Me to Your Liter, Le Cigare Volant, Red Wine of the Earth. 2023, Central Coast, CA. Blend of Grenache, Syrah Cinsaut and Petite Sirah. Delightful wine with expressive red fruit flavors, casual drinking. Doon lovers of a certain age will remember Randall Grahm’s Big House Red; this is more in that style than his original Le Cigare Volant, modeled after Chateauneuf du Pape. The liter bottle makes it an even better value. I see this online at about $15. Great value. Albert Bichot Bourgogne Pinot Noir Origines 2023. 13% - Textbook pinot noir and an excellent, affordable entry (regional) Burgundy. Wine Enthusiast Top 100 Wines of 2025. $24 at Total Wine & More. Loma Larga Pinot Noir 2021 “Coastal Cool Climate Wine”, Valle de Casablanca, Chile. An older sample, showing beautifully. Spicy and fruit forward. I’m seeing widely varied pricing online, from $18-$32. At the lower end, it’s a terrific value. 13.5% Dr. Loosen Riesling Dry 2016, Mosel, Germany. Found this “in the stack.” And it stacked up well, shedding some of its youthful acidity for opulent Riesling character, including a hint of the mineral oil older Riesling often features. A great value, as I’m seeing it as low as $14 online. 12% abv. Red Tail Ridge Blau Franc Blend 2024, Sans Oak, Finger Lakes. 13.4% abv. The name is a neat portmanteau of Blaufrankisch and Cabernet Franc, thus Blau Franc. The blend is 50-50, no oak involved. The Blau dominates on the palate, with the spicy caraway seed (think New York deli rye bread). The Franc adds body. The result is juicy, energetic and joyful. Sokol Blosser Estate Rosé of Pinot Noir 2025, Dundee Hills, Willamette Valley, Oregon. This first rosé of 2025 was a welcome respite to our cold, snowy winter here in the Mid-Atlantic. Oh man, I needed this! Bright and energetic, exuberant even, it perks up the mood and goes down fast. 13%. Certified B Corp. Ingredient and nutrition labeling, and in a modest way that doesn’t occupy a lot of label space. (Since it’s not required, presumably there are no minimum font size requirements.) More wineries should follow this example. Dave McIntyre's WineLine is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe Thanks for reading Dave McIntyre's WineLine! This post is public so feel free to share it. Share 1 Some restraint may be required. 2 Especially the bubblies.
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