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Patriots set to kick off region slate with unbeaten Science Hill
The most pivotal stretch of the year for the Jefferson County Patriots has officially arrived. This week begins the Patriots’ Region 1-6A slate for the 2026 season, and it gets underway with Science Hill and Dobyns-Bennett, two perennial threats to win the league each year, in back-to-back weeks. “Obviously two football games that are very,
‘All INdiana Politics’: Property tax reform and childcare costs dominate debate in key State Senate race
INDIANAPOLIS — The race for Indiana’s 29th State Senate district has emerged as a focal point for the upcoming elections as candidates compete for an open seat in a key swing district. The vacancy follows State Senator J.D. Ford’s decision to challenge U.S. Representative Victoria Spartz for her seat in Congress. The 29th District stretches […]
Sinkers, Floaters, And Hunters: Carl Sagan Once Proposed There Could Be Gigantic Life On Jupiter, Stretching Kilometers Across
According to Sagan, creatures on Jupiter would be incentivized to grow larger than any in Earth's history. The larger they got, the more advantage they would have.
Mizzou soccer blanked 2-0 in loss to Auburn
Mizzou stretched its SEC winless streak to 12 in a 2-0 loss to Auburn on Thursday night in Columbia.
John E. Sununu pressed on loyalty to Trump in Nashua forum
John E. Sununu pointed to his bipartisan approach to politics during his previous stretch in Congress while answering voter questions in Nashua on Monday.
Vinyl record junkies find a lot to love at Utica's Record Riots
Kirkland was one of hundreds of vinyl record enthusiasts to brave the chilly temperatures Saturday morning, Oct. 17, to attend the Record Riots traveling convention at the Deerfield Fire Station. Based in New Jersey, Record Riots is one of the largest network of vinyl shows in the country, with pop-ups stretching from Utica to Ohio to Virginia. The Utica Record Riot typically takes place three times a year.
The race for NH governor is heating up. Here’s what to know.
As this campaign enters the home stretch, the outcome may hinge on what voters find least distasteful.
Post-Shanghai ATP Power Rankings: Alexander Zverev Takes Charge
As you already know, this is not the ATP rankings list; rather, these are ATP power rankings that combine 2026 results, recent form, performance against elite opposition, current fitness, and the level each player is realistically capable of producing during the final stretch of the season. The picture has changed considerably since our pre-Wimbledon rankings. …
Pony Cars Don't Always Have To Be American-Made
Jensen, Holden, and even Toyota have made automobiles that could easily be considered pony cars if you're willing to stretch the definition a bit.
Trump's team is in chaos as midterms enter final stretch
A White House that has enjoyed relative stability over the past two years has returned to a state of disarray that characterized much of Trump's early political career.
AMC Entertainment Holdings (AMC) Shares Just Moved, So What Is Driving Attention Now?
AMC Entertainment Holdings (AMC) has just refinanced about $3.97b of existing borrowings, rolling them into new first and second lien facilities and notes that run out to 2031 and beyond. The refinancing arrives after a volatile stretch for AMC Entertainment Holdings, with the share price at $2.95 and a 90-day share price return of 54.45%, alongside an 83.23% year-to-date gain that points to building short-term momentum, despite a weaker 3-year total shareholder return of 70.26% and a 5-year...
US services sector activity slows in September; price pressures mount
US services sector activity slowed in September, with strong domestic demand stretching supply chains and raising prices paid by businesses for inputs, indicating that inflation could remain high into next year.
The Pacific Guitarfish May Be Far Rarer Than Scientists Thought
What if a species we thought stretched across thousands of miles of Pacific coastline actually lives in only a fraction of that range? A new look at the Pacific guitarfish suggests exactly that.
Los Angeles Clippers revive ClipperVision for 2026-27 season
Well, there’s at least one good thing about the 2026-2027 NBA season involving the Los Angeles Clippers: ClipperVision is back. The Clippers have had a unique stretch over the last year. Between Chris Paul’s aborted retirement run, an epic collapse to end the season, a quick playoff exit, the cloud of Pablo Torre’s Pulitzer-winning report…
U.S. House Speaker Johnson returns to New Mexico for GOP congressional hopeful's fundraiser
By Patrick Lohmann, Source New Mexico — U.S. House Speaker Mike Johnson (R-La.) made his second New Mexico visit Monday evening in support of Republican Greg Cunningham, where he led a fundraiser in Las Cruces in the final stretch of the closely watched 2nd Congressional District race. Johnson last visited New Mexico in late August […]
House Speaker Mike Johnson draws on faith as he fights to hold the Republican majority
Speaker Mike Johnson says he believes Republicans will hold on to their House majority on Election Day and defy a surge of Democratic momentum in the final stretch of the midterm campaign.
Military & Veterans Campus has new way to build teamwork
On a recent Friday at the Easterseals NH Military & Veterans Campus in Franklin, I found myself about 30 feet in the air. I was holding onto a pole and contemplating what suddenly seemed like a rather narrow log stretching out over a great deal of empty space toward another pole, which also seemed remarkably distant.
Archaeologists reveal huge stretch of ancient Lower Aqueduct into Jerusalem
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BREAKING: Valverde questionable against Villarreal
Real Madrid midfielder Fede Valverde is questionable to face Villarreal this Saturday, coach José Mourinho announced during today’s pre-match press conference. Mourinho did not disclose Valverde’s issue, but it looks like the Uruguayan midfielder could sit this one out as Real Madrid get ready for a crucial stretch of the 2026-27 season. In other news, […]
How will humans of the future be augmented? Six striking ideas from science fiction
From expanded vision to immortal bodies, these screen depictions have all stretched our understanding of what technology could do to humans.
Election homestretch proves politics ain’t softball
One thing that is nearly assured in politics: whatever transgressions of polite behavior or amorous peccadilloes in which one might have indulged is nearly certain to surface during a campaign. Artificial intelligence will make this risk far greater for candidates as it scours the internet for their every video clip, photo, text or public record […]
What the final stretch of the midterms says about the 2028 presidential field
A shake-up of the Democratic primary calendar adds to the intrigue as potential hopefuls join a sprint to help their parties in the midterms.
Maryland fires coach Mike Locksley after 2-5 start, dismal 3-season stretch: Source
Locksley was in his eighth season of this tenure at Maryland and was retained for 2026 after back-to-back 4-8 seasons.
‘These are really tough times’: House Republicans confront voter fury over Trump’s Washington in final midterm stretch
GOP operatives conducting a focus group in a traditionally red Midwestern state this month were shocked by what they heard from Republican voters.
Beijing Zhongke WengeAI Science And Technology (SEHK:1956) Jumped 7%, Is It Fully Priced?
Beijing Zhongke WengeAI Science and Technology (SEHK:1956) drew attention after a sharp 7.4% gain in the latest session, a move that contrasts with its weaker performance over the past month and past three months. The sharp move in Beijing Zhongke WengeAI Science and Technology comes after a tougher stretch, with the share price return down 7.49% over the past month and 22.93% over the past quarter, contributing to a 38.63% year to date share price decline from the current HK$68.55...
Dodgers Remove Kim From NLCS Roster; Add Wrobleski
Prioritizing mound depth for a grueling seven-game stretch, Los Angeles Dodgers' Dave Roberts swaps an infielder for a left-handed pitcher.
The science, instinct and hard work behind Roosters’ success
Enter your email address to get each Tribune edition sent to your inbox Subscribe There’s a fair bit of unseen work that goes into winning an NRL premiership, dating back many months - just ask Simon Jones. The Sydney Roosters Head of Performance, who hails from Southland, has been in the thick of it. He played a lead role in guiding the 2026 champions through a marathon campaign that ended with a grand final win over the Newcastle Knights. The Roosters had to navigate the lengthy round-robin competition, including the pre-season, before playing through all four weeks of the finals series. It was a demanding stretch that tested the players and the staff responsible for keeping them on the field. “It is a hell of a beast, mate, to be honest,” Jones told The Roar Podcast. “There’s such a great group of staff there that know what they’re doing, and the boys are pretty professional.” Jones believed the Roosters managed the physical demands well, pointing to the health of the squad throughout the campaign and the decision to rest a significant portion of the playing group in the final round of the regular season. That call, made by head coach Trent Robinson and his coaching staff, proved valuable as the Roosters entered the finals with some energy in reserve. “We did finish the season physically where we needed to be, and we’d sort of had a pretty healthy squad all year,” Jones said. “To the team that do that, mate, mission accomplished, really.” It is the sort of work that often goes unnoticed when the spotlight falls on the players scoring tries and making match-winning plays, but Jones knows the cumulative effect of those decisions can be significant over a long season. After a win over Penrith had helped establish them as premiership favourites, losses to the Wests Tigers and Dolphins were followed by a defeat to the Panthers in the opening week of the finals. Rather than panic, the club refocused to position itself to challenge for the title. “The Tigers’ performance was probably the only one where you’re really quite disappointed because it’s hard to get to the top of the competition,” Jones told The Roar Podcast. “We had proof that we could; we knew what we needed to do. We just had to get back to that.” For Jones, the answer was not necessarily a radical change to the programme. It was about executing the basics consistently, both on the field and in preparation. “We just do the basics better than anybody else,” he said. “Whether that is actually the way you play the game or how you’re preparing, it’s just be really consistent, do the basics really, really well.” Like many professional sports teams, the Roosters are entrenched in sports science and performance data. The club has access to a range of information, including players’ sleep, GPS metrics and neuromuscular scores, helping staff assess how individuals are coping with training and competition. “We are very science-backed, and some people would say data-driven, but it’s people first,” he said. “The reason you collect all this data is to try and be the best for that person.” Jones said the club was also prepared to reconsider testing methods if they were not generating useful discussions or helping staff make better decisions. In an environment where technology is continually evolving, he believes experience and gut instinct remain important. “The data is no good unless you have conversations,” he said. “When you strip it right back, mate, trust the gut still and obviously, you know, just doing the basics really, really well.” The return of halfback Sam Walker provided a further example of the importance of individual determination and the work of the club’s medical team. Walker underwent ankle surgery late in the regular season, with his premiership campaign appearing in doubt. However, he was determined to return for the preliminary final. Jones said Walker was back at the training ground three days after surgery, walking freely enough to surprise those around him. While the surgeon’s work was crucial, Jones credited the halfback’s mindset as a major factor in the remarkable turnaround. “He was quite clear with Robbo after he got the surgery that he was going to make it back for the prelim finals,” Jones said. The Roosters’ performance programme also sits within a wider club culture that Jones believes is central to their success. Each season, players develop their own team mantra through a lengthy process facilitated by Robinson. It provides principles that the squad can connect to its actions on the field. Rather than simply carrying over the previous year’s wording after a successful campaign, the club repeats the process because the players’ ownership of it is what gives it meaning. “When it’s led, player-owned and player-led, mate, it’s really powerful,” Jones said. Get more from Logan Savory in the Substack app Available for iOS and Android Get the app Jones joined the Roosters in 2024 and said the environment had evolved as experienced players departed and younger members of the squad took on greater responsibility. Maintaining continuity in the club’s culture and preparation had helped the group navigate those changes. The premiership was a significant achievement for Jones, who acknowledged how difficult it was to win the NRL’s ultimate prize. However, he is already looking at how the performance programme can improve. “There’s still things within my role and things that I’d like to help improve at the club,” he said. For Jones and his team, the challenge now is to review the season, refine their systems and prepare for another campaign. The celebrations may have followed a memorable title win, but the work behind the scenes never really stops. The Southland Tribune is a reader-supported publication. To receive new posts and support my work, consider becoming a free or paid subscriber. Subscribe
Buccaneers' Star Says Little on Bowles' Job Security
Tristan Wirfs’ hesitant reaction to questions regarding Todd Bowles’ future highlights the growing tension in Tampa Bay as a dismal 2-11 stretch puts the veteran coach’s tenure at risk.
Rallying in Sao Paulo, Presidential Candidates Seek Votes and Political Support
By Isabel Teles and Luciana Magalhaes SAO PAULO, Oct 11 (Reuters) - With Brazil's polarized presidential election entering its final stretch, candidates rallied supporters and politicians on Sunday in Sao Paulo, the nation's largest state capital, ahead of the October 25 runoff. Conservative ...
What was Austin Wells thinking on costly Yankees baserunning play?
In a measured tone, Austin Wells talked about his decision to stretch a double into a triple in ALDS Game 1.
11 Players Withdraw From WTA Wuhan Open
As the Asian swing continues the final stretch of the season prior to the WTA Finals, a significant number of withdrawals have affected the Wuhan Open just days before the tournament starts. Which Players Withdrew from the WTA Wuhan Open? Elena Rybakina is among the most surprising withdrawals from the tournament. Weeks after becoming World …
Contact with Reddick sends Gaulding spinning at Charlotte
Gray Gaulding spins on the backstretch after contact with Tyler Reddick, bringing out the caution on Lap 205.
Honda’s engine business goes from lawnmowers to jets
Honda’s reach stretches from everyday equipment to business jets, with endurance racing revealing the challenges behind dependable power.
East Colfax businesses look toward revitalization with completion of BRT stretch
Dal researcher Dr. Rita Orji named Fellow of the International Science Council
Latest international recognition caps a remarkable stretch of honours and recognition for the Dal computer scientist, who has emerged as a global leader in responsible and human-centred AI.
MTA axes G train shutdowns planned for December after outcry from small businesses
The dreaded December G train shutdowns have been scrapped, to the relief of business owners and residents in North Brooklyn. Long-overdue repairs initially scheduled to stretch through the end of the year have been finished ahead of schedule, according to the MTA, and though the G still needs some work, it will run like…
Josh Pate Thinks Florida Was Screwed Over in New Rankings
Despite a massive jump to eighth, critics argue the Gators' elite resume deserves more respect. A brutal October stretch will determine if Florida belongs in the playoff conversation.
‘Let Troy be Troy’: How Maine Democrats’ hope to beat Sen. Susan Collins is working to quiet doubters
As Democrats enter the homestretch of their longtime quest to defeat Maine GOP Sen. Susan Collins, they are placing their hope in a fifth-generation logger from the state’s rural north who speaks with a distinct Allagash accent, displays an apparent penchant for boba tea and has never been this close to the national spotlight before.
Claude just found a CRISPR-like DNA pattern, but even Anthropic's scientists aren't sure what it does
The large language model took less than a day to identify the curious stretch of DNA
Official UFC Raoni Barcelos health update
The UFC has provided an official update on bantamweight Raoni Barcelos, after he was stretchered out of the cage at UFC Vegas 121.
Pep Guardiola gives backing to Man City after guilty verdict: ‘We will get through this’
Pep Guardiola has broken his silence after Manchester City were found guilty of the majority of the 115 charges against them, reiterating his backing of the owners and the chairman. An independent commission, which was appointed following a four-year investigation to rule over the charges which stretch between 2009 and 2018, ruled that the current Premier League leaders had "sham contracts" arranged for a number of its commercial partners, finding that their income over eight seasons was “hugely overstated by over £830m”. The club vehemently deny the breaches with chief executive Ferran Soriano branding the process a “Premier League conspiracy theory” in a message to players and staff, while City have confirmed they will appeal against the ruling.
AI midwife seeks to fill gaps in Zimbabwe's maternal health care
With public health services stretched thin, women in Zimbabwe sometimes struggle to access reliable information about pregnancy and childbirth. A locally developed app aims to answer their questions…
Ramaswamy’s ad splits the GOP in Ohio’s closing stretch: From the Politics Desk
Plus, Black voters play a crucial role in the battle for the Senate.
Rafael Navarro Outscoring Messi at St. Louis City
Rafael Navarro has outscored Lionel Messi over the same stretch. Since joining St. Louis City, the Brazilian forward has scored seven goals in six matches — two more than Messi managed for Inter Mia...
Ike Perlmutter helps James Uthmeier stretch fundraising lead in AG race
The business titan and his wife combined to give half a million dollars to the AG's PC.
TV Tinsel: 'NCIS' franchise explores new territory in Big Apple
The long arm of naval law is stretching into the Big Apple as the new “NCIS: New York” premieres on CBS Tuesday and streams on Paramount+ Wednesday. The omnipresent “NCIS”
In Midterm Campaign’s Final Stretch, Trump Can’t Stop Praising Men’s Bodies
As he stumps for midterm candidates, the president has been especially eager to talk about the physical appearance of some men.
A Massive Hole Opened Up in Antarctica. Scientists May Have Finally Figured Out Why
The open-water hole stretched across 34,400 square miles, or roughly the size of Portugal.
WATCH: NASA launches Crew-13 to International Space Station
Four astronauts rocketed into orbit Thursday on a space station mission that will stretch until spring, among them a Canadian whose wife will give birth while he’s away.
‘We don’t want this right now’: James Talarico off the trail with the flu for 12 days
In final stretch of the Texas Senate race, Talarico has not appeared in person since Sept. 26; he is expected to be back this weekend. Opponent Ken Paxton is calling for “proof of life.”
Buccaneers' Star Says Little on Bowles' Job Security
Tristan Wirfs’ hesitant reaction to questions regarding Todd Bowles’ future highlights the growing tension in Tampa Bay as a dismal 2-11 stretch puts the veteran coach’s tenure at risk.
The Chase still has NASCAR chasing its former viewership
While NASCAR reintroduced its final stretch run, The Chase, to rekindle postseason interest, viewership for the races has remained lackluster. Over six races, the 2026 NASCAR Cup Series Chase averages 1.62 million viewers, up just 1% year over year (1.61 million), per NASCAR Communications. So far, The Chase hasn’t delivered the viewership renaissance NASCAR hoped…
Messi goal not enough to end Inter Miami's winless run
Lionel Messi's 21st league goal of the season was not enough to stop Inter Miami falling to a 2-1 defeat at Columbus. The teams were tied at 1-1 nine minutes into stoppage time before Jamal Thiare grabbed a late winner to stretch Miami's winless run in the MLS to five games.
Unlock free AI tools for your small business through UH Maui College webinar
Small business owners and sole proprietors across Hawaiʻi are invited to learn how autonomous AI tools can streamline operations, save time and stretch limited resources in an upcoming free webinar offered by University of Hawaiʻi Maui College.
What to watch in the CNN & Jubilee town hall with James Talarico
James Talarico’s bid to become the first Democrat in a generation to win statewide in Texas after three decades of disappointments is in its final stretch.
Film Room: What’s Wrong With the Steelers Offense?
The Pittsburgh Steelers offense is off to an anemic start, with the third-worst opening stretch among all teams in EPA/play […]
Brookfield Business (TSX:BBUC) Rebound Hopes Meet A Fair Value Reality Check
Brookfield Business (TSX:BBUC) has been drawing attention after its share price closed at CA$35.96, with recent returns showing mixed momentum over the past week, month, and past 3 months for investors tracking the stock. For context, Brookfield Business is coming off a weak stretch, with the share price down 27.31% year to date and 15.15% over the past 3 months. However, the 3-year total shareholder return of 84.94% still points to a much stronger longer-term outcome than the recent pullback...
Riders see improvements, businesses struggle as Maryland Parkway construction stretches on
While some RTC riders say service has improved, local business owners say the ongoing construction is still hurting their bottom line.
Tough stretch will define Raiders’ schedule
Las Vegas’ schedule will get more difficult starting in Week 4
New eligibility rules may stretch NRF, science minister says
Blade Nzimande admits regulations expanding pool of potential beneficiaries might put pressure on grants budget
Flutter Entertainment (FLUT) Could Be 40% Undervalued On Revenue Beat And EPS Miss
Flutter Entertainment (FLUT) just delivered a mixed earnings update that drew a sharp response from the market, with revenue ahead of analyst expectations but earnings per share falling well short of forecasts. That miss on profitability lands on top of a weak stretch for Flutter Entertainment, with the share price down 18.23% over the past 30 days and falling 61.87% year to date. The 1-year total shareholder return has declined 70.29%, suggesting momentum has been fading as investors...
Honda’s engine business goes from lawnmowers to jets
Honda’s reach stretches from everyday equipment to business jets, with endurance racing revealing the challenges behind dependable power.
Pope celebrates giant Paris Mass in landmark visit
Some 700,000 people had gathered over a stretch of more than two kilometres in central Paris
In this vast stretch of northern Minnesota, shifting politics make every vote count
A state Senate rematch and a closely watched House race has a once-reliable DFL stronghold in northeastern Minnesota at the center of the fight for control of the Legislature.
UCF’s Scott Frost Shares Injury Updates After Houston Loss
Keyone Jenkins battles through late-game scares and center Jacob Maiava undergoes X-rays as the Knights’ depth chart thins ahead of a grueling stretch against ranked conference opponents.
FSU May Be Finding the Consistency Norvell Has Been Chasing
Florida State may finally be finding consistency, responding to adversity with dominant stretches and showing growth on both sides of the ball.
This Guy Is Endurance-Racing 1:64 Diecast Cars On A Belt Sander And The Cars Have Been Running 29 Days Nonstop - Watch Live!
A clever youtuber is racing 1.64 ("Hot Wheels sized") cars using a belt sander as a treadmill/road for endurance races that stretch on for weeks
San Antonio-area Week 7 high school football schedule
Teams are about to begin the home stretch and their push to toward the playoffs. Here is the high school football schedule for Week 7
Experts Recommend Ways To Stretch Vaccine Supplies In Face Of Dwindling Budgets
In the face of dwindling health budgets, the World Health Organization’s (WHO) expert committee on immunisation has made several suggestions to enable
House Speaker Mike Johnson draws on faith as he fights to hold the Republican majority
Ever the optimist, Speaker Mike Johnson said he believes Republicans will hold on to their U.S. House majority, defying a surge of Democratic momentum in the final stretch of the midterm elections that will determine control of Congress.
Cookies, liquor and mocking Nazis fuel final stretch in fiery Texas House race
Katy Padilla Stout's Texas Democratic campaign reported over $4,300 in cookies, beer and wine, and Mexican restaurant spending per FEC records.
In the midterm ad wars, Republicans are spending more to get less
Republicans are spending hundreds of millions of dollars on advertising in battleground Senate races as they scramble to defend increasingly competitive GOP seats in the final stretch of the midterms.
Packers’ Josh Jacobs Saga Drags On With Latest Legal News
The waiting game surrounding Green Bay Packers running back Josh Jacobs keeps stretching further, and the latest development doesn’t mark an end in sight.ESPN’s Rob Demovsky reported Tuesday that the Hobart-Lawrence Police Department completed its review of records tied to Jacobs’ case and determined that “certain records could be released with appropriate redactions.” An update […] The post Packers’ Josh Jacobs Saga Drags On With Latest Legal News appeared first on HEAVY.
Roma leading Serie A in high ball recoveries
Gian Piero Gasperini can look at his Roma’s performances and see exactly what his playing style is. For long stretches of their first five league games, the Giallorossi prevented their opponents fro...
Red River Rivalry: OU quarterback John Mateer will 'never forget' his redemption over Texas
DALLAS — John Mateer stood atop the Schooner wagon with a smile stretched across his face. Beaming, he received the “golden hat” and encapsulated the feeling of taking down No.
Philly fans anxious, excited during busy sports stretch
It's a busy time for Philadelphia sports fans.
Welcome to the home stretch
💰 And a first look at an unusual new spending effort on behalf of U.S. Rep. Brian Fitzpatrick.
Official UFC Raoni Barcelos health update
The UFC has provided an official update on bantamweight Raoni Barcelos, after he was stretchered out of the cage at UFC Vegas 121.
House Speaker Mike Johnson draws on faith as he fights to hold the Republican majority
Speaker Mike Johnson says he believes Republicans will hold on to their House majority on election day and defy a surge of Democratic momentum in the final stretch of the midterm campaign
Green Bluff growers rely on fall festival profits
For the dozens of independent growers of Green Bluff, October isn't just pumpkin season — it's the four-week stretch that determines whether farms turn a profit or end the year in the red. Following a summer marked by wildfire smoke, high well-water pumping costs, and rising inflation, farmers are…
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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