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Beyond Finger Pointing: The Fight to Lower Health Care Costs
In a live conversation recorded at Aspen Ideas: Health, executives from a hospital, insurer and pharmacy join a top Trump administration official and leading health economist to discuss how to collectively bring down health care costs.
911 Fails People in Mental Health Crises. Here's a Plan to Fix It.
911 calls related to mental health are the most likely to involve police use of force. A new book offers a blueprint for a 911 redesign that could save lives.
How will tax ballot issues affect you?
What if you temporarily had the power to decide what our state spends its money on? Try Colorado Tradeoffs.
Paid Leave at a Crossroads: Business Leadership, Caregiving, and the Power of Story | National Partnership for Women & Families
Every day, working people across the country wake up already making tradeoffs. They plan their commutes around childcare drop-offs, take calls from doctors' offices during lunch breaks, and quietly calculate how many sick days they have left if something goes wrong. For millions of caregivers, work and care are not separate parts of life — they are deeply intertwined, often in ways that leave little margin for error.
The NCAA idea that could reshape college sports: 'It's not a tweak, it's a structural shift'
NCAA’s five-year eligibility bet: Simpler rules, cleaner rosters, new tradeoffs. USA TODAY Sports canvassed college sports stakeholders on proposal.
Live Nation Entertainment (LYV) And The Valuation Debate Around Its Global Expansion Story
Event backdrop and what is worrying investors Live Nation Entertainment (LYV), owner of Ticketmaster and the EDC music festival, is under scrutiny as slower sales growth, rising capital intensity and pressure on operating margins raise fresh questions about the stock’s risk and reward tradeoff. See our latest analysis for Live Nation Entertainment. Live Nation Entertainment’s share price has climbed over the past year, with a year to date share price return of 21.97% and a 1 year total...
Lankas turns multi-disciplinary drive at Nebraska Into Hudl career
“I’ve always been super passionate about dance, sports, academics, entrepreneurship and keeping my social life interesting. When searching for colleges, it can sometimes feel like you’re having to settle for less in one area to get more in another. However, as an overly ambitious person, those weren’t really tradeoffs I wanted to make, and I’ve been able to do so much at such a high level all at Nebraska.” — Lena Lankas, May 2026 graduate
Your Thymus and Your Healthspan
Our thymus gland plays a central role in the development or our immune system, specifically for supporting T cell development (how these cells got their name, maturation and differentiation in the thymus) and discriminating between self and foreign, non-self antigen proteins with production of dendritic cells. As we age, our thymus gland shrinks—the process known as involution—with progressive change from spongy to fatty tissue, with loss of functionality. But this process, with respect to timeline and extent, markedly varies from one person to the next. And to make things even more complicated, our thymus gland anatomy and precise location in the chest also is highly variable. So the famous Frank Netter diagrams from the 1960s (such as at left below) don’t capture the remarkable heterogeneity that a random set of 12 chest CT scans (below at right). What I consider as 2 landmark papers in Nature this week (here and here) used AI to quantify health of the thymus in 2 large cohorts, and then correlate the metric to a broad array of health outcomes. In this edition of Ground Truths, I’m going to cover three questions: (1) How was thymus health determined by AI?; (2) How is thymus health linked to key clinical outcomes? and (3) Are there ways we can promote a healthy (aka rejuvenate) thymus gland in our later years? Subscribe 1. How was thymus health determined by AI? This was accomplished by extensive work developing and validating an AI pipeline for 2 stages, the first for localization and segmentation of the thymus bed, and the second to quantify a digital marker, termed the thymic health score. There’s a lot to this algorithmic development, so I won’t go into all the details, but just provide a rudimentary outline of what was done. The 1st stage used supervised learning with 2 radiologists reviewing 2,461 chest CT scans. That work trained a 3D U-Net model to automatically identify the thymic bed’s 3D cropped region using center of mass coordinates, which reached 99.8% accuracy. The 2nd stage used a foundation model that was pre-trained with SwAV (which stands for Swapping Assignment between multiple Views), a self-supervised model, that generated a high-dimensional thymus representation of 4,096 features. That compares to the radiology reductionist and subjective scoring of 0 to 3 where 0 means the thymus is fully degenerated and fatty, and 3 is considered dense, intact glandular soft tissue. Notably, the self-supervised learning (SSL) performance was superior to supervised (AUC ~0.75 vs 0.55, respectively) reflecting the shallowness of the 0-3 classifier vs SSL’s holistic, self-taught AI. The thymic health score ranged from 0 to 100, with the highest number indexed to fully preserved thymic health. The algorithmic work extended to explainability with both Shapely value distribution, meaning the model was holistic not relying on any “magic” pixel, and occlusion sensitivity, demonstrating the model’s performance was not affected by ribs, sternum, lung tissue, but rather focused on the thymic bed directly. Below are a few saliency maps from the occlusion sensitivity that indicate the thymic bed focus, not affected by neighboring structures, using the jet color scale. Now the AI was ready for processing ~25,000 CT scans, each over 30 MB files, from the 2 large participant cohorts to provide a thymic health score, it did so in less than 14 hours, which is less than 2 seconds per scan! Share 2. How is thymus health linked to key clinical outcomes? The two cohorts were the National Lung Screening Trial, NLST (N=25,031) and the Framingham Heart Study, FHS (N=2,581) each with baseline demographics and long term follow up of >12 years for health outcomes. From the NSLT, you can see below that increased age and body-mass index were correlated to reduced thymic health. And, overall, men had reduced thymic health scores compared with women. There are a lot of graphs in the paper for outcomes, for both the NLST and FHS cohorts. To simplify the major outcomes, below is a composite Figure with striking reduction of all-cause mortality and for the different causes of death. The results were consistent between the 2 cohorts. For example, the cardiovascular mortality hazard ratio average was 0.57 in NLST and 0.38 in FHS (weighted to be 0.53 for the aggregate). The reduction of mortality also extended to digestive diseases and pulmonary disease (data not shown below). Lung cancer incidence was reduced by 36% for high vs low thymic health (Figure below, with a panel -incidence and b panel-mortality, adjusted for age, sex, BMI, smoking status). Notably, there was a smoker’s paradox: lower incidence and improved survival for lung cancer in smokers who had a high thymus health score. Smoking was associated with lower thymic scores whereas alcohol was not. Higher thymic health was linked to higher HDL cholesterol, lower triglycerides, lower fasting blood glucose, and lower systolic and diastolic blood pressure. Inflammation biomarkers, such as C-reactive protein and interleukin-6, were elevated in the people with lower thymic health scores. In their second paper, the same team looked at the relationship between thymic score and outcomes for 3,476 patients receiving cancer immunotherapy. The non-small cell lung cancer progression-free survival was reduced in patients with low thymic health score. A parallel relationship for survival was seen for other types of cancer including melanoma, breast, and kidney with a 44% lower risk among high thymic scores (Figure). A similar pattern was seen with different immune checkpoint inhibitors. The thymus health score outperformed programmed death ligand-1 (PD-L1)and tumor mutation burden (TMB) assay of the tumor and was an independent prognostic marker of progression-free survival. In this dataset, a direct connect with thymus score and adaptive immune function was noted with a correlation before cancer treatment for both T-cell diversity and thymus T-cell production (a metric known as T cell receptor excision circles). Thymus Removal Study There is a highly relevant citation about thymus function before moving onto ways to rejuvenate it. In 2023, a very important study of thymus removal during cardiothoracic surgery was published, with 1146 patients undergoing thymus removal vs 1146 matched controls (mean age 55 years). The adverse outcomes for thymus removal were striking, with a 2.9 higher risk of all-cause mortality and doubling of cancer incidence, 1.5 fold increase in cancer mortality, and 1.5-fold increase in autoimmune diseases. The immune function showed marked compromise after thymus removal, as reflected by CD4+ and CD8+ T cells (Figure below) Share Ground Truths 3. Are there ways we can promote a healthy (aka rejuvenate) thymus gland in our later years? In recent months we’ve learned a lot about the process of thymus involution and the pathways by which this may be modulated. Thymus involution is primarily due to loss to thymus epithelial cells (TECs) and there are 2 subtypes with different functions: the cortical, responsible for positive selection of T cells, and the medullary, for negative selection. When adipose tissue infiltrates the thymus, thymic adipocytes are pro-inflammatory, knocking out T-cell output. Likewise, systemic inflammation, or “inflammaging,” from smoking, obesity, and chronic stress promote thymic adipocytes. Now, from preclinical studies, we know about key pathways that account for these processes. Historically, back in 2014, FOXN1 was recognized as a single master transcription factor essential for TEC function, with studies in mice with forced FOXN1 upregulation leading to thymus regeneration. That laid the foundation for potential regrowth of quiescent thymus cells. It took awhile to find pathways to accomplish this goal and to even refute its role as the master regulator. The Liver-Thymus Axis Feng Zhang and his team recently showed that injection of an mRNA vaccine to the liver encoding DLL1, IL-7 and FLT3-L in combination, factors known to support thymopoiesis (Figure), successfully enhanced immune function in aged mice. However, the effect was transient. The FGF21 Story Two reports in 2025 addressed the thymus gland’s production of FGF21, a growth factor (fibroblast growth factor 21) and its control of thymus involution. This growth factor is also produced by the liver, but it doesn’t have impact on the thymus in aged rodent models. In contrast, The liver’s hepatocyte growth factor (HGF) has been shown to reverse senescent TEC structural changes. Growth hormone stimulates production of insulin growth factor-1 (IGF-1) in the liver and the thymus. Two small studies in human participants (TRIIM, for Thymus Regeneration, Immunorestoration, and Insulin Mitigation) of 6 and 50 people, respectively, treated with combined human growth hormone, metformin and DHEA, suggested the potential of slowing epigenetic aging and improving thymus mass and function. But the combination of drugs, small sample, and lack of controls make conclusions murky. Increased thymus FGF21 led to increased CD8 T cells in old mice and extended healthspan and improved physical performance. Building on the previous FOXN1 data, ablation of β-klotho, the obligatory co-receptor for FOXN1, accelerated thymic aging. The benefit to FGF21 was confirmed in a companion paper using an FGF21 knock-in mouse model showing thymus enlargement and increased TECs throughout the lifespan. (schematic Figure below). The accompanying editorial for these 2 papers speculated: “The proposed link between age-associated thymus involution and organismal aging is intriguing, and suggests we might seek to achieve systemic rejuvenation by counteracting thymic involution.” Other Factors Lessons from the Axolotl (Mexican Salamander) In an elegant set of experiments of the axolotl (Figure), known for its complete thymus regeneration after total surgical removal, mediators were identified. Surprisingly FOXN1 was dispensable. But midkine, a growth factor, appeared to be the driver, the initiator of thymus cell growth, survival, and repair. Other components that contributed were Postn+ (periostin-expressing mesenchymal niches) and Ccl19, a chemokine protein from the bloodstream. RANK and RANKL RANK (receptor activator of nuclear factor κB its ligand (RANKL) have been considered key regulators of medullary TECs. In a study of both aged mice and human thymus cell cultures, their key role was confirmed, with multiple benefits of resorting TEC function, recruitment of progenitor cells, and T cell development. Subscribe Summing Up This body of work strongly supports the health of the thymus gland as a critical regulator of human healthspan, not just a correlate or link. The new landmark studies are reinforced by the regenerative biology experimental models that have shown, via an array of mediators, that healthspan of aged mice is at least in part dependent on thymus gland function and its critical role for maintaining adaptive immunity. It sure seems that we’d be better off having an immune reservoir of naive T cells instead of a profile in older adults of exhausted, low quality, memory T cells, with a senescent phenotype. It is striking that we ignored the importance of the thymus gland for many decades. A wake-up call was the results of the thymectomy matched control study reviewed here, with the opposite of high thymic health score improved health outcomes. The convergence of AI and healthspan here is notable. The exceptional and laborious work for developing and validating (no less explaining) the AI to quantify thymus health set the foundation for probing the connect the major health outcomes in two cohorts with extensive follow-up. We’ve never had a way to meaningfully quantify the thymus gland before, so this represents important leverage of supervised, self-supervised, and transformer models. The study wouldn’t have been possible without AI. And it begs the question as to whether there are ways we can maintain our thymus at a high health score. But it’s not so simple to rejuvenate our thymus. There are multiple risks including the induction of autoimmunity, increasing the risk of cancer, and inducing a pro-inflammatory state. For example, factors that increase TEC proliferation could compromise the medulllary negative selection process and leak out auto-reactive (self-attacking) T cells. Thymic cells could be induced to proliferate, but we know, for example, that growth hormone and IGF-1 are associated with an increase risk of cancer. If thymus rejuvenation doesn’t clear out the accumulated senescent cells in older adults, then inflammation within the gland could block the production of TECs. Keeping these risks in mind, we now have identified many ways to keep our thymus healthy as we age that undoubtedly will be tested in clinical trials going forward. Ultimately, the benefit-to-risk tradeoffs will be defined. In the meantime, we have desperately needed an immunome. As I’ve stressed in multiple prior Ground Truths, we have no test in the clinic to assess a patient’s immune status! It was very encouraging for me to get an email from Hugo Aerts, the senior author of the landmark papers in the days after they were published: “I also wanted to say that your Substack on “Why We Need an Immunome” was inspiring for this work. We found it a very compelling perspective and greatly enjoyed reading it.” Just having an assessment of a person’s immune status via a chest CT scan, with millions of these performed per year, might help in guiding the right immunotherapy for cancer (e.g. more intensive, combinations for those with low thymic health scores) and help define people who are increased risk for age-related diseases of cancer, cardiovascular, and neurodegenerative. The main theme of Super Agers is that we now have many layers of data (genetics, proteins, biomarkers, organ clocks that can be integrated via multimodal AI) for us to define a person’s specific risk decades before one of these age-related diseases leads to symptoms, enabling prevention. From the new studies this week, we can add thymus health score as yet another way to understand a person’s risk, a window into their adaptive immune system and healthspan. And perhaps someday we will be able to safely rejuvenate the thymus, or maintain its health through one’s life, and use the thymus health score to monitor. NB: I wrote this post (No A.I.) A Quick Poll Loading... ********************************************************************* Thanks to Ground Truths subscribers (now > 200,000) from every US state and 212 countries. Your subscription to these free essays and podcasts makes my work in putting them together worthwhile. Please join! If you found this interesting PLEASE share it! Share Ground Truths Paid subscriptions are voluntary and all proceeds from them go to support Scripps Research. They do allow for posting comments and questions, which I do my best to respond to. Please don’t hesitate to post comments and give me feedback. Let me know topics that you would like to see covered. Leave a comment Many thanks to those who have contributed—they have greatly helped fund our summer internship programs for the past two years. It enabled us to accept and support 47 summer interns in 2025! We aim to accept even more of the several thousand who will apply for summer 2026.
Reimagining the Future of Health Research After Sweeping Cuts
The Trump administration’s decimation of the Agency for Healthcare Research and Quality has many academics deeply concerned.
The myth of the innovation tradeoff: Our chemical safety law protects health without stifling progress
The Toxic Substances Control Act is the primary safety law protecting Americans from harmful chemicals in everyday products. Bipartisan updates in 2016 strengthened the law by giving EPA the authority and responsibility to evaluate new chemicals more effectively, and to protect vulnerable populations, including children, pregnant women and those who work at or live by
New Year's Predictions: What Business School Thought Leaders Say About 2026
Business school leaders see 2026 as a year of sharper choices – and clearer tradeoffs – for management education.
Affordability and Preventive Public Health Policy
Affordability pressures increasingly shape health risk in the United States, influencing both the upstream conditions that sustain health and the downstream ability to access health promoting resources. Financial stability is a key driver of health, affecting patterns of health, health care use, and the tradeoffs people must make among competing needs. The economic policy landscape aimed at improving financial security for Americans is expansive, complex, and often difficult to organize, making it challenging to discuss how different policies influence financial resilience and population health. We propose the Earn–Keep–Grow framework as a practical way to organize and guide discussion of these policies in population health research and policy decision-making.
Mental Health Courts Offer People Facing Prison an Imperfect Alternative
Hundreds of U.S. courts offer treatment over prison for some defendants with mental illness. But critics say mental health courts have outpaced research on their effectiveness.
Funding “Rural Health Care Transformation” Without Shoring Up Failing Hospitals
The unusual policy symmetry involved in the Big Beautiful Bill’s Medicaid cuts and new rural health innovation initiative may not bode well for rural health care quality and outcomes.
Combining AI And Human Judgment In Strategic Business Decisions
Strategic decisions require human judgment on capital-labor tradeoffs, future flexibility, and safety standards—areas where AI provides data but humans drive choices
The Rise of AI Reasoning Models Comes With a Big Energy Tradeoff
Nearly all leading artificial intelligence developers are focused on building AI models that mimic the way humans reason, but new research shows these cutting-edge systems can be far more energy intensive, adding to concerns about AI’s strain on power grids.
Butterfat, Bots, and Bureaucrats: The Limits of Optimization
Across various fields, we constantly attempt to refine, control, and optimize complex systems. But whether it’s chatbots reshaping beliefs, cows engineered for more nutritious milk, drugs that suppress desire, or regulators chasing vanishingly small risks, each effort reveals the same tension: control involves tradeoffs. The issue isn’t whether optimization works—it’s what it costs and whether we notice it in time.
Employment or autonomy? Comparing pathways and tradeoffs for PCPs
Primary care physicians who are on the payrolls of hospitals and health systems enjoy well-supported practice infrastructure and robust peer engagement. But they’re sometimes vexed by red tape and style-cramping oversight. Meanwhile independent PCPs …
Immigration Enforcement’s Twin Threats to Health Care
Patients are afraid to show up to medical appointments, while workers are being detained, deported or losing their visa statuses.
Trump blasted Obama’s Iran deal. Now he faces similar tradeoffs.
As U.S. envoys pursue peace talks, the president confronts persistent sticking points: sanctions relief, enrichment limits and the risk of empowering Tehran.
What You Need to Know About the New $50 Billion Rural Health Fund
The Trump administration recently announced how much money each state will receive under an ambitious 5-year initiative known as the Rural Health Transformation Program.
States Are Forcing Hospitals To Offer More People Financial Aid. In Oregon, It’s Working.
Oregon passed a law to require hospitals to proactively screen patients to see if they qualify for financial aid. Patients got immediate relief. Hospitals pushed to roll back the law following federal cuts to Medicaid and Affordable Care Act subsidies.
Anthropic says 'we made the wrong tradeoff' in new model guardrails
"We're changing Fable 5's safeguards for frontier LLM development to make them visible," an Anthropic spokesperson said.
Review: AMD's Ryzen 7 9850X3D is a little faster and a lot more power-hungry
The tradeoffs for the $499 9850X3D make it hard to get excited about.
Trump officials push for skimpier coverage in ACA marketplaces
The Trump administration wants the 2027 ACA marketplace to offer plans with lower premiums — but the tradeoff is high deductibles and risk for those needing care.
Breaking Down Trump's $50 Billion Rural Health Fund
Rural health experts dig into the Trump administration’s effort to transform rural health care.
High Health Care Costs Are Fueling a New Fight Over Old Laws
The White House wants states to drop certificate of need laws in hopes of lowering health care costs. Researchers and state leaders are split.
Medical Debt Is Crushing Hospital Patients in Los Angeles. Public Health Officials May Have a Fix.
In Los Angeles County, the nation’s most populous, a new system could screen hospital patients for financial aid, preventing hundreds of thousands from getting bills they can’t pay.
Inside Maryland’s High-Stakes Bid for Trump’s $50 Billion Rural Health Fund
The White House asked states to compete for a rare pot of new money dedicated to transforming health care across rural America.
The Real Truth About The Upsides And Downsides Of Generative AI As A Mental Health Advisor
Most discussions about AI that's used for mental health is tilted to one side or the other, either its good or its bad. The full story is a tradeoff. An AI Insider scoop.
Californians are ‘really losing sleep’ over this financial burden
Medical bills have become Californians’ top financial worry, a new survey finds, with many saying health care costs are forcing them to delay care and make painful tradeoffs.
Employer health costs are set to jump the most since 2003—and even health care workers are struggling to afford care
Nurses, doctors and medical practices are making difficult tradeoffs as premiums rise and health benefits consume more of household budgets.
7 Takeaways From an Investigation Into Financial Aid at Texas Hospitals
Hospitals can prevent medical debt by preemptively wiping out a patient’s bill. But a Tradeoffs analysis finds that few nonprofit facilities in Texas use this tool to the maximum benefit of patients.
7 Takeaways From an Investigation Into Financial Aid at Texas Hospitals
Hospitals can prevent medical debt by preemptively wiping out a patient’s bill. But a Tradeoffs analysis finds that few nonprofit facilities in Texas use this tool to the maximum benefit of patients.
Making Medical Decisions with Uncertain Science
What is the best way to make medical and health policy choices in the face of uncertainty? That question was the focus of the Tradeoffs podcast and an Aspen Ideas: Health panel.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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Rising housing costs in Bexar County tied to growing public health crisis
As housing costs climb across Bexar County, data from Metro Health reveals families are increasingly forced to choose between housing and healthcare — a tradeoff now being linked to worsening physical and mental health outcomes.
Engrams Embedding Entendre: Codesign for Efficient DRAM/SSD Offloading
Engram extends standard token embeddings with learned multi-token lookups. Recurring local patterns retrieve vectors directly, reducing the need to reconstruct them through attention and feed-forward layers. With Engram model architecture optimization, it allows for lower HBM capacity to be needed for models at the same quality. This does not mean there won’t be an insane demand for HBM but it just means that model architecture will continue to innovate around constraints. This model architecture design is naturally codesigned for parameter offloading: each token accesses a few embedding rows whose addresses depend on token IDs, not hidden states. The runtime can prefetch those rows from host DRAM while earlier layers compute, keeping the table outside HBM without transferring entire weight matrices. Our Memory model contains our latest estimates of quarter by quarter HBM, DRAM, & NAND supply and demand. Offloading frees HBM for model weights and KV cache, potentially supporting larger batches or more concurrent sessions. When DRAM becomes the next constraint, NVMe offers another tier. Recommendation systems already cache frequently or recently accessed embedding rows in faster memory while backing colder rows with SSDs. After NVIDIA roadmap had to change due to massively despec’ing Rubin Ultra from 1024GB to now ~200GB of HBM per chip, model architecture optimizations like emgram maybe helpful. Our DeepSeek-V4.1-Flash configuration uses roughly 189 GiB of memory for Engram. We replace it with a memory-mapped (mmap) file and measure serving performance with offload to SSD. Later on in our report, we will show our Engram offloading experiments along with the official InferenceX agentic inference serving results on Engram models like DeepSeekv4.1 Flash across all 6 NVIDIA GPU SKUs along with MI355X. Unsurprisingly, the CUDA Moat is still mogging MI355X on the ultra popular DeepSeekV4.1 Flash model. We also show how even on high capacity HBM SKUs, offloading emgrams to DRAM could result in even better performance for most of the pareto than keeping the emgram in HBM. Our benchmark has been widely reproduced, validated and/or supported by almost every major buyer of compute from Google Cloud to Microsoft Azure to Oracle, to Meta and many more. Furthermore, it has the support of the ML community including from vLLM, LMCache, SGLang, PyTorch, Huggingface and the support of major labs like OpenAI, MiniMax, ZAI, Qwen, Moonshot Kimi, etc. Star the InferenceX GitHub repository if you find the open-source benchmark and data useful!. InferenceX is the only inference benchmark in the world to have TPUv7, Jalapeño, Nvidia Rubin NVL72, AMD, and soon, SambaNova and Trainium. Due to how realistic AgentX scenario is to real world agentic inference workloads, AMD has committed to collaborating on MI455X UALoE72 too. DeepSeek did not release the original paper’s two trained Engram models. We replicated its setup on fineweb-edu using the released code and training hyperparameters, at an estimated 6E18 FLOPs per run. We observed the same U-shape scaling: Engram improved performance over pure MoE baselines. We also reproduced DeepSeek’s results, where earlier-layer representations with Engram resembled those of later layers. Like the original Engram paper, it is possible to probe Engram’s gate scores to see what n-grams DeepSeek-V4.1-Flash makes the most use of. Our gate scan finds names, code fragments, relational phrasing, and boilerplate. These examples prioritize interesting-ness over gate strength. One unexpected result was Wright : Ace Attorney. These examples suggest learned memory optimizes the training objective, not a judgment of which facts deserve storage. Licenses, bibliography fragments, API scaffolding, and website furniture can provide prediction shortcuts, so the value of additional Engram capacity may depend on what survives data preparation. This does not show that table capacity is “wasted”: the evaluation-corpus scan establishes neither training exposure nor the capacity occupied by each category. For offloading, strong gates do not identify cache-hot rows. Low gates do not automatically save reads either: computing the gate requires the retrieved key and undoes the performance gain of a fused kernel. Skipping reads would require a separate usefulness predictor before retrieval. In the original paper’s inference-time ablation, factual-knowledge benchmarks retained just 29–44% of their original performance, while reading comprehension retained 81–93%. This is due to the training–inference mismatch. The resulting degradation therefore measures this trained model’s dependence on Engram, not the performance difference between models trained with and without it. In our ablations, suppressing Engram worsens token likelihood across all evaluated domains, especially encyclopedia text and several code corpora. Surprisingly, GSM8K accuracy stays within measured run-to-run variation and removing Engram has no effect. Engram is not a detachable dictionary beside an unchanged MoE. Removing it changes downstream features and expert selection. We tested whether rerouting hurts or compensates by holding tokens fixed in a teacher-forced experiment on CRUXEval, a code-reasoning benchmark of small Python functions where the model predicts a function’s output from its code and an input, and scoring the reference answer. Removing Engram raised answer loss from 0.2848 to 0.3093 bits/token. Forcing the ablated model to use the original Engram-on expert choices made it worse still, at 0.3375 bits/token. Rerouting partially compensates for the missing memory. Memory features and expert selection work together, rather than following a clean “memory stores facts; experts reason” division. On the same CRUXeval, removing Engram during either phase reduced accuracy and increased generated tokens; removing it throughout produced the largest changes. Keeping Engram for prefill leads to more correct answers than keeping for decode likely due to semantically richer KV cache transferred to decode workers, allowing it to mitigate some of the performance loss. Engram’s table is large, but each lookup is small. DeepSeek-V4.1-Flash requests 24 rows at each of two Engram layers, about 12.4 KiB per processed token position across the model, or 3.1 KiB per GPU when split across four GPUs. Currently as of Day 7 since Model Release, MI355X is still 2-4x worse performance per dollar compared to B200 even when normalized by Mi355X’s lower TCO. Our full total cost of ownership breakdown comes from our AI Cloud TCO Model along with monthly market surveys of over 100+ gpu clouds & gpu cloud customers. On the Day 0 release of DeepSeekv4.1 Flash, NVIDIA vLLM works out of the box with zero issues across all 6 SKUs: H100, H200, B200, B300, GB200, GB300! This was thanks to the amazing work by the NVIDIA & Interact teams! In comparison, AMD vLLM did not work on day 0 for DeepSeekv4.1 Flash.Source: SemiAnalysis InferenceX AMD’s vLLM documentation points to using vllm/vllm-openai-rocm:deepseekv41-flash-0909, but from hour 0 of the model release to hour 23, AMD has not publicly released the image. AMD claims, “SPEED IS THE MOAT,” yet it has still not released it by the 23rd hour. We wish that, going forward, the AMD team has a better process for hour 0 model releases. Eventually when they did publicly release for “day 0” image support, performance-wise, it is currently up to 14.8x worse perf per dollar than H200 and up to 42x worse perf per dollar than B200/B300. The power of the CUDA MOAT is NVIDIA’s collaboration with its massive 6 million-developer community ecosystem including most of the vLLM & SGLang & Tokenspeed maintainers which means that CUDA is optimized on day 0. Overall, AMD did make significant improvements but the performance per dollar is still currently 2-4x worse than B200. AgentX Engram DRAM Offloading Improving Performance The HBM and DRAM offload use the same GPU kernel to select and dequantize rows. With HBM, it reads GPU memory; with Unified Virtual Addressing (UVA), it reads pinned host memory directly. Both support full decode graphs. Moving the table into HBM accelerates only the sparse lookup, leaving decoder computation and communication unchanged, resulting in little overall benefit while consuming memory otherwise available to KV cache. Another benefit of Engram offloaded to DRAM which means you can reduce the communication overhead by using less HBM GPUs per replica. For example, when enabling Engram offloading on B300, we are able to switch from TP4 to now TP2 which improves the pareto curve by up to 1.6x. When iso-model quality, less HBM is required as the engrams could be offloaded to host DRAM. Thus HBM bandwidth matters way more than HBM capacity. For inference workloads where memory bandwidth matters the most, 4-hi HBM provides the best $/bandwidth and therefore lowest cost per token. If China continues to make more and more revolutionary model architecture innovations, soon it could potentially 0Hi HBM stacks. [ ](https://newsletter.semianalysis.com/p/long-live-the-short-king-why-4-hi) [ Long Live the Short King: Why 4-hi HBM Wins ](https://newsletter.semianalysis.com/p/long-live-the-short-king-why-4-hi) Myron Xie, Bryan Shan, and 3 others · Sep 13 [ Read full story ](https://newsletter.semianalysis.com/p/long-live-the-short-king-why-4-hi) Moreover, on B300 and week-0 stack, moving the Engram table back to HBM did not improve results and stay within run-to-run variance. This is a result of the work optimizing DRAM offload, such as async, and overlap. SSD Offloading On B200, we created a unoptimized vLLM fork and stored the Engram tables in memory-mapped files on local SSDs. File backing lets the OS reclaim table pages when other applications need RAM. Pages already cached in memory can be served without reading the SSD again. Furthermore, note that we were unable to turn on GDS The unoptimized SSD implementation changes how rows reach the GPU. It copies row IDs to the CPU, deduplicates them, gathers the requested rows into pinned buffers, copies those rows back to the GPU and dequantizes them. This work runs between segments of the GPU execution graph. Native UVA performs row selection and dequantization directly on the GPU, avoiding the CPU round trip. A warm filesystem cache removes physical SSD reads, but leaves the coordination, row gathering and transfers. This is why a file already cached in RAM can still perform worse than a pinned DRAM table. The comparison measures the whole serving path; it does not separate the time spent on each of these operations. B200 DRAM dominates both measured SSD serving curves in total tokens per dollar and P90 interactivity. Near 125 tokens/s/user, DRAM delivers 121 million total tokens per dollar versus 52 million for SSD. For production serving, SSD offloading is likely not worth the tradeoff. On the B200 configurations we measured, SSD offloading loses on both measures: every observed SSD point has a DRAM alternative that delivers higher P90 interactivity and more total tokens per dollar. The only points where Cheaper storage does not automatically produce a cheaper inference service. Moving Engram to SSD leaves the same four expensive GPUs and the rest of the server in place. Reclaiming RAM only creates an economic benefit if it enables a cheaper server configuration or additional useful capacity. The current unoptimized path provides neither benefit, and the filesystem cache still consumes RAM when table pages are resident. Next we will look at the mechanisms and specific implementation of ngrams from DeepSeekv4.1 Flash, LongCat, Qwen3.8 Flash Next.
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Republicans Want to Change How You Buy Health Care
President Trump and other leading conservatives are pushing policies they hope will empower patients to shop more wisely for the health care they need.