SCROLL NEWS / DISCOVERY
Search headlines
Find the stories shaping the conversation.
Results for " yield " 201 found 🔀 AI-powered Shuffle
Florence Regional Airport
Florence Regional Airport is a small airport looking to yield big growth for its surrounding area & communities.
Suns-Trail Blazers Injury Report: Pair of Key Players Headline
Wednesday's injury report yields interesting conversations across both teams.
Agassi Sports Entertainment Converts $1M Note, Raises $1.5M From Andre Agassi Affiliate at $5 Units
Agassi Sports Entertainment executed multiple financing actions, converting a $1,000,000 insider note into equity and warrants and raising $1,500,000 in a new unit purchase by Investments AKA at $5.00 per unit. The conversion yielded 200,000 common shares and 200,000 three-year cash-only warrants w…
Real Madrid’s 4-1 win yielded little from set pieces
Real Madrid beat Sevilla 4-1 at the Santiago Bernabéu on Sunday, October 18, but the set-piece analysis published by Managing Madrid found little threat from either side’s dead-ball situations. Kyl...
Mom-and-Pop Business Owners Grapple with Harsh Times
Report shows small business owners in NYS less optimistic about the economy. Taxes, inflation, labor costs and competition from larger businesses are major concerns right now, they say By Aaron Gifford [caption id=attachment_11067 align=alignright width=300] Ashley Ranslow is director for New York state at The National Federation of Independent Business (NFIB).[/caption] Owners of mom-and-pop businesses in New York state have been less optimistic lately than their peers in other parts of the country, a recent report indicates. The National Federation of Independent Business (NFIB), based on a survey of 11,000 of its members in the Empire State, reported that taxes, inflation, labor costs and competition from larger businesses are major concerns right now. “Indeed, while taxes are a major problem in New York and the United States overall, New York small businesses notably are struggling more with the state’s onerous, multi-level tax burden,” Ashley Ranslow, NFIB’s director for New York state, said in the July report. Compared with surveys of business owners in other states, far fewer New York respondents rated their businesses as in excellent or good health. The report also said labor costs here are about 25% higher than the national average and are the “single most important problem” facing businesses. One respondent to the New York-specific survey complained that too much red tape, taxes and laws that restrict high-yielding companies have stifled their operation’s growth. Others said high disability and workers’ compensation insurance costs, alarming increases in utility rates and excessive building regulations are discouraging. Statewide, New York has a gross domestic product of $2.53 trillion (third in the nation, followed by Texas, $2.90 trillion; and California, $4.25 trillion), a per capita income of $90,500 (sixth) and an unemployment rate of 4.6% (34th). There are 2.4 million small businesses that employ 3.9 million people. [caption id=attachment_11112 align=alignright width=451] Member of the Greater Liverpool Chamber of Commerce gather at one of the several functions the chamber organizes monthly. “Everyone in this business community encourages each other to shop local. Everyone just wants to see each other succeed,” says Megan Wilmot, the chamber director[/caption] “New York state boasts one of the largest, wealthiest and most diverse cities in the world — and that’s still only about half the state’s population,” the report said. “In other words, the state is both its iconic city and so much more — geographically, demographically, economically. But New York is not without its challenges, challenges that include notably high taxes and other weaknesses that impact the small business environment,” it said. The report includes an optimism index that compares responses from New York (NFIB) members with those of their peers in other states across several categories. This ranges from plans to increase employment to expectations for higher sales, to plans to increase inventory or expand. The scores for Empire State business owners were lower in most categories, but they did score higher than the national average in noting that they have current employment openings, and that they are hopeful that the economy will improve. “The metrics so far paint a picture of a state with a series of challenges for small businesses, from a slightly below national average Optimism Index to a more seriously below national business health to very substantially below national Employment Index. What is going on with businesses that are creating these differences?” the report stated. In Central New York, the regional labor force comprises nearly 398,000 workers. The median household income here is $71,463, and the gross domestic product for the region last year totaled $61.3 billion, according to the CenterState CEO economic development and research organization. About half of the region’s labor force works for small and mid-sized businesses, although the number of people employed in that sector has decreased by 7% since 2010, according to CenterState’s 2026 economic forecast report. “While record-high employment in large-scale enterprises provides a strong foundation for Central New York,” the report says, “the long-term health of communities depends on a thriving small business sector to serve as a stabilizer.” Area employers identify several barriers to Central New York’s anticipated growth, including lack of specialized or skilled workers, government regulations, unaffordable housing options and long-term construction disruptions. In the city of Syracuse, the number of jobs in retail trade decreased by 1,500 or 4.7% between July 2025 and this past July. By contrast, the number of jobs in the leisure and hospitality sector increased by 2.5% or 700 jobs, in the same annual period, according to the New York State Department of Labor. Still, there’s plenty of interest for new businesses across Central New York. U.S. Census figures show that the number of applications for new businesses in all four counties increased significantly in the past 20 years. In Cayuga County, there were 324 applications in 2005 compared to 470 last year. In Madison County, the number increased from 385 to 480; Onondaga County, from 2411 to 4132; and Oswego County, from 553 to 836. Downtown Cazenovia is exemplary of Madison County’s trend: In the past year, the village welcomed a bait shop, a thrift store, a vitamin infusion center, a pizzeria, a Pilates studio and an Italian restaurant. A candy store is scheduled to open on the main drag in the months ahead. Oswego’s list of interesting new businesses in the past year includes a bubble tea shop, a hot dog eatery in Fulton, a specialty grocery store that features New York state products in Mexico, a beauty and esthetics studio in Hannibal and a hardware and farm supply store in Sandy Creek. In Onondaga County, the Liverpool area has also enjoyed a steady stream of new shops and eateries in recent years. That suburban community is unique in that, unlike neighboring communities, most of the restaurants are family-owned and not part of a national chain. [caption id=attachment_11116 align=alignright width=300] Megan Wilmot is the executive director of the Greater Liverpool’s Chamber of Commerce.[/caption] Megan Wilmot, executive director of the Greater Liverpool Chamber of Commerce, said independent business owners in her community maintain a strong sense of pride in holding their own against national companies. The chamber helps boost morale with red carpet events, ribbon cuttings, coffee hours and five-year anniversary celebrations for participating businesses. “We have built such a strong community,” Wilmot said. “Everyone in this business community encourages each other to shop local. Everyone just wants to see each other succeed.” In Syracuse, the downtown retail occupancy rate last year was about 82%, a slight improvement from 2024, according to the Downtown Syracuse Committee’s most recent annual report. Buildings with the largest amount of vacant space included The Galleries, One Park Place, and Equitable Towers, though not all of those spaces are designated for retail use. New businesses that opened in downtown Syracuse last year: Better with Time Clothing, Dakshin Curry & Biriyani, Havana Tattoo Society, Milano Bean Café, Miss Daisy, Pausa Coffee, Sweets for Babe, The Society CNY and Yafah Beauty Studio. The Destiny USA mall’s occupancy rate decreased from 80% in 2023 to 72% by the end of 2024, according to Integra Realty Resources. That leaves more than a quarter of the mall’s retail space vacant. “Looking ahead, the retail market is expected to see minimal rent growth, with vacancy rates likely remaining stable in community and neighborhood centers but continuing to rise in enclosed malls,” Integra’s report said. “New construction activity is low and redevelopment plans for former malls like Shoppingtown and Great Northern are still in the planning stages. The proposed Micron chip plant may spur development, but challenges remain in finding co-developers for large-scale projects.” Nationally, the U.S. Chamber of Commerce expects that small businesses will remain resilient and see their sales and revenues eventually improve. That organization, in a recent national survey, found that 25% of small business owners expect the economy to improve in 2027, while 45% indicated that they plan to increase employment in the next 12 months. And 69% said they believe their small business is in good shape and 70% said they are comfortable with their current cash flow. Thirty-one percent of small businesses reported raising their prices in July and 28% are planning to raise their prices within the next three to four months, the report said. Twelve percent indicated that this is a good time to expand their business. “Small business owners voice optimism for future revenues and hiring,” the report said. “High costs continue to be a wet blanket on reinvestment.” The NFIB reported in July that Main Street, despite gas price hikes, “is OK … for now.” Its small business economics trend report said sales across the country have been strong compared to last year, but continued inflation and higher prices from mom-and-pop establishments are causing some “cracks” to show. “If costs stay this high for much longer, reduced investment will have a tangible economic impact,” the report said. “The status quo is OK, but the outlook? The outlook is uncertain.”
When it comes to France's public finances, the problem is politics
Rising yields signal trouble, but consensus for radical fiscal change remains elusive
Business Monday: He went from telescope engineer to making craft chocolate in Honokaʻa
It took a few years to have a significant harvest, but now the Pollard’s farm has more than 1,000 producing cacao trees, each of which yields five pounds of chocolate each season.
New Alaska sea sponge species fuel debate over fishery practices
Alaska’s little-explored ocean floor continues to yield scientific discoveries, including a sponge species in a new-to-science genus.
Albums with the most No. 1 hits: Taylor Swift, Katy Perry, Drake, more
Taylor Swift's "The Life of a Showgirl" has yielded three No. 1 hits on the Billboard Hot 100, joining an elite list of blockbuster albums.
Bessent mocks Sen Warren, wishes her 'Happy Indigenous Peoples' Day' in response to letter
Scott Bessent accused Elizabeth Warren of having little knowledge about financial markets in a snarky response to her 10-year treasury yield letter.
Wall Street finishes its record-setting week with gains - The Business Journal Stocks Rise as Wall Street Closes Record-Setting Week Amid Inflation Worries
U.S. stocks gained Friday as the S&P 500, Dow and Nasdaq rose, while higher oil prices, Treasury yields and inflation concerns weighed on investors.
Ohio State alumnus David Jacobs’ interest in investing yields high return for students
David C. Jacobs began plotting his career path early in high school. It would begin at The Ohio State University with a bachelor’s degree in finance and marketing before continuing on Wall Street as a stockbroker. “It didn’t quite work out as planned,” he said. “But my time at Ohio State afforded me the opportunity to pivot quickly int...
Beef Industry political ‘isms’
Amidst this high-tension political season, everybody and their dog (er, cow) wants to lay strident, negative political monikers on all the political persons that they disagree with. All the good ol’ political system standard “isms”...
Lower US Treasury yield view persists despite biggest quarterly surge since 1994
US Treasury yields are forecast to fall over coming months, according to fixed income strategists in a Reuters poll who clung to their long-held view despite the benchmark 10-year yield recording its biggest quarterly jump since 1994.
High health care spending yields large job growth
The health sector added three times as many jobs as the rest of the economy over the past year.
New agriculture scouting business takes off
Delmarva farmer Nichole Krambeck uses drones and soil DNA testing at Insight Ag Scouting to cut costs and boost crop yields.
Wall Street is booming. Surging yields could shake things up
The boon comes at a time when consumer sentiment is at historic lows and with heightened concerns about the cost of living, from rising energy prices to stubborn food inflation.
Euro faces political, fiscal reckoning as it hovers near 17-month low
The euro struggled near a 17-month low on Tuesday, weighed down by political uncertainty and fiscal concerns across the euro zone, while the dollar extended its blistering rally as it rode US Treasury yields higher.
Rebuked by Bond Market, Bessent Says ‘House’ Does Not Always Win
The Treasury secretary said in an interview with Axios that he cannot control the Treasury market but argued that U.S. bond yields would come back down over time.
Fed rate hike odds plunge, stocks soar after dismal jobs report
The soft September jobs report suggests the Fed might not have to rush to raise rates this month. Stocks surged and bond yields dropped on Friday.
The Latest Challenge to Data Centers? Restive Investors.
Rising government bond yields are beginning to upend the economics around the artificial intelligence build-out.
Rising yields are wreaking havoc on stocks outside the AI trade
After the 10-year Treasury yield rose as high as 5.34% for the first time since 2002, stock traders are fiercely debating when the selloff in bonds will start to trigger
Equities rebound to close higher as surging Treasury yields recede
Us stocks closed higher after treasury yields reversed course from multi-decade highs, easing inflation fears and boosting energy and technology sectors.
New “plant armor” more than triples strawberry yields
A new protective fabric boosted strawberry yields by as much as 3.56 times while blocking insects and still allowing sunlight, rain, and airflow to reach the plants. Originally inspired by research on military clothing, Plant Armor could also help farms reduce pesticide and water use.
Fahy plans new bill to address chronic absenteeism
An effort last year in response to violence in Albany yielded two bills, now Fahy is preparing to introduce a third in response to the killings of four children in Mechanicville over the summer.
Fahy plans new bill to address chronic absenteeism
An effort last year in response to violence in Albany yielded two bills, now Fahy is preparing to introduce a third in response to the killings of four children in Mechanicville over the summer.
How Are Corn Growers Protecting Their Yields From Bird Damage?
Every spring, corn growers face a threat that rarely shows up in a budget until it’s too late: flocks of birds pulling freshly planted seed out of the ground before it can sprout. The resulting stand loss can quietly erase thousands of dollars in expected revenue per field, which raises a practical question for growers […]
US futures dragged lower as oil prices and Treasury yields climb
U.S. futures are edging lower as oil prices climb and bond yields continue to pressure stocks. Futures for the S&P 500 dipped 0.1% on Wednesday, while those for the Dow
Nearly 40% of global population exposed to dangerous ozone pollution in 2026: Report
Ground-level ozone harms human health, ecosystems and crop yields.
Midwest nonprofits HealthPartners, Essentia Health announce merger plans
Minnesota-based nonprofits HealthPartners and Essentia Health have announced plans to combine, setting the stage for an integrated 22-hospital system spanning multiple Midwest states. | The deal would yield a roughly $12.5 billion, multi-state integrated nonprofit with 22 hospitals and a 1.6 million-member insurance business.
iPhone Duo Reportedly Facing Production Problems Ahead of Launch
The iPhone Duo is reportedly facing production difficulties ahead of its October launch, with early output expected to be limited. A person said to be close to Foxconn's supply chain told China's Jiemian News that final assembly yields for Apple's first foldable iPhone were only slightly above 60% as of September 17. The source said that, under Apple's current quality standards, it could take another six months to a year for the assembly line to reach a mature yield.
The Value Of Basic Science Celebrated With The 2026 “Golden Goose” Awards
The 2026 Golden Goose Awards, an honor spotlighting obscure, often trivial sounding basic research that ultimately yields significant social benefits have been announced.
Stocks cautious in Asia as oil gains, yields rise
By Wayne Cole SYDNEY, Sept 28 (Reuters) - Share markets made a cautious start on Monday as oil prices popped higher again amid doubts the United States and Iran will
This ancient fruit tree thrives with little water—and hides surprising health benefits - Futura-Sciences
An Overlooked Mediterranean Classic This fruit tree yields small “apples” that ripen from yellow to red in September, yet it’s been off the horticultural radar for a long time. That tree is the azarole (Crataegus azarolus), sometimes called the Spanish thorn or azarolier. Rare and seldom noticed, it’s high time...
Coffee Could Be Messing With Your Sleep—Even When You Drink It the ‘Right’ Way
A new study yields some surprising findings.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. [1] Intel, “Intel Tech Tour 2025 Panther Lake recap,” Doc. 866361, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/866361/ITT_2025_Panther_Lake_Recap1.pdf [2] Intel, “Core Ultra processors Series 3 datasheet, volume 1,” Doc. 872188-001, Jan. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/872188/872188-001.pdf [3] N. Horiguchi and E. Beyne, “Backside power delivery: How to power chips from the backside,” imec Reading Room, Nov. 25, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/how-power-chips-backside [4] W. Hafez et al., “Intel PowerVia technology: Backside power delivery for high density and high-performance computing,” in Proc. IEEE Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2023, pp. 1–2, doi: 10.23919/vlsitechnologyandcir57934.2023.10185208. [5] K. Fischer et al., “Intel 18A platform technology featuring RibbonFET (GAA) and PowerVia for advanced high-performance computing,” in Proc. Symp. VLSI Technol. Circuits, Kyoto, Japan, Jun. 2025, pp. 1–3, doi: 10.23919/vlsitechnologyandcir65189.2025.11075006. [6] K.-F. Cheng, C.-L. Teng, H.-Y. Huang, and H.-C. Chen, “Metal oxide composite as etch stop layer,” U.S. Patent 12 176 247 B2, Dec. 24, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12176247B2/en [7] S. W. King, “Dielectric barrier, etch stop, and metal capping materials for state of the art and beyond metal interconnects,” ECS J. Solid State Sci. Technol., vol. 4, no. 1, pp. N3029–N3047, 2015, doi: 10.1149/2.0051501jss. [8] A. V. Mule’, D. J. Towner, D. Seghete, C. R. Ryder, and A. A. Gonzalez, “Multi-layer etch stop layers for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20220102343 A1, Mar. 31, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20220102343A1/en [9] C.-C. Wang and J. H. Wang, “Interconnect structure with dielectric cap layer and etch stop layer stack,” U.S. Patent Appl. 20230253247 A1, Aug. 10, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20230253247A1/en [10] Y. J. Wu, K.-F. Cheng, C.-C. Lee, H.-K. Chang, and H.-Y. Huang, “Etch stop layer for interconnect structures,” U.S. Patent Appl. 20240332070 A1, Oct. 3, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240332070A1/en [11] M. G. Rainville, N. Shankar, K. S. Reddy, and D. M. Hausmann, “Deposition of aluminum oxide etch stop layers,” U.S. Patent Appl. 20180197770 A1, Jul. 12, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20180197770 [12] J. S. Leib et al., “Conductive lines having molybdenum liner and tungsten fill for advanced integrated circuit structure fabrication,” U.S. Patent Appl. 20240429126 A1, Dec. 26, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.justia.com/patent/20240429126 [13] M. Naik, “Cobalt enables power and performance scaling at single-digit logic nodes,” Applied Materials, Dec. 17, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://www.appliedmaterials.com/us/en/blog/blog-posts/cobalt-enables-power-and-performance-scaling-at-single-digit-logic-nodes.html [14] Lam Research, “Breaking through AI’s invisible barrier with molybdenum,” Lam Research Newsroom, May 6, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://newsroom.lamresearch.com/molybdenum-metallization-ai-revolution [15] P. Yashar, G. Malyavanatham, and H. Vijwani, “Integrated circuit interconnect structures with niobium barrier materials,” U.S. Patent Appl. 20240112951 A1, Apr. 4, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20240112951A1/en [16] Applied Materials, “Applied Materials unveils chip wiring innovations for more energy-efficient computing,” Applied Materials Investor Relations, Jul. 8, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://ir.appliedmaterials.com/news-releases/news-release-details/applied-materials-unveils-chip-wiring-innovations-more-energy [17] Samsung, “Samsung showcases AI-era vision and latest foundry technologies at SFF 2024,” Samsung Semiconductor, Jun. 13, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://semiconductor.samsung.com/news-events/news/samsung-showcases-ai-era-vision-and-latest-foundry-technologies-at-sff-2024/ [18] C. W. Yeung et al., “Channel geometry impact and narrow sheet effect of stacked nanosheet,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2018, pp. 28.6.1–28.6.4, doi: 10.1109/iedm.2018.8614608. [19] S. Mochizuki et al., “Evaluation of (110) versus (001) channel orientation for improved nFET/pFET device performance trade-off in gate-all-around nanosheet technology,” in Proc. Int. Electron Devices Meeting (IEDM), Dec. 2023, pp. 1–4, doi: 10.1109/iedm45741.2023.10413854. [20] D. G. Ouellette et al., “Fabrication of gate-all-around integrated circuit structures having molybdenum nitride metal gates and gate dielectrics with a dipole layer,” U.S. Patent 12 051 698 B2, Jul. 30, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US12051698B2/en [21] imec, “Advancing the CFET-based device roadmap with novel integration modules and standard-cell architectures,” imec, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/advancing-cfet-based-device-roadmap-novel-integration-modules-and-standard-cell [22] A. Reznicek, X. Miao, C. Lee, and J. Zhang, “Wrap around contact for nanosheet source drain epitaxy,” U.S. Patent 11 302 813 B2, Apr. 12, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US11302813B2/en [23] J. A. Kittl, J. G. Hong, D. R. Palle, and M. S. Rodder, “Methods for varied strain on nano-scale field effect transistor devices,” U.S. Patent 9 978 833 B2, May 22, 2018. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9978833B2/en [24] S. Gandikota et al., “Method of reducing metal gate resistance for next generation NMOS device application,” Int. Patent Appl. WO 2024/137272 A1, Jun. 27, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/WO2024137272A1/en [25] J. Zhang et al., “Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), Dec. 2019, pp. 11.6.1–11.6.4, doi: 10.1109/iedm19573.2019.8993490. [26] C. Yoo, J. Chang, Y. Seon, H. Kim, and J. Jeon, “Analysis of self-heating effects in multi-nanosheet FET considering bottom isolation and package options,” IEEE Trans. Electron Devices, vol. 69, no. 3, pp. 1524–1531, Mar. 2022, doi: 10.1109/ted.2022.3141327. [27] S. S. Pradhan, D. B. Bergstrom, J.-S. Chun, and J. Chiu, “Tungsten gates for non-planar transistors,” European Patent Appl. EP 3 506 367 A1, Jul. 3, 2019. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/EP3506367A1/en [28] L. Schloss and X. Ba, “Tungsten films having low fluorine content,” U.S. Patent 9 754 824 B2, Sep. 5, 2017. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US9754824B2/en [29] Intel Foundry, “Accelerating AI and HPC with advanced process and packaging technologies,” Doc. 367370-001US, Jun. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-11/intel-foundry-hpc-ai-brief.pdf [30] M. Lofrano, X. Chang, H. Oprins, and Z. Tokei, “Mitigating the thermal bottleneck in advanced interconnects,” imec, Sep. 28, 2023. Accessed: Sep. 14, 2026. [Online]. Available: https://www.imec-int.com/en/articles/mitigating-thermal-bottleneck-advanced-interconnects [31] S. Bair, “Intel at ISSCC 2025: Navid Shahriari invited talk, eight papers, forums, panelist & product details,” Intel Community, Feb. 19, 2025. Accessed: Sep. 14, 2026. [Online]. Available: https://community.intel.com/t5/Blogs/Tech-Innovation/Edge-5G/Intel-at-ISSCC-2025-Navid-Shahriari-Invited-Talk-Eight-Papers/post/1667592 [32] D. Chandra, E. Potladhurthi, D. R. S. Reddy, and K. S. Rengarajan, “Tunable negative bitline write assist and boost attenuation circuit,” U.S. Patent Appl. 20160203857 A1, Jul. 14, 2016. Accessed: Sep. 14, 2026. [Online]. Available: https://patents.google.com/patent/US20160203857A1/en [33] Synopsys, “Advantages of firmware-based training in high-speed DDR IP,” Synopsys IP Technical Bulletin. Accessed: Sep. 14, 2026. [Online]. Available: https://www.synopsys.com/articles/firmware-based-training-ddr-ip.html [34] N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, “CACTI 6.0: A tool to understand large caches,” Hewlett-Packard Laboratories, 2009. Accessed: Sep. 14, 2026. [Online]. Available: https://users.cs.utah.edu/~rajeev/cacti6/cacti6-tr.pdf [35] Intel, “Intel Tech Tour 2024 Lunar Lake AI hardware accelerators,” Doc. 824436, 2024. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/824436/2024_Intel_Tech%20Tour%20TW_Lunar%20Lake%20AI%20Hardware%20Accelerators.pdf [36] Y.-H. Chen, J. Emer, and V. Sze, “Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks,” in Proc. 43rd ACM/IEEE Annu. Int. Symp. Comput. Archit. (ISCA), Jun. 2016, pp. 367–379, doi: 10.1109/isca.2016.40. [37] Intel, “Introduction to the Xe-HPG architecture,” Doc. 758306, Nov. 4, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/developer/articles/technical/introduction-to-the-xe-hpg-architecture.html [38] Intel, “Core Ultra processors Series 3 for the edge,” Doc. 855291. Accessed: Sep. 14, 2026. [Online]. Available: https://cdrdv2-public.intel.com/855291/Intel%C2%AE%20Core%E2%84%A2%20Ultra%20Processors%20Series%203%20for%20Edge%20Overview_2.pdf [39] Intel Foundry, “Foveros technology brief,” Doc. 366411-001US, Feb. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/dam/www/central-libraries/us/en/documents/2025-07/foveros-25d-product-brief.pdf [40] D. Das Sharma, “UCIe: Building an open chiplet ecosystem,” UCIe Consortium, 2022. Accessed: Sep. 14, 2026. [Online]. Available: https://www.uciexpress.org/_files/ugd/0c1418_c5970a68ab214ffc97fab16d11581449.pdf [41] Intel, “Intel launches Intel Core Series 3 processors,” Intel Newsroom, Apr. 16, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-launches-intel-core-series-3-processors-changing-the-game-for-everyday-computing.html [42] Intel, “Core Series 3 launch press deck,” Apr. 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://download.intel.com/newsroom/2026/Intel-Core-Series-3/Intel-Core-Series-3-Launch-Press-Deck.pdf [43] Intel, “Intel outlines architectures for agentic AI at Hot Chips 2026,” Intel Newsroom, Aug. 24, 2026. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intel.com/content/www/us/en/newsroom/news/client-computing/intel-outlines-architectures-for-agentic-ai-at-hot-chips-2026.html [44] Intel, “Intel accelerates process and packaging innovations,” Intel Investor Relations, Jul. 26, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/filings-reports/all-sec-filings/content/0001193125-21-224438/d199788dex991.htm [45] Intel, “Intel reports third-quarter 2021 financial results,” Intel Investor Relations, Oct. 21, 2021. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/1505/intel-reports-third-quarter-2021-financial-results [46] Intel, “3rd generation Intel Core processors bring exciting new experiences and fun to the PC,” Intel Investor Relations, Apr. 23, 2012. Accessed: Sep. 14, 2026. [Online]. Available: https://www.intc.com/news-events/press-releases/detail/577/3rd-generation-intel-core-processors-bring-exciting
Dollar perched at two-month high as hot PMI fuels inflation fears, rate hike bets
The dollar clung to a two-month high on Thursday after a strong manufacturing reading reignited inflation fears and rate-hike bets, while a weak Treasury auction sent yields higher across the curve, providing fresh impetus to the US currency.
Hands-on science can be cool
After spending many long days conducting experiments to find a new way to combat bacterial infections in crops, Misha Hegde and Mia Soleil Maurer have been rewarded with international recognition and access to top research facilities. But these are not typical scientists. They are 16-year-old German high school students.“Our supervisor told us that in order to start a project, you need to begin with either a question or a problem,” says Misha, adding that she and Mia had read about antibiotic resistance in certain plants being treated for bacterial infections. “We found out that antibiotics overuse is very common in agriculture,” explains Mia. “Our aim was to create an alternative to antibiotics and to try to raise awareness of the problem of overusing antibiotics.”Their subsequent research has focused on harnessing bacteriophages, the natural predators of bacteria, to eliminate pathogens threatening food crops treated with antibiotics. At the Schuldorf Bergstraße Jugend forscht MakerLab in Seeheim-Jugenheim, located in the German state of Hesse, they discovered a novel phage that infects the Rhizobium rhizogenes bacterium, which causes the hairy root disease that can reduce yields of tomatoes, carrots, soya beans and other food staples.The students believe their method could curb antibiotic use, while protecting plants from infections without disturbing the natural soil microbiome. “The application of phages is host-specific, so they would only kill the targeted pathogen or disease-causing bacteria,” explains Mia. It may also offer environmental benefits, since applying antibiotics can contaminate groundwater.Getting to this point has not been easy. The childhood friends admit to feeling frustrated when their trials did not yield the expected results. “We spent six months on our first experiment, just doing the same thing over and over and over again, to the point where we thought, is it even worth it? Why are we doing this?” Misha says. “You just need to be brave enough to take that first step and keep going.”The benefits of inquiry-based learningTheir determination has paid off. In 2025, the pair won first prize in biology at Jugend forscht, Germany’s national competition for young people interested in science, technology, engineering and mathematics. They were also among the winners of the German Research Foundation Europa-Preis, which is awarded to selected national winners at Jugend forscht, and took third place in the 2025 European Union Contest for Young Scientists.The Jugend forscht Foundation opens doors for young people to connect with scientists as well as industry professionals. Jessica Bönsch, executive director of the Foundation, sees Misha and Mia as prime examples of how young people can develop a deeper understanding of science through their own research projects. “The experience of working on your own research question is very important,” she explains, adding that “inquiry-based learning engages with real-life problems in a way that can be more motivating than traditional classroom teaching.”The Jugend forscht Foundation offers financial support through sponsor pools in Germany’s federal states. Some projects are developed in cooperation with student research centres, university labs or informal collaborative learning areas called makerspaces. Other activities start as hands-on “garage projects” and can grow within the Jugend forscht network and infrastructure.The Jugend forscht Foundation is also a partner of Science Comes to Town, an EU initiative to strengthen public awareness about science and create bridges between researchers and communities. The EU-financed project involves universities, research institutions and other stakeholders in three host cities — Brest (France), Kiel (Germany) and Split (Croatia).“It's so important for people not to live in a bubble, because I think science can be very scary if you misunderstand it,” Mia says of SCTT. The initiative’s aim of raising awareness about science is “absolutely amazing,” Misha adds. “I think it's the best way to kind of make science digestible for the public. In a world where misinformation in science is getting more radical, more dangerous, becoming more of a threat to the trust in scientific infrastructure and foundations, we need such programmes.”Misha and Mia also believe that SCTT can help break down gender stereotypes in science by encouraging young women to study and pursue careers in scientific fields. Both students have benefited from female mentors and encouragement they had when they were much younger. Mia’s love of science began with a class trip to a lab, while Misha — with a smile on her face — says she wanted to study history until “a teacher kind of coerced me into joining a school science club.”Recognition beyond EuropeIn May, Misha and Mia were among the finalists at the Regeneron International Science and Engineering Fair held in Phoenix, Arizona, and involving nearly 1,700 pre-university students from over 60 countries. “It was very crazy because there were so many people and so many teenagers interested in science,” Mia recalls. The event was also challenging. “It was eight hours of continuously presenting your project,” adds Misha.Attending the fair was a chance for the young women to see first-hand the value of international collaboration as well as how research cultures differ. “America is a bit more willing to take risks, and I think that's something we can learn about here in Europe,” Misha explains. However, she continues, “I think Europe has the talent, has the innovation and has the resources” to be competitive.Misha and Mia plan to continue their phage experiments in the new school year, inspired by the project’s hands-on nature and the support they receive from their supervisors. They have also attracted the interest of professional scientists and received invitations to leading research facilities, including the Centre for Synthetic Microbiology, jointly run by the University of Marburg and the Max Planck Institute for Terrestrial Microbiology in Germany. “It is so cool that we can do something to try to move the world in our school and at this age,” Mia says.After completing secondary school, Mia plans to study microbiology and pursue a career in medical research, focusing on Ebola and other infectious diseases. “This has been my dream for so long,” she says. Her friend Misha is interested in biological research with a focus on medicine. “I've gotten addicted to the process of going to the lab, planning out experiments, then failing, trying again,” Misha says. “I think there's just so much to be discovered, so much to be done.”The students' names and photos were published with the permission of their parents.Science|Business, which connects policymakers, academics and industry through its news reporting, analysis and events, is an SCTT partner.
Wall Street ends down as oil prices, Treasury yields rise
Wall Street ended lower as oil prices surged nearly 4% and treasury yields hit multi-year highs amid escalating tensions with Iran and rising interest rate expectations.
Why Japan’s markets matter so much for America
From surging bond yields to US intervention to support the yen, Japan’s financial markets are undergoing major shifts that have consequences for investors and borrowing costs around the globe.
PENN Entertainment, Inspired, Lovesac, Rush Street Interactive, and Marriott Vacations Stocks Trade Down, What You Need To Know
A number of stocks fell in the afternoon session after rising Treasury yields and higher interest rates intensified worries over household finances and discretionary consumption, creating headwind conditions for consumer-facing companies. According to Reuters, as borrowing costs on mortgages, auto loans, and credit cards climb, household budgets are increasingly squeezed, encouraging consumers to prioritize saving and basic necessities over non-essential purchases. In addition, recent economic d
Wall St ends mixed as oil takes a pause
Wall Street closed mixed as US Treasury yields topped 5% and oil prices paused above $100 per barrel, keeping inflation concerns in focus.
Amex launches high-yield savings account to complement business checking
Amex Business Savings offers an above-average return, plus no minimum balance requirement or monthly fees.
PENN Entertainment, Inspired, Lovesac, Rush Street Interactive, and Marriott Vacations Stocks Trade Down, What You Need To Know
What Happened? A number of stocks fell in the afternoon session after rising Treasury yields and higher interest rates intensified worries over household fin...
Wall Street drifts as bond yields rise and oil prices swing
Wall Street is drifting toward the finish of an up-and-down week, and U.S. stock indexes are mixed following losses in Europe and gains for Asia. The S&P 500 was virtually
Stocks fall as Fed delivers hawkish rate hike
The U.S. Federal Reserve raised interest rates by 25 basis points, causing global stocks to fall and bond yields to rise amid inflation concerns.
American Express Escalates Business Banking War With High-Yield Savings Launch
American Express launched a new high-yield Business Savings account as part of its strategy to add integrated financial solutions to Amex Business
Tackling crop lodging: new study unlocks genetic keys to stronger rapeseed stems
Lodging, the bending and breaking of plant stems, is a primary threat to global rapeseed production, causing significant yield losses and complicating mechanical harvesting.
American Express Looks Beyond Cards With New Business Savings Offering
AXP expands beyond cards with a high-yield business savings option, aiming to deepen customer relationships and broaden product usage.
‘Even KP couldn’t come close’: Ben Stokes makes huge Harry Brook-Kevin Pietersen comparison
Harry Brook scored an unbeaten 114 off 49 balls against Sri Lanka. Ben Stokes lauded Brook's talent, comparing him favorably to Kevin Pietersen. Brook's recent move to number three has yielded significant T20I success. He joined Jos Buttler as the second Englishman with centuries in all formats. England secured a dominant 119-run victory in the first T20I.
American Express Now Offers High-Yield Business Savings Account
American Express launched a 2.95% APY Business Savings account with no minimum balance or monthly maintenance fee.
Greening in China and India reshapes climate both locally and far away
A new study published in Advances in Atmospheric Sciences shows that greening in China generally cools the local climate with more rainfall over southern and northeastern China, while greening in India tends to produce warming and less rainfall. The Co-occurring greening in China and India yields uniform climate feedbacks across over half global lands, producing cooler and wetter southern China, cooler western Eurasia, and warmer northern North America.
Newsom says he won't run for president if Harris does
Newsom's effective yield to Harris diminishes the possibility of a 2028 showdown between two of California’s most powerful political figures.
Wall Street ends down, calls for AI slowdown pummel chipmakers
Wall Street declines as Nvidia and chipmakers drop amid AI safety calls and rising 10-year Treasury yields ahead of the Federal Reserve meeting.
US SECTORS CALL: Energy, Information Technology & Health Care
Rising bond yields and oil prices weighed on stocks last week, though a mostly in-line CPI report on Friday sparked a rebound. The S&P 500 still fell 0.8%, with nine of the 11 sectors declining. Energy (OW) led, rising 2.0%, and it tops the sector derby
'Hoped to die here': Elon Musk's growing Bastrop County empire yields bittersweet feeling for neighbors
Longtime Bastrop County residents face industrial expansion and environmental concerns as Elon Musk’s business empire acquires thousands of acres of land.
Global oil hits $105 per barrel and bond yields surge
Oil prices rose Thursday, with Brent crude hitting $105 per barrel for the first time since May, as conflict in the Middle East continued to roil global markets.
Goldman says Treasury buybacks won't be enough to tame bond yields
Treasury yields remained elevated after the department said it would repurchase up to $6 billion of 10- to 20-year debt.
Is Accenture's Business Falling As Fast As Its Stock?
Accenture (ACN) trades at $179.03, about 53% below its two-year high, the price of a business the market thinks is ending. Over the last twelve months, it generated $12.58 billion of free cash flow, a yield of 11.5% on its market value against a 4.4% median for the S&P 500. Both facts are true. The argument between them is about growth.
Is Accenture’s Business Falling As Fast As Its Stock?
Accenture (ACN) trades at $179.03, about 53% below its two-year high, the price of a business the market thinks is ending. Over the last twelve months, it generated $12.58 billion of free cash flow, a yield of 11.5% on its market value against a 4.4% median for the S&P 500. Both facts are true.
Border Operations Yield 247 Additional Cases in Early September
Another 247 people have been charged, including 232 illegal aliens, in 239 cases involving immigration and border security-related crimes from Aug. 28-Sept. 3.
Why Treasury Yields Near 5 Percent Are Keeping Your Mortgage (and Business Loan) Expensive
Everyone watches the Fed for lower interest rates. But Treasury yields can matter just as much.
How the surging yen could hit your portfolio
The yen carry trade lets investors borrow cheaply in Japan and put the money into higher-yielding currencies and riskier assets around the world.
Current events: Scientists keep close eye on Atlantic Ocean changes
The year is 2060. London shudders through months of Nordic winter freezes. Across northern Europe, oak and beech forests wither under severe frost and drought, while cereal yields collapse from temperatures ...
One arrested after vehicle crashes into Watsonville business, yields 3 injuries
Watsonville police arrested Edwin Wetterstrom, 73, on suspicion of driving under the influence after his SUV crashed into the 98 Cents Store on Freedom Boulevard, injuring two others.
Sunflowers could help improve South Dakota soil health, crop yields
A 26-year USDA study reveals that adding sunflowers to corn-soybean crop rotations boosts dry-year corn yields by 35% and improves overall soil health.
Qalibaf Mocks US over Oil, Treasury Yield Pressures
TEHRAN (Tasnim) – Iran’s Parliament speaker warned that the US is facing growing pressure from rising oil futures prices, elevated Treasury yields and the depletion of the country’s Strategic Petroleum Reserve (SPR), saying the consequences of US’ policies are increasingly difficult to conceal.
Looking for your next big idea? Start at Farm Science Review 2026
By Greg LaBarge, Ohio State University Farm Science Review brings together expertise from every corner of the agriculture and natural resources sectors for three days of demonstrations, education, and conversations. Whether you’re a farmer looking to improve yields or add a new enterprise, a landowner interested in conservation, or simply curious about how food and
Looking for your next big idea? Start at Farm Science Review 2026
By Greg LaBarge, Ohio State University Farm Science Review brings together expertise from every corner of the agriculture and natural resources sectors for three days of demonstrations, education, and conversations. Whether you're a farmer looking to improve yields or add a new enterprise, a land
Seattle science powerhouses bet big on AI-designed biology
A new $95 million project could yield cancer treatments, genetic switches and plastic-eating enzymes.
Bond yields are surging around the world as macro concerns spiral
Bond yields were on the rise globally on Tuesday, with investors spooked about wars, inflation, and a shaky fiscal outlook.
Integrated pollution and carbon mitigation delivers major health and economic cobenefits in China
Synergistic mitigation of air pollutants and greenhouse gases is crucial for achieving clean air and carbon neutrality, but quantitative evidence of sectoral and regional health co-benefits in China remains limited. Authors develop an integrated Energy-Economy-Air Quality-Health framework coupling CEEPA, GAINS, and a province-level health module to simulate fourteen policy scenarios from 2020 to 2050. Coordinated strategies reduce CO2 and pollutants (SO2, NOX, PM2.5) by 75% relative to 2020, avoiding more than 500,000 premature deaths by 2050 and yielding monetized gains of 1.07 trillion CNY. Health benefits concentrate in industrially dense and populous provinces, with near-term PM2.5 reductions driven by pollution control and long-term improvements reliant on decarbonization. The integrated approach achieves a benefit-to-cost ratio of 1.42, lowering abatement costs by 11% relative to pollution-only measures. These findings highlight the value of coordinated, sector- and region-specific strategies for simultaneous climate mitigation, air quality improvement, and public health protection.
A sea cucumber venture in Zanzibar seeks to balance business and conservation
PEMBA, Tanzania — Like many coastal communities across East Africa, the residents of Shamiani have grown accustomed to watching the sea yield less and less. Warming waters, degraded marine habitats and decades of fishing pressure have all taken a toll on the resources that once sustained local livelihoods, according to community members. On Tanzania’s Pemba […]
Fed Chair Warsh faces Jackson Hole spotlight with inflation, rate path in focus
Federal Reserve Chair Kevin Warsh delivers his first Jackson Hole keynote as bond yields near highs and markets demand clarity on the Fed's rate path.
The ROI of resilience: The economic case for healing Israel’s traumatized children
There is no greater hidden liability than untreated childhood trauma, and no higher-yield investment than breaking the intergenerational cycle of abuse.
After 25 years
The kid in a sweet shop, or not being able to sleep on Christmas Eve, is genuinely how gnarly old me feels about the Sky Blues being back in the Premier League after 25 long years away! The landscape, particularly financially, has changed enormously in the intervening quarter of a century, which is why it's refreshing – and slightly surprising – to see the owner Doug King sanction spending of – by all accounts – more than £120m of their £200m-plus windfall on enhancing last season's Championship-winning squad. Frank Lampard was vibrant and positive at his pre-match media conference, while at the same time acknowledging that their front foot, attacking philosophy, which yielded 95 points and 97 goals last season, might have to be tempered, particularly at places like Arsenal.
Gold steadies, heads for third straight weekly gain
Gold held steady on Friday but was on track for a third straight weekly gain, buoyed by a weaker dollar and U.S. Treasury Department efforts to hold down longer-term yields.
Apple Card Turns Seven With Big Change Ahead
Today marks the seventh anniversary of the Apple Card becoming widely available in the U.S., following a more limited preview period. Apple's credit card can be managed in the iPhone's Wallet app, with key benefits including color-coded spending summaries, no fees, and Daily Cash cash back paid out daily. Apple Card holders can also open a high-yield savings account. The anniversary comes ahead of a big change planned for the Apple Card.
Treasury's surprise bond-market move could hit your wallet. Here's how.
Surging Treasury yields can ripple through mortgage rates, stocks, corporate borrowing, and the broader US economy.
The bond market is sounding an alarm. Here’s what it means.
Long-term Treasury yields rose to their highest point since 2007, creating another headwind for the economy and lifting borrowing costs for consumers and businesses.
Phillies 9, Twins 1: Yield of Dreams
In a game that definitely needed to be consumed, and then recapped, the Philadelphia Phillies continued their late-summer dominance of the Twins with a decisive 9-1 victory, headlined by Philly’s seven-run, fifth-inning explosion. As we were reminded in the pregame, the American League Wild Card situation is a bit of a cluster, especially with midgame […]
Jayden Daniels Takes Legal Action Against Louisiana State
The Louisiana State Tigers are one of the most successful football programs in the nation.LSU is one of few other programs that have yielded multiple Heisman Trophy victors. Unfortunately, it appears as if they find themselves on less-than-ideal terms with one of the winners.ESPN obtained a copy of a letter sent by Jayden Daniels‘ legal […] The post Jayden Daniels Takes Legal Action Against Louisiana State appeared first on HEAVY.
Sick Kids, Stalled Science: America’s Pediatric Health Funding Crisis
Pediatric health is critically underfunded, despite 1/3 of the global population being kids. But the ROI of investing in kids yields profound health and economic returns.
GungHo Online Entertainment (TSE:3765) P/E Premium Clashes With Shrinking Margins
GungHo Online Entertainment stock came into this earnings release with a muted setup, slightly weaker over the past week but modestly higher over the past month. The headline today is not a revenue story. It is the squeeze between a rich P/E of 52.1x and a thin 2.5% trailing net margin that keeps slipping from the 5.8% level a year earlier. The market is being asked to pay up for future growth while living with weaker profitability and a dividend yield of 3.77% that is not well covered. That...
This A.I. Just Created Viruses Not Found in Nature
Scientists trained artificial intelligence on libraries of DNA and then asked the model to create recipes for viral genomes. Sixteen of them were viable, yielding new viruses.
Chartbook 464 The"China squeeze" - the politics of development counterfactuals.
There are three types of China shock discourse. Each has a distinct temporal register. China shock 1.0 was a phrase coined by US academics in the 2010s to retrospectively summarize the impact on particular US labour markets, which they identified through painstaking empirical investigation. China shock 2.0 on everyone’s lips in Europe in the mid 2020s is an alarm raised by trans-Atlantic policy thinkers warning of a coming disaster which they project onto Europe’s ailing car industry. The third type of China shock discourse - commonly known as the “China squeeze” launched most recently by Indian economists Shoumitro Chatterjee and Arvind Subramanian in the pages of Foreign Affairs - mobilizes a different, more speculative temporal register: the counterfactual realm of alternate history. The China squeeze argument asks not what has happened, or what is going to happen, but what might have been. Specifically, what options for economic development might have been open to Global South economies like India or the economies of sub-Saharan Africa, had it not been for China’s spectacular industrialization since the late 1990s and the persistent competitiveness of China’s manufacture in low-skilled segments. Chatterjee and Subramanian’s argument is that whilst China has built a powerful position in electrical machinery and other high-skill manufacturing, which is now delivering China Shock 2.0, it also continues to run a trade surplus in low-skill, labour-intensive manufacturing. This surplus is large and has remained largely unchanged in fifteen years. Indeed, in the 2010s, in trade with low-income countries, China’s surplus rapidly increased. On their reading, this squeezes low-income producers in low-skill sectors in which they “should” be able to compete. Source: “China’s Mercantilist Squeeze on Developing Countries” Shoumitro Chatterjee and Arvind Subramanian. Peterson Institute for International Economics 26-7 May 2026 Chatterjee and Subramanian’s wording is telling: (emphasis mine) The canonical trajectory of economic development in the post-World War II period is for countries to transition from agriculture to manufacturing, first in low-skilled manufacturing and then later on to high-skill manufacturing (Herrendorf, Rogerson, and Valentinyi 2013). At the global level, this implies that high-income countries (HICs) that once specialized in low-skilled activities cede manufacturing export space to poorer countries that come along to occupy that space. In 1965, advanced economies accounted for about 60 percent of global value-added exports in four key low-skilled manufacturing sectors, i.e., apparel, leather, textiles, and footwear. Over time this share declined and began to be occupied first by the East Asian tigers and, beginning in the late 1990s, by China. Today China accounts for about 50 percent of the global market. The question is whether China, with its rising prosperity, is continuing to behave like its richer counterparts and ceding export space to poorer followers or to behave unlike them and continuing to occupy space. In terms of the conceptual maneuvers it performs, of the three China shock discourses, the “China squeeze” argument is by far the most ambitious. After all, it bases its critique of China on a counterfactual imagining of the world. Like any counterfactual argument, to construct this alternative reality it must rely on a heuristic model. To make their argument Chatterjee and Subramanian mobilize two key claims. The first reference point is the actual history of rich-country industrialization, what they refer to as the “canonical path”. The idea is that countries transition from agriculture to light industry and low-skilled manufacturing and from there up the value chain. To make this useful as a standard of comparison and a means to construct a normative standard, they adjust sectoral export shares for two factors: 1. the underlying level of economic development of the exporting country, as measured by national income and 2. the degree to which the sector in question is internationalized. The idea being that for a high income country to have a high export share in low-skill sectors is anomalous and even more so if that particular product is highly internationalized and thus suitable for being “conceded” to lower-income competitors. Where should this process end? Here Chatterjee and Subramanian introduce their second benchmark. Their normative idea of a global development path is one in which, in due course, low-skill manufacturing exports are distributed in proportion to a country’s share in the global labour force. They imagine, in other words, a world of proportional, polycentric global development without much national specialization in low-skill manufacturing. A useful benchmark is that, in labor-intensive manufacturing sectors, a country’s share of world exports should be broadly commensurate with its share of the world’s low-skilled labor endowment. … In the Heckscher-Ohlin model, this would be true if value added per worker and export propensities, i.e., fraction of output that is exported, are the same across countries. It is this pleasant liberal vista of orderly global development, progressing towards a general distribution of low-skilled manufacturing against which they judge reality and conclude that the low-income countries are suffering a “China squeeze”. China is not exiting low-skill sectors fast enough Allowing for its gdp level and the degree of globalization, China’s share of low-skill manufacturing exports is far higher than it “should” be. Relative to population, its low-skill share of exports is far too high. That in turn yields the conclusion that huge numbers of jobs - the authors suggest tens of millions - are being hoarded by China. For the four sectors captured in figure 4, this excess in value-added exports is $110 billion in 2022. For all low-skilled sectors overall captured in appendix figure D.1, excess value-added exports amount to $365 billion. The crowding out of LMIC exports by China is therefore substantial. Both these claims have in common that they are strong structuralisms. The first is that development paths ought to resemble each other. The second is that broadly speaking as far as low-skilled manufacturing is concerned, all countries are alike. If the world currently diverges from the distribution of trade implied by these assumptions, if China is not following the advanced economy path and has huge exports, this must be the result of “policy”, which the authors then put in question as illegitimate or unfair. Thus the naturalistic construction of a canonical path leading to a “level” distribution of low-skilled manufacturing reveals itself to be a polemical tool. From the point of view of China shock polemics, this discourse is no doubt welcome. But as an account of economic history, it must surely be regarded as nothing short of bamboozling. Development paths do not follow a regular, natural sequence. As David Fishman put it aptly, “development is not a queue”. They are always and everywhere, through and through political. Development is not so much a process, as a project. Each such project is more or less well adjusted to its context. As Gerschenkron taught uneven and combined development implies differentiation rather than simple imitation on a single parth. It may be true that Europe and the US exited relatively early from low-skill work. But clearly technology has changed. As C&S themselves point out, China no longer enjoys a low wage environment. Do they really believe that such huge differences can be accounted for either by industrial policy, which as they admit does not operate powerfully in low-skill sectors, or by exchange rate manipulation? What is overwhelmingly dominant in explaining the persistence of “low-skill” manufacturing in China are surely the network effects of complex supply chains. Indeed the label of “low-skill” may miss the point. The degree of globalization which Chatterjee and Subramanian decide to conjure away in their model of the development path - to allow for the fact that Europe and American textiles exporters did not enjoy just-in-time logistics in the 1950s - obscures the point that the networks through which Chinese factories supply the world are themselves key parts of the low-skill industrialization project. China isn’t knocking out 1970s style “cheap”. It has redefined the entire product cycle. C&S’s casual reference to “T-shirts” is telling. In today’s “fast fashion”, there is weight on both terms. Fashion and fast. China’s success in delivering on both at unprecedentedly high speed and at unprecedentedly low cost, isn’t a low-skill operation at all. If we see development trajectories not as the serial repetition of the same, but as distinctive, crafted projects that cumulate in complex agglomerations of skill, technology and labor, then this explains why the assumption that low-skilled manufacturing should follow the distribution of population flies in the face of all experience. As countless cases attest, low-wage, low-income developed economies are not by themselves the makings of a competitive production base. As Leon Liao puts it quite fairly: “International trade has never been allocated according to population. A country’s population gives it no natural claim to an equivalent share of global exports." And the remarkable fact is that Subramanian alone and with co-authors has long been making this point, not to pillory China, as is the case of the tendentious _Foreign Affair_s and Peterson pieces, but to highlight the great counterpart to China’s industrial success, namely India’s relative failure. The much-quoted Foreign Affairs piece showed low-skill export shares only for China, not for India. If you put both countries in the picture as Chaterjee and Subramanian have done on other occasions, the picture looks like this. China is far above the line, but India, almost as large in terms of population, is no less anomalous, just in the opposite direction. As far as global populations are concerned, and the imagining of tens of millions of “squeezed” jobs, it is this Sino-Indian pair that account for a huge share of the action. What this graph reveals is not China’s cheating, but India’s “greatest development failure”, at least this is the argument made Arvind Subramanian, this time in co-authorship with Devesh Kapur, in their major book, A Sixth of Humanity. Independent India’s Development Odyssey which appeared with Oxford University Press earlier this year. In this highly critical work on India’s development, China is repeatedly evoked, not to criticize but as a benchmark against which to illuminate what India’s political economy has not delivered i.e. large-scale formal employment for hundreds of millions of citizens. Kapur and Subramanian leave no doubt, if you want to understand why China, not India was the main driver of manufacturing globalization from the 1980s, don’t look to slots opening up in the division of labour thanks to the liberal mindedness of advanced economies, look to the contrasting political economy of the Maoist PRC and India’s post-independence political economy. As Kapur and Subramian note: The great divergence between China and India did not begin in 1978 with the Deng reforms—it was well underway by then. In one of the great ironies of modern history, the conditions created by Maoism turned out to be a great launching pad for industrial globalization. As the comparison of India and China in 1980 makes clear, to imagine manufacturing would be equally distributed when populations are so differently endowed in terms of educational and nutritional is fanciful. Here is the data from Kapur and Subramanian, data which I explored back at the very beginning of Chartbook. As Kapur and Subramanian insist, the striking fact is that even as India’s growth accelerated from the 1980s, structural change has not. Formal employment in India lags woefully behind. Why? As Kapur and Subramanian note, the path-dependent impact of India’s poor early start was devastating. The list of factors they mention is long and weighty: We argue for a new five-fold explanation applicable at different stages of Indian history: in the initial stages, the legacy of two key pre-1980s policies, the neglect of agriculture and the strangling of the domestic private sector, were critical. The failure of broad-based agricultural growth militated against rural industrialization, which would have been devoted to satisfying local needs that would have necessarily been labour intensive. Then, when the boom came after 1980, the thicket of regulation and broader labour protections that were legislated prematurely in a nascent democracy, underpinned by a deep ideological aversion to private capital in general and big capital specifically, became a barrier to attaining the size that would be necessary to compete globally. Similarly, the reforms after 1991, while wide-ranging, did not quite encompass non-tradeable inputs critical to manufacturing, namely, land, logistics infrastructure and power. A combination of low investment (logistics infrastructure), regulation (land) and the continued monopoly supply by state governments (power), combined with residual socialism, kept costs at 75–100 per cent above efficient supply. These factors were compounded on the supply side by the government, which dominated the formal labour market and established exorbitantly high wages at the lower end of the skill spectrum. This made their employment in the labour-intensive sector by the private sector less attractive. Finally, when the services sector and its exports boomed, wages soared even further via a Dutch Disease effect: one successful tradeable sector killed and cannibalized another less-skilled tradable sector, namely, manufacturing. Thus, scarcity-inducing policies of the planning era, precocious democracy and a Gandhian aversion to size; inefficient, monopolistic supply of critical non-tradable inputs; the behemoth of government; and super-successful skill-intensive services successively undermined India’s unskilled labour employment opportunities. The employment failure seems to have been over-determined. … Less quantifiable but no less important are some of the sociological factors that have undermined manufacturing and factory jobs. Take the impact of the success of the IT sector—located in urban areas with better working conditions, such as air-conditioned offices, good schools for children and attractive entertainment options. It became a more attractive place for engineering and management graduates to flock to. … Consider manufacturing and female employment. Indian society makes it difficult for women to work, reflected in India’s unusually low female labour force participation (elaborated in Chapter XIII). Indian society, in particular the routine harassment of women in public spaces, makes it even more difficult for them to travel long distances to take up work.37 Combined with onerous regulations on creating hostels and dormitories for women—which, in turn, prevents multiple shifts of operation—factories need to be located in areas with a large female labour pool. While firms can take apparel plants to female labour or bring them to the plants by building large-scale dormitories, this raises costs. If there was a case for subsidies to encourage labour-intensive manufacturing, housing subsidies to build dormitories for women workers would be a good place to start. All of this meant, that when opportunities did open up, in part thanks to adjustments in China, India was in no position to take advantage. Here is the account of the 2020s from Kapur and Subramanian. It stands in dizzying contrast to the one-sided, “China squeeze” argument delivered in the Peterson and Foreign Affairs pieces: In 2022, for example, India’s share of global exports in clothing (the canonical labour-intensive sector) was 3.1 per cent compared to 32 per cent for China. This is extremely disappointing because China started vacating export space in this sector after the Global Financial Crisis as its wages started rising; it then vacated further space in the aftermath of geopolitical developments that led investors to seek alternative investment locations. Between its peak and today, China lost about 7.5 percentage points of global export share (worth about $43 billion in 2022); over this period, India’s export share remained stagnant at 3 per cent, while that of Vietnam and Bangladesh rose by 3.5 to 4 percentage points. China’s loss did not translate into any gain for India in terms of low-skill exports and employment. Put differently, when the conditions for dynamism and prosperity were established after 1991, and even more tantalizingly when the global export opportunities opened up, it was as if India was a high-wage economy and only skilled labour could benefit from the dynamism. It had converted its physically abundant unskilled workforce into an economically expensive resource, penalizing its use. It is not my mission here to argue for or against Kapur and Subramanian’s interpretation of India’s development trajectory. The point in this context is simply that the “China squeeze” such as it is can only be understood, in relation to the heavy burden of domestic constraints that Kapur and Subramanian so unsparingly enumerate. I am concentrating here on India because it is the great counterpart to China and the unspoken reference point of the “China squeeze” discourse. But the point is more general. Can anyone with a straight face suggest that the main problems afflicting the development of South Africa or Nigeria, the great centers of mass underemployment in sub-saharan Africa, are cheap competition from China driven by Beijing’s industrial policy and an undervalued RMB? Likewise, is the main problem of the American working-class the threat of Chinese competition or the manifest crisis of social reproduction in the United States itself? The point here, as in the discourse around China shock 2.0 in Europe, is to insist that we should not normalize the world and pathologize China, without actually investigating what is going on in America’s industrial wastelands, the German car industry, or India’s lopsided labour market. One-sided pathologization should be understood for what it is, a polemical gesture. Concepts like China shock and China squeeze are, what Reinhart Koselleck, following Carl Schmitt, would have described as “asymmetrische Kampfbegriffe”, or “asymmetrical counter-concepts” or “asymmetrical combat concepts”. If the function of arguments like the “China squeeze” is to alert elites in the rest of the world of the need to rejuvenate and energize their development projects, so be it. But let us see the resulting discourses as the mobilizing interventions that they are. Interestingly, a significant slice of China’s public sphere - the so-called industrial party - have been obsessed for the last twenty years with precisely these questions of counterfactual economic history. Since the mid 2000s, a massive online discourse developed around an alternative history in which Chinese techno-patriots were asked to imagine how they would proceed if they had the possibility of traveling back in time to transport modern technology into the Ming dynasty (1368-1644) thus averting the “great divergence” of the 18th and 19th centuries. It is a fantasy of course, but also a goad. The point was not directed at Westerners. The alternate history is dramatically nationalist, but few n the West had even heard of it until recently. The adherents of the industrial party are not liberal moralists. They don’t project natural ladders of international development and ask why others don’t cede space. They take the Realpolitik of global economic development for granted. Their pointe was directed against fellow Chinese. The rallying cry of the alternative narrative was this: Now that we are beginning to gain steam and push forward on our national development path, now that we are breaking out of the inferior position assigned to us even in the early years following WTO accession, do not lose yourself in humanistic imaginings about better futures. In the spirit of Deng, they called on China to embrace the hard truth of development. Perhaps one might of the Industrial Party as a cultural trend born out of desire for symbolic revenge against those who had inflicted the century of humiliation. In terms of the various temporalities of the “China shock” - retrospective, prospective and counterfactual - one might think of the Industrial Policy discourse as truly speculative, conjuring up the China shock that never was. Or perhaps one might better think of it as imagining a world in which a powerful China was no shock at all, but simply a defining fact of modern history. I love putting out Chartbook. I am particularly pleased that it goes out for free to thousands of subscribers around the world. But, writing this newsletter takes a lot of work. If you are enjoying it and would like to support the project, sign up for one of the subscription options here. It is the equivalent of a fancy cup of coffee per month! Subscribe
Can Mamdani plan for city-owned stores deliver cheap food for New Yorkers?
Food costs have soared but existing businesses fear unfair competition and programs elsewhere yielded mixed results
‘Worst we’ve known’: UK turns to imports as drought and heat hit vegetable crops
Growers in dismay after scorching weather and lack of rain affect yields, sending wholesale prices rocketing
Immersive Experience Bolsters Sphere Entertainment’s (SPHR) Strong Performance
O’Keeffe Stevens Advisory, an investment advisory firm, released its second-quarter 2026 investor letter. A copy of the letter can be downloaded here. During Q2 2026, the market experienced notable dispersion between perceived AI losers and winners. The firm has made investments early in AI infrastructure companies, which yielded gains during market repricing. The second quarter […]
Mets Could Implement Bold Blueprint for Potential Sean Manaea Blockbuster
New York Mets veteran left-hander Sean Manaea does not seem like a valuable trade chip. Buried in the rotation due to a youth push and his own rough season, the southpaw still could command a decent yield in a trade. Is it considered a smart move by general manager David Stearns or a salary dump […] The post Mets Could Implement Bold Blueprint for Potential Sean Manaea Blockbuster appeared first on HEAVY.
Kustom Entertainment Amends Divestiture Terms With Cycurion Into Upgraded $6.1M Deal Featuring Immediate Cash Injection And 12% Yielding Preferred Equity
Cycurion Inc NASDAQ:CYCU:
Kustom Entertainment Amends Divestiture Terms with Cycurion into Upgraded $6.1M Deal Featuring Immediate Cash Injection and 12% Yielding Preferred Equity
Captures $250,000 in immediate non-refundable capital, eliminates warrants in favor of preferred equity, and sharpens execution on its $100B live...
Kustom Entertainment Amends Divestiture Terms with Cycurion into Upgraded $6.1M Deal Featuring Immediate Cash Injection and 12% Yielding Preferred Equity
Captures $250,000 in immediate non-refundable capital, eliminates warrants in favor of preferred equity, and sharpens execution on its $100B live entertainment and ticketing expansion. OVERLAND PARK, KS, July 27, 2026 (GLOBE NEWSWIRE) -- Kustom Entertainment, Inc. (Nasdaq: KUST) (“Kustom” or the “Company”), an emerging force in live music festival production and proprietary ticketing operations, today announced a major upgrade to its divestiture strategy. On July 23, 2026, the Company executed t
Political turmoil, lower pay yield small candidate pool for HTA’s top job
The Hawai‘i Tourism Authority has attracted about 60 applicants in its search for a new president and CEO, a significantly smaller candidate pool than past searches as the agency tries to recruit a leader after years of political turmoil and uncertainty about its future.
Erlanger Health System signs letter of intent to join Prisma Health
Erlanger Health System plans to join Prisma Health, creating a 27-hospital system in exchange for a $2 billion strategic capital commitment toward care in the Chattanooga, Tennessee area. | The tentative deal includes a $2 billion strategic capital commitment from Prisma, and would yield a 27-hospital, $9 billion operating revenue nonprofit in the southeast.
Science can serve dark as well as light
I’m not sure how many of you are watching “Star City,” Apple TV’s spin-off of its “For All Mankind” program (2019-present), but it’s one of the better sci-fi series I’ve seen in a while, with an impressively dark political message. (Some light spoilers below.) For the uninitiated, “For All Mankind” presented a slightly tweaked history of the U.S. space program in which it was the USSR that landed on the Moon first in 1969, and shortly thereafter put a woman cosmonaut on the lunar surface. This sparks an ongoing space race that, in the original series, yields a lot of benefits for humanity. President Nixon’s insistence on a female astronaut corps to compete with the Soviets boosts the feminist movement of the 1970s and the ERA passes. New fuels generated for the space program create clean and cheap energy around Earth. There are also some darker changes — the USSR is thriving well into the 2000s, there are terrorist counter-technology movements around the globe, laborers on Mars work in nightmarish conditions and organize strikes and riots, etc. the @smotus report is a reader-supported publication. To support this work, please become a paid subscriber. Subscribe That show offers glimpses into the subtle ways this Earth is different. Teddy Kennedy never went to Chappaquidick because he was racing back to Washington to deal with the space program crisis; he gets elected President in 1972. John Lennon survives his early 1980s shooting but Pope John Paul II does not. The Apple Newton succeeded. Pretty much the whole of season 4 is a setup for an Al Gore joke. Again, mostly, the vision that “For All Mankind” presents is a positive one, with technology advancing many human interests. “Star City” goes in a very different direction. This spin-off show is about the same set of events but from the Soviet perspective. As we meet them, the team of scientists and cosmonauts responsible for the lunar landing are still basking in their hero status, but their program is embedded deep in the Soviet security state of the late 1960s. Everyone’s apartment is bugged. Whole teams of clerical staff spend their days transcribing recordings of people’s lives. People in the program, including respected cosmonauts, are regularly arrested. An incredibly menacing Colonel Lyudmilla Raskova (Anna Maxwell Martin) forces confessions and tortures and kills, expressing little more than annoyance in the process. Meanwhile, the space program’s highly respected Chief Designer (Rhys Ifans) has a vision for the program that he knows the government will not approve. He insists that they need to think past the Moon to focus on colonizing the solar system, starting with Venus. (This is a rough parallel to the Americans’ pivot to Mars in the original show.) He essentially builds a secret space program within the space program, calculating that the government will embrace the mission after it has succeeded. (As an aside, I’m not sure why the Venus obsession, as a successful mission can’t produce the biggest public relations payoff: a cosmonaut standing on the surface holding the Soviet flag. Anyone standing on Venus would be immediately crushed by the 92-bar atmosphere and then cremated in the 900°F temperatures. But in a country with no free press perhaps the visual payoff was less valued.) But the overall vision is that the technological advances have only amplified the most fearsome aspects of the Soviet system. The state is paranoid (but not incorrect) about American spies and does monstrous things to protect its secrets. People are terrified to trust each other. Classic banality-of-evil figures order people to harm those they care about; those people comply rather than get shot. Others are forced into criminal behavior to protect loved ones. We’re reminded all the time these days of what happens when a government despises science. It manifests in the defunding of schools, the elevation of fossil fuels as the rest of the world pivots to solar, outbreaks of measles and diarrhea, etc. But “Star City” offers a vision of a bad government that likes science. It’s not encouraging. It’s not yet clear if there will be a season two of this show. But I strongly recommend season one. It’s both thoughtful and gripping. Share
USF marine science fire: St. Pete recovery operations save vital scientific research despite heavy damage
University leaders announced that recovery operations have yielded remarkably successful results two months after a lightning fire heavily damaged the University of South Florida St. Petersburg's College of Marine Science in May.
How smarter water management can reduce arsenic in rice
Rice is a staple food for more than half of the world's population. But unlike other major grains, it naturally absorbs arsenic — a known carcinogen — because of the unique way it is grown.For years, scientists have searched for ways to reduce arsenic in rice without sacrificing crop yields or creating new food safety concerns. Now, new research co-authored by an Arizona State University professor shows that a relatively simple change in how rice fields are managed could help accomplish both.
Bombing Iran, Then a Tentative Accord Didn’t Work. Does Trump Have a Plan C?
The administration appears to be reverting to an all-stick, no-carrot approach. But it has yet to answer why it believes economic warfare and bombing will yield a different result this time.
Japan benchmark bond yield hits 30-year high on inflation, fiscal health concerns
The benchmark 10-year Japanese Government Bond (JGB) yield hit a 30-year high on Thursday, as rising oil prices rekindled inflation concerns and investors remained wary of Japan's fiscal health.