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Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?
Almost four years ago, we published that SMIC had started shipping 7 nm (N+1) chips. Now, SMIC is shipping its third-generation 7 nm (N+3) process in Huawei’s Kirin 9030, with a minimum metal pitch of 32.5 nm, about 10% tighter than the 36 nm minimum metal pitch shipping in Intel’s latest Panther Lake CPUs on 18A. The headline is true, but incomplete cherry picked metric. N+3 reaches the density of TSMC N6 through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control. We found this and more in our reverse engineering and teardown where we cover SMIC’s N3 process technology, Huawei’s packaging, memory, architecture, and more. SemiAnalysis has been building a state-of-the-art teardown lab in Oregon capable of analyzing the world’s most advanced and important chips over the last year and half. We have already generated revenue on advanced datacenter chip teardowns including our recent reverse engineering of a major TSMC customer’s COUPE CPO optical engine + EIC 3D stack. This is the first public report from the SemiAnalysis Teardown Engineering & Evaluation Lab, or STEEL for short. The lab is aggressively scaling up and out and we’re excited to announce it publicly. This is a bit of inconvenient timing for TechInsights as they are private equity owned and currently being sold while having enjoyed virtually no credible competition for decades. This has led to TechInsights underinvesting in CAPEX. SemiAnalysis exceeds TechInsights in revenue despite no venture or private equity ownership and being founded only 6 years ago. Because we have no external investors and are founder led, we move faster, build faster, and we can release client chip teardowns for free regularly, while focusing on datacenter for our major clients. Here’s the first public image from our lab, the HiSilicon Kirin 9030 Pro SoC: This report will detail our teardown of the Kirin 9030 and our findings on SMIC’s N+3 process, the most advanced in China. For comparison, we’ll show our teardown of the MediaTek Helio G99, made on TSMC N6. Through this comparison, we can look at the effect of export controls – SMIC N+3 and TSMC N6 are comparable nodes, but one is heavily export-controlled, the other free to use the West’s most advanced equipment. Here we see both China’s progress and constraints. SMIC N+3 reaches TSMC N6-class logic density, but it requires far more aggressive DUV multi-patterning, so it does not match N6 on process maturity or cost. The Kirin 9030 Pro performs similarly to three-year-old Android flagships, and trails far behind the current flagship SoCs from Apple, Qualcomm, MediaTek, and Samsung. The efficiency gap is even wider. Export controls have not stopped Huawei and SMIC from shipping advanced silicon, but they have forced a different path. Without EUV, SMIC is leaning harder on DUV multi-patterning, DTCO, and increasingly complex integration. The roadmap continues forward through tighter design rules and backside power, but each step adds cost and process risk. Huawei’s τ scaling and LogicFolding show another path: stacking active logic and recovering density through advanced packaging and system-technology co-optimization (STCO). To understand the Kirin 9030, we must first understand Huawei’s SoC history. HiSilicon is Huawei’s chip design arm, responsible for the Kirin smartphone SoCs, Kunpeng server CPUs, Ascend AI accelerators, and switch/router networking silicon. Before export controls, Huawei was TSMC’s largest customer – the only customer on TSMC’s first EUV node, N7+, and among the first on N5, alongside Apple. That ended in late 2020. Huawei switched to Qualcomm SoCs in its flagship smartphones, though export controls limited them to 4G-only variants. In late 2023, Huawei returned to in-house silicon with the Kirin 9000s, a successor to the Kirin 9000, fabricated on SMIC N+2 instead of TSMC N5. In the following years, they released the Kirin 9010 and 9020 on the same N+2 process. These chips used Huawei’s in-house TaiShan CPU cores and Maleoon GPU. We have not torn down a Kirin 9020 ourselves, so the predecessor die shot is from Kurnal. The die shots show how Huawei spent its silicon budget: which functional blocks are where, and how their areas compare to the predecessor. First, a quick guide to the major blocks on the die. The total die area is nearly identical, but the 9030 uses that area more aggressively. A denser process lets Huawei fit an extra middle CPU core, more GPU and NPU cores, and larger caches into the same footprint. In contrast, the Helio G99 is a much smaller, low-cost SoC, built for budget smartphones rather than a flagship device. While the Kirin 9030 is ~140 mm², the G99 is only ~29 mm², roughly one-fifth the area. The underlying TSMC process technology, however, is directly comparable as a baseline for analyzing SMIC’s. The Kirin 9030 is an evolutionary refresh, not a clean-sheet design. Its CPU, GPU and NPU cores carry over the 9020’s families, and the gains come from three levers: the SMIC N+2-to-N+3 process step, DTCO and floorplan work, and incremental microarchitecture. Area is where the first two show up, and the 9030 scales well here. Performance and efficiency are the harder test. Huawei’s design holds up better than its node would suggest, but the chip still trails, both because N+3 sits behind the leading-edge nodes and because its cores, while competent, remain a few generations behind the newest designs. The new prime core is an incremental update. The main changes are a 10% frequency increase from 2.5 GHz to 2.75 GHz and a doubling in the L2 cache from 1 MiB to 2 MiB. Despite the increased cache, the core size decreased by 7.6%. Excluding the private L2 cache, the core size decreased by 21%. This is a large reduction for an incremental node. Compared with the TaiShan New V120 core in the Kirin 9020, the Kirin 9030’s middle core is almost unchanged architecturally, yet each core shrinks by ~22%. Most of that comes from the move from N+2 to N+3, with layout likely accounting for the rest. Visually, the most noticeable change is the increase from 3 middle cores to 4. There is also a 20% increase in the shared L3 cache of the big cluster. This helps to improve multi-core performance without sacrificing much in terms of area. Even with each core shrinking, the big CPU cluster’s total area is essentially unchanged. The per-core savings went back into an additional middle core and larger caches. The tiny cores shrank less than the prime core (excluding its L2 cache) and less than the middle cores. This is likely because fixed overhead is a larger share on a small core. We cannot resolve any architectural changes from the die shot alone, but the per-clock and efficiency gains shown below point to more than pure process and layout scaling. The area reduction was offset by a doubling of the shared L2 cache from 2 MiB to 4 MiB, leaving the total tiny CPU cluster area slightly larger. Area is the easiest improvement to see from a die shot, but it is only one part of PPA (power, performance, area). For modern logic, power and performance matter just as much, and often more. Since Dennard scaling broke down in the mid-2000s, voltage and frequency have not scaled in step with transistor dimensions, so each node has had to fight harder for gains in performance and efficiency. The starkest comparison is not Kirin 9020 versus Kirin 9030 Pro. Apple’s efficiency cores run circles around Huawei’s prime core. Apple’s low-power core delivers 20% higher integer performance while drawing only 1 W, compared with 4.5 W for Huawei’s prime core. N+3 matches TSMC N6, but N6 is several generations old. Apple and Qualcomm build on N4 and N3P, which are denser and sit on a better voltage-frequency curve, giving them a larger transistor budget and more performance per watt. The 9030’s own cores did improve. The middle and tiny cores gained 17% and 14% in per-clock integer performance over the 9020, with floating-point flat on the middle core and up 11% on the tiny. The tiny core improves cleanly, with performance rising while power falls and efficiency increases by 45% in integer and 24% in floating point. The middle core is mixed: integer performance rises but power rises faster, cutting integer efficiency by 7%, while lower power lifts floating-point efficiency 16%. Per-clock gains at the same or lower frequency are microarchitectural, so the cores are tuned, not just shrunk. Both also failed to hold their rated maximum frequencies, pointing to thermal, power, or stability limits. Per clock, the middle core sits around Arm Cortex-A720 and the tiny core near the Cortex-A520; absolute performance trails because Huawei clocks them much lower. The prime core is roughly Cortex-X2 class per clock, a 2021 design. Apple’s 2020 M1 Firestorm core is still 35% higher per clock and 57% faster in absolute integer performance at a similar 4.5 W. The current leading edge is further ahead again: the Apple M5 P-core is 60% higher per clock and 2.7× faster, the Arm C1 Ultra 45% higher and 2× faster. Matching older high-end cores per clock is a genuine design achievement. What Huawei cannot match is the voltage-frequency curve and transistor budget of leading-edge nodes, which let Apple, Qualcomm and others spend more transistors in the same area on wider cores, larger caches and deeper buffers while running at lower voltage. Huawei’s LogicFolding roadmap is one answer, stacking active logic to recover density and shorten signal paths. We return to it later. The GPU compute units (CUs) changed more visibly than the CPU cores, moving to a more rectangular layout for both the arithmetic logic unit (ALU) clusters and the CU overall. Even with ray-tracing support added, a CU shrank ~28%. However, that shrink is offset by the increase from 4 to 6 CUs and the area outside the CUs grew 33%. Overall, the GPU cluster is larger by ~10%. The GPU is where Huawei makes its biggest gains. The Maleoon 935 is not competitive with current flagships, but it is a large step up from the 920 and reaches older-flagship territory. In 3DMark it is 70% faster in Wild Life Extreme (WLE) and 79% faster in Steel Nomad Light (SNL) than the 920; with 11% higher clocks and 50% more CUs, the ~67% theoretical uplift roughly matches WLE and is beaten by SNL. It edges ahead of the Snapdragon 8+ Gen 1 in WLE and SNL, and the Dimensity 9200 and Apple A16 in WLE, but stays far behind newer parts: the Snapdragon 8 Elite Gen 5 and Dimensity 9500 are ~2.4–2.6× faster in WLE and ~3.2× faster in SNL. The Maleoon 935 is Huawei’s first GPU with hardware-accelerated ray tracing; there it lands slightly ahead of the Exynos 2200, and on par with the Apple A16, with current flagships up to 3.7× faster. The Neural Processing Unit (NPU) saw the largest structural changes of any block, moving from a Lite and a Tiny core in the Kirin 9020 to a Lite and two Tiny cores in the Kirin 9030. Both core types also show significant layout changes. This is a reversal in Huawei’s NPU design. The Kirin 9000 5G, its last flagship chip on TSMC N5, used two Lite and one Tiny core. The series of SoCs on SMIC N+2 moved to one Lite and one Tiny core, likely for area savings. With the Kirin 9030, Huawei has shifted back toward a larger multi-core NPU cluster, but with the additional area going to a Tiny core rather than a Lite core. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Before diving into the process stack, the package and memory are worth separating from the SoC itself. The Pro variant of the Kirin 9030 carries 12 GB of Samsung DRAM, with two stacks of four dies each. The dies were identified as the K4L2E165YD, a 12 Gb LPDDR5X-9600 device fabricated on Samsung’s 1a node, the fourth generation of its 10 nm-class DRAM after 1x, 1y and 1z. 1a has shipped in volume since 2022, so this is current memory rather than older-node inventory. The 16 GB Pro Max variants we obtained were found with both CXMT and Samsung packages. The CXMT package is marked CXDD7JEDM, with two stacks of four dies, packaged in week 45 of 2025. The inferred die dimensions from X-ray computed tomography (CT) are consistent with a known density of ~0.3 Gib/mm² for the CXMT G4 process, roughly equivalent to other manufacturers’ 1z processes. The Kirin 9030 uses a typical integrated package-on-package (iPoP) stack: multiple DRAM dies in a memory package sit above an organic redistribution layer (RDL) interposer, which sits above the SoC and package substrate. The full package is then mounted to the printed circuit board (PCB) through ball-grid array (BGA) solder bumps. The memory package substrate is a thin bismaleimide-triazine (BT) laminate carrying the LPDDR5X stack. The organic RDL interposer over the SoC routes the PoP signals around the die and carries possible dummy thermal copper pillars. The package substrate, a thicker Ajinomoto Build-up Film (ABF) build-up over a BT core, fans the flip-chip bumps out to BGA pitch and embeds the power planes. The whole stack is organic. The only silicon is the SoC and the LPDDR5X dies; there is no silicon interposer. Keeping it all-organic brings the package’s coefficient of thermal expansion (CTE) close to the PCB’s, reducing board-level warpage, and avoids the cost of a silicon interposer the SoC’s bandwidth does not need. In an iPoP stack, the memory package connects to the organic RDL interposer through an array of solder bumps. Underfill fills the gap around those bumps, adding stiffness and protecting the joints from mechanical stress. The Pro and Pro Max variants differ here, which we cover behind the paywall. The die shot and architecture tell us how Huawei allocated its silicon budget. The process tells us what SMIC can manufacture. We use the Helio G99 as the process reference for TSMC N6. Both SMIC N+3 and TSMC N6 are evolutions of previous 7 nm-class nodes. We used targeted TEM cross-sections through logic and memory regions, imaged in both fin-cut and gate-cut directions. Each cross-section caption gives its horizontal field width (HFW), the real width of the imaged area. We start at the transistor fins, then move up through standard cells, local interconnect, and SRAM. SMIC has not overtaken Intel or TSMC. It uses aggressive DUV scaling and DTCO to reach N6-class density, but that density doesn’t translate into comparable performance and efficiency, for two reasons: the node gap to leading-edge nodes, and Huawei’s core designs. Fin Profile One of the most important knobs in a FinFET process is the fin profile: the shape of an individual fin and the channel where current passes from source to drain. The ideal fin is tall, narrow, and nearly vertical. A taller fin increases effective channel width, while a narrower fin improves electrostatic control by thinning the body the gate must control. Push either too far, and the process pays for it: weaker drive current, fragile fins, taper, footing and line-edge variation that hit yield and device variability. The Intel 22 nm, 14 nm, and 10 nm fin cross-sections show how FinFET nodes have improved over time. 22 nm fins were a first-generation structure, relatively short, wide and strongly tapered. The shape limits current density and reduces gate control uniformity across the height of the fin. At 14 nm and 10 nm, Intel pushed the fins taller and narrower while also making the sidewalls more vertical. Rather than shrinking the device, these changes increase the effective channel width per fin and improve electrostatic control. The trade-off is that taller fins at tighter pitches are much more difficult to manufacture. Now, let’s compare the Helio G99 on TSMC N6 with the Kirin 9030 on SMIC N+3. Both processes are in the same class, with fin pitch of 30-32 nm on N+3 and 34 nm in our N6 cross-section. The pitch for N6 is especially interesting as N7’s HD library is generally listed with a 33 nm fin pitch, and N6 did not shrink pitches directly. Its density gains came from DTCO instead of tighter pitches. The 34 nm pitch was stable across our sampled region and serves more as a comparison against the SMIC N+3 we have not investigated further. Pinning down N+3’s fin patterning scheme takes more than one core unit. The CPU cores show a dense ~32 nm pitch, with the pitch between N-P fin pairs alternating between 78 and 88 nm. Logic alone may be consistent with dual-pitch mandrels of 120 and 110 nm, but this is a complex and unusual approach. Combining the pitch from the the 8T SRAM, which has more complex repeat unit, with the CPU core sequence allows us to reverse engineer the patterning steps with more confidence. As both the logic and SRAM should share the same base grid, a single CD mandrel lithography pattern with 128 nm pitch undergoing SAQP produces a die-wide ~32 nm grid (128 nm/4), which supports the pitch sequencing seen in both logic and SRAM cells. In the sampled cross-sections, N+3 shows a taller, narrower, higher-aspect-ratio fin than N6. The measured fin aspect ratio is ~9.5:1 on N+3 versus 7.8:1 on N6. N+3 also shows less top rounding, with an estimated radius of ~2 nm, compared with 2.8 nm on N6. Even though the fin widths differ, the ratio of top rounding to fin width tells the same story, with N+3 at 0.37 and N6 at 0.44. In a geometric sense, lower is better; a perfectly rectangular fin would have no top-rounding penalty. These are single-digit-nanometer features measured from a handful of cuts, so treat the absolute numbers as approximate. The important result is the relative gap: N+3’s fins are consistently taller, narrower and less rounded than N6’s. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. Standard Cell A standard cell is the basic building block of chip layout: a fixed-height row pairing one NMOS and one PMOS transistor that share a gate, tiled in a grid to build logic blocks. The key dimensions are contacted gate pitch (CGP), cell height (CH), fin count, and the lower-metal routing grid. To measure density, we use the Bohr metric: a weighted average of NAND2 gate area (60%) and scan flip-flop area (40%). This represents a realistic mix of combinational and sequential logic. This metric has its limitations, especially for complex cell layouts like TSMC’s FinFLEX, which alternates cells with different fin counts. Even so, it is the best metric for a pure process-level comparison. Another important measurement is the fin pitch; it refers to the distance between two fins of the same transistor. In a FinFET process, multiple fins are used in each transistor to increase the drive current and thus performance. TSMC N6 ships both a high-density (HD) library with 2 PMOS and 2 NMOS fins per cell, and a high-performance (HP) library with 3 of each. More fins under the shared gate mean more effective channel width. HP cells switch harder at the cost of area. Designers mix the two on a die, primarily spending HP cells on timing-critical paths, and matching their PPA targets. In the Cortex-A55 core of the Helio G99, we found a cell height of 240 nm for the HD cell. MediaTek has used HD cells in the G99 to minimize die size and thus cost. As an SoC for budget smartphones at ~$100, this is essential. By contrast, we found only one library in the Kirin 9030, with 2 NMOS and 2 PMOS fins. This suggests a narrower library strategy than TSMC N6, where both HD and HP libraries are widely used. This likely reflects the smaller customer base and the more constrained domestic design and electronic design automation (EDA) ecosystem. In all three CPU cores of the Kirin 9030, we found cell heights of 228 nm, 5% smaller than on N6. This is also a reduction of 9.5% over SMIC N+2’s cell height of 252 nm. SMIC N+3 and TSMC N6’s HD library both feature a CGP of 57 nm. For SMIC, this is a 9.5% shrink over N+2. In the past, CGP and cell height alone may have been enough to compare transistor density. Now, however, we must consider scaling boosters and DTCO as well. SMIC’s density gain does not come from EUV. It comes from using every available DTCO booster aggressively. First is fin depopulation: reducing the number of NMOS and PMOS fins in each cell. The first FinFET nodes started with 3 or 4 fins for each transistor. SMIC N+3 and TSMC N6 HD both use only 2 fins per transistor, trading drive strength for density. Next is contact over active gate (COAG). By landing the gate contact directly over the active gate, instead of out over the isolation region, the cell height drops. N+3 integrates COAG while N6 does not. Our N+3 gate-cut cross-sections indicate COAG, with the gate contact sitting over the active region, while N6 shows an off-gate contact. Last is single diffusion break (SDB). Diffusion breaks are inserted between cells in the same row to provide electrical isolation, but they also introduce local layout effects (LLE), layout-dependent shifts in electrical characteristics. In the past, a double diffusion break was used, consuming the space of two CGPs. SMIC N+3 and TSMC N6 instead use SDB, saving area but increasing LLE sensitivity. This must be controlled at the process level and accurately modeled in the process design kit (PDK) so that EDA tools can account for it. Overall, SMIC N+3 has a transistor density of 113.4 MTr/mm², slightly above TSMC N6 at 107.7 MTr/mm². Even without EUV, SMIC has achieved density beyond TSMC’s mature N6 node which utilizes EUV. Metal Stack The smallest critical dimension in the teardown is M0; SMIC N+3 uses a 32.5 nm local metal pitch. That is smaller than the 36 nm M0 pitch on Intel 18A in Panther Lake. However, this does not mean that SMIC has a better process than Intel 18A or TSMC N3P. M0 is a local intra-cell routing layer. Its usefulness depends on the full interconnect stack: M1 and M2 pitch, track count, via and line resistance, design rules, mask count, overlay control, and routing flexibility. The 32.5 nm M0 is consistent with self-aligned quadruple patterning (SAQP), whose four-population line-width loading we read coarsely as alternating widths of 21.5 to 24 nm; M1 and M2, at 38 and 40 nm, are consistent with self-aligned double patterning (SADP), a single A/B split. On TSMC N6, M0, M2, and M3 sit at a relaxed ~40 nm and are consistent with SADP-class double patterning, with no need for quadruple patterning. That said, we measure M2 for example at ~43 nm, likely inflated by sparse routing. We do not assign any specific layer to EUV from our cross-sections; the distinction we can draw is double versus quadruple patterning, not lithography wavelength. Transistor-level density in the front-end-of-line (FEOL) sets an upper bound, but the design is ultimately limited by what the interconnect stack can route. The lowest metals are the most important for standard-cell density, but the semi-global and global layers determine how usable that density is at the block and chip level. Two axes are commonly used for chip cross-sections: the fin-cut and the gate-cut. The micrograph above is a fin-cut and shows metals 0 through 3. This axis lets us see the even-numbered metals, with M0 right above the fins. There are two kinds of M0 lines. The first are the power rails; these are wide wires for the VDD and VSS running horizontally at the top and bottom edges of each standard cell. The wide wires measure 55 nm across, more than double the other M0 lines. Their width minimizes resistance and reduces IR drop. The second kind are intra-cell wires, short segments within the cell that connect terminals to M1. These have alternating widths between 21.5 and 24 nm. The M0 pitch is 32.5 nm, a 19% reduction versus N+2 and N6. At this pitch, DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost. M0 is below what a single DUV-defined spacer (SADP) can resolve, so SMIC cascades a second spacer step (SAQP). The cross-section reflects the cost: the M0 trenches are visibly more re-entrant (narrower at the bottom than the top) than M1 or M2 on the same chip and carry a bright barrier-rich foot where the trench meets the etch-stop layer. That shape is partly the intended damascene profile, as a slightly narrow bottom helps void-free copper fill, but its magnitude at M0 is driven by the tight pitch and the higher trench aspect ratio. Intel 18A supports an M0 pitch of 32 nm, although Panther Lake has only shipped with a looser 36 nm pitch. This is due to Intel’s heavy usage of HP libraries. Among leading-edge nodes, 18A has the loosest M0 pitches due to PowerVia. With power routing moving to the backside, congestion is reduced, and the entire front-side metal stack can be used for signal routing. M2 is the first true inter-cell routing layer. It runs horizontally like M0 but spans across multiple cells to carry block-level signals. The M2 pitch sets the cell’s track height – the number of M2 tracks that fit between the VDD and VSS rails, defining what the library calls a 6-track or 7.5-track cell. This layer is the most important, limiting the routing of entire blocks. SMIC N+3 features a 5.7-track cell. The M2 pitch is 40 nm, a 5% decrease over N+2 and the same as N6. This shrink keeps the pitch at the edge of what is possible with double patterning. Future nodes will need to increase the number of masks for M2 as reducing the number of tracks is much harder due to the limitations in routing. The micrograph above is in the perpendicular direction, the gate-cut, and shows metals 0 through 4. This allows us to see and measure the odd-numbered vertical metal layers. The M1 pitch is 38 nm, 9.5% less than N+2 and 33% less than N6. The M1-to-gate ratio matters because it sets local routing flexibility. N+2 and N+3 use a 3:2 ratio, while N6 uses a 1:1 ratio, explaining the huge differences in M1 pitch. The more M1 lines there are compared with the gates, the more flexibility there is for power and signal crossing within the cell. Routing flexibility enables more complex and better cells. Clean fractional ratios are also preferred as a grid is periodic and improves layouts. The 3:2 ratio gives SMIC more local routing flexibility than a strict 1:1 grid, but it also complicates layout and patterning. This is a DTCO choice, with SMIC increasing process complexity to recover density and routability without EUV. This 3:2 ratio is not very popular in the leading-edge nodes. TSMC has only used it on N7+, the N5 family, and the short-lived N3(B). They have switched back to a 1:1 ratio for N3E. Intel has only used it on the 10 nm/Intel 7 family, with Intel 4, 3 and 18A all using a 1:1 ratio. Samsung is the only one still using a 3:2 ratio at the leading edge, using it in the SF4 and SF3 families. It remains to be seen if SMIC will remain at a 3:2 ratio or move to a 1:1 ratio with its future nodes. The industry is still actively exploring these local-routing ratios. At VLSI 2026, imec will be presenting work on even higher ratios, including a 2:1 scheme that can reduce area by up to 14%. We will be covering the conference in a future newsletter article. Subscribe We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Interested in joining us on this ride and think you can be a difference maker? Check out our Careers page. The final local interconnect layer for N+3 is M3, with a pitch of 44 nm. The M3 pitch is the same as on N+2 and 10% larger than on N6. The semi-global layers carry the majority of block-level signal routing. They have a coarser pitch than the lower local layers. On leading-edge nodes, they are designed to sit at the limit of DUV single patterning. M4 through M11 pitches were found divided between 80–82 nm (M4–M6), 128 nm (M7–M10), and 148 nm (M11). Given limited sampling, it is possible these are divided further in dense routing areas. At the top are two giant metal layers, M12 and M13. These have kept the same pitches as N+2 at 1920 nm and 4600 nm respectively. While the lower layers’ pitches are generally fixed by the process and library, the upper layers vary much more in pitch and count, depending on the design. Even two smartphone SoCs on the same process can have wildly different metal stacks. The Helio G99 carries fewer routing layers, reaching coarse metal pitches of 850 nm by M9, while the larger and higher-performance Kirin 9030 keeps fine pitches until M11. SRAM At the leading edge, SRAM is much more difficult to scale than logic. TSMC’s latest nodes have seen little to no bitcell scaling, while logic still has more DTCO levers to pull. While looking for other logic libraries in the GPU compute units, we stumbled upon the SRAM. The most common type of SRAM has 6 transistors (6T), but this cell had 8 transistors (8T) instead. 8T SRAM adds two transistors to form a dedicated read port. Unlike a 6T cell, where reading disturbs the storage, the decoupled read port removes read-disturb, improving read stability and letting the cell be pushed harder for performance. At first glance, the cut looked like an unusual logic library, with each cell row having 3 fins of one polarity and 5 fins of another. The rows also alternated in orientation. Energy-dispersive X-ray spectroscopy (EDS) resolved our confusion. The cut had not landed on the GPU logic, but on the SRAM macro beside it. The unusual fin pattern was due to the SRAM library. We return to EDS in the process flow analysis behind the paywall. SRAM libraries are not like traditional logic libraries. Due to the unequal number of PMOS and NMOS transistors, they require specialized rules and layout libraries. They do not need the flexibility of logic libraries, so they are hyper-optimized for one purpose: dense, reliable memory. The SRAM cell we found is a 1:2:2-2:2 cell. This means there is 1 fin per pull-up (PU) PMOS transistor, and 2 fins per pull-down (PD) and pass-gate (PG) NMOS transistor. These 2 PU, 2 PD and 2 PG transistors would usually form a single 6T high-current cell (HCC). An 8T HCC adds a read-pull-down (RPD) and a read-pass-gate (RPG) NMOS transistor, each with two fins. We measured a cell height of 406 nm, which brings the bitcell size to 0.0463 µm². That is a theoretical peak density of 21.6 Mib/mm². We estimate that a 6T HCC would have a cell height of 292 nm and a size of 0.0337 µm². This is ~12% larger than a 6T HCC on Intel 3 and 4. We also estimate the 6T high-density cell (HDC) to have a cell height of 228 nm and a size of 0.0260 µm². This is coincidentally the same as the logic standard-cell height measured earlier. The estimate puts the cell near Samsung 7LPP/5LPP and slightly below TSMC N7/N6. That is a theoretical peak density of 38.5 Mib/mm². 6T HDC is arguably the most important cell as it is used for the largest caches in a chip, the L3 caches and system-level cache (SLC). Both the Kirin 9020 and 9030 have split the SLC into 4 banks to raise total SLC bandwidth. In the Kirin 9030, the SLC increased from 2 MiB to 3 MiB per bank. Correspondingly, the number of arrays within the bank also increased by 50%, from 16 to 24. Each array can store 128 KiB and forms an orderly pattern on the die shot. From the Kirin 9020 to the Kirin 9030, the area of a 128 KiB SLC array decreased from 0.0477 mm² to 0.0392 mm², an 18% shrink. The achieved density is 25.5 Mib/mm², 66% of the theoretical maximum. While the SLC was quite similar across both chips, the L3 has seen some major changes, particularly in terms of its layout. The total capacity also went up from 10 MiB to 12 MiB. Much like the SLC, the L3 is also split into 4 banks. In the Kirin 9020, an L3 bank consisted of 16× 128 KiB arrays and 16× 32 KiB arrays. However, an L3 bank in the Kirin 9030 instead consists of 48× 64 KiB arrays. In the Kirin 9020 L3, a 128 KiB array was 0.0513 mm² and a 32 KiB array was 0.0154 mm². The size of the 128 KiB array is different on the L3 and SLC as the assist circuitry for the two arrays differs depending on their purpose. In the Kirin 9030 L3, a 64 KiB array is 0.0210 mm². Although not a like-for-like comparison, normalized for capacity, it is 18% smaller than the 9020’s 128 KiB L3 array and 31% smaller than its 32 KiB L3 array. The achieved density is slightly lower than the SLC, at 23.8 Mib/mm², 62% of the theoretical maximum. Unlike the L3 and SLC, the prime cores’ private L2 cache uses a 2-bank design. As the prime cores’ L2 is latency-critical, it likely uses 6T HCC instead of 6T HDC. The 9020 has 16 arrays in each bank while the 9030 has 32. Each array has a capacity of 32 KiB. A 32 KiB array in the L2 shrank from 0.0171 mm² to 0.0142 mm², ~17% smaller. The density is 17.6 Mib/mm², ~59% of the theoretical maximum for 6T HCC. SRAM scaled well from N+2 to N+3, shrinking by ~19%, close to the theoretical logic shrink. The caveat is that N+2’s bitcells were unusually large, bigger than comparable 7 nm-class nodes, so part of the gain is catch-up rather than true scaling. With the insights from STEEL’s teardowns, we will be doing a deep dive into SRAM in a future newsletter article. Subscribe Everything above came out of a single STEEL teardown: die annotation, block-level area analysis and TEM cross-sections through logic and SRAM. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline or to commission a custom teardown, contact sales@semianalysis.com. Future Roadmap The same cross-sections that pin down N+3 also show where SMIC can go next. Although N+3 is already close to the practical limits of DUV multi-patterning in several layers, SMIC still has a few scaling levers left. A theoretical N+4 would likely start with cell height. N+3 uses 5 M0 tracks between its power rails. Moving to 4 M0 tracks, as on SMIC N+2 and TSMC N6, could reduce cell height by roughly 15%. The routing grid is only one side of the shrink; the front end also must fit into the smaller cell. One possible FEOL lever is reducing the p-to-n isolation spacing from two diffusion grid units to one. Intel used this scaling booster on Intel 4, and TSMC did so on its N3 family. This path trades layout flexibility for density. Fewer M0 tracks reduce local routing resources, while tighter p-to-n spacing raises integration and design-rule difficulty. M2 is also constrained by the cell height shrink. For SMIC to maintain a ~5.7-track cell, M2 would need to move toward ~35 nm. That would move another layer into SAQP territory. SMIC could also reduce the CGP from 57 nm to 54 nm. Intel reached a similar CGP on Intel 10 nm/Intel 7 without EUV. The local interconnect is also tougher. If SMIC keeps the 3:2 M1-to-gate ratio, M1 would need to shrink to 36 nm and would likely require SAQP as well. If SMIC moves to a 1:1 ratio, M1 could relax to 54 nm, but it would give up routing flexibility. Under this theoretical path, we estimate that SMIC N+4 could reach a cell height of 198 nm and a CGP of 54 nm, implying a Bohr density of 137.8 MTr/mm², on par with TSMC N5 or Samsung SF4. However, the difficulty is cumulative. Each step is individually plausible, but together they make N+4 harder than the transition from N+2 to N+3. It will likely take longer, cost more, and carry less process margin. A theoretical N+5 would require a larger integration shift. One possible path is backside contacts (BSCon), moving power routing and source/drain contacts to the backside, which would reduce front-side routing pressure and enable another reduction in cell height. The front-side metal pitches could relax to reduce the process complexity. M0 would likely relax slightly to ~34 nm, and M2 and M4 pitches could relax further. CGP is unlikely to shrink much further. Even with EUV, 48 nm has been the practical limit for yield and process control. This approach would allow N+5’s cell height to fall to 170 nm and its CGP to 53 nm. This implies a Bohr density of 163.6 MTr/mm², on par with Intel 18A’s HP library. However, this would not make N+5 cost-competitive with the leading edge. It would reach a similar density through a much more expensive route. The integration difficulty rises sharply, with new process flows for backside alignment, wafer thinning, contact reveal, and backside metallization. Past this point, standard density and interconnect scaling become increasingly unattractive. That is where Huawei’s roadmap stops looking like a normal foundry roadmap and starts looking like a packaging roadmap. At ISCAS 2026, Huawei unveiled its tau (τ) scaling law, reframing process scaling in the time domain. τ is the time cost of data movement and processing: switching delays in transistors, RC signal propagation delays in circuits, compute, memory, and networking latency. Outside Huawei’s terminology, this is called system-technology co-optimization. This is Huawei’s answer to its lack of EUV lithography. Without EUV, planar density cannot keep pace with TSMC, Intel, or Samsung. If transistor density cannot shrink further, Huawei’s alternative is to shorten wires, reduce buffering, and stack logic vertically. “LogicFolding”, Huawei’s implementation of this new scaling idea, is, in practice, an aggressive 3D stacking approach. AMD V-Cache places SRAM above or below a CPU die. AMD’s MI350X places active interposer dies (AIDs) underneath accelerator and compute dies (XCDs), with the AIDs handling cache, IO interfaces, the network-on-chip (NoC) and embedded metal-insulator-metal (MIM) capacitors. With LogicFolding, parts of the same logic block are split across multiple active dies bonded face-to-face at ultra-fine pitch. This allows Huawei to shorten some critical paths and reduce buffer overhead, not merely add cache capacity or offload the IO and interconnect. Shortening wires is where the higher clocks come from. A large share of a modern core’s delay and energy budget goes into driving long interconnects and the repeater buffers along them. LogicFolding distributes a block’s critical-path gates across multiple stacked tiers bonded at a very fine pitch, so the bond interface behaves like an additional metal layer and the longest paths get shorter. That is how Huawei expects to recover frequency and efficiency it cannot get from the process alone. Huawei’s roadmap shows its intent. Prime core frequency is targeted to rise from 2.75 GHz in the Kirin 9030 to roughly 5 GHz by 2031, far beyond what planar scaling alone could deliver. Prime cores with 3.1 and 3.39 GHz clocks are being tested in its labs, although their power consumption is unknown. Beyond that, chips are in the design, simulation or pathfinding phase, meaning the frequencies are targets. However, the direction matters more: LogicFolding also helps with performance, not just density. The catch is that Huawei’s density claim is not directly comparable to foundry densities. A stacked design can report more transistors per package footprint by adding active layers, even if each patterned die remains well behind TSMC or Intel in front-end density. This is how Huawei can claim to reach foundry 14A-equivalent density by 2031. This is not a like-for-like foundry comparison, with Huawei using stacked logic and measuring density per package footprint. On a normalized Bohr-density basis, SMIC N+3 is ~114 MTr/mm², 38% less than Intel 18A’s HD library. Huawei’s 3D roadmap closes the gap by stacking active logic, reaching 215 MTr/mm² by 2030. In 2031, the roadmap density jumps to 295 MTr/mm², implying either a third active layer, partial EUV insertion or aggressive planar DUV scaling. Huawei’s methodology makes other foundries look much denser as well. Applying it to AMD’s MI450X with an N2 top die on an N3P base die yields a theoretical density of 460.2 MTr/mm² in 2026, compared with Huawei’s 295 MTr/mm² in 2031. This Kirin 9030 does not use LogicFolding, remaining in a conventional mobile SoC package. Instead, it forms the baseline for how far Huawei and SMIC can push planar scaling. Future teardowns of Kirin and Ascend chips will show both planar logic density and Huawei’s hybrid bonding solutions. Export controls changed China’s optimization problem rather than ending it. EUV restrictions raised the cost and complexity of leading-edge manufacturing without freezing it. SMIC reaches N6-class logic density through DUV immersion, SAQP and DTCO, while Huawei shifts more of the burden onto architecture, packaging and system-level integration. Future nodes will be tougher. N+3 still had room to tighten local metals and reduce cell height and CGP. Further scaling without EUV leaves fewer levers. More aggressive multi-patterning adds masks and overlay error. SMIC can keep pushing DUV, but each step will get more expensive and less forgiving. The design side is just as critical. Huawei had domestic EDA tools and flows before the Kirin 9030, with the Kirin 9000s, 9010 and 9020 making that clear. Huawei was able to ship multiple consumer SoCs on SMIC N+2 and N+3 while cut off from the Western EDA stack. US export controls restricted EDA tools for advanced chips in 2022 but did not target tools for more mature chips. In 2025, the US government briefly placed much broader restrictions on EDA software from Synopsys, Cadence, and others, before lifting them less than two months later as part of a trade deal tied to rare earths. Huawei has been unable to access those tools because it remains on a US trade blacklist. That forced Huawei, SMIC and Chinese academic institutions to build their own tools and flows. Researchers at Peking University recently announced a prototype EDA tool for Huawei’s LogicFolding architecture, which requires a new flow to handle the multilayer layout and floorplan. This is not the same as replacing the full Synopsys or Cadence stack, but it shows where domestic EDA is headed: toward tighter co-optimization between architecture, process and packaging. These advances are also diffusing into the Chinese ecosystem. SMIC is licensing its N+2 and N+3 processes to HLMC/Hua Hong at the government’s direction rather than by choice. If the same process learning feeds into Ascend accelerators for AI training and inference, the choke point shifts from one named fab to an ecosystem. Alibaba’s T-Head silicon arm and Cambricon, a Chinese AI chip designer that is expected to supply ByteDance, could also be major beneficiaries. Sanctions aimed at SMIC alone become less effective once the manufacturing knowledge has spread to other fabs and design houses. China is not closing the gap with Intel, Samsung and TSMC. The teardown shows the opposite in several places: no EUV, no backside power, higher process complexity, and visible trade-offs. But China is still advancing. If domestic chips become good enough for phones, inference, networking and security-sensitive workloads, they can matter strategically without matching TSMC at the leading edge. Behind the paywall, we show what else STEEL can do, with material and process flow analysis of SMIC N+3, and analysis of the Kirin 9030 package. We’re diving deep into the most advanced datacenter and AI hardware hitting the market. To learn more about what’s in the pipeline, access the full Kirin 9030 and SMIC N+3 analysis or to commission a custom teardown, contact sales@semianalysis.com.
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Social Security is Facing a Political Crisis
On Tuesday the Social Security Trustees released their latest report on the system’s finances. The numbers didn’t change much: Unless something is done, the Old Age Survivors and Disability Insurance (OASDI) program, Social Security’s official name, will be unable to pay full benefits starting in either 2032 or 2034, depending on some technical issues. That’s not far away: If the Trustees are right, the prospect of a Social Security crisis will loom over the next presidential administration. It’s important to understand, however, the nature of the looming crisis. It won’t be an economic crisis. It won’t even be a serious fiscal crisis. Whatever you may have heard, Social Security isn’t in danger of going bankrupt. What we’re facing, instead, is potential political crisis. Congress and the White House could easily take action to sustain America’s retirement system. But given the current state of our politics, there’s no guarantee that they will. There is a widespread misunderstanding of how Social Security works. While Social Security was designed to look like a pension fund, it isn’t. A pension fund pays benefits out of a stock of assets it has accumulated over time. In contrast, Social Security operates as a government transfer program, like food stamps or Medicaid. Now, unlike food stamps — but like the highway trust fund — Social Security is on paper supported by a dedicated tax, the payroll tax, that is assigned to that program. But I say “on paper” because from an economic point of view assigning the payroll tax to Social Security is just an accounting convention. What matters for the U.S. economy is the overall balance between government spending and government revenue, not the difference between one type of spending and one source of revenue. So there’s no inherent economic significance to the fact that by 2034 payroll tax receipts will be insufficient to cover promised benefits. There is, however, a legislative issue. As long as the Social Security Administration can pay benefits out of payroll taxes and its cash reserve, there’s no need for Congress to vote each year to authorize benefits — they just keep going out until further notice. However, once those resources become insufficient, benefits will fall —by 17 percent according to the Trustees — unless Congress passes new legislation that “tops up” Social Security’s finances. Yet the current administration and Republican party are such extremists that there is a real risk that Social Security will be held hostage on behalf of their goals. If this should come to pass, the hostage-takers will claim that shoring up Social Security is unaffordable. Right on cue, Mike Johnson, the Trump-sycophant Speaker of the House, declared on Monday that “entitlement programs” like Social Security “have to be adjusted and fixed,” and that Republicans will introduce a plan to that effect next year. But this is a ploy, because while the cost of maintaining Social Security benefits at their promised level isn’t trivial, it is in fact affordable. According to the Trustees’ report, the actuarial balance of OASDI up through 2050 — the amount of additional funds it would need to keep paying full benefits for the next 25 years — is 1.06 percent of GDP. To put that number in perspective, the Trump administration proposes increasing military spending next year by $420 billion, equivalent to about 1.4 percent of GDP – without any discussion of whether that’s affordable Yet how did we get to the point where Social Security will need to be topped up? The main answer is that we have an aging population, with a growing ratio of retirees collecting benefits to workers paying into the system: Trump’s anti-immigration policies are making this problem worse. According to the Trustees’ report, lower immigration will deepen Social Security’s financial hole because many immigrants are working-age adults who will pay into the system for decades before they collect benefits. In fact, this problem may be much bigger than the report acknowledges: The report’s baseline assumption is that we’ll have net immigration of almost 1.2 million people a year, and even the pessimistic case assumes 750,000 a year. Meanwhile actual net immigration has already been cut far below that — and may now be negative. Moreover, Social Security is being financially damaged by growing income inequality in America. Payroll taxes are levied only on wages up to $184,500, and they don’t touch capital income. With the distribution of income increasingly shifting from labor to capital, as well as becoming more unequal among wage-earners, revenue from the Social Security payroll tax has been falling as a share of national income. From 1990 to 2024, it fell from 5.02 percent of gross domestic income to 4.46 percent. Which brings me to the question that, these days, we ask about everything: How might Social Security be affected by the advent of AI? A short answer: If, as many of us fear, AI accelerates rising income inequality, it will further reduce the payroll tax receipts that currently pay for Social Security and further endanger its finances. On the other hand, if AI, as its advocates promise, leads to faster economic growth, it will increase the potential tax base that could and should be used to support Social Security and other social insurance programs. But to take advantage of that larger base, we’ll have to get serious about taxing wealth and capital income. Is Social Security in trouble? Yes, but only because of the way its financing is currently structured — a structure that no longer works well because our society and economy have become so unequal. Moreover, Trump’s immigration policies are further endangering its already deteriorating financial condition. So don’t believe Republicans’ gaslighting that it will be necessary to cut Social Security benefits. All that is necessary to preserve Social Security is political will to raise taxes on the wealthy and a sensible immigration policy. MUSICAL CODA Actually 67 under current law.
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‘The reality, for better or worse’: Columbia comp sci students and faculty grapple with AI’s disruption of the field
‘The reality, for better or worse’: Columbia comp sci students and faculty grapple with AI’s disruption of the field ‘The reality, for better or worse’: Columbia comp sci students and faculty grapple with AI’s disruption of the field A field that once seemed like a direct path to stable, lucrative work is becoming less certain under AI, students and faculty told Spectator. By Ria Vasishtha and Arjun Menon May 3, 2026 Shanying Liu / Deputy Illustrations Editor Asia Genawi, SEAS ’29, first encountered artificial intelligence during her sophomore year at her high school in Indiana. Back in 2023, policies on AI varied widely—even within the same district—and some schools had no guidance at all. As Genawi began to see the effects of AI trickle into her classroom, she turned to guidance from her home state’s Department of Education, which she said she found “outdated and inaccessible.” Genawi spent the rest of her high school career dedicated to the issue, including writing a 15-page memo exploring varying AI policies across Indiana schools, which she sent to every Indiana state senator and representative whose contact information she was able to find. She later helped draft a bill that would have required public high schools to establish and share their own AI policies with students in an accessible format. But with so many other bills already awaiting referral, hers never made it to committee. When Genawi arrived at Columbia to study computer science, she found that the gaps she had spent years trying to address in Indiana had followed her there. Many students and professors were also grappling with what AI meant for the field. Across Columbia’s undergraduate schools, computer science has become the most popular major—accounting for around 11 percent of degrees awarded in Columbia College, 32 percent in the School of Engineering and Applied Science, and 12 percent in the School of General Studies in 2024. While the number of computer science majors in SEAS grew from 166 to 173 during the 2024-25 academic year, the total number across the three schools fell around 4.5 percent from 393 to 375, driven by declines at Columbia College and General Studies. At Barnard, it has grown to become the second most popular major as of 2025, up from third the year prior. The number of degrees awarded have grown fivefold since 2016. Faculty members and students in the department told Spectator that the surge in the major’s popularity has been driven in large part by its apparent promise of a secure, well-paid career path. However, they noted that the recent rise of generative AI has compromised the sense of stability that once defined the field, even as interest in technical skills among students persists. According to data from the Federal Reserve Bank of New York in 2024, out of 74 majors tracked, computer science had the fifth highest unemployment rate among majors at 7 percent, while computer engineering had the second highest at 7.8 percent. “Anecdotally, people are moving away from CS as a major,” Daniel Bauer, a senior lecturer in the computer science department, said. “They’re still taking some of our classes, right, because they think they need that, but they’re instead majoring in other things.” Bauer described a field that had shifted from what he called a “nerdy outlier discipline” to one that “everyone needs,” a sign that technical skills have become a baseline expectation across industries with the emergence of AI. “A lot of people thought, ‘Oh, it’s a guaranteed path to a stable income. You get a six-figure job right out of your undergrad,’” Bauer said. Now, companies may see AI as a way to reduce demand for entry-level programmers, especially in what he calls “code monkey jobs,” roles where a large number of employees are “just writing out code nine-to-five.” Chris Murphy, a senior lecturer in the computer science department, described the current moment as the convergence of two forces: the downturn of the job market and generative AI coming onto the scene. “Things kind of started to really pick up in 2014, 16,” he said, recalling the years after the weaker 2010 market. Murphy added that this was also a period where “students were getting more experience outside of class than they were inside of class” through internships, jobs, and side projects. Murphy suggested that the earlier momentum helped make computer science feel like both an academic program and a reliable pathway into work. That feeling is harder to sustain now as the industry reconfigures, which is a shift that students are seeing firsthand. Rebecca Yu, SEAS ’27, said that during a recent internship in Big Tech, she saw that “every single tech company was racing to integrate” large language models. She added that her manager said her intern class was the first to complete their assigned projects, which she attributed to the increased efficiency that comes with AI. Frank Liu, SEAS ’29, said that with AI lowering the barrier to coding, companies now expect everyone to write code. “A lot of companies outright say if you’re not using coding in your job, you might get fired for not being productive enough,” Liu said. Yu similarly expressed that students increasingly have to accept AI being a part of industry workflow, adding that many also “make use of it to maximize their productivity.” Richard Li, CC ’28, described a “franticness” among his peers as the pace of change accelerates. He explained how “some new tool” is released regularly, noting that tools rise and fall in prominence within weeks. He has come to believe that he doesn’t need to “match that speed all the time” and keep up with every development. Li has learned that AI tools allow him to “take a breath” and “get back into the loop much easier than before” when he needs to. While some companies specifically target Columbia when hiring, sending representatives to campus career fairs and recruiting large numbers from Columbia, a computer science degree cannot be treated as a static credential, Yu described. “You can’t just get your degree and stop learning after that. You have to always be learning,” Yu said. “That is something you basically have to expect for your job.” AI has not only affected students’ decisions to major in computer science, but also reshaped how the subject is taught. Across departments, faculty members no longer treat work done outside the classroom as a reliable measure of understanding, shifting instead toward in-person exams, quizzes, and attendance checks. While homework once made up as much as 60 to 70 percent of a student’s grade in computer science classes, Murphy said that breakdown has since flipped, with exams and quizzes now accounting for the majority. “The assumption—especially among pessimists—is that they’re using it to do their homework,” Murphy said. “They take the homework assignment. They put it into generative AI. Out comes the solution. Submit solution. The end.” Murphy said that faculty members ranged in their responses from fully prohibiting AI use to actively teaching students how to effectively work with AI. He said he shifted his approach this year after his teaching assistants called his belief that students weren’t using the technology “naïve,” and now permits students to use AI on assignments. His surveys of students in his introductory classes have told a more complicated story than the one so-called pessimists offer: Around 60 to 70 percent of students who reported using AI said they used it to have concepts explained to them, to clarify assignment instructions, to generate test cases, or to create practice questions. “Those are all ways that you might have had a tutor in the past to do that, and now you have this AI essentially as your tutor,” he said. Bauer has taken a different approach, teaching students how to use AI productively without sacrificing the core principles of the discipline. “People who are trained to actually use AI tools productively, while being in charge of designing the overall project, will be very much in demand in the next couple of years,” he said. Over the past year, a working group of computer science faculty has been redesigning the introductory and intermediate programming sequence to integrate generative AI as both a subject and a tool, representatives from SEAS wrote in a statement to Spectator. The effort is “coordinated” across the department, “not course-by-course,” with a systematic assessment of how AI integration is affecting student outcomes underway to shape the next round of changes. The goal, the department explained, is for students to be able to “read, verify, and reason about code, whether they or a model wrote it.” Tony Dear, senior lecturer in the computer science department, is piloting individualized AI feedback in a discrete mathematics course, while a machine learning course is also testing a Socratic AI dialogue system designed to “guide inquiry rather than supply answers,” the statement reads. Beyond individual courses, SEAS funded seven cross-departmental faculty projects in generative AI this past academic year, spanning biomedical engineering, chemical engineering, industrial engineering, and computer science, according to the statement. This phenomenon extends beyond the computer science department. SEAS’ new AI minor, which it announced in November 2025, reflects the University’s attempt to adapt. The minor is specifically designed for noncomputer science majors and aims to provide “essential AI knowledge” while emphasizing practical and responsible use across disciplines, according to the SEAS website. At the center of the minor is AI in Context, a course taught by a team of faculty from the departments of computer science, applied mathematics, philosophy, music, literature, and the Writing Center, the representatives told Spectator. Bauer described it as targeted at students who want to bring AI into fields like economics or biology, rather than as a path into software engineering itself. At the graduate level, SEAS announced a new Master of Science in artificial intelligence in February, with the inaugural cohort starting in the fall. While recognizing how AI has helped them navigate coursework, students also described its rise as isolating, even among members of the Application Development Initiative, one of Columbia’s largest computer science clubs. “As people start to ask AI for questions that they would normally ask students and members, it starts to isolate people” Li said. Alexa Kafka, BC ’27, echoed Li’s sentiment, pointing out that computer science has always been a collaborative discipline with code reviews and pull requests, even as AI makes independent work easier. Despite this, Kafka noted that she hasn’t been to office hours “in at least a year.” Bauer added that faculty are exploring long-term solutions to the assessment problem. “One of the things that we’re trying to do at the department or school level is to maybe move towards computerized testing facilities,” Bauer said, referring to ideas in the department to revitalize computer labs as an alternative to pen-and-paper exams. “We have to accept that this is the reality, for better or worse.” But more exams, students say, does not mean better learning, nor does it reflect how computer science is actually done. “Code is so variable and can be approached in so many directions, there’s never just going to be one correct answer. There can be multiple optimal solutions,” Kafka said. Students also expressed concern that the shift toward exam-heavy grading pulls focus away from the applied, project-based work that better reflects both discipline and industry expectations. ADI has tried to respond more quickly than the curriculum can. Through a vibe coding workshop this past semester, club members said they wanted to help students understand not just that AI exists, but how to use it deliberately. “Vibe coding” refers to the practice of prompting AI to write code for a task or project, and has become widespread enough that ADI felt the gap in formal instruction was worth addressing, according to Sophia Huang, BC ’29. The workshop introduced students to the concept of context engineering, which Shaina Sahu, SEAS ’27, described as not just writing a prompt, but optimizing “the rest of the relevant information that you would feed into the model.” Without that, students said that AI-generated code can fail at scale or introduce difficult-to-detect bugs. Genawi said the shift toward AI has changed what it means to be good at computer science. “I think the shift has kind of gone towards what can you create and what can you do, instead of, what do you know,” she said. Indeed, during ADI DevFest, its annual hackathon, Li said more teams are trying to complete their projects than in years past. While sign-ups have historically outpaced submissions, Li said this is beginning to change because teams “have a tool that completes the vision for them.” While many students see AI as an equalizer that lowers the barrier to entry for coding and technical work, Murphy said it also creates new equity concerns inside the classroom around who can afford stronger tools and who already knows how to use them. “The equity issues I worry about are students who have access to paid versions of things versus free versions of things,” he said. Although popular AI models like ChatGPT and Claude have free versions available, both have paid models that can reach over $100 per month, which output different qualities of code. Murphy also pointed to differences in prior exposure to AI literacy itself. “Students who go to high schools or K-12 education, where they’re taught AI literacy, prompt engineering, context engineering, they understand how to do this, as opposed to students who go to schools who don’t teach that,” he said. “Then they come in, and then they’re somehow expected to know how to use these tools.” For Genawi, those disparities begin long before students arrive on campus. “It’s very interesting to consider how lucky you were geographically,” she said. “To be born where you were is influencing your ability to get access to these spaces.” Students like Yu, though broadly apprehensive about the future of computer science, are not without hope. “I’m optimistic, because I think if you’re truly passionate about CS, there will definitely be a place in the field to do something you want to do,” she said. Senior Staff Writer Ria Vasishtha can be contacted at ria.vasishtha@columbiaspectator.com. Follow Spectator on X @ColumbiaSpec. Staff Writer Arjun Menon can be contacted at arjun.menon@columbiaspectator.com. Follow Spectator on X @ColumbiaSpec. Want to keep up with breaking news? Subscribe to our email newsletter and like Spectator on Facebook. Produced with Spectate by Emily Ta
Bradley Staats Appointed Dean of McCombs School of Business
He will begin his appointment on July 1, succeeding Lillian Mills, who has served as dean since 2020 and will return to the Department of Accounting as a distinguished faculty member.
Two CSUF Students Compete in Business Ethics Competition
Two Cal State Fullerton students were quarter finalists at the 9th Annual Lockheed Martin Ethics in Engineering Case Competition held on Feb. 23-25, a record for Titan achievement in this annual event that features teams of undergraduate students presenting on ethics in the workplace. The CSUF team, which included accounting junior Clint Cox and computer science […]
April 2026 Tournament Rules Update & Changelog
Updates to Riftbound’s tournament rules explained.
Unleashed Rules FAQ and Clarifications
Sharing clarifications and answering some frequent questions regarding Unleashed’s core rules updates.
Springfield awards accounting firm small business improvement grant
413 Multi Service has been operating in Indian Orchard for 13 years.
Teamfight Tactics patch 17.2
Opening Encounters & new God Blessings make 17.2 a celestial encounter you won’t want to miss.
San Francisco State University Partners with UC Law San Francisco to Expand Downtown Presence - UC Law San Francisco (Formerly UC Hastings)
SFSU’s Lam Family College of Business will use classroom and office space at 198 McAllister Street to establish a new downtown campus. San Francisco State University (SFSU) and UC Law San Francisco have reached an agreement that establishes a new downtown home for SFSU’s Lam Family College of Business at UC Law SF’s Academic Village. The agreement places SFSU business students in close proximity to leading employers, industry partners and transit hubs, enhancing opportunities for internships, networking and career advancement. The UC Law SF Academic Village is a shared-campus model designed to foster collaboration among higher education institutions and contribute to San Francisco’s ongoing revitalization. San Francisco State University (SFSU) and UC Law San Francisco have reached an agreement that establishes a new downtown home for graduate business programs from SFSU’s Lam Family College of Business at UC Law SF’s Academic Village. The agreement creates a new downtown campus location for SFSU, giving students direct access to San Francisco’s thriving business environment. Beginning in Fall 2026, graduate business students will take classes at the UC Law SF building at 198 McAllister Street, at the nexus of the Civic Center, Mid-Market and Tenderloin communities. Under the agreement, SFSU will occupy 3,200 square feet of exclusive teaching and office space and will share additional classrooms with UC Law. The move positions students in close proximity to leading employers, industry partners and transit hubs, enhancing opportunities for internships, networking and career advancement. “This partnership is an example of the growing strategic collaborations that expand opportunities for our students,” said SFSU President Lynn Mahoney. “By situating graduate business programs in the city’s urban core, we will help students build connections, gain experience and achieve their goals for meaningful careers and upward mobility.” Students enrolled in select Lam Family College of Business graduate programs will have access to the Academic Village’s modern classrooms, conference facilities, library, study spaces and resident and event support services. The site also includes lounges, on-site dining and newly built, fully furnished, apartment-style housing for students and professionals. As institutional partners, SFSU College of Business students and alumni are eligible for tuition discounts if they enroll in the UC Law SF Master of Legal Studies program, designed for professionals whose work intersects with the law. “San Francisco State University is an excellent addition to our Academic Village, and we are excited to have the Lam Family College of Business join us in the fall,” said UC Law SF Chancellor & Dean David Faigman. “The partnership advances UC Law SF’s commitment to collaborate with California’s other great public schools and adds vibrancy and energy to the heart of the city. Our students and programs will benefit from the interdisciplinary opportunities that will arise.” The UC Law SF Academic Village is a shared-campus model designed to foster collaboration among higher education institutions and contribute to San Francisco’s ongoing revitalization. The Lam Family College of Business will begin occupying its new space there in July 2026, with classes beginning in August. The move continues SFSU’s longstanding presence in downtown San Francisco and reflects a broader effort to align academic programs with the needs of both career-minded students and the region’s expanding and evolving workforce. For more than 60 years, the Lam Family College of Business has delivered high-quality, AACSB-accredited business education across the San Francisco–Silicon Valley region. Its graduate programs — including the MBAand the STEM-designated Master of Science in Business Analytics and Master of Science in Accounting and Analytics — are designed to help students develop the skills they need to navigate the complex challenges of a global, data-driven economy. About San Francisco State University San Francisco State University is a public university serving students from the San Francisco Bay Area, across California and around the world, with nationally acclaimed programs that span a broad range of disciplines. More than 20,000 students enroll at the University each year, and its more than 304,000 graduates have contributed to the economic, cultural and civic fabric of San Francisco and beyond. Through them — and more than 1,300 world-class faculty members — SFSU proudly embraces its legacy of academic excellence, community engagement and commitment to social justice. For more information, visit sfsu.edu. About UC Law SF UC Law San Francisco is a public law school of the University of California, founded in 1878 as the first law school in the UC system. Located in San Francisco’s Civic Center, it offers a comprehensive legal education with a strong emphasis on experiential learning, public service and professional preparation. Through its Academic Village, UC Law SF brings together students, faculty and partner institutions in a collaborative campus environment in the heart of the city. Other Academic Village partners include UC San Francisco, UC Davis, the University of San Francisco and the University of the Pacific Dugoni School of Dentistry. For more information, visit www.uclawsf.edu.
Preparing for the Unleashed Pre-Rift
Get ready to play Riftbound’s newest set at your local Pre-Rift.
Connections: Tyson Foods appoints chief accounting officer - Talk Business & Politics
Springdale-based meat producer Tyson Foods Inc. has named Phillip Thomas as its new chief accounting officer and controller effective April 6. He replaces Lori Bondar, who is stepping down and...
UF expands certificates in business and education
By: Erin Moran Morane@findlay.edu The University of Findlay has announced a graduate certificate expansion, adding new opportunities in accounting, business fundamentals, finance, human resources, operations management, and trauma-informed education. The additions are part of the university’s effort to meet the evolving needs of the workforce and prepare their students post graduation. Kirby Overton, dean of […]
Lille’s Top Decks
RQ Lille’s 1800 players display the latest and greatest decks in Riftbound.
/dev: Apex Tier Ranked Reset
Why we’re doing a Ranked reset for Master+ in NA, EUW, EUNE, BR, LAN, and TR in 26.9.
Quarter of a million people could lose job by middle of 2027 as UK ‘flirts with recession’, analysis says
Twin reports from top accounting firms underline scale of economic threat as Iran war shatters business confidence
Exclusive | Ilhan Omar Says She Isn’t a Multimillionaire, Blames Accounting Error
The Minnesota Democratic congresswoman, facing potential investigations pushed by President Trump and House Republicans, said she isn’t as wealthy as documents she previously submitted to Congress suggest.
UW College of Business Selects Reimann as 2026 Distinguished Alumnus
The University of Wyoming College of Business has selected Richard “Rick” Reimann as its 2026 Distinguished Alumnus, recognizing his leadership in accounting, business and community service across Wyo
TFT patch 17.1
Choose your Space God, earn their powerful boon, and assemble your galactic roster!
Why Warren Buffett Believes Book Value Cannot Capture a Business's Real Worth
With Berkshire Hathaway's book value per share over- or under-estimating the true value of its businesses, Warren Buffett prefers alternatives to this accounting metric.
First-Generation Accounting and Finance Double Major Sets Sights on Future as Business Leader
Joana Camarena arrived with a plan to pursue accounting and financial literacy skills. On the cusp of graduating, she is completing her degree with a job offer and more.
Club Corner: Business Professionals of America
The Business Professionals of America on NW Campus is more than just a club. Students also have the opportunity to explore possible future careers through competitive events. The BPA doesn’t hold regular weekly meetings. Instead, students typically meet individually with their faculty mentors as they prepare for regional, state and national competitions. “It is a lot of work,” said BPA adviser Jaye Simpson, an associate professor of accounting and department chair. “They’re working a couple hours every week, usually meeting with their mentor....
WHO calls for science-led action and stronger One Health approach to address evolving health risks
The World Health Organization today called for urgent scale-up of research, innovation, and collaboration to accelerate momentum towards ending tuberculosis in the WHO South-East Asia Region, which continues to bear nearly half of the global TB burden, accounting for the highest share of cases and deaths worldwide. To build momentum, experts, national TB programme managers, researchers, along with partners and members of civil society, began a three-day virtual workshop organized by WHO for ‘Advancing research and Innovation to accelerate momentum towards ending TB in the WHO South-East Asia Region.’
FTI Consulting Adds Three Leading Mining and Resources Business Improvement Experts
SYDNEY, April 06, 2026 (GLOBE NEWSWIRE) -- FTI Consulting, Inc. (NYSE: FCN) today announced the appointments of James Chapman, Steve Dyson and Franz Wentzel as Senior Managing Directors in its Australian Transformation practice, bringing their experience as former global heads of Big Four accounting firm mining practices to help clients realise their full value potential. The appointments of Mr. Chapman, Mr. Dyson and Mr. Wentzel continue the firm’s growth of its Transformation – Mining team, fo
TFT patch 16.8
It’s our final patch before this set becomes the stuff of legend and lore.
Flash Promos & Origins Reprint Updates
Learn about Flash Promos for stores, and updates on Origins and Proving Grounds reprints.
Pinched from all sides, Marylanders focus on the costs of everything
Marylanders continue to feel pinched on all sides by rising costs, with pocketbook issues accounting for four of the top six concerns in a new poll from UMBC. It found that crime was last on the list and "politicians, Trump, federal ... or state government" was fourth.
Riftbound Core Rules: Unleashed Patch Notes
Learn all about the updates to Riftbound’s rules which arrive with Unleashed.
Announcing Riftbound's First Bans
Effective March 31, 2026, four cards and three battlefields will be banned in constructed.
Marathon has sold 1.2M copies across Steam, PS5, and Xbox
Alinea Analytics estimates show that Marathon has generated gross revenues of $55M via 1.2M copies sold on Steam, PS5, and Xbox: Looking at the split between Steam, PS5, and Xbox, Steam is clearly the main platform for Marathon, accounting for a little under 70% of the audience (800K copies sold). Meanwhile, PS5 takes about 19% (217K) and Xbox (including console, PC, and cloud) accounts for a bit over 11% or 133K. Marathon is technically a first-party Sony title, so seeing the home console struggle to break 20% of the volume is a notable data point for the ongoing platform-agnostic debate. PlayStation Studios online games will almost certainly continue being multiplatform (despite Sony reportedly pulling back on PC releases). Subscribe for free to get the most accurate games estimates in your inbox twice a week 🫶 Subscribe As for Marathon, the consensus among hardcore players who pushed through the awkward onboarding phase – myself included – is that it’s fantastic. The gunplay, aesthetic, and presentation are among the best in the shooter genre. A great game doesn’t always equal an immediate hit, though, as shown by our estimates. Things are looking lukewarm right now. But this might be one of those marathon-not-a-sprint situations. Had to, didn’t I? Why wasn’t Marathon a hit on the same level as Arc Raiders? One topic that came up in a lot of conversations at GDC this year was why Marathon hasn’t hit the same stratosphere as Arc Raiders. On paper, they’re both extraction shooters, and Marathon has the Bungie pedigree – the house that built the gold standard for gunplay in Halo and Destiny. Marathon’s neon-futuristic aesthetic also distinguishes itself from the gritty realism of Tarkov or the post-apocalyptic hope of ARC Raiders. But vibes can only get you so far for first impressions if the onboarding feels like a brick wall. Marathon is a sweaty PvP-focused experience with a first-time user experience and UI that I can only describe as dreadful. Players are dropped into a complex ecosystem where the UI, though visually striking, is functionally uninformative, forcing users to manually hover over nondescript, identical icons just to identify basic gear or weapon mods. This lack of clarity is compounded by punishing mechanics like a severe heat gauge for movement and a scarcity of vital resources, all without a clear tutorial or a low-stakes mode to learn the ropes. Most people – even top streamers and veteran shooter players – have no idea what’s going on in Marathon at first. Arc is on the complete other end of the spectrum. As we covered here and here, Arc Raiders offers a more collaborative, approachable loop where players often work together toward shared goals. And the objectives are instantly clear. To many players, this contrast only emphasised Marathon’s issues, especially during the testing period. Players understand the Arc Raiders loop within 30 minutes, while Marathon acts as a massive filter, chewing up newcomers and spitting them out before they can experience the depth of Bungie’s signature gunplay. What I’m getting at here is that the poor first-time user experience of Marathon’s Server Slam likely stifled launch sales, while the opposite was true for Arc. Let’s look at the pre-launch copies sold for each game during their respective Server Slams (launch-aligned) : Looking at the trajectory: Arc Raiders saw a massive 80% jump in copies sold during its three-day Server Slam (day -13 to -11). Players jumped in, realised the water was fine, and immediately opened their wallets. Marathon, meanwhile, saw a 49% increase in the four days following its Slam (Day -7 to -3). At the time of each game’s respective launch, Arc Raiders had nearly double the Steam footprint of Marathon – and word of mouth only continued to grow. Bungie could have had more time to fix the onboarding process had the beta happened earlier. But Marathon launched three days after the beta finished. These factors limited the launch sales quite a bit, I reckon. Marathon has found a niche audience, though Despite the friction-heavy start, the data suggests that those who survived Marathon’s onboarding are loving life. We’ve been tracking cross-platform DAUs, and while there’s the expected post-launch leakage, many players are sticking with it. After peaking at 478K total DAUs on its first Saturday, Marathon has settled into a respectable rhythm, holding 345K DAUs as of yesterday and averaging 380K DAUs across the weekend. Steam continues to do the heavy lifting here, consistently accounting for the lion’s share of the daily players. Players have been putting in the hours, too: On Steam, Marathon’s average playtime has climbed to 27.8 hours, significantly outpacing the console averages on PS5 (16.5h) and Xbox (17.3h). Even more telling than the averages: 22% of the Steam audience has surged past the 50-hour mark, and nearly 7% have already logged over 100 hours. Subscribe for free to get the most accurate games estimates in your inbox twice a week 🫶 Subscribe This data suggests that once the Bungie magic clicks, it hooks players deeper than the average extraction shooter. There’s also started to be a shift in the game’s discourse. Marathon launched as one of those games that’s cool to hate. But as Marathon’s 100-hour club grows, we’re seeing conversations around its mechanical merit outweigh the negativity. Several high-profile creators, who were initially vocal critics, have spent the last week coming around on the mechanical depth of the endgame. It’s a subtle but positive signal; the hate train is losing steam, and a new narrative about the game is emerging. Bungie faithfuls unite Another interesting metric in Marathon’s first few weeks is who, exactly, is playing. Bungie leans heavily on its prestige as the “makers of Halo and Destiny,” in its marketing, and that message has clearly hit the mark. On Steam, the gravity (hammer) of Bungie’s previous work is unavoidable. A staggering 78.2% of Marathon players also played Destiny 2. The trend carries across other platforms, with 74.2% of PS5 players and 82.7% of Xbox players also having played Destiny 2. The Halo legacy lives on, it seems. More on that in a bit. While Destiny 2 went free to play, these numbers still represent a high-intent migration of a fanbase that trusts Bungie’s specific brand of kinetic gunplay and cryptic world-building. The Xbox data adds another layer of legacy. About 85.7% of Marathon players on Xbox have played Halo Infinite, while over half of the Steam audience has spent time in Halo Infinite and 36.1% in the Master Chief Collection (a paid collection of the old Bungie-made legacy games). Interestingly, we see a 55.9% overlap with ARC Raiders on Steam. Overlap is even higher there on PlayStation (60.5%) and Xbox (66.5%). And there’s also significant crossover with Helldivers 2 on all platforms, too. Subscribe for free to get the most accurate games estimates in your inbox twice a week 🫶 Subscribe Bungie has found some of its fans with Marathon, and the challenge now is keeping this engaged in a high-stakes PvP environment when they’ve spent the last decade primarily enjoying the power fantasies of PvE. On that note… Go the full 26 miles? Or cut and run? Time for some could’ve, should’ve, would’ve. These things would have improved Marathon’s performance at launch: A more robust onboarding process, perhaps in the form of a short single-player/PvE campaign. We know Bungie fans love this stuff. A traditional arena-based mode akin to Destiny’s Crucible could have been a bridge for the cautious players who’d have been otherwise deterred by the Server Slam. It’s also a great palate cleanser after getting merked. Introducing a dedicated PvE environment would have similarly diversified the conversation and lowered the barrier for the Bungie faithful who found the pure PvP extraction loop too abrasive. PvE is safer than PvP these days. There’s an argument that a thin PvE mode would have just felt like a budget Destiny, potentially hurting the brand more. But given how dire the FTUE is, I think it would have been a net positive. Any kind of tutorialised loop that demystifies the stakes, really. While there is merit in a studio sticking firmly to a singular creative vision, and going all in on the hardcore extraction loop. Less forgiving is the technical reality is that the user interface and first-time user experience (FTUE) were not at a commercial standard for launch. Subscribe for free to get the most accurate games estimates in your inbox twice a week 🫶 Subscribe In a landscape where player time is oversaturated and the most contested currency, a flawed FTUE is a critical failure point. But it’s not all doom and gloom, as Marathon has an incredible, unique gameplay loop, suggesting that financial success is still attainable if Bungie can pivot effectively. Bungie and PlayStation now face a difficult strategic crossroads, though – one within a challenging games market. They could: Double down on Marathon with a long-term Rainbow Six Siege- or No Man’s Sky-style recovery plan, which is something I heard Last Stand Media’s Chris Maldonado mention last week. While this could be a sunk-cost fallacy in action, it could eventually yield the audience the game’s mechanical depth deserves. Shift focus toward the inevitable Destiny 3 or another project, mitigating the escalating opportunity cost and cutting their losses, so to speak. Doing both is an expensive proposition, given the high overhead and burn rate of operating out of Bellevue, Washington. With Sony recently demonstrating a lower threshold for underperforming studios and projects, the margin for error has vanished. Whatever happens, the next six months will determine whether Marathon becomes a cornerstone of Sony’s live-service portfolio or a cautionary tale of vision exceeding accessibility. I’m hoping it’s the former, because Marathon rocks. As always, hit subscribe to get updates on Marathon and other relevant games. Subscribe Want to get your hands on our data for yourself – for free? We’re offering a free trial of our platform for games companies. Send us a message here, or reply to this email, and we’ll set you up. The last word Reply to this email – or reach out here – if you have any feedback for the newsletter – or want to request a game for us to cover. [Alinea Analytics boasts the most accurate PC and console estimates in the business. Game makers use our platform to understand their audience, keep an eye on the competition, monitor sales trends, and spot new opportunities. We equip game studios and financial institutions with accurate data and the confidence to make smarter, data-driven decisions. Want to talk about all things games market data? We’d love to chat!]
Europe’s trade with Iran: Which countries do the most business with Tehran?
EU–Iran trade fell to its lowest level in two decades in 2025 due to sanctions. Trade continues on a limited scale, with Germany accounting for the largest share.View on euronews
Study finds ChatGPT gets science wrong more often than you think
A new study put ChatGPT to the test by asking it to judge whether hundreds of scientific hypotheses were true or false—and the results were far from reassuring. While the AI got it right about 80% of the time on the surface, its performance dropped significantly when accounting for random guessing, revealing only modest reasoning ability. Even more concerning, it frequently contradicted itself when asked the exact same question multiple times, sometimes flipping answers back and forth.
New Business Licenses: 3.13.26
Home care, restaurants, accounting services, magic tattoos and more. (BizSense Pro required)
S&W names James Wright as partner in Birmingham business tax team
UK-based accountancy and advisory firm S&W has appointed James Wright as a Partner within its business tax practice in Birmingham.
TL;DW: Ranked, Shyvana & More Dev Update
A short rundown of changes from today’s Dev Update.
Best Sole Trader Accounting Software (2026): Sage Awarded for Simplicity and Compliance in the UK by Better Business Advice
Sage has been recognised by Better Business Advice for its accounting software designed for UK sole traders, highlighting its role in helping individuals manage bookkeeping, meet HMRC requirements, and maintain accurate financial records in a changing regulatory environment.
McCord: Run Huntington Beach Like a Service Business
Run Huntington Beach like a service business—not a political stage. Demand accounting on the 25-year Pacific Airshow deal, stop “balanced” budgets that rely on reserve raids and one-time patches, and tackle deferred maintenance and real hazard risks. November 2026: vote for competence, not drama.
TFT patch 16.5
We’re past the halfway mark with Lore & Legends and we’re focusing on more specific balance changes.
iPhone 17 Pro Max Curiously Becomes Most Traded-In Smartphone
New trade-in data indicates that Apple's iPhone 17 Pro Max has rapidly become the single most traded-in smartphone. According to a new report from SellCell, Apple's latest flagship iPhone has quickly risen to the top of the independent trade-in market, accounting for 11.5% of all devices appearing in the top-20 trade-in rankings just months after release. The analysis is based on SellCell internal trade-in data and secondary market pricing trends gathered from 40 independent iPhone buyers.
Conflict and instability make pregnancy more dangerous
This brief aligns the latest maternal mortality estimates with whether a country is conflict-affected or considered institutionally fragile. Nearly two-thirds of all maternal deaths worldwide occur in countries marked by conflict or fragility. The risk of a woman who lives in a country affected by conflict dying due to maternal causes is around five times higher for each pregnancy she undergoes compared to her peers in stable countries. In 2023 alone, an estimated 160,000 women died from preventable maternal causes in fragile and conflict-affected settings, that is 6 in 10 maternal deaths worldwide, despite these countries accounting for only around one in ten of global live births.
UAMS offers quick, noninvasive heart screenings during American Heart Month
American Heart Month is putting a spotlight on cardiovascular health, as heart disease remains the leading cause of death in the United States, accounting for n
Can AI Build You A Gaming PC? Here's The Truth
AI can suggest parts to use in a gaming PC; however, it fails at accounting for size and models to use. Instead, go with real people for help when building.
I am a Black man diagnosed with prostate cancer. This is my story.
Prostate cancer is the most common cancer diagnosis in men, accounting for 30% of male cancers.
Why Berkshire Hathaway Is a Better Business Than You Might Think
Some fundamental misunderstandings about the way Warren Buffett's pride and joy reports its financial results can be misleading.
Teamfight Tactics patch 16.4
16.4 brings new Augments, leveling adjustments, and balance changes!
Rider’s 2025 business Hall of Fame inductees announced
Honorees’ expertise spans finance, accounting, entrepreneurship, operations
Patriots Defender Squashes ‘Crazy’ Drake Maye Playoff Narrative
Despite stringing together three dominant postseason outings, the New England Patriots defense doesn’t want to hear about carrying Drake Maye to Super Bowl LX. Maye led New England to a 14-3 season and AFC East championship by accounting for 35 touchdowns with a league-leading 72.0 completion percentage. The MVP finalist hasn’t lived up to those […]
Owner of Wichita accounting business charged with 50 counts in federal court
She is accused of using client money for personal expenses, including more than $11,000 to the Plastic Surgery Center, court documents say.
Local Small Business Owner Opens Pak Mail Inside of His Existing Accounting Business in Springville, Alabama--Offering Shipping and Office Services
Annex Brands, Inc., one of the leading franchisors in the packing, shipping and office services industries, is excited to announce the opening of its newest Pak Mail location inside of Chapman Accounting Solutions in Springville, AL to new owner, Edward Chapman. This new Pak Mail is set to offer a wide range of essential shipping and office services to the local community, making it easier to provide more service to more people in more places.
Investment and Statecraft: The International Politics of Sovereign Wealth Funds - Georgetown Journal of International Affairs
In 1953, Kuwait established the world’s first sovereign wealth fund to invest the country’s oil revenues and generate returns that would reduce its reliance on a single resource. Since then, over 100 separate funds have been created to preserve national wealth and ensure long-term fiscal sustainability. Today, they manage over $10 trillion in global assets. In this discussion with GJIA, political economist Kathryn Lavelle explains the increasingly novel dynamics that surround fund behavior and what the world can come to expect from their growing presence in international financial markets. GJIA: When it comes to the roles sovereign wealth funds (SWFs) play in global markets and politics, what would you say makes them unique? Kathryn Lavelle: Sovereign wealth funds (SWFs) operate on behalf of governments as investors. That in itself is a strange relationship. Within them, a core contest takes place between the state’s interests (or sovereign) part of the dynamic, and the money interests (or wealth) part of it, and these two aspects are frequently in contradiction, serving fundamentally different goals. SWFs are also quite fascinating because when you talk to the people who manage these funds, they have an interest in convincing you that the decisions are made almost exclusively on a financial basis—they really will go to great lengths to differentiate their government owners and those who make the management decisions. At the same time, these people ultimately answer to someone in power. Therefore, for most SWFs, it remains deeply unclear who is actually making the investment decisions and for what purposes. Of course, it is not always clear how other vehicles, such as hedge funds and private equity make the decisions they do, but I think what a lot of people find particularly disconcerting about SWFs is that they seem to act on behalf of people who have a different identity from their own. People who could be trying to manipulate politics and markets in a way that would have a long-term effect on their own populations. Regular investors come and go at will, and they only share an interest in profit as far as most of us understand. However, SWFs have that extra “sovereign” part right behind them that obscures their true interest. GJIA: These funds can be found in countries all across the globe, in both authoritarian states and democracies. Would you say SWFs differ in their goals and structures between regime-type? KL: It is not necessarily regime type that makes the goals and structures of SWFs different. It has to do with their economies. Let’s look at a country like China. There’s going to be a debate about exactly how to characterize the regime, but it is a country with many different kinds of sovereign wealth funds, and a particularly opaque state connection to each. At one time, some of the state-owned Chinese oil companies created specialized investment vehicles listed outside Chinese markets that excluded parts of the firms that were more associated with human rights violations. At the same time, the China Investment Corporation (CIC)—China’s largest SWF—draws a lot of concern, not necessarily because of its investment activities, but because of the dynamics of global politics. So, I wouldn’t really tie differences to regime types themselves in a wholesale way, but rather to how such funds are perceived and how they are structured. Saudi Arabia’s SWF is getting all kinds of attention for its involvement in Hollywood, and this takes me right back to when I was a student in the 1980s, when people were concerned about Japanese investment entities buying assets in Hollywood. They aren’t quite the same in financial terms, but it’s the same kind of concern about foreign investment that drives people to be suspicious, and the whole idea that “foreigners are influencing Hollywood.” This holds true across industries, and it reflects where politics are in places like the United States right now. One metric we can try to look at is transparency, where all the funds will tell you, “we are transparent.” The problem you’ll keep running into with this approach is how you value things. When trying to do comparative studies of equity markets, you’ll find that every country doesn’t use Generally Accepted Accounting Principles like we do in the United States. A fund may appear opaque politically and not want people to show what they’re invested in or what their intent with that investment is, but they could also just not be able to report it because of the way it was purchased, or the kinds of shares they purchased. There are some assets out there that really are difficult to put a monetary value on. GJIA: To what extent do domestic politics shape SWF behavior in both the investing “home” country and the recipient “host” country? KL: This depends on the type of fund present and also on the extent to which voters’ political views are able to influence the fund. For example, in a democratic home state like Norway, the SWF doesn’t invest in nuclear weapons or tobacco because of social concerns, but there is a continuing debate over whether it should invest in oil, even though that’s where most of the money comes from. The degree to which Norway will continue to make those investments, and whether they contradict the government’s overall climate goals, is an open question in Norwegian politics. Because of the way the fund’s governance is structured, it may not be easy to resolve. On the other hand, some people consider pension funds, like the State Teachers Retirement System (STRS) in Ohio, to be quasi-SWF. They have a very strict separation between the people who make up the management division and the fund owners. No teacher or professor would want to invest in things that may harm the future of their students. At the same time, a fund manager might see an opportunity in a diversified multinational corporation that offers a good return, despite it deriving part of its revenue from e-cigarettes. These contests are very apparent. Domestic politics can work in host countries too. A good example is Singapore’s SWF, Temasek, investing in Thailand’s telecommunications sector. If you study political economy, you already know that countries everywhere are uncomfortable with foreign ownership of their telecom sectors because a foreign entity could monitor or manipulate our communications with each other. In the case of Temasek, there was significant pushback from Thai citizens surrounding the deal, which went on to influence national political sentiment toward Singapore as a whole, underscoring the risks some SWFs may face with their investment choices. In this case, fund behavior led to the dissolution of the entire Thai government in 2006 and a subsequent coup d’état. GJIA: To address some of this unease, the Santiago Principles were established in 2009 to ostensibly promote trust and transparency. From your perspective, have these mechanisms actually changed fund behavior? KL: In international relations theory, we always like to have a clear set of norms and best practices—the orientation we want the proverbial ship to be going in. In that regard, the Santiago Principles at least got the discussion going about which direction SWFs should take at a time when people were very skittish about the growing size of these funds. Nobody wanted them to be out there and potentially destabilizing economies, so talks about disclosure, conditions for withdrawal, and the independence of managers were helpful when initiated. The biggest stumbling block was that there wasn’t exactly a good way to measure compliance with the Principles, let alone how to hold funds to them. If you read the Principles, they’re overall quite vague. In general, a fund doesn’t want to reveal how and why they make certain investment decisions because that information is proprietary—a fund makes money off of how and why it makes decisions—so how do you reconcile that with loosely-defined ideas of openness? Some decisions might have a political purpose. The bottom line is that trying to figure out and assign a score to compliance is not easy, and it is therefore the reason why the Santiago Principles never really got off the ground to the point where they could truly direct fund behavior. GJIA: Many emerging markets are looking to build their own SWFs from mineral and oil revenues. Historically, have funds shaped development trajectories in these countries? KL: I think the big story in international emerging markets investment is that the investment is increasingly no longer unidirectional. In the past multinational corporations of primarily Western background were the main form of foreign direct investment in a country. That has changed dramatically, to the point where you have companies from so-called “developing countries” taking over companies in the United States. Therefore, the landscape of international investment has changed, and I think SWFs are certainly a possibility to be the next step in the game. Historically, you didn’t need an entire financial vehicle to reinvest commodity revenues in your country, but as emerging markets get more financially sophisticated, their capacity to operate such funds has increased. SWFs would allow treasuries to move from relying on holding foreign exchange assets like cash or government bonds to having broader financial markets and targeted growth areas, while easing pressure on welfare expenditures. GJIA: With their increasing financial weight, do you see the presence of SWFs being a factor in the political choices leaders will have to make with regard to domestic and foreign policy? KL: It will depend on just how big the funds get. One of the reasons people are already apprehensive is because of their scale, and if certain SWFs in certain countries achieve a large-enough size, the presence will absolutely be cause for concern. The other factor political leaders will have to consider are their objectives. It’s not always clear how to define a SWF, or even where its activity is concentrated, but it is certainly a worry from the perspective of national security of opaque external investment. More than that, I think one of the most interesting questions going forward is whether the United States, the home to the world’s largest financial markets, will develop its own fund, for which the Trump administration announced a plan. There have also been several proposals in Congress. Were it to come into being, it would have tremendous weight. At the same time, one of the hallmarks of U.S. capitalism is a lack of government ownership of shares, so it would not be clear how such a fund would be received in domestic politics, or which direction it would take. Given how politically fragmented the country is, a Democratic administration would likely be concerned about different sectors of the economy, such as healthcare, and want investment there, rather than a Republican administration, which might prefer defense industries. No investment vehicle could thrive under conditions of such instability. Moreover, it remains unclear where the money to fund a theoretical U.S. SWF would come from. It would be a fundamentally different entity depending on whether it is financed with debt, economic surplus, commodities, or the sale of state companies, as in the case of Singapore. If it is debt, or government borrowing of some form, then the fund would have to outperform whatever the cost of that debt is, which is not an easy thing to do. I think our political leaders have enough on their plate. Our system has worked well keeping political and investment functions generally separate. We have seen different forms of business rise and fall, and even the perception of different countries, all of which funds are tied to. Unless a major SWF either starts—like in the case of the United States—or collapses—an issue that concerns the Saudis, I don’t see any political tsunamis on the horizon. . . . Kathryn Lavelle is the Ellen and Dixon Long Professor of World Affairs at Case Western Reserve University in Cleveland, Ohio. Her research explores the exchange between domestic and international and political institutions with a particular emphasis on political economy and multilateralism. Dr. Lavelle’s first book, The Politics of Equity Finance in Emerging Markets, explored the political circumstances that surround large issues of stock in the developing world. After being granted tenure at Case Western, she was awarded an American Political Science Association Congressional Fellowship and named the William A. Steiger fellow, a designation given to the most promising political scientist in her class of fellows. While in Washington during 2006-2007, she worked on the staff of the House Committee on Financial Services on issues related to domestic and international monetary policy. Dr. Lavelle holds a PhD in political science from Northwestern University; an M.A. in government and foreign affairs from the University of Virginia; and a bachelor’s degree in international economics from Georgetown University. She is a permanent member of the New York Council on Foreign Relations. This transcript has been lightly edited for clarity and length. Interview conducted by Sid Mehrotra. Image Credit: Jason Leung, Unsplash Content Licenses, via Unsplash
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