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Baylor debuts new health programs at annual Career Day event
At this year's event, brand-new graduate health programs, including master's programs in Bioethics and Health Data Analytics, were featured to undergraduates for the first time.
GFCB to invite John Taft for business lecture series
The Gordon Ford College of Business will welcome a vice chairman for financial services firm Baird to the Experiencing Business Speaker Series. John Taft will share career insights on Thursday at 3:45 p.m. in Chandler Hall’s Houchens Industries Auditorium, Room 1001. Taft’s 40 years of experience in the finance industry include serving as CEO for...
UNR launches animal science program to keep students in-state
University of Nevada, Reno launches a new bachelor's degree in animal science to train students for livestock and biotech careers.
Central College receives $2.5 million for TRIO Talent Search program
Central College has been awarded a $500,000 annual grant from the U.S. Department of Education to continue its Federal TRIO Talent Search Program for another five years. The funding, totaling $2.5 million, will support a program that serves about 1,000 students in the Des Moines area. Talent Search provides tutoring, counseling, mentoring, career exploration and…
NMSU College of Business to honor 2026 Hall of Fame recipients, community partners
New Mexico State University’s College of Business will celebrate accomplished alumni, valued corporate partners and community leaders whose careers and contributions have made a lasting impact at...
Sandhills Community College Small Business Center expands to Moore and Hoke Counties
Small Business Center Director, Laura Kinsman. Photo provided by: SCCSandhills Community College (SCC) is launching a redesigned Small Business Center model that expands no-cost entrepreneurial support across Moore and Hoke Counties. Rooted in the College’s commitment to strengthening small businesses and entrepreneurship as drivers of economic growth, the enhanced model is led by recently appointed Small Business Center Director, Laura Kinsman. The model also includes two new Senior Business Advisors who will provide trusted expertise, stronger community connections, and individualized guidance to entrepreneurs and business owners throughout the region.Kinsman brings a unique perspective to the director’s role as both a local business owner, operating in downtown Southern Pines, and a former Moore County educator. “Her combination of education, business ownership, leadership, and community involvement make her a great fit for the Small Business Center and the work we are continuing to build across Moore and Hoke counties,” said Taylor L. McCaskill, senior director of Workforce Development & Corporate Partnerships in a press release.Kinsman is an active member of the Southern Pines Business Association and has been connected to the Sandhills Small Business Center since the beginning of her entrepreneurial journey. She looks forward to building on that experience by strengthening the Center’s partnerships and expanding its connections throughout the community.She will lead the Center's efforts to support entrepreneurs and business owners throughout Moore and Hoke County and be the connector to the North Carolina Community College System Small Business Center Network operations. The Center offers no-cost, confidential one-on-one counseling, practical workshops, and connections to the resources and partners that help local businesses start, grow, and create jobs.A key part of this new approach, only offered at SCC, is a network of Senior Business Advisors, experienced professionals who will provide individualized guidance in areas such as business planning, finance, marketing, operations, growth strategy, and problem-solving. These advisors will serve as trusted partners to entrepreneurs and business owners, helping them turn ideas into action, overcome barriers, strengthen existing businesses, and pursue new opportunities. This one-on-one counseling is available at no cost, ensuring that high-quality business support is accessible to entrepreneurs at every stage.Senior Business Advisor for Hoke County, Kenna Parks. Photo provided by: SCCKenna Parks has been named the senior business advisor for Hoke County. She is a business professional, entrepreneur, and educator who brings a unique combination of academic training and real-world business experience. She earned her Master of Business Administration (MBA) in 2017 and has built her career around entrepreneurship, marketing, business development, and helping others turn ideas into sustainable opportunities.Senior Business Advisor for Moore County, Katrin Henderson. Photo provided by: SCCAs a military spouse, she has successfully launched and operated businesses across five states, giving her firsthand experience in adapting to diverse markets, building new customer bases and understanding the importance of global reach in today’s business environment. Over the last decade, her areas of focus include business planning, marketing strategy, branding, customer development, financial preparedness, operational planning and connecting entrepreneurs with educational programs and community resources.Parks brings an especially valuable perspective to business advising because she is an entrepreneur herself. She is the owner of Glamo Society Bridal & Formal Wear in Raeford, N.C., giving her firsthand experience with the realities of launching, operating, marketing and growing a small business. She understands that entrepreneurship extends far beyond developing a great idea; it requires strategy, financial awareness, adaptability, strong customer relationships, and consistent execution.Katrin Henderson will serve as the senior business advisor for Moore County. Thriving in hospitality and retail, Henderson has enjoyed positions in Food & Beverage Management and Retail Management in various fine dining and retail establishments in the area, before opening her own children's shop in 2015, in the Village of Pinehurst. She is a native of Moore County.Quickly immersing herself in this new world of small business ownership, Henderson joined various boards and committees, including President Elect of Pinehurst Business Partners and Event Chair for the Holly Arts & Crafts Festival. She also partnered with local organizations such as Moore County Economic Development and Moore County Chamber of Commerce and Sandhills Community College Small Business Center in events and educational opportunities. In 2026, Henderson sold her shop and now offers full-time support to both new and seasoned entrepreneurs through freelance consulting mentorship and the SCC Small Business Center program.The Small Business Center team is passionate about making business resources more accessible, and ensuring entrepreneurs know they do not have to navigate business ownership alone. Through their work with SCC, they are committed to building meaningful relationships with local businesses, community organizations, and industry partners while helping entrepreneurs move from idea to strategy, strategy to action, and action to sustainable growth.“Sandhills Community College believes deeply in the power of small business and entrepreneurship because strong local businesses create jobs, spark innovation, generate investment, and strengthen the communities we serve,” said McCaskill in press release. “Through this new Small Business Center model, Sandhills is building a stronger ecosystem where entrepreneurs can connect, grow, and thrive, while helping drive long-term economic vitality throughout our region.”To learn more about the Center's services or to schedule a consultation, please contact Kinsman directly at kinsmanl@sandhills.edu or 910-695-3938.
Small Business Center Relaunch Brings New Director, Advisors
The North Carolina Community College system, and Moore County’s Sandhills Community College, is a resource for secondary and continuing education, allowing students to step into careers, find a new path
UAMS Conference Introduces College Students to World of Behavioral Health Careers
The University of Arkansas for Medical Sciences (UAMS) Psychiatric Research Institute is holding a free conference Oct. 24 aimed at introducing college students to the world of behavioral health careers.
Hairdressing Is an Art; Let’s Remember It’s Also a Business
Across the country, hair salons are seeing demand for their services grow. And while beauty professionals may have amazing skills as far as their craft, what almost none of them have been taug | L.A. hairstylist, salon owner, and educator Paula Peralta argues that while technical skills may launch a career, business education is what helps stylists build their futures.
Top Ranking for Bellevue University's Counseling Master's
CounselingPsychology.org ranked Bellevue University's Master of Science in Clinical Mental Health Counseling program No. 2 among counseling master's programs in Nebraska for 2027. The ranking recognizes Bellevue University's CACREP-accredited program and its online format designed to support students preparing for counseling careers and licensur...
Intern program highlights careers beyond bedside
ECU Health's Talent Acquisition team launched a new non-clinical internship program this past summer to promote careers in health care.
Could Trent Alexander-Arnold Ever Return To Liverpool?
Trent Alexander-Arnold's Real Madrid career continues to confuse with the right back back in Thomas Tuchel's good graces for England.
Fraud, compromise, and groupthink. How warped research incentives undermine science
Science is supposed to correct its own errors. In practice, distorted academic incentives often block that quality control. Universities produce far more PhDs than faculty jobs, then judge survival by grants—especially federal awards that benefit the schools themselves. Researchers who stray from funders’ preferred questions face stalled careers. The unfortunate result is groupthink that often hinders scientific progress.
A wild playoff day in 2 sports. Plus: NHL’s No. 1 pick debuts
Good morning! A lot happened yesterday. Inside: ⚾ Postseason = on 🏀 Top seed = out 🏒 Puck = dropped The Postseason: Six stats from a massive day October started on Sept. 29 this year. All four of MLB’s best-of-three Wild Card Series got underway yesterday. Here’s a key number from each of them: 71.5 percent: The Phillies’ win probability in Game 1 against the Braves when Austin Riley, the Atlanta third baseman who had the worst season of his career, came to the plate against lights-out reliever
Esteban Ocon to leave Haas putting F1 future in doubt
Esteban Ocon is fighting to save his Formula 1 career after the Haas team announcement that they are splitting with the Frenchman at the end of the year.
How a neighbor and daughter inspired Aric Putnam's political career
Aric Putnam first ran because a Republican neighbor told him he should. Now, he wants to build on the successes he's seen while in office.
The Premier League footballers studying to become sporting directors
Kiernan Dewsbury-Hall, Taiwo Awoniyi and others have been juggling education with a football career - even studying on the team bus during away trips.
The Premier League footballers studying to be sporting directors
Kiernan Dewsbury-Hall, Taiwo Awoniyi and others have been juggling education with a football career - even studying on the team bus during away trips.
Remove the blinders about ‘office housework’
Research highlights the invisible labor and emotional toll women in virginia workplaces endure, affecting their time and career advancement.
Lansing Construction Science Expo returns, connecting 450 students to construction careers
Hundreds of students gathered in Lansing to learn about careers in construction science.
Tiffani Thiessen said she was ‘questioning my career’ after not landing role in James Bond film
‘Saved by the Bell’ alum Tiffani Thiessen said she was one of the final three candidates in an audition process for a James Bond film and the rejection was ‘one of the hardest’ she endured.
Texas sports anchor says goodbye to state in last-day career reveal
The move closes nearly a decade in Texas sports media.
My husband and I met at work; then I switched careers
I met my now-husband while we were working together at the same place in similar jobs as teachers. A few years later, I switched careers and fields.
Heart of a Fighter: A Colonel’s Journey from Silent Heart Attack to Triple Bypass at Broward Health
Dr. Alexander Justicz, Tim Irvin, Dr. Kenneth Herskowitz September 29, 2026- Tim Irvin II, a colonel with the Broward Sheriff’s Office (BSO), doesn’t back down from a challenge, even when it’s literally his heart on the line. Over the course of his more than 30-year career in law enforcement, the 51-year-old husband and father moved […]
Case Keenum puts on masterful performance with on Caleb Williams sidelines for MNF
Case Keenum put on one of his career's more masterful performances in the Chicago Bears' "Monday Night Football" win over the Philadelphia Eagles.
Kings’ Ben Simmons addresses critics, mental health; says he is in top form
The three-time All-Star is back after physical and mental health struggles nearly derailed his career.
Titan Business EDGE: Building career readiness from the first year to the first job
By Daniel Coats Career prep is most effective when it begins long before graduation. For Cal State Fullerton College of Business and Economics(opens in a new tab) students, knowing how to build professional skills, gain meaningful experience and ultimately launch a career requires intentional development over time. The new Titan Business EDGE program provides that pathway […]
BMW Manufacturing hosting 900 students for career day Oct. 6
BMW Manufacturing will welcome more than 900 middle and high school students Oct. 6 for the company’s Manufacturing Careers Day 2026.
Now an elder statesman, former Gov. Gray Davis surveys his career in a major Berkeley project
After 17 lengthy recording sessions and more than a decade of review and revision, Davis and the Oral History Center at Bancroft Library are releasing their monumental history of a career that help shape modern California.
TeraOpenScience Launches Global Innovation Contest: Idea • Innovation • Business: A Science Challenge uniting Students & Professionals
WOODBURY, Minn., September 28, 2026--TeraOpenScience, the open-innovation platform accelerating real-world scientific and technological breakthroughs, today announced the launch of its global contest, Idea • Innovation • Business: A Science Challenge. The competition invites students and early-career researchers to lead one of the platform’s featured technologies, build a multidisciplinary team, and propose a full innovation and commercialization plan to bring the solution to industry.
Stony Brook University Professor Daniel Klein Receives a 2027 Lifetime Achievement Award from the Association for Psychological Science (APS)
STONY BROOK, NY—September 28, 2026—The State University of New York (SUNY) at Stony Brook (Stony Brook University) Distinguished Professor in the Department of Psychology Daniel Klein has been awarded a 2027 Association for Psychological Science (APS). “Mentor Award.” This award recognizes APS members who have significantly helped foster the careers of others, honoring those who
Axios Live: Utah's health worker shortage is more than a numbers problem
Utah's health care workforce shortage reflects gaps in pay, clinical training and access to career pathways
The United States Will Be Worse off for Losing International Scientists
The U.S. has long benefited from the scholarship of international scientists. The Trump administration's policies are forcing many to reconsider their careers here.
Business Insider: The Hidden Sacrifices of Chasing an H-1B Career in America
Partner Aaron Blumberg discusses how proposed changes to the H-1B program could affect workers facing layoffs and families navigating dependent visa status.
One of Brett Favre's interception records was broken on 'SNF'
Brett Favre's record for career pick-sixes thrown was broken on "Sunday Night Football." It lasted 18 years.
Justin Herbert and Patrick Herbert’s Unexpected Football Connection Revealed
Patrick Herbert spent years building his own football career away from his famous brother Justin Herbert. He went undrafted, worked through practice squad rosters, and kept fighting for his opportunity. That relentless grind reached a defining moment when Los Angeles promoted the tight end to the active roster. The move sets up a rare family […] The post Justin Herbert and Patrick Herbert’s Unexpected Football Connection Revealed appeared first on Gridiron Heroics.
Dominique Lewis, Spotlighted By Influential Women, Connects Life Science Expertise With Holistic Wellness
A Career Rooted in Scientific Knowledge, Personal Growth, and Meaningful Transformation Washington, DC – Dominique Lewis has developed a distinctive
How a UTC professor is helping first-year chemical engineering students explore career paths
What does a chemical engineer do? How can a student prepare for medical or pharmacy school? Where can students find people and resources to help answer those questions? Dr. Bradley Harris, head of UTC’s Department of Civil and Chemical Engineering in the College of Engineering and Computer Science (CECS), is helping students begin those conversations through A Moc’s First Year, a campuswide program designed to help incoming first-time, full-time undergraduates make connections to UTC, Chattanooga and one another.
How a family garden center sparked a four-decade career in science
After becoming fascinated by chemistry as a boy, Robert Fanick dedicated his life to research and teaching youngsters about science.
HEALTH AND FITNESS: This is your brain on football
Football season is underway, much to the delight of professional, college and high school fans. Football has also been in the news for another more serious reason – the association with brain injury. Over the years, it has been reported that several former NFL players suffered from brain injury because of concussions sustained over years of playing. Some players have even retired early in their careers to avoid such injury. Recently reported research suggests that this brain damage may start earlier and be the result of cumulative “minor” injuries rather than a single major trauma.
Harriet Slater ready to fight in ‘Outlander: Blood of My Blood’ S2
Playing a passionate woman in 18th century Scotland in the hit prequel “Outlander: Blood of My Blood” has certainly changed Harriet Slater’s career.
Ted Hurst III records first-career TD
Tampa Bay Buccaneers wide receiver Ted Hurst III posted a 40-yard reception on his only catch of the Week 3
Travis Etienne Injury Update is Key News for Saints
Travis Etienne hasn’t gotten his New Orleans Saints career off to a great start. It might be getting worse in Week 3. He appears to have sustained an injury. While the Saints were in the midst of throwing four touchdowns to tight ends (two to Juwan Johnson, two to Noah Fant), Etienne left the field […] The post Travis Etienne Injury Update is Key News for Saints appeared first on HEAVY.
NASCAR Cup Series Standings After Kansas: Full Chase Points Update
Kyle Larson did more than win Sunday at Kansas Speedway. He left the track with a commanding lead atop the NASCAR Cup Series Chase standings. Larson’s victory, his fourth career Cup win at Kansas, capped a massive points day for the Hendrick Motorsports driver. He earned 76 points, the most by any driver in a […] The post NASCAR Cup Series Standings After Kansas: Full Chase Points Update appeared first on HEAVY.
Barbour Community Health psychologist wins statewide award for school-based mental health work
The West Virginia Psychological Association named Dr. Casey Jo Cottrill of Barbour Community Health Association its 2026 Early Career Citizen Psychologist for her work expanding behavioral health care in rural schools.
Max Scherzer Gets A Win To Finish The Season
Reds 1 Blue Jays 5 If I were Max Scherzer, that’s how I’d want to end my career. He threw seven innings, allowed six hits, one earned run, one walk, and seven strikeouts (which would finish him with 3,557 strikeouts, three fewer than Justin Verlander). Max threw 114 pitches. That’s just amazing, especially on short […]
Chris Messina wants a new vision for Orange County
Messina, who is competing in a runoff for Orange County Mayor, says career politicians should no longer be in charge.
Tennessee players who set or tied career highs against Texas
Tennessee versus Texas: Vols who set or tied career highs
Jimmy Butler and Draymond Green Could Reportedly Retire With Warriors
Stephen Curry's new extension settled one big question in Golden State, and a new report says two other veterans want to finish their careers there too.
South Texas Health System (@stxhealthsystem)
0 likes, 1 comments - stxhealthsystem on September 27, 2026: "Support Recovery, Strengthen Your Future: South Texas Health System, the Rio Grande Valley's largest integrated healthcare network, is seeking passionate physical therapy professionals to join its nationally recognized inpatient and outpatient rehabilitation teams at STHS McAllen, STHS Edinburg and STHS Heart. Physical therapists play a vital role in helping patients regain strength, mobility and independence following illness, injury or surgery. If you're passionate about empowering patients on their road to recovery, STHS offers an opportunity to make a lasting impact every day. Join a collaborative team dedicated to exceptional patient care and helping individuals return to the activities and quality of life they value most. Ready to move your career forward? View current openings and apply today at the link in our bio.".
Erling Haaland and Kylian Mbappé battle for international scoring milestones
thenews2.com/Depositphotos Erling Haaland and Kylian Mbappé lead world scoring Erling Haaland and Kylian Mbappé remain among international soccer’s leading scorers in 2026. Haaland is Norway’s career goals leader, while Mbappé holds the same distinction for France. As of September 27, Haaland has scored 64 goals in 56 senior appearances for Norway. Mbappé has scored 67…
Anna Kendrick Is “Over the Moon” About Directing ‘The Seven Husbands of Evelyn Hugo’
The 'Babies' actress covered George Clooney, 'Twilight' ("what the f*** am I doing here?") and 'Pitch Perfect's "revisionist history" in a career-spanning conversation at the Zurich Film Festival.
Karim Adeyemi recalls being cut by Bayern Munich
The former FC Bayern academy player has had quite the career journey.
Animal Science teacher leads agriculture tour in Belgium and the Netherlands
The Niagara Career and Technical Education Center’s Animal Science teacher Todd Eick offered Orleans/Niagara BOCES students a unique adventure over the summer. He and a group of students spend eight
Democrat José Javier Rodríguez launches 'Give 'Em Hell' statewide ad campaign in Florida AG race
The ad, released in both English and Spanish, centers on Rodríguez's background and career while sharply criticizing incumbent Republican Attorney General James Uthmeier.
Video: Neto lands in Turin to complete Juventus transfer
Brazilian goalkeeper Neto has arrived in Turin and is now ready to sign a contract until the end of the season.Neto is ready to join Juventus for the second time in his career. The 37-year-old Brazili...
From BCG to Juul: A journey through consulting and strategy
Daniel Dantus spent eight years at BCG before transitioning to Juul. Here's his advice on building a career post consulting.
Around the Empire: Wild Card Series previews and predictions
All your Wild Card Series questions answered; Wells’ well-timed turnaround; JV calls it a career.
England’s Harry Kane eyes NFL kicking career
England soccer captain Harry Kane said he's interested in pursuing an NFL career as a kicker.
England’s Harry Kane eyes NFL kicking career
England soccer captain Harry Kane said he's interested in pursuing an NFL career as a kicker.
Arizona at Washington State: Players of the Game
Saturday night saw the Arizona Wildcats travel to Pullman, Washington to take on the Cougars of Washington State. After a pretty up and down first half, the ‘Cats settled down and found their rhythm in the second half, winning a hard-fought contest 34-24. Even with the inconsistencies, there were plenty of clutch plays and career […]
Revisiting Dontrelle Willis’ Career With Miami Marlins
From Rookie of the Year honors to a World Series ring, witness the electric rise of the "D-Train" and his lasting legacy as a Marlins Hall-of-Famer.
Pirates’ Kirby Yates announces retirement; ‘Completely at peace with it’
Kirby Yates is calling it a career. The 39-year-old confirmed after Saturday’s 4-3 loss to the Tigers at Comerica Park that the 2026 season will be his last.
Justin Verlander’s Daughter Tells Her Dad His Career is Over
Justin Verlander’s daughter, Genevieve, walked to the mound to tell her father his final MLB start—and legendary career—was over.
Justin Verlander Empties the Tank in Final MLB Start
Justin Verlander pitched 5.1 innings with six strikeouts before his daughter, Genevieve, joined him on the mound to end his legendary career.
Detroit Tigers Reveal Lineup for Justin Verlander’s Final Start
The Detroit Tigers have revealed their starting lineup for Justin Verlander's final career start Saturday against the Pittsburgh Pirates.
Intel Panther Lake Teardown, 18A, BSPD, GAAFET, SemiAnalysis STEEL
Panther Lake debuts the first commercial implementation of backside power delivery (BSPDN), introduces Intel’s first iteration of gate-all-around (GAA) transistors, and showcases their advanced packaging capabilities with its Foveros-S assembly. With Panther Lake, Intel’s manufacturing arc has shifted from nebulous roadmaps to shipped silicon, a significant milestone on their long road back to competitive semiconductor manufacturing. To evaluate the extent of Intel’s comeback, we tore down Panther Lake. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Our teardown traces 18A from its four-sheet RibbonFETs (Intel’s marketing name for GAAFETs) and gate stacks through contacts, frontside and backside wiring, and the bonded carrier. We explain how these material and integration choices improve gate control and reduce resistance, while adding capacitance, thermal resistance, and process complexity. Our measurements put Panther Lake’s 18A compute logic and TSMC N3E GPU logic at similar logic density. However, 18A does not lead TSMC N3P, N2 or Samsung SF2 in peak density. Panther Lake’s CPU cores are incremental updates, and the high-end GPU still uses TSMC N3E. Panther Lake assembles one compute tile, one GPU tile, and one I/O tile atop a passive base tile using Intel’s Foveros-S advanced packaging. Both compute tile variants use Intel 18A. The Xe3 GPU options are a 4-core GT1 tile on Intel 3 and a larger 12-core GT2 tile on TSMC N3E. Both I/O tile variants use TSMC N6. [1], [2] Our analysis centers on the PTL-U compute tile, both the 4-core and 12-core GPU tiles, as well as the 12-lane I/O tile. In conventional chips, power and signal are routed through the same frontside metal stack towards the device frontend. Power rails consume scarce routing resources near the transistors, while tall via stacks carry VDD and VSS from the coarse upper wires to local rails. Backside power delivery (BSPD) moves the main power network behind the transistor layer, to the backside, separating it from frontside signal routing. We covered BSPD and its impacts in 2024. [3], [4], [5] Intel’s BSPD implementation, branded as “PowerVia”, routes power through dedicated backside metals to nano-TSVs, which connect those rails to local source/drain (S/D) contacts. Implementing that separation requires Intel to build the interconnect stacks from both sides of the wafer. The frontside comprises the M0-M14 signal stack, while the backside comprises the BM0-BM5 power stack. M0 and BM0 are closest to the transistors. The nano-TSVs connect the two sides, but Intel patterns and etches each via from the front after forming the contacts. A narrow via runs from the side of the contact deep into the silicon substrate. Intel then completes the frontside signal metal stack, bonds the wafer to a carrier, flips it and removes the original substrate until the buried via tips are exposed. The backside metal stack is then deposited directly on the revealed vias. The nano-TSV and backside-via profiles taper in opposite directions because Intel forms them from opposite sides of the wafer. The transistor structures form the FEOL. Local contacts and nano-TSVs connect them to the wiring. M0 begins the frontside interconnect stack. The silicon carrier remains attached above the frontside interconnects. It supports the device wafer during substrate removal and backside processing and remains part of the finished chip’s thermal path. PowerVia removes the main power distribution from the congested frontside metals, routing supply through shorter and wider backside wires. Its lateral landing still occupies area in the standard cell, so it recovers less cell area than a direct backside contact. [3] Nano-TSVs beside the logic devices carry VDD or VSS from the backside power network, while signal connections continue upward through the frontside metals. Backside Interconnects Samsung SF2 data is included for comparison to Panther Lake’s within this article. SF2 is the incumbent GAA foundry node but lacks BSPD, serving as a useful reference to evaluate 18A. A full teardown of Samsung’s S26 products, processed on SF2, will be shared soon.Nanosheet-cut EDS comparison. The PowerVia supply path runs from the backside Cu rails through Mo-lined W nano-TSVs to the local transistor contacts. In this cross section, the tapered connection spans roughly 150 nm from the contact level to BM0. The Ta liner confines Cu and promotes adhesion to the surrounding stack; the AlOₓ etch stop controls the next dielectric etch above the rail. Dielectric beneath the ribbons electrically separates the devices from the backside wiring and removes the conducting silicon body below the channel. [6] AlOₓ serves as an etchstop (ES), enabling endpointing and protecting the underlying layers. Low-volatility aluminum fluoride reaction products resist the fluorinated plasma, allowing a thin AlOₓ film to protect the metal while the surrounding low-k dielectric is removed. [6], [7]. While the BM0 and layers above the M1 lines show double AlOx layers, Our SMIC N+3 teardown showed single AlOₓ layers. SMIC uses a simpler local AlOₓ substack, while the remaining cap and etch sequence provide the required landing protection. So why double layers? The closely spaced AlOₓ doublets provide two protected endpoints in the etch sequence. Intel documents an AlOₓ/SiN/AlOₓ stack that explains the benefit. The main dielectric plasma etch stops on the first AlOₓ film; a selective wet clear opens that film; a second plasma etch removes the intermediate SiN and stops on the second AlOₓ film. The final wet clear exposes the metal landing surface. SiN is the intermediate dielectric in Intel’s published example. [8] The second stop protects the metal through a cap breakthrough. Wide openings can etch faster than narrow ones, and etch depth varies across the wafer. Metal under an early-clearing opening would otherwise be exposed while other openings still need more etching. Staged protection widens the process window and reduces metal erosion, corrosion and void formation. [8] TSMC documents AlN/AlOₓ/SiOC/AlOₓ above Cu, with AlN blocking Cu diffusion, and a simpler AlN/SiOC/AlOₓ variant that omits one AlOx film. [9] Levels with different opening sizes, aspect ratios, pattern densities and cap materials need different etch margins. A double AlOx stop is useful where another protected endpoint justifies the added processing. The extra film adds formation, selective opening and cleaning steps, plus another set of interfaces to control adhesion, moisture, and stress. These blanket films are opened through the existing via pattern, so each film does not require another lithography mask. AlOₓ adds parasitic capacitance when it replaces lower-k dielectric; two thin AlOₓ films can nevertheless contain less AlOₓ than one thick film. Total thickness, placement, and theintermediate dielectric determine the electrical cost. Deposition chemistry also changes AlOx permittivity and residual hydroxyl content, which can oxidize the underlying metal. [7], [8], [10], [11] The backside stack separates into relatively fine BM0-BM2 wiring near the devices and coarser BM3-BM5 power distribution. The largest pitch increase occurs between BM2 and BM3. BM0’s pitch closely matches the logic-row height, fitting local power delivery to the cell rows. Higher levels aggregate current through larger conductors: routing density becomes less important than low resistance and current capacity as the network approaches the package. This hierarchy provides wide power wiring for the power delivery network without consuming scarce frontside signal-routing resources. [3] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Frontside Interconnects Intel 18A combines Mo-lined W contacts and nano-TSVs with a separate backside Cu power network. Samsung SF2 keeps power on the frontside, using Ti-based contact interfaces and Ta-based barriers and Co liners around Cu wiring. In 18A standard-cell rows, backside power rails supply the devices through nano-TSVs within the cells, freeing frontside routing resources. Samsung’s M0 accommodates both power and signal connections. From the device toward M0, the connection runs through a Ti-based S/D interface, W contact fill, a Mo-lined W via, and the Cu M0 wire. Mo supplies a conductive nucleation and adhesion layer for W, replacing the resistive TiN liner used in conventional W integration. This increases the effective conduction volume within the feature while retaining W fill and its established polishing, cleaning and etching processes. Intel’s Mo/W patent describes this integration tradeoff. The nano-TSV uses the same Mo-lined W construction in the backside supply path. [12] The move from TiN to Mo is an incremental change. While a full Co or Mo fill can also reduce the volume lost to liners in very small features, it requires new integration schemes that increase complexity and risk. Cu remains attractive for wider wires due to its low resistance. As wires and vias shrink, the diffusion barrier consumes an increasing fraction of their cross-section. [12], [12], [14] Intel uses Co/Ru liners at M0-M1, Co at M2-M4, and Nb at M5-M9. The lower-level liners help Cu adhere and reduce void formation during trench fills. Applied Materials’ Endura has new thermal control that facilitate wetting process, so the thin film continuity is good enough that good capillary pressure will drive Cu atoms to the via bottom without voiding. Intel’s choice to use Nb is particularly interesting. Intel’s Nb patent describes a conductive diffusion barrier intended to reduce the barrier’s contribution to resistance relative to conventional Ta-based barriers, particularly at via bottoms where all current crosses the barrier. The patent pairs Nb in coarser levels with the option of lower-cost PVD processing. [15], [16] The upper metal layers support thicker barriers formed through physical vapor deposition (PVD) despite its worse coverage and uniformity. Meanwhile, the lower metal layers require thinner barriers deposited through conformal atomic layer deposition (ALD). Co/Ru adds another material interface and requires controlled deposition and Cu fill. Changing liners and barriers by metal layer allows Intel to optimize interconnect resistance, process complexity, and reliability. [15, 16] RibbonFET, Intel’s name for its gate-all-around FETs (GAAFETs), replaces the FinFET’s vertical fins with four stacked horizontal silicon nanosheets, allowing the gate to surround the channel on every side. The path to GAAFET begins with the planar transistor. A planar MOSFET places the gate above the channel between its source and drain. Pairing an NMOS with a PMOS transistor creates a CMOS inverter, in which the NMOS pulls the output low for a high input, and the PMOS pulls it high for a low input. The gate must retain electrostatic control of the channel to ensure clean switching. As gate lengths shrank, the drain began to compete with the gate for that control, increasing off-state leakage. Electrostatic control was restored through an architectural evolution that raised the channel into a vertical fin and wrapping the gate around three sides. Called “FinFET”, this new architecture packed more effective channel width into a smaller footprint. Further scaling made it harder to maintain both drive current and leakage within smaller cells, and reintroduced the same problems planar MOSFETs faced. Nanosheet GAAFETs close the fourth side by replacing the vertical fin with a stack of horizontal nanosheets, each surrounded by the gate. The tighter electrostatic control suppresses leakage at shorter gate lengths while stacking adds effective channel width within the cell footprint. In a FinFET process, channel width changes in discrete steps as designers must add or remove whole fins. Nanosheet width can instead be adjusted continuously within the process’s design rules. Wider sheets increase drive current, while narrower sheets reduce capacitance at the cost of drive current. Intel 18A uses stacks of four nanosheets each and varies their widths across logic and SRAM. At the process level, adding more sheets to each stack increases effective channel width and drive current, but complicates fabrication. RibbonFET vs MBCFET Samsung began GAAFET production in 2022 with SF3E, following with SF3 and now SF2. Its ‘MBCFET’ provides a useful structural comparison with Intel’s first RibbonFET implementation. [17] STEEL is digging deeper into SF2, used in the Exynos 2600, and TSMC’s GAAFET N2, used in Apple’s A20 Pro, in upcoming newsletter articles. We’re throwing some teasers on X. Let’s compare Samsung SF2’s MBCFET with Intel 18A’s RibbonFET. Subscribe Even to the untrained eye, Intel’s extra nanosheet is obvious. Intel stacks four ribbons to Samsung’s three. Samsung’s sheets are much wider in these fields, so both sheet count and width matter to the available channel perimeter. Sheet width also changes which silicon surfaces carry current. On conventional (001) silicon, wide nanosheets emphasize the broad top and bottom surfaces, favoring electron transport; the larger sidewall contribution in a narrow sheet favors hole transport. Thinner sheets improve gate control but increase confinement and scattering. This makes width and thickness part of the NMOS/PMOS balance, alongside strain and threshold voltage. [18], [19] GAAFET designs like 18A use different work-function-metal (WFM) stacks for NMOS and PMOS. Around each ribbon, a thin SiOx interfacial layer separates the silicon channel from the HfOx high-k dielectric, with La providing dipole tuning and the WFM wrapping the dielectric. NMOS uses a TiAl-based stack, while PMOS uses TiN WFM. W fills the remaining gate trench, providing a lower-resistivity path where the work-function layers are no longer needed. In this field, the PMOS stacks leave room for W between ribbons, while the NMOS stacks occupy more of those gaps. A silicon-based dielectric marks the P/N boundary, allowing the PMOS and NMOS gates, sharing the same gate trench, to be processed sequentially. Fast logic paths, retention circuits, and SRAM need a family of threshold options. Changing threshold without substantially changing device dimensions, capacitance or fabrication complexity is valuable. FinFET processes typically use different work-function-metal stacks. In a four-ribbon GAA stack, the narrow sheet-to-sheet gap limits how much WFM can fit around each channel. La in the gate dielectric creates interfacial dipoles at the SiOx/HfOx boundary, shifting effective work function and tuning threshold voltage. This gives Intel another control alongside its NMOS and PMOS WFM stacks. Low-threshold devices improve critical-path drive; higher thresholds reduce leakage elsewhere. Dipole tuning is especially useful in GAA because it changes threshold without consuming the narrow intersheet gap with thicker WFM. Precise control of La incorporation, diffusion and interface quality has long been a challenge, limiting viability in high volume production but is now seen from every leading-edge foundry. Intel’s patent describes depositing a dipole-forming oxide above HfOx and annealing it toward the interfacial oxide before completing the work-function and fill metals. This separates threshold tuning from the space available for metal. Newer research addresses the thermal cost: imec’s 2026 dipole-middle research inserts the shifter between two HfOx depositions, shortening the diffusion path while protecting SiOx during patterning. [20], [21]Matched-cut EDS, Intel 18A (left) vs. Samsung SF2 (right). Intel retains raised source/drain epi beneath its contacts, while Samsung recesses W deep into the epi to form a V-shaped Ti-lined interface. The deeper contact increases metal-to-semiconductor area and shortens the current path from the lower sheets, reducing contact and spreading resistance. It also removes epi volume and brings the contact etch closer to the channel ends. Retaining more epi preserves the material available for strain transfer, especially from SiGe into PMOS. These geometries balance contact access against stress engineering and etch margin. [22], [23] Samsung stacks three sheets to Intel’s four ribbons, and both processes use sheet width to tune drive strength. In our Samsung cross-sections, widths range roughly from 19 to 30 nm in the NPU rows and 37 to 50 nm in the CU cell. The Samsung nanosheets taper, with the widest sheet at the bottom and the narrowest at the top. Both processes use HfOx gate dielectric and Ti-based work-function stacks, with Al in the NMOS stack. In the Samsung devices shown here, the dielectric and WFM occupy the intersheet gaps, leaving W above the top sheet. Intel’s PMOS stack leaves more room between ribbons, and W fills those gaps while the thicker NMOS stack leaves W mainly in the upper trench. Gate-stack EDS maps. The W between Intel’s PMOS ribbons provides a conductive path close to the lower gates. Where WFM fills the entire gap, the gate still surrounds the channel, but voltage reaches it through the more resistive work-function films. Thinner WFM and dipole tuning preserve room for low-resistivity fill; Mo and Ru are alternative fill metals being developed for further scaling. [24] A masked, sequential WFM flow explains the different gate heights and inter-nanosheet fill. The proposed sequence below shows how separate NMOS and PMOS work-function steps produce that geometry. Enabled by the BSPDN process, Intel replaces the dense-logic silicon subfin with dielectric, removing the parasitic conduction path below the ribbons and reducing substrate-related capacitance. A retained silicon body as in classical, non-SOI, planar and FinFET designs needs junction and punchthrough-stop engineering to suppress leakage. Dielectric isolation makes that leakage less sensitive to the subfin doping profile but adds removal and fill steps. It also weakens the direct thermal path through silicon, making the contacts, metal stacks and package more important for heat extraction. [24], [26] Fluorine is concentrated around selected Intel device structures in the maps. WF6 is a standard precursor for W nucleation and fill, while barrier films protect adjacent dielectrics from fluorine attack. Low-fluorine W processes reduce the residual-F burden. Chloride-based precursors avoid introducing F during W deposition, but require control of chlorine attack, nucleation and fill quality. The integration target is a continuous, low-resistance W path with a thin protective liner and minimal chemical damage to the surrounding stack. [20], [27], [28] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. We measured cell height, gate pitch, metal geometry, and ribbon dimensions at the XTEM sites shown below. The tables group these dimensions by site and device polarity. Our “sheet cuts” cross the silicon channel and show the ribbons end-on. “gate cuts” run along the channel through successive gates. The 18A logic cell dimensions point to a five-track logic library while the N3E and Intel 3 cell dimensions evidence a seven-track logic library. The DDR-PHY uses wider M0 wires and much larger spacing than core logic. That trades routing density for lower wire resistance and weaker coupling between neighboring nets. The geometry suits the current delivery and coupling requirements of analog, clock, and I/O circuitry. PowerVia lets 18A combine a compact cell height with wider M0 geometry by moving the main power rails off the signal-routing tracks. That relaxes local wire scaling while preserving a small cell footprint. Cell height and gate pitch set the geometric density; pin access and routability determine how much of it a real block can use. [29] The biggest takeaway from our gate-pitch measurements is that Intel 18A compute logic and TSMC N3E GPU logic have similar density in the Bohr representative-cell model. The 18A example is 18.6% denser than the Intel 3 GPU example. Gate pitches are nearly identical across the three sites, so cell height drives most of the difference. The Bohr model combines a four-transistor NAND2 spanning three gate pitches and a 32-transistor scan flip-flop (SFF) spanning nineteen pitches, weighting their densities 60:40. The sensitivity column shows how independently changing cell height and gate pitch by ±1 nm changes the result. This compares representative cell geometries; whole-die density also depends on cell mix and placement. The 18A P-core gives M0 substantially more metal cross section than the N3E vector engine. Treating each profile as a trapezoid gives 2.63 times the area per line and 1.84 times the area after normalization by routing pitch. The larger section reduces the geometric contribution to line resistance and lowers current density for a given current. Taller and wider wires also add capacitance, so circuit delay depends on the balance of resistance and capacitance. The DDR-PHY has less metal area per routing width than the 18A core fields, while remaining above N3E. [30] Area = height × (top CD + bottom CD) / 2, including liners. Area/pitch normalizes by routing width. Taper is the symmetric sidewall angle from vertical, with the largest angle belonging to the DDR-PHY. Compute tile The measurements show how ribbon dimensions and gate-stack geometry vary across the compute tile and between NMOS and PMOS to balance channel drive, gate load and the space needed for the dielectric/WFM stack across logic, SRAM and the DDR-PHY. Width mainly changes available channel perimeter; thickness also changes electrostatic control and carrier confinement. Gate-stack thickness then determines the space left for low-resistivity fill P-core and LP E-core logic Both the P-core and LP E-core use multiple nanosheet widths. Widths are measured on high-magnification XTEMs while wider-field images demonstrate additional width choices within the LP E-core. Multiple widths are expected even within an LP E-core. Timing-critical paths, buffers and cells with different fanout need different drive strengths. The lower-magnification fields show this width diversity beyond the sites quantified in the table. L2 and L3 SRAM GAA gives SRAM designers another way to balance the pull-up (PU), pass-gate (PG), and pull-down (PD) transistors. FinFET bitcells set device strength through fin count while GAA adds nanosheet width as a sizing knob. In a 6T SRAM cell, a strong pull-down relative to the pass-gate limits read disturbance, while a strong pass-gate relative to the pull-up improves writability. During a write, the pass-gate and write driver pull the node storing “1” below the inverter trip point. During a read, the pull-down holds the node storing “0” low. Bias, threshold voltage, mismatch and assist circuitry set the remaining margin. FinFET high-current cells commonly use a PU:PG:PD fin-count pattern of 1:2:2, a device-sizing ratio rather than a current ratio. Ribbon width lets Intel balance SRAM strengths without adding whole fins. The L2 cell uses its narrowest ribbons for PU and widest for PD, improving writability and read stability respectively. Intel’s disclosed HCC operates without assist; its denser HDC uses negative-bitline write assist. Pulling the selected bitline briefly below ground increases pass-gate overdrive so it can overpower the pull-up at lower supply voltage. That buys density and low voltage writability at the cost of boosting circuitry, switching energy, and additional voltage stress that must be controlled. [31], [32] Four rectangular ribbons give the perimeter = 8 × (width + thickness), before corner rounding. PG/PU is 1.49 and PD/PG is 1.16. The L3 structures closely resemble L2 in layout and cell height. Fewer L3 nanosheet widths are tabulated because fewer high-magnification images were available. DDR PHY The DDR-PHY trades density for controlled analog behavior and reliable off-chip signaling. It contains drivers, receivers, delay circuits, and calibration logic that set drive strength, sampling time, and voltage margin. Repeated four-sheet devices with similar widths fit the use of regular transistor units for matching and programmable drive. Its wider local wiring provides room for current delivery and separation of sensitive signals, while consuming more area than a dense core-logic grid. The layout serves the memory channel’s electrical requirements as well as digital logic density. [33] The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page. Intel 3 GPU devices Vector engine logic Intel 3’s XVE logic uses two-fin PMOS and NMOS devices with power rails in M0. Its cell height and M0 pitch give a seven-track geometry, two tracks more than the 18A logic. One-fin groups also appear among the two-fin devices. Intel 3 L2 SRAM The Intel 3 L2 SRAM uses the familiar HCC sizing pattern: one PU fin, two PG fins, and two PD fins. N3E GPU devices Vector engine logic The N3E XVE field contains repeated two-fin devices with seven-track cell geometry. N3E remains a FinFET process, giving Panther Lake a direct FinFET-to-RibbonFET comparison. N3E L2 SRAM The N3E L2 SRAM uses the same PU:PG:PD fin-count pattern of 1:2:2. Panther Lake-U follows Lunar Lake’s floorplan quite closely. Both pair 4 P-cores with 4 LP E-cores and NPU, media and display engines in similar locations. Lunar Lake also uses Xe2, the direct predecessor to Panther Lake’s Xe3 GPU. This makes Lunar Lake the most direct basis for our comparisons. Arrow Lake differs in core count and uses the older Xe-LPG GPU architecture, so we only use it where it offers a more direct component-level comparison. Compute tile Panther Lake compute-tile floorplans remain sparse even months after launch. Intel 18A’s backside metal and dielectric stack must be removed without damaging the underlying structures before a clean transistor-level floorplan can be imaged. Most published die shots hide or heavily process the background, but we are quite proud of the die shot we achieved and are excited to show the work we have done. We measured the areas of the key components on the compute tile and compared them with their Lunar Lake predecessors on TSMC N3B. These help us to capture changes in block area and compare the two chips across process nodes and designs. Our total tile areas exclude the scribe-line area. The compute-plus-GPU subtotal below uses the PTL-U compute tile and GT1 GPU; it excludes the I/O tile and passive base. Individual block areas use the boundaries marked on the floorplans The compute-plus-GPU row is recomputed from the displayed PTL-U and GT1 areas. Component rows use their stated per-region counts and are not an additive partition of the whole tile. The P-core area remains almost unchanged between Lunar Lake and Panther Lake, despite L2 capacity increasing from 2.5 MiB to 3 MiB. Arrow Lake uses the same Lion Cove core as Lunar Lake but also has a 3 MiB L2. Cougar Cove fits 20% more L2 into the same P-core area. The larger private cache keeps more of each core’s working set close to its execution units, reducing access to shared L3 and DRAM. Extra capacity adds storage leakage and lookup energy, so designers balance it against avoided lower-level accesses. The shared P-core L3 cache also shrank by 14.8%. [2] Cougar Cove combines a similar footprint with Intel’s reported power-efficiency improvements. RibbonFET’s tighter channel control reduces leakage, while PowerVia reduces supply droop and allows tighter voltage guardbands. [1] Darkmont’s four-core LP E-core cluster is 5.0% smaller than Skymont’s on Lunar Lake, with most of the reduction in its L2 regions. The 1 MiB region shrank by 8.4% and the 1.5 MiB region by 14.9%. The tag arrays also use one fewer visible row. Tags identify which memory addresses the data array holds, so rearranging them changes the cache’s layout and wiring without requiring less data capacity. [2] The LP E-cores share one L2. This pools capacity and avoids duplicating all the cache machinery, but the four cores contend for its banks and bandwidth. Their separate cluster also keeps light work away from the performance cluster and its L3, allowing that larger domain to sleep. [1], [2] Cache area includes more than the storage cells. Tags identify each line, decoders select rows, sense amplifiers read the small bitline signal, and wires connect to the banks. Splitting an array into smaller sections shortens wordlines and bitlines, improving access speed, but duplicates peripheral circuits. Panther Lake’s smaller cache regions therefore reflect the complete memory implementation, including how much of each region is devoted to storage. [34] Unlike Meteor Lake and Arrow Lake, Panther Lake has no separate SoC tile. The NPU, LP E-cores, memory controllers, PHYs, media and display engines now share the compute tile. This removes an active die and keeps CPU memory traffic on one die. The cost is moving PHY and I/O-related circuitry onto 18A: drivers, receivers and analog circuits must still meet external voltage, loading and signal-integrity requirements, so their area does not shrink like dense digital logic. [1], [2] The biggest shrink comes from the NPU, which occupies 36.9% less area. NPU 5 consolidates the same total INT8 MAC count into half as many neural compute engines. Each of the three NCEs has a larger MAC array to make the complete NCE envelope 22.6% larger than an NPU 4 engine. Consolidation also halves the number of scratchpads and SHAVE DSPs, from 12 to 6. The MAC array handles matrix multiplication and convolution, while SHAVE executes vector and custom operations that fit the array poorly. [1], [2], [35] The paired floorplans identify each NCE envelope and its scratchpad, MAC, and SHAVE regions. Each measured MAC polygon is counted once per NCE in the area accounting below. The scratchpads store weights, activations, and intermediate results near the MAC arrays, allowing repeated use without fetching them again from DRAM. Halving their number delivers the largest measured area saving but leaves less local storage for the same total MAC count. Layers that no longer fit locally require smaller working tiles or more transfers of intermediate data. The benefit depends on keeping the enlarged arrays busy while managing that tighter storage budget. [36] NPU 5 also adds native FP8. Using half the operand width of FP16 reduces storage and transfer demand, helping workloads fit the smaller local memory budget. Lower precision and format-dependent range make scaling and model validation part of deployment. Hardware activation functions further reduce work that would otherwise occupy the programmable DSPs. [1], [2] Microsoft requires an NPU to deliver at least 40 TOPS for Copilot+ PCs. Both Lunar Lake and Panther Lake meet this threshold, but Panther Lake uses significantly less silicon. GPU tiles Panther Lake is Intel’s first product with Xe3, its latest GPU architecture. It offers two different GPU tiles: a smaller GT1 tile with 4 Xe3 cores on Intel 3 and a larger GT2 tile with 12 Xe3 cores on TSMC N3E. Panther Lake allows us to compare the same GPU architecture across both Intel 3 and TSMC N3E. Wildcat Lake adds a third Xe3 implementation on Intel 18A. A future newsletter will detail Xe3 and its implementation differences across all three process nodes. GT2 scales Xe3 to a different physical layout, with render slices arranged vertically instead of GT1’s horizontal arrangement. Slice placement sets the distances to shared cache banks and the D2D interface. Those wires consume area and add delay, so scaling the number of Xe cores also requires a new balance of cache placement, routing and timing. [1] What’s immediately obvious is that the GT2 tile on TSMC N3E has much smaller Xe cores than GT1. These block areas include logic, caches, and routing. An Xe core on the GT1 tile is ~69% larger than one on Lunar Lake, and ~55% larger than one on GT2. Intel 3 therefore uses substantially more area per Xe core. The block-area gap exceeds the measured logic and SRAM density gaps, bringing routing, timing targets, cell mix, and floorplan allocation into the comparison. The measured vector/matrix engine region is almost unchanged between Lunar Lake and Panther Lake’s GT2 tile. Xe3 retains eight 512-bit vector engines and eight 2048-bit XMX engines per core. Its gains also come from feeding those engines more effectively: more resident threads hide stalls, and variable register allocation lets shaders trade registers per thread against the number of threads kept active. [1] The shared L1/SLM capacity increased by 33% from 192 KiB to 256 KiB, while its area increased only 5%, raising effective density by 27%. L1 retains reused cache lines, while software-managed SLM lets a thread group share data locally. Both reduce traffic to more distant memory. Allocating more SLM per group can also limit how many groups reside on a core at once. [1], [37] The GT1 tile carries 4 MiB of L2 against 16 MiB on the GT2 tile. GT1 divides its L2 cache into four 1 MiB banks, while GT2 uses eight 2 MiB banks. Each bank contains 128 macros, but each N3E macro stores 16 KiB, twice the Intel 3 macro’s 8 KiB capacity. The N3E macro is only 54% larger while holding twice as many bits, giving it 30% higher density: ~23.7 Mbit/mm² versus 18.3 Mbit/mm². Including bank-level circuitry, the gap widens to ~16.9 Mbit/mm² on GT2 versus ~10.4 Mbit/mm² on GT1. GT2 gains density with its macros storing more bits per unit area, and those macros occupy more of each cache bank. Larger macros spread decoder and sense-amplifier overhead across more storage, while a more compact bank layout reduces the share spent on control and routing. The compromise is longer wordlines and bitlines that carry more capacitance. [34] I/O tile Panther Lake uses two I/O tile variants, both fabricated on TSMC N6. The smaller one provides 4 PCIe 5.0 and 8 PCIe 4.0 lanes and serves lower-tier systems as well as those without a discrete GPU, while the larger one adds 8 PCIe 5.0 lanes, bringing the total to 20 lanes, for discrete-GPU connectivity. Panther Lake SKUs with the larger 10- or 12-Xe GPUs use the smaller I/O tile. [38] The smaller I/O tile adds a PCIe 4.0 block and a Thunderbolt block to Lunar Lake’s I/O layout, providing four additional PCIe 4.0 lanes and another Thunderbolt 4 port. Its repeated N6 blocks retain nearly identical areas and layouts. Reusing these proven PHYs and controllers avoids porting and requalifying external interfaces on 18A, where faster digital logic offers less benefit to circuits constrained by the off-chip link. [38] SemiAnalysis’s teardown lab (STEEL) dives deep into the world’s advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. We’re hiring technical experts from system to transistor and everywhere in between. Check out our Careers page. Panther Lake offers scalability and modularity through its disaggregated packaging that partition compute, GPU, and I/O silicon into separate tiles allowing for a suite of tile configurations. This partitioning makes the package part of Intel’s node economics as it determines how much leading-edge wafer area each product consumes, which functions can remain on other processes, and how much configuration freedom Intel can offer from a shared set of tiles. Furthermore, fabricating the compute and GPU tiles separately confines the new 18A process to the compute tile and allows graphics and I/O to use other, more established, and more cost-effective processes. For Panther Lake, the GPU and I/O tiles are assembled alongside the compute tile on a passive silicon base using Foveros-S. Intel’s current technology brief lists a nominal 36 µm pitch for Foveros-S. Through-silicon vias (TSVs) in the base connect the fine wiring above to the larger package connections below. The functional tiles sit side by side on that passive base in a 2.5D configuration. [39] Our cross-section through the compute and GPU tiles shows the package’s wiring hierarchy. Microbumps connect each active tile to the passive silicon base; its fine redistribution layer (RDL) carries the short, dense tile-to-tile links. TSVs carry connections through the base to the package substrate, which fans them out to the much coarser motherboard solder joints. The base supplies interconnect, while computation remains in the active tiles above it. [39] At the compute-tile edge, the higher-magnification inset shows a local microbump spacing of approximately 25.24 µm and a feature width of 12.33 µm. These local spacings are finer than Intel’s nominal Foveros-S value. The X-ray fields further confirm tighter neighboring bumps, consistent across every die-to-die area found on each tile. Additional X-ray analysis is offered after the paywall. Putting the memory controller beside the CPU removes the D2D transfer that CPU memory requests required in Meteor Lake and Arrow Lake. This avoids the extra transmitter, receiver, and link traversal, saving interface energy and latency. Panther Lake’s separate GPU still crosses a D2D link to reach DRAM, so its larger local caches also help contain package traffic. [1], [40] Smaller dies are less likely to contain a random fatal defect, and screening them before assembly prevents one bad tile from consuming a complete package of good silicon. Reuse also spreads design and qualification work across more products. Against those gains, Intel pays for the passive base, D2D circuits, extra bonding and test steps, and losses during assembly. Cost per working product across the portfolio captures the combined effect of wafer yield, reuse, test, and assembly. [29] Wildcat Lake packaging Intel launched Core Series 3, formerly Wildcat Lake, on 16 April 2026 for value mobile and edge systems. Wildcat Lake keeps 18A but removes the passive base and combines more functions on one die to simplify the package. The two products therefore reveal two distinct ways to commercialize the same leading-edge process. [41] Wildcat Lake’s 18A die combines up to two Cougar Cove P-cores, four Darkmont LP E-cores, two Xe3 cores and a smaller NPU. A separate platform-controller die supplies I/O, connected through UCIe, Intel’s first processor implementation of the standard. Consolidating graphics remove a tile boundary and the passive base, reducing assembly complexity for a modest-bandwidth value product. It also ties CPU and graphics scaling to the same die, giving up Panther Lake’s ability to swap in a much larger GPU. [42], [43] In July 2021, Intel CEO Pat Gelsinger set out an ambitious process roadmap aimed at regaining performance leadership by 2025, later described as five nodes in four years. Five years and one CEO later, Intel’s comeback story is not as unambiguously positive as Pat may have hoped. [44], [45] Intel once set the pace for process technology, bringing high-k metal gate technology and FinFETs into volume production years ahead of the rest of the industry. Its 22 nm FinFET process reached consumers with Ivy Bridge in 2012. [46] Intel’s integrated device manufacturing (IDM) model allowed its architects and process engineers to co-optimize products and processes. Starting with Sandy Bridge, Intel dominated x86, while AMD struggled with Bulldozer. That lead faltered at 14 nm and broke at 10 nm. Intel targeted a massive 2.7× density increase, but the node arrived years late and required several revisions before it could support Intel’s full lineup. This delay forced Intel to stretch 14 nm across six generations, while TSMC moved ahead in process technology and AMD recovered in x86. By 2019, Intel was still shipping 14 nm across most of its product stack, with its 10 nm client ramp focused on Ice Lake mobile processors. Meanwhile, TSMC was shipping N7 and N7+, and AMD’s Zen 2 compute chiplets used N7 to raise core counts and improve efficiency. Intel’s process failures were central to its decline, but unsound business decisions furthered their downward slide. Product delays compounded product mistakes, pushing client, server, and FPGA roadmaps off schedule. Several attempts to enter AI (Nervana and Gaudi) and networking (Tofino) also failed to establish lasting businesses. Intel’s recovery has focused on consumer CPUs and advanced packaging. Tiger Lake, Alder Lake, Lunar Lake and now Panther Lake have restored Intel’s consumer roadmap. On the process side, Intel 4 shipped with Meteor Lake, Intel 3 with Granite Rapids and Sierra Forest, and Intel 18A with Panther Lake. Intel has also made advanced packaging part of its foundry offering. However, Intel is still playing catch-up in servers. Several Xeon generations arrived years late and trailed contemporary AMD and Arm server CPUs in performance, efficiency, and core count. The process roadmap is back, but Intel does not hold the same process-technology leadership position it held prior to 10 nm. The introduction of gate-all-around nanosheets and backside power delivery are two of the biggest changes to transistor integration in a decade. Intel took on both changes at once: 18A paired its first RibbonFET with PowerVia in Panther Lake. Panther Lake is a substantial manufacturing milestone. Our cross-sections show how RibbonFET and PowerVia reshape local contacts and wiring, while the floorplans show where architectural consolidation and process choices save area. A sustained competitive lead depends on product performance, cost, yield, and the next implementation. The SemiAnalysis STEEL teardown lab breaks down advanced datacenter and AI hardware. To learn more about our pipeline or to commission a teardown, contact sales@semianalysis.com. WE’RE HIRING: Architecture, floorplan, packaging, manufacturing, and labs experts. Opportunities from system to transistor and everywhere in between. Check out our Careers page.. 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